From 9166833edc0119e093401f6a44a17642a323bee3 Mon Sep 17 00:00:00 2001 From: Matt Borgerson Date: Tue, 6 Oct 2026 17:11:45 -0700 Subject: [PATCH 1/3] Don't regenerate sleigh source when extracting library --- scripts/sleigh_download.sh | 22 +++++++++++++--------- 1 file changed, 13 insertions(+), 9 deletions(-) diff --git a/scripts/sleigh_download.sh b/scripts/sleigh_download.sh index b92fb76..30adf0d 100755 --- a/scripts/sleigh_download.sh +++ b/scripts/sleigh_download.sh @@ -8,16 +8,20 @@ git clone --depth=1 -b Ghidra_${TAG}_build https://github.com/NationalSecurityAg # We just need Makefile and $(LIBSLA_SOURCE) defined inside Makefile. Do it this # way to make sure we stay up to date with the list of required files. -SLEIGH_SRC_DIR=sleigh +# +# Only evaluate the variable; don't build anything. Ghidra ships the bison/flex +# generated sources checked in and does not regenerate them during its build, so +# copy them as-is. DEPNAMES= skips including the depend files, which would +# otherwise cause make to regenerate parsers depending on checkout timestamps. +SLEIGH_SRC_DIR=${PWD}/sleigh pushd ${GHIDRA_SRC_DIR}/Ghidra/Features/Decompiler/src/decompile/cpp/ - -# Touch fake dependency files recently removed upstream. Not having these triggers build steps. -mkdir -p com_opt com_dbg -touch com_opt/depend com_dbg/depend - -echo -e "$SLEIGH_SRC_DIR:\n\tmkdir -p $SLEIGH_SRC_DIR\n\tcp \$(LIBSLA_SOURCE) Makefile $SLEIGH_SRC_DIR" >> Makefile -make $SLEIGH_SRC_DIR -SLEIGH_SRC_DIR=${PWD}/${SLEIGH_SRC_DIR} +LIBSLA_SOURCE=$(make -s --no-print-directory -f Makefile -f - print-libsla-source DEPNAMES= <<'EOF' +print-libsla-source: + @echo $(LIBSLA_SOURCE) +EOF +) +mkdir -p ${SLEIGH_SRC_DIR} +cp ${LIBSLA_SOURCE} Makefile ${SLEIGH_SRC_DIR} popd mkdir ${TAG} From 7bcf627cd08a6602478390072baab2a5938f4585 Mon Sep 17 00:00:00 2001 From: Matt Borgerson Date: Tue, 6 Oct 2026 17:15:23 -0700 Subject: [PATCH 2/3] Bump sleigh_download.sh to 12.1.4 --- scripts/sleigh_download.sh | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/scripts/sleigh_download.sh b/scripts/sleigh_download.sh index 30adf0d..cc70dee 100755 --- a/scripts/sleigh_download.sh +++ b/scripts/sleigh_download.sh @@ -2,7 +2,7 @@ set -e set -x -TAG=12.1 +TAG=12.1.4 GHIDRA_SRC_DIR=ghidra_src_${TAG} git clone --depth=1 -b Ghidra_${TAG}_build https://github.com/NationalSecurityAgency/ghidra.git ${GHIDRA_SRC_DIR} From 8bee505dc8ec44c934385c7d8cfd3a940b41a3c6 Mon Sep 17 00:00:00 2001 From: Matt Borgerson Date: Tue, 6 Oct 2026 17:32:46 -0700 Subject: [PATCH 3/3] Add updates from Ghidra 12.1.4 --- .../68000/data/languages/68000.ldefs | 13 + .../68000/data/languages/68000.sinc | 173 +- .../68000/data/languages/CPU32.slaspec | 6 + .../processors/8051/data/languages/8051.ldefs | 12 + .../8051/data/languages/cip-51.pspec | 389 ++ .../8051/data/languages/keil-cx51.cspec | 187 +- .../AARCH64/data/languages/AARCH64base.sinc | 6 +- .../data/languages/AARCH64instructions.sinc | 24 +- .../AARCH64/data/languages/AARCH64neon.sinc | 30 +- .../data/languages/ARMTHUMBinstructions.sinc | 20 +- .../HCS12/data/languages/HCS_HC12.sinc | 6 +- .../Hexagon/data/languages/hexagon.ldefs | 2 +- .../Hexagon/data/languages/hexagon.sinc | 5370 ++++++++++------- .../Hexagon/data/languages/hexagon.slaspec | 191 +- .../Hexagon/data/languages/hexagon_float.sinc | 305 +- .../Hexagon/data/languages/hexagon_hvx.sinc | 1932 +++--- .../Hexagon/data/languages/hexagon_hvx.txt | 618 -- .../Hexagon/data/languages/hexagon_hvx2.sinc | 1065 ++++ .../Hexagon/data/languages/hexagon_left.sinc | 156 +- .../Hexagon/data/languages/hexagon_right.sinc | 167 +- .../MCS96/data/languages/MCS96.sinc | 6 +- .../processors/MIPS/data/languages/mips.ldefs | 78 +- .../processors/MIPS/data/languages/mips.sinc | 9 +- .../MIPS/data/languages/mips32_16e.pspec | 79 + .../MIPS/data/languages/mips64_16e.pspec | 81 + .../MIPS/data/languages/mips_dsp.sinc | 10 +- .../NDS32/data/languages/nds32.sinc | 8 +- .../PowerPC/data/languages/altivec.sinc | 9 + .../data/languages/ppc_32_e500mc_be.cspec | 2 +- .../data/languages/ppc_32_e500mc_le.cspec | 2 +- .../PowerPC/data/languages/ppc_common.sinc | 18 +- .../data/languages/ppc_instructions.sinc | 125 +- .../PowerPC/data/languages/ppc_isa.sinc | 132 +- .../RISCV/data/languages/riscv.csr.sinc | 60 +- .../RISCV/data/languages/riscv.rv32a.sinc | 40 +- .../RISCV/data/languages/riscv.rv32d.sinc | 20 +- .../RISCV/data/languages/riscv.rv32f.sinc | 28 +- .../RISCV/data/languages/riscv.rv32m.sinc | 10 + .../RISCV/data/languages/riscv.rv32q.sinc | 7 +- .../RISCV/data/languages/riscv.rv64d.sinc | 5 +- .../RISCV/data/languages/riscv.rv64f.sinc | 5 +- .../RISCV/data/languages/riscv.rv64i.sinc | 8 +- .../RISCV/data/languages/riscv.rv64m.sinc | 4 + .../RISCV/data/languages/riscv.table.sinc | 24 +- .../Sparc/data/languages/SparcV9.sinc | 14 +- .../SuperH/data/languages/superh.ldefs | 3 + .../SuperH/data/languages/superh.sinc | 10 +- .../processors/SuperH/data/manuals/superh.idx | 95 + .../SuperH4/data/languages/SuperH4.sinc | 2 +- .../data/languages/Helpers/Conditions.sinc | 38 - .../V850/data/languages/Helpers/Extras.sinc | 131 - .../V850/data/languages/Helpers/Macros.sinc | 254 - .../V850/data/languages/Helpers/Register.sinc | 36 - .../V850/data/languages/Helpers/Tokens.sinc | 105 - .../data/languages/Helpers/Variables.sinc | 49 - .../languages/Instructions/Arithmetic.sinc | 336 -- .../data/languages/Instructions/Float.sinc | 498 -- .../languages/Instructions/Load_Store.sinc | 368 -- .../data/languages/Instructions/Logic.sinc | 167 - .../data/languages/Instructions/Special.sinc | 372 -- .../processors/V850/data/languages/V850.dwarf | 14 + .../processors/V850/data/languages/V850.ldefs | 19 +- .../V850/data/languages/V850.opinion | 8 +- .../processors/V850/data/languages/V850.pspec | 7 +- .../processors/V850/data/languages/V850.sinc | 748 +++ .../V850/data/languages/V850.slaspec | 41 +- .../data/languages/V850_instructions.sinc | 1764 ++++++ .../V850/data/languages/V850e3.pspec | 23 + .../V850/data/languages/V850e3.sinc | 323 + .../V850/data/languages/V850e3.slaspec | 16 + pypcode/processors/V850/data/manuals/v850.idx | 18 +- .../tricore/data/languages/tricore.sinc | 29 +- .../processors/x86/data/languages/avx.sinc | 291 +- .../processors/x86/data/languages/avx2.sinc | 84 +- .../x86/data/languages/avx2_manual.sinc | 20 +- .../processors/x86/data/languages/avx512.sinc | 353 +- .../x86/data/languages/avx512_manual.sinc | 72 +- .../x86/data/languages/avx_manual.sinc | 30 + .../processors/x86/data/languages/cet.sinc | 4 +- .../x86/data/languages/cmpccxadd.sinc | 27 + .../processors/x86/data/languages/fma.sinc | 1011 ++-- .../processors/x86/data/languages/gfni.sinc | 193 + pypcode/processors/x86/data/languages/ia.sinc | 855 ++- .../x86/data/languages/lockable.sinc | 7 +- .../processors/x86/data/languages/rao.sinc | 44 + .../processors/x86/data/languages/rdrand.sinc | 6 +- .../processors/x86/data/languages/sgx.sinc | 45 + .../x86/data/languages/x86-64.slaspec | 1 + .../processors/x86/data/languages/x86.ldefs | 12 +- .../processors/x86/data/languages/x86.slaspec | 2 + pypcode/sleigh/Makefile | 4 - pypcode/sleigh/address.hh | 9 + pypcode/sleigh/error.hh | 2 + pypcode/sleigh/loadimage.cc | 7 +- pypcode/sleigh/marshal.cc | 14 +- pypcode/sleigh/marshal.hh | 4 +- pypcode/sleigh/pcodeparse.cc | 1124 ++-- pypcode/sleigh/pcoderaw.cc | 2 +- pypcode/sleigh/semantics.cc | 4 +- pypcode/sleigh/semantics.hh | 2 +- pypcode/sleigh/sleigh.cc | 2 +- pypcode/sleigh/slgh_compile.cc | 40 +- pypcode/sleigh/slgh_compile.hh | 17 +- pypcode/sleigh/slghparse.cc | 1842 +++--- pypcode/sleigh/slghparse.hh | 240 +- pypcode/sleigh/slghparse.y | 54 +- pypcode/sleigh/slghpatexpress.cc | 17 +- pypcode/sleigh/slghpattern.cc | 14 +- pypcode/sleigh/slghscan.cc | 8 +- pypcode/sleigh/slghsymbol.cc | 119 +- pypcode/sleigh/slghsymbol.hh | 12 +- pypcode/sleigh/space.hh | 12 +- pypcode/sleigh/translate.cc | 111 +- pypcode/sleigh/translate.hh | 3 + 114 files changed, 14201 insertions(+), 9449 deletions(-) create mode 100644 pypcode/processors/68000/data/languages/CPU32.slaspec create mode 100644 pypcode/processors/8051/data/languages/cip-51.pspec delete mode 100644 pypcode/processors/Hexagon/data/languages/hexagon_hvx.txt create mode 100644 pypcode/processors/Hexagon/data/languages/hexagon_hvx2.sinc create mode 100644 pypcode/processors/MIPS/data/languages/mips32_16e.pspec create mode 100644 pypcode/processors/MIPS/data/languages/mips64_16e.pspec create mode 100644 pypcode/processors/SuperH/data/manuals/superh.idx delete mode 100644 pypcode/processors/V850/data/languages/Helpers/Conditions.sinc delete mode 100644 pypcode/processors/V850/data/languages/Helpers/Extras.sinc delete mode 100644 pypcode/processors/V850/data/languages/Helpers/Macros.sinc delete mode 100644 pypcode/processors/V850/data/languages/Helpers/Register.sinc delete mode 100644 pypcode/processors/V850/data/languages/Helpers/Tokens.sinc delete mode 100644 pypcode/processors/V850/data/languages/Helpers/Variables.sinc delete mode 100644 pypcode/processors/V850/data/languages/Instructions/Arithmetic.sinc delete mode 100644 pypcode/processors/V850/data/languages/Instructions/Float.sinc delete mode 100644 pypcode/processors/V850/data/languages/Instructions/Load_Store.sinc delete mode 100644 pypcode/processors/V850/data/languages/Instructions/Logic.sinc delete mode 100644 pypcode/processors/V850/data/languages/Instructions/Special.sinc create mode 100644 pypcode/processors/V850/data/languages/V850.dwarf create mode 100644 pypcode/processors/V850/data/languages/V850.sinc create mode 100644 pypcode/processors/V850/data/languages/V850_instructions.sinc create mode 100644 pypcode/processors/V850/data/languages/V850e3.pspec create mode 100644 pypcode/processors/V850/data/languages/V850e3.sinc create mode 100644 pypcode/processors/V850/data/languages/V850e3.slaspec create mode 100644 pypcode/processors/x86/data/languages/cmpccxadd.sinc create mode 100644 pypcode/processors/x86/data/languages/gfni.sinc create mode 100644 pypcode/processors/x86/data/languages/rao.sinc diff --git a/pypcode/processors/68000/data/languages/68000.ldefs b/pypcode/processors/68000/data/languages/68000.ldefs index 5115f2d..7fe13fc 100644 --- a/pypcode/processors/68000/data/languages/68000.ldefs +++ b/pypcode/processors/68000/data/languages/68000.ldefs @@ -73,4 +73,17 @@ + + Motorola 32-bit CPU32 (MC68340) + + + diff --git a/pypcode/processors/68000/data/languages/68000.sinc b/pypcode/processors/68000/data/languages/68000.sinc index 674c9d0..b6a8b95 100644 --- a/pypcode/processors/68000/data/languages/68000.sinc +++ b/pypcode/processors/68000/data/languages/68000.sinc @@ -59,6 +59,10 @@ define register offset=0x746 size=10 [ FP7 ]; @define DAT_DIR_CTL_ADDR_MODES2 "(mode2=0 | mode2=2 | mode2=5 | mode2=6 | mode=7)" # Data direct and control addressing modes @define CTL_ADDR_MODES2 "(mode2=2 | mode2=5 | mode2=6 | mode2=7)" # Control addressing modes +@ifdef CPU32 +@define TBL_ADDR_MODES "(tbl_mode=2 | tbl_mode=4 | tbl_mode=5 | tbl_mode=6 | tbl_mode=7)" +@endif + # Floating-point condition code bits within FPSR @define N_FP "FPSR[27,1]" @define Z_FP "FPSR[26,1]" @@ -173,9 +177,29 @@ define token extword (16) reg12x = (12,15) reg12xwu = (12,15) reg12xwl = (12,15) -@endif +@endif +@ifdef CPU32 + tbl_dr_size = (6,7) + tbl_dr_round = (10,10) + tbl_dr_sign = (11,11) + tbl_dr_reg = (0,2) +@endif ; +@ifdef CPU32 +define token tbl_instrA(32) + tbl_regan=(16,18) + tbl_mode=(19,21) + tbl_op37=(19,23) + tbl_op67=(22,23) + tbl_opbig=(24,31) + tbl_size=(6,7) + tbl_round=(10,10) + tbl_sign=(11,11) + tbl_regxdn=(12,14) +; +@endif + define token extword2 (16) regda2 = (12,15) ext2_911 = (9,11) @@ -307,12 +331,20 @@ define context contextreg extGUARD = (14,14) # guard for saving off modes before starting instructions ; +@ifdef CPU32 +attach variables [ regdn regxdn reg9dn regdr regdq regsdn regdu regdc regdu2 regdc2 tbl_regxdn tbl_dr_reg ] [ D0 D1 D2 D3 D4 D5 D6 D7 ]; +@else attach variables [ regdn regxdn reg9dn regdr regdq regsdn regdu regdc regdu2 regdc2 ] [ D0 D1 D2 D3 D4 D5 D6 D7 ]; +@endif attach variables [ fldoffreg fldwdreg f_reg fcnt fkfacreg fldynreg ] [ D0 D1 D2 D3 D4 D5 D6 D7 ]; attach variables [ regdnw regxdnw reg9dnw regsdnw regduw regdcw regdu2w regdc2w ] [ D0w D1w D2w D3w D4w D5w D6w D7w ]; attach variables [ regdnb reg9dnb regsdnb regdub regdcb ] [ D0b D1b D2b D3b D4b D5b D6b D7b ]; attach variables [ regda regda2 ] [ D0 D1 D2 D3 D4 D5 D6 D7 A0 A1 A2 A3 A4 A5 A6 SP ]; +@ifdef CPU32 +attach variables [ regan regxan reg9an regfan regsan aregx tbl_regan ] [ A0 A1 A2 A3 A4 A5 A6 SP ]; +@else attach variables [ regan regxan reg9an regfan regsan aregx ] [ A0 A1 A2 A3 A4 A5 A6 SP ]; +@endif attach variables [ reganw regxanw regsanw ] [ A0w A1w A2w A3w A4w A5w A6w A7w ]; attach variables [ reganb regsanb ] [ A0b A1b A2b A3b A4b A5b A6b A7b ]; @@ -1051,6 +1083,7 @@ with : extGUARD=1 { local source = regdn; mask:4 = 1 << (const8 & 31); ZF = (source & mask) == 0; regdn = source & (~mask); } +@ifndef CPU32 bfOffWd: {f_off:f_wd} is f_off & f_wd { } :bfchg e2l^bfOffWd is opbig=0xea & op67=3 & $(DAT_DIR_CTL_ADDR_MODES); bfOffWd & f_off & f_wd; e2l [ savmod2=savmod1; regtsan=regtfan; ] { logflags(); @@ -1144,6 +1177,7 @@ bfOffWd: {f_off:f_wd} is f_off & f_wd { } getbitfield(tmp, f_off, f_wd); resbitflags(tmp, f_wd-1); } +@endif # CPU32 - no bitfield instructions define pcodeop breakpoint; :bkpt "#"op02 is opbig=0x48 & op67=1 & op5=0 & op34=1 & op02 { breakpoint(); } @@ -1205,7 +1239,8 @@ define pcodeop breakpoint; } @endif # COLDFIRE -# TODO: Determine layout of a module descriptor +@ifndef CPU32 +# TODO: Determine layout of a module descriptor define pcodeop callm; :callm const8,e2l is opbig=6 & op67=3 & $(CTL_ADDR_MODES); const8; e2l [ savmod2=savmod1; regtsan=regtfan; ] { PC = callm(const8, e2l); @@ -1283,6 +1318,7 @@ define pcodeop callm; ZF = 1; NF = 0; } +@endif # CPU32 - no CALLM, CAS, CAS2 :chk.w eaw,reg9dnw is (op=4 & reg9dnw & op68=6 & $(DAT_ALTER_ADDR_MODES))... & eaw { build eaw; @@ -1771,37 +1807,37 @@ r2mfl0: { r2mfl1} is mvm15=0 & r2mfl1 { } # Register to memory, backward direction, via word -r2mbwf: A7w is A7w & mvm0=1 { movemptr = movemptr - 4; *movemptr = A7w; } +r2mbwf: A7w is A7w & mvm0=1 { movemptr = movemptr - 2; *movemptr = A7w; } r2mbwf: is mvm0=0 { } -r2mbwe: r2mbwf" "A6w is A6w & mvm1=1 & r2mbwf { movemptr = movemptr - 4; *movemptr = A6w; } +r2mbwe: r2mbwf" "A6w is A6w & mvm1=1 & r2mbwf { movemptr = movemptr - 2; *movemptr = A6w; } r2mbwe: r2mbwf is mvm1=0 & r2mbwf { } -r2mbwd: r2mbwe" "A5w is A5w & mvm2=1 & r2mbwe { movemptr = movemptr - 4; *movemptr = A5w; } +r2mbwd: r2mbwe" "A5w is A5w & mvm2=1 & r2mbwe { movemptr = movemptr - 2; *movemptr = A5w; } r2mbwd: r2mbwe is mvm2=0 & r2mbwe { } -r2mbwc: r2mbwd" "A4w is A4w & mvm3=1 & r2mbwd { movemptr = movemptr - 4; *movemptr = A4w; } +r2mbwc: r2mbwd" "A4w is A4w & mvm3=1 & r2mbwd { movemptr = movemptr - 2; *movemptr = A4w; } r2mbwc: r2mbwd is mvm3=0 & r2mbwd { } -r2mbwb: r2mbwc" "A3w is A3w & mvm4=1 & r2mbwc { movemptr = movemptr - 4; *movemptr = A3w; } +r2mbwb: r2mbwc" "A3w is A3w & mvm4=1 & r2mbwc { movemptr = movemptr - 2; *movemptr = A3w; } r2mbwb: r2mbwc is mvm4=0 & r2mbwc { } -r2mbwa: r2mbwb" "A2w is A2w & mvm5=1 & r2mbwb { movemptr = movemptr - 4; *movemptr = A2w; } +r2mbwa: r2mbwb" "A2w is A2w & mvm5=1 & r2mbwb { movemptr = movemptr - 2; *movemptr = A2w; } r2mbwa: r2mbwb is mvm5=0 & r2mbwb { } -r2mbw9: r2mbwa" "A1w is A1w & mvm6=1 & r2mbwa { movemptr = movemptr - 4; *movemptr = A1w; } +r2mbw9: r2mbwa" "A1w is A1w & mvm6=1 & r2mbwa { movemptr = movemptr - 2; *movemptr = A1w; } r2mbw9: r2mbwa is mvm6=0 & r2mbwa { } -r2mbw8: r2mbw9" "A0w is A0w & mvm7=1 & r2mbw9 { movemptr = movemptr - 4; *movemptr = A0w; } +r2mbw8: r2mbw9" "A0w is A0w & mvm7=1 & r2mbw9 { movemptr = movemptr - 2; *movemptr = A0w; } r2mbw8: r2mbw9 is mvm7=0 & r2mbw9 { } -r2mbw7: r2mbw8" "D7w is D7w & mvm8=1 & r2mbw8 { movemptr = movemptr - 4; *movemptr = D7w; } +r2mbw7: r2mbw8" "D7w is D7w & mvm8=1 & r2mbw8 { movemptr = movemptr - 2; *movemptr = D7w; } r2mbw7: r2mbw8 is mvm8=0 & r2mbw8 { } -r2mbw6: r2mbw7" "D6w is D6w & mvm9=1 & r2mbw7 { movemptr = movemptr - 4; *movemptr = D6w; } +r2mbw6: r2mbw7" "D6w is D6w & mvm9=1 & r2mbw7 { movemptr = movemptr - 2; *movemptr = D6w; } r2mbw6: r2mbw7 is mvm9=0 & r2mbw7 { } -r2mbw5: r2mbw6" "D5w is D5w & mvm10=1 & r2mbw6 { movemptr = movemptr - 4; *movemptr = D5w; } +r2mbw5: r2mbw6" "D5w is D5w & mvm10=1 & r2mbw6 { movemptr = movemptr - 2; *movemptr = D5w; } r2mbw5: r2mbw6 is mvm10=0 & r2mbw6 { } -r2mbw4: r2mbw5" "D4w is D4w & mvm11=1 & r2mbw5 { movemptr = movemptr - 4; *movemptr = D4w; } +r2mbw4: r2mbw5" "D4w is D4w & mvm11=1 & r2mbw5 { movemptr = movemptr - 2; *movemptr = D4w; } r2mbw4: r2mbw5 is mvm11=0 & r2mbw5 { } -r2mbw3: r2mbw4" "D3w is D3w & mvm12=1 & r2mbw4 { movemptr = movemptr - 4; *movemptr = D3w; } +r2mbw3: r2mbw4" "D3w is D3w & mvm12=1 & r2mbw4 { movemptr = movemptr - 2; *movemptr = D3w; } r2mbw3: r2mbw4 is mvm12=0 & r2mbw4 { } -r2mbw2: r2mbw3" "D2w is D2w & mvm13=1 & r2mbw3 { movemptr = movemptr - 4; *movemptr = D2w; } +r2mbw2: r2mbw3" "D2w is D2w & mvm13=1 & r2mbw3 { movemptr = movemptr - 2; *movemptr = D2w; } r2mbw2: r2mbw3 is mvm13=0 & r2mbw3 { } -r2mbw1: r2mbw2" "D1w is D1w & mvm14=1 & r2mbw2 { movemptr = movemptr - 4; *movemptr = D1w; } +r2mbw1: r2mbw2" "D1w is D1w & mvm14=1 & r2mbw2 { movemptr = movemptr - 2; *movemptr = D1w; } r2mbw1: r2mbw2 is mvm14=0 & r2mbw2 { } -r2mbw0: { r2mbw1" "D0w} is D0w & mvm15=1 & r2mbw1 { movemptr = movemptr - 4; *movemptr = D0w; } +r2mbw0: { r2mbw1" "D0w} is D0w & mvm15=1 & r2mbw1 { movemptr = movemptr - 2; *movemptr = D0w; } r2mbw0: { r2mbw1} is mvm15=0 & r2mbw1 { } @@ -2060,6 +2096,7 @@ macro negResFlags(result) { :ori const8,"CCR" is opbig=0 & op37=7 & op02=4; const8 { packflags(SR); SR=SR|zext(const8); unpackflags(SR); } :ori const16,SR is SR; opbig=0x00 & d8base=0x7c; const16 { packflags(SR); SR=SR|const16; unpackflags(SR); } +@ifndef CPU32 :pack Tyw,Txw,const16 is op=8 & op48=20 & Txw & Tyw & rmbit=0; const16 { local value = (Tyw & 0x0F0F) + const16; Txw = (Txw & 0xFF00) | ((value & 0x0F00) >> 4) | (value & 0x000F); @@ -2070,6 +2107,7 @@ macro negResFlags(result) { local result:2 = ((value & 0x0F00) >> 4) | (value & 0x000F); Txb = result:1; } +@endif # CPU32 - no PACK :pea eaptr is (opbig=0x48 & op67=1 & $(CTL_ADDR_MODES))... & eaptr { value:4 = eaptr; SP = SP-4; *SP = value; } @@ -2227,9 +2265,11 @@ ptestLevel: "#"^mregn is mregn { export *[const]:1 mregn; } :rtd const16 is opbig=0x4e & op37=14 & op02=4; const16 { PC = *SP; SP = SP + 4 + zext(const16); return [PC]; } :rte is d16=0x4e73 { tmp:4 = 0; return [tmp]; } +@ifndef CPU32 define pcodeop rtm; :rtm regdn is opbig=0x06 & op37=24 & regdn { PC = rtm(regdn); return [PC]; } :rtm regan is opbig=0x06 & op37=25 & regan { PC = rtm(regan); return [PC];} +@endif # CPU32 - no RTM :rtr is opbig=0x4e & op37=14 & op02=7 { SR = *SP; SP = SP+2; PC = *SP; SP = SP+4; unpackflags(SR); return [PC]; } @@ -2306,6 +2346,7 @@ define pcodeop stop; :unlk regan is opbig=0x4e & op37=11 & regan { SP = regan; regan = *SP; SP = SP+4; } +@ifndef CPU32 :unpk Tyw,Txw,const16 is op=8 & Txw & op48=24 & Tyw & rmbit=0; const16 { Txw = (Txw & 0xF0F0) | ((((Tyw & 0x00F0) << 4) | (Tyw & 0x000F)) + const16); } @@ -2315,7 +2356,9 @@ define pcodeop stop; source = (((source & 0x00F0) << 4) | (source & 0x000F)) + const16; Txw = (Txw & 0xF0F0) | source; } +@endif # CPU32 - no UNPK +@ifndef CPU32 # Floating Point Instructions # 68040 directly implements Floating Point instructions but requires Coprocessor ID be 001 @@ -2883,6 +2926,7 @@ fsubrnd: "d" is fdst & fopmode=0x6c { tmp:4 = float2float(fdst); fdst = float2f :ftwotox.x fsrc, fdst is op=15 & $(FP_COP) & op68=0 & mode=0 & regan=0; frm=0 & f1515=0 & f1313=0 & fsrc & fdst & fopmode=0x11 { fdst = ftwotox(fsrc); } +@endif # CPU32 - no FPU instructions @ifdef COLDFIRE @@ -3151,4 +3195,97 @@ moveaccreg2: ACC3 is ACC3 & op01=3 { export ACC3; } @endif +@ifdef CPU32 + +tbl_eal: (tbl_regan) is tbl_mode=2 & tbl_regan { export *:4 tbl_regan; } +tbl_eal: -(tbl_regan) is tbl_mode=4 & tbl_regan { tbl_regan = tbl_regan - 4; export *:4 tbl_regan; } +tbl_eal: (d16,tbl_regan) is tbl_mode=5 & tbl_regan; d16 { local tmp = tbl_regan + d16; export *:4 tmp; } +tbl_eal: (extw) is tbl_mode=6 & tbl_regan; extw [ regtfan = tbl_regan; pcmode = 0; ] { build extw; export *:4 extw; } +tbl_eal: (d16,PC) is PC & tbl_mode=7 & tbl_regan=2; d16 { tmp:4 = inst_start + 2 + d16; export *:4 tmp; } +tbl_eal: (extw) is tbl_mode=7 & tbl_regan=3; extw [ pcmode=1; ] { build extw; export *:4 extw; } +tbl_eal: (d16)".w" is tbl_mode=7 & tbl_regan=0; d16 { export *:4 d16; } +tbl_eal: (d32)".l" is tbl_mode=7 & tbl_regan=1; d32 { export *:4 d32; } +tbl_eal: "#"^d32 is tbl_mode=7 & tbl_regan=4; d32 { export *[const]:4 d32; } + +tbl_eaw: (tbl_regan) is tbl_mode=2 & tbl_regan { export *:2 tbl_regan; } +tbl_eaw: -(tbl_regan) is tbl_mode=4 & tbl_regan { tbl_regan = tbl_regan - 2; export *:2 tbl_regan; } +tbl_eaw: (d16,tbl_regan) is tbl_mode=5 & tbl_regan; d16 { local tmp = tbl_regan + d16; export *:2 tmp; } +tbl_eaw: (extw) is tbl_mode=6 & tbl_regan; extw [ pcmode=0; regtfan=tbl_regan; ] { build extw; export *:2 extw; } +tbl_eaw: (d16,PC) is PC & tbl_mode=7 & tbl_regan=2; d16 { tmp:4 = inst_start + 2 + d16; export *:2 tmp; } +tbl_eaw: (extw) is tbl_mode=7 & tbl_regan=3; extw [ pcmode=1; ] { build extw; export *:2 extw; } +tbl_eaw: (d16)".w" is tbl_mode=7 & tbl_regan=0; d16 { export *:2 d16; } +tbl_eaw: (d32)".l" is tbl_mode=7 & tbl_regan=1; d32 { export *:2 d32; } +tbl_eaw: "#"^d16 is tbl_mode=7 & tbl_regan=4; d16 { export *[const]:2 d16; } + +tbl_eab: (tbl_regan) is tbl_mode=2 & tbl_regan { export *:1 tbl_regan; } +tbl_eab: -(tbl_regan) is tbl_mode=4 & tbl_regan { tbl_regan = tbl_regan - 1; export *:1 tbl_regan; } +tbl_eab: (d16,tbl_regan) is tbl_mode=5 & tbl_regan; d16 { local tmp = tbl_regan + d16; export *:1 tmp; } +tbl_eab: (extw) is tbl_mode=6 & tbl_regan; extw [ pcmode=0; regtfan=tbl_regan; ] { build extw; export *:1 extw; } +tbl_eab: (d16,PC) is PC & tbl_mode=7 & tbl_regan=2; d16 { tmp:4 = inst_start + 2 + d16; export *:1 tmp; } +tbl_eab: (extw) is tbl_mode=7 & tbl_regan=3; extw [ pcmode=1; ] { build extw; export *:1 extw; } +tbl_eab: (d16)".w" is tbl_mode=7 & tbl_regan=0; d16 { export *:1 d16; } +tbl_eab: (d32)".l" is tbl_mode=7 & tbl_regan=1; d32 { export *:1 d32; } +tbl_eab: "#"^d8 is tbl_mode=7 & tbl_regan=4; d8 { export *[const]:1 d8; } + +tblsign: "u" is tbl_sign=0 { } +tblsign: "s" is tbl_sign=1 { } + +tbldrsign: "u" is tbl_dr_sign=0 { } +tbldrsign: "s" is tbl_dr_sign=1 { } + +define pcodeop tableLookup; + +# Rounded Table Lookup and Interpolate + +:tbl^tblsign^".b" tbl_eab,tbl_regxdn is (tbl_opbig=0xF8 & tbl_op67=0 & $(TBL_ADDR_MODES) & tbl_size=0 & tblsign & tbl_round=0 & tbl_regxdn) ... & tbl_eab + { tbl_regxdn = tableLookup(tbl_regxdn, tbl_eab); } + +:tbl^tblsign^".w" tbl_eaw,tbl_regxdn is (tbl_opbig=0xF8 & tbl_op67=0 & $(TBL_ADDR_MODES) & tbl_size=1 & tblsign & tbl_round=0 & tbl_regxdn) ... & tbl_eaw + { tbl_regxdn = tableLookup(tbl_regxdn, tbl_eaw); } + +:tbl^tblsign^".l" tbl_eal,tbl_regxdn is (tbl_opbig=0xF8 & tbl_op67=0 & $(TBL_ADDR_MODES) & tbl_size=2 & tblsign & tbl_round=0 & tbl_regxdn) ... & tbl_eal + { tbl_regxdn = tableLookup(tbl_regxdn, tbl_eal); } + +# Unrounded Table Lookup and Interpolate + +:tbl^tblsign^"n.b" tbl_eab,tbl_regxdn is (tbl_opbig=0xF8 & tbl_op67=0 & $(TBL_ADDR_MODES) & tbl_size=0 & tblsign & tbl_round=1 & tbl_regxdn) ... & tbl_eab + { tbl_regxdn = tableLookup(tbl_regxdn, tbl_eab); } + +:tbl^tblsign^"n.w" tbl_eaw,tbl_regxdn is (tbl_opbig=0xF8 & tbl_op67=0 & $(TBL_ADDR_MODES) & tbl_size=1 & tblsign & tbl_round=1 & tbl_regxdn) ... & tbl_eaw + { tbl_regxdn = tableLookup(tbl_regxdn, tbl_eaw); } + +:tbl^tblsign^"n.l" tbl_eal,tbl_regxdn is (tbl_opbig=0xF8 & tbl_op67=0 & $(TBL_ADDR_MODES) & tbl_size=2 & tblsign & tbl_round=1 & tbl_regxdn) ... & tbl_eal + { tbl_regxdn = tableLookup(tbl_regxdn, tbl_eal); } + +define pcodeop interpolate; + +# Rounded Data Register Interpolate + +:tbl^tbldrsign^".b" regdn:tbl_dr_reg,regxdn is opbig=0xF8 & op37=0 & mode=0 & regdn ; tbl_dr_size=0 & tbldrsign & tbl_dr_round=0 & tbl_dr_reg & regxdn + { regxdn = interpolate(regdn, tbl_dr_reg); } + +:tbl^tbldrsign^".w" regdn:tbl_dr_reg,regxdn is opbig=0xF8 & op37=0 & mode=0 & regdn ; tbl_dr_size=1 & tbldrsign & tbl_dr_round=0 & tbl_dr_reg & regxdn + { regxdn = interpolate(regdn, tbl_dr_reg); } + +:tbl^tbldrsign^".l" regdn:tbl_dr_reg,regxdn is opbig=0xF8 & op37=0 & mode=0 & regdn ; tbl_dr_size=2 & tbldrsign & tbl_dr_round=0 & tbl_dr_reg & regxdn + { regxdn = interpolate(regdn, tbl_dr_reg); } + +# Unrounded Data Register Interpolate + +:tbl^tbldrsign^"n.b" regdn:tbl_dr_reg,regxdn is opbig=0xF8 & op37=0 & mode=0 & regdn ; tbl_dr_size=0 & tbldrsign & tbl_dr_round=1 & tbl_dr_reg & regxdn + { regxdn = interpolate(regdn, tbl_dr_reg); } + +:tbl^tbldrsign^"n.w" regdn:tbl_dr_reg,regxdn is opbig=0xF8 & op37=0 & mode=0 & regdn ; tbl_dr_size=1 & tbldrsign & tbl_dr_round=1 & tbl_dr_reg & regxdn + { regxdn = interpolate(regdn, tbl_dr_reg); } + +:tbl^tbldrsign^"n.l" regdn:tbl_dr_reg,regxdn is opbig=0xF8 & op37=0 & mode=0 & regdn ; tbl_dr_size=2 & tbldrsign & tbl_dr_round=1 & tbl_dr_reg & regxdn + { regxdn = interpolate(regdn, tbl_dr_reg); } + +define pcodeop low_power_stop; +:lpstop "#"^d16 is opbig=0xf8 & d8base=0x00; opbig=0x01 & d8base=0xC0; d16 { SR = d16; low_power_stop(); } + +define pcodeop background_mode; +:bgnd is opbig=0x4A & d8base=0xFA { background_mode(); } + +@endif # CPU32 } # end with : extGUARD=1 diff --git a/pypcode/processors/68000/data/languages/CPU32.slaspec b/pypcode/processors/68000/data/languages/CPU32.slaspec new file mode 100644 index 0000000..dc2c54a --- /dev/null +++ b/pypcode/processors/68000/data/languages/CPU32.slaspec @@ -0,0 +1,6 @@ +# Motorola's CPU32 processor + +@define CPU32 "" +@define MC68332 "" + +@include "68000.sinc" diff --git a/pypcode/processors/8051/data/languages/8051.ldefs b/pypcode/processors/8051/data/languages/8051.ldefs index 7c2700f..ef4f11c 100644 --- a/pypcode/processors/8051/data/languages/8051.ldefs +++ b/pypcode/processors/8051/data/languages/8051.ldefs @@ -50,4 +50,16 @@ + + Silicon Labs CIP-51 Microcontroller Family + + diff --git a/pypcode/processors/8051/data/languages/cip-51.pspec b/pypcode/processors/8051/data/languages/cip-51.pspec new file mode 100644 index 0000000..d342b93 --- /dev/null +++ b/pypcode/processors/8051/data/languages/cip-51.pspec @@ -0,0 +1,389 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/pypcode/processors/8051/data/languages/keil-cx51.cspec b/pypcode/processors/8051/data/languages/keil-cx51.cspec index 14efe89..b74d954 100644 --- a/pypcode/processors/8051/data/languages/keil-cx51.cspec +++ b/pypcode/processors/8051/data/languages/keil-cx51.cspec @@ -1,118 +1,77 @@ - - + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + - - - - - - - - - + + + + + - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - \ No newline at end of file + diff --git a/pypcode/processors/AARCH64/data/languages/AARCH64base.sinc b/pypcode/processors/AARCH64/data/languages/AARCH64base.sinc index 2811de5..e7568c5 100644 --- a/pypcode/processors/AARCH64/data/languages/AARCH64base.sinc +++ b/pypcode/processors/AARCH64/data/languages/AARCH64base.sinc @@ -5659,7 +5659,7 @@ is size.ldstr=2 & b_2429=0x8 & b_23=1 & L=0 & b_21=0 & b_15=1 & addrReg & Rt_GPR :stlrb Rt_GPR32, addrReg is size.ldstr=0 & b_2429=0x8 & b_23=1 & L=0 & b_21=0 & b_15=1 & addrReg & Rt_GPR32 { - *addrReg = Rt_GPR32; + *:1 addrReg = Rt_GPR32:1; } # C6.2.312 STLRH page C6-1849 line 108967 MATCH x48808000/mask=xffe08000 @@ -5670,7 +5670,7 @@ is size.ldstr=0 & b_2429=0x8 & b_23=1 & L=0 & b_21=0 & b_15=1 & addrReg & Rt_GPR :stlrh Rt_GPR32, addrReg is size.ldstr=1 & b_2429=0x8 & b_23=1 & L=0 & b_21=0 & b_15=1 & addrReg & Rt_GPR32 { - *addrReg = Rt_GPR32; + *:2 addrReg = Rt_GPR32:2; } # C6.2.313 STLUR page C6-1850 line 109030 MATCH x99000000/mask=xbfe00c00 @@ -6355,7 +6355,7 @@ is sf=0 & op=1 & S=1 & b_2428=0xb & opt=0 & b_2121=1 & ExtendRegShift32 & Rn_GPR # AUNIT --inst xeb000000/mask=xffc00000 --status pass --comment "flags" :subs Rd_GPR64, Rn_GPR64xsp, ExtendRegShift64 -is sf=1 & op=1 & S=1 & b_2428=0xb & opt=0 & ExtendRegShift64 & Rn_GPR64xsp & Rd_GPR64 +is sf=1 & op=1 & S=1 & b_2428=0xb & opt=0 & b_2121=1 & ExtendRegShift64 & Rn_GPR64xsp & Rd_GPR64 { tmp_2:8 = ExtendRegShift64; subflags(Rn_GPR64xsp, tmp_2); diff --git a/pypcode/processors/AARCH64/data/languages/AARCH64instructions.sinc b/pypcode/processors/AARCH64/data/languages/AARCH64instructions.sinc index 03afdd1..ceeb9ef 100644 --- a/pypcode/processors/AARCH64/data/languages/AARCH64instructions.sinc +++ b/pypcode/processors/AARCH64/data/languages/AARCH64instructions.sinc @@ -2190,17 +2190,19 @@ RegShiftVal64: "" is aa_extreg_imm3=0 { export 0:8; } LSL_Sp_Special64: Rm_GPR64, "LSL " is Rm_GPR64 & aa_extreg_imm3 { export Rm_GPR64; } LSL_Sp_Special64: Rm_GPR64 is Rm_GPR64 & aa_extreg_imm3=0 { export Rm_GPR64; } -ExtendReg64: Rm_GPR32, "UXTB " is Rm_GPR32 & b_2121=1 & aa_extreg_option=0 { tmp0:4 = Rm_GPR32; tmp:8 = zext(tmp0:1); export tmp; } -ExtendReg64: Rm_GPR32, "UXTH " is Rm_GPR32 & b_2121=1 & aa_extreg_option=1 { tmp0:4 = Rm_GPR32; tmp:8 = zext(tmp0:2); export tmp; } -ExtendReg64: Rm_GPR32, "UXTW " is Rm_GPR32 & b_2121=1 & aa_extreg_option=2 { tmp:8 = zext(Rm_GPR32); export tmp; } -ExtendReg64: LSL_Sp_Special64 is Rm_GPR64 & b_2121=1 & aa_extreg_option=3 & b_29=1 & b_25=1 & (Rn=0x1f) & LSL_Sp_Special64 { tmp:8 = Rm_GPR64; export tmp; } -ExtendReg64: LSL_Sp_Special64 is Rm_GPR64 & b_2121=1 & aa_extreg_option=3 & b_29=0 & b_25=1 & (Rd=0x1f | Rn=0x1f) & LSL_Sp_Special64 { tmp:8 = Rm_GPR64; export tmp; } -ExtendReg64: Rm_GPR64, "LSL " is Rm_GPR64 & b_2121=1 & aa_extreg_option=3 & b_29 & b_25=0 { tmp:8 = Rm_GPR64; export tmp; } -ExtendReg64: Rm_GPR64, "UXTX " is Rm_GPR64 & b_2121=1 & aa_extreg_option=3 { tmp:8 = Rm_GPR64; export tmp; } -ExtendReg64: Rm_GPR32, "SXTB " is Rm_GPR32 & b_2121=1 & aa_extreg_option=4 { tmp0:4 = Rm_GPR32; tmp:8 = sext(tmp0:1); export tmp; } -ExtendReg64: Rm_GPR32, "SXTH " is Rm_GPR32 & b_2121=1 & aa_extreg_option=5 { tmp0:4 = Rm_GPR32; tmp:8 = sext(tmp0:2); export tmp; } -ExtendReg64: Rm_GPR32, "SXTW " is Rm_GPR32 & b_2121=1 & aa_extreg_option=6 { tmp:8 = sext(Rm_GPR32); export tmp; } -ExtendReg64: Rm_GPR64, "SXTX " is Rm_GPR64 & b_2121=1 & aa_extreg_option=7 { tmp:8 = Rm_GPR64; export tmp; } +ExtendReg64: Rm_GPR32, "UXTB " is Rm_GPR32 & aa_extreg_option=0 { tmp0:4 = Rm_GPR32; tmp:8 = zext(tmp0:1); export tmp; } +ExtendReg64: Rm_GPR32, "UXTH " is Rm_GPR32 & aa_extreg_option=1 { tmp0:4 = Rm_GPR32; tmp:8 = zext(tmp0:2); export tmp; } +ExtendReg64: Rm_GPR32, "UXTW " is Rm_GPR32 & aa_extreg_option=2 { tmp:8 = zext(Rm_GPR32); export tmp; } +ExtendReg64: LSL_Sp_Special64 is Rm_GPR64 & aa_extreg_option=3 & b_29=1 & b_25=1 & (Rn=0x1f) & LSL_Sp_Special64 { tmp:8 = Rm_GPR64; export tmp; } +ExtendReg64: LSL_Sp_Special64 is Rm_GPR64 & aa_extreg_option=3 & b_29=0 & b_25=1 & (Rd=0x1f | Rn=0x1f) & LSL_Sp_Special64 { tmp:8 = Rm_GPR64; export tmp; } +# These two are only used by load/store (register) instructions +ExtendReg64: Rm_GPR64, "LSL " is Rm_GPR64 & b_1212=1 & aa_extreg_option=3 & b_25=0 { tmp:8 = Rm_GPR64; export tmp; } +ExtendReg64: Rm_GPR64 is Rm_GPR64 & b_1212=0 & aa_extreg_option=3 & b_25=0 { tmp:8 = Rm_GPR64; export tmp; } +ExtendReg64: Rm_GPR64, "UXTX " is Rm_GPR64 & aa_extreg_option=3 { tmp:8 = Rm_GPR64; export tmp; } +ExtendReg64: Rm_GPR32, "SXTB " is Rm_GPR32 & aa_extreg_option=4 { tmp0:4 = Rm_GPR32; tmp:8 = sext(tmp0:1); export tmp; } +ExtendReg64: Rm_GPR32, "SXTH " is Rm_GPR32 & aa_extreg_option=5 { tmp0:4 = Rm_GPR32; tmp:8 = sext(tmp0:2); export tmp; } +ExtendReg64: Rm_GPR32, "SXTW " is Rm_GPR32 & aa_extreg_option=6 { tmp:8 = sext(Rm_GPR32); export tmp; } +ExtendReg64: Rm_GPR64, "SXTX " is Rm_GPR64 & aa_extreg_option=7 { tmp:8 = Rm_GPR64; export tmp; } ExtendRegShift64: ExtendReg64^RegShiftVal64 is aa_extreg_shift = 0 & aa_extreg_option & aa_extreg_imm3 & ExtendReg64 & RegShiftVal64 diff --git a/pypcode/processors/AARCH64/data/languages/AARCH64neon.sinc b/pypcode/processors/AARCH64/data/languages/AARCH64neon.sinc index 4ff3386..9da59d1 100644 --- a/pypcode/processors/AARCH64/data/languages/AARCH64neon.sinc +++ b/pypcode/processors/AARCH64/data/languages/AARCH64neon.sinc @@ -734,7 +734,7 @@ is b_3131=0 & q=1 & u=0 & b_2428=0xe & advSIMD3.size=0 & b_1721=0x18 & b_1216=0x Rd_FPR8 = Rd_FPR8 + Rn_VPR128.16B[104,8]; Rd_FPR8 = Rd_FPR8 + Rn_VPR128.16B[112,8]; Rd_FPR8 = Rd_FPR8 + Rn_VPR128.16B[120,8]; - zext_zq(Zd); # zero upper 31 bytes of Zd + zext_zb(Zd); # zero upper bytes of Zd } # C7.2.6 ADDV page C7-2027 line 118452 MATCH x0e31b800/mask=xbf3ffc00 @@ -753,7 +753,7 @@ is b_3131=0 & q=0 & u=0 & b_2428=0xe & advSIMD3.size=0 & b_1721=0x18 & b_1216=0x Rd_FPR8 = Rd_FPR8 + Rn_VPR64.8B[40,8]; Rd_FPR8 = Rd_FPR8 + Rn_VPR64.8B[48,8]; Rd_FPR8 = Rd_FPR8 + Rn_VPR64.8B[56,8]; - zext_zq(Zd); # zero upper 31 bytes of Zd + zext_zb(Zd); # zero upper bytes of Zd } # C7.2.6 ADDV page C7-2027 line 118452 MATCH x0e31b800/mask=xbf3ffc00 @@ -7275,6 +7275,7 @@ is b_1031=0b0001111001111110000000 & Rd_GPR32 & Rn_FPR64 & Rd_GPR64 is m=0 & b_3030=0 & s=0 & b_2428=0x1f & ftype=1 & b_21=0 & Rm_FPR64 & b_15=0 & Ra_FPR64 & Rn_FPR64 & Rd_FPR64 & Zd { Rd_FPR64 = Ra_FPR64 f+ (Rm_FPR64 f* Rn_FPR64); #NEON_fmadd(Rn_FPR64, Rm_FPR64, Ra_FPR64); + zext_zd(Zd); # zero upper bytes of Zd } # C7.2.100 FMADD page C7-2246 line 131323 MATCH x1f000000/mask=xff208000 @@ -7286,6 +7287,7 @@ is m=0 & b_3030=0 & s=0 & b_2428=0x1f & ftype=1 & b_21=0 & Rm_FPR64 & b_15=0 & R is m=0 & b_3030=0 & s=0 & b_2428=0x1f & ftype=0 & b_21=0 & Rm_FPR32 & b_15=0 & Ra_FPR32 & Rn_FPR32 & Rd_FPR32 & Zd { Rd_FPR32 = Ra_FPR32 f+ (Rm_FPR32 f* Rn_FPR32); #NEON_fmadd(Rn_FPR32, Rm_FPR32, Ra_FPR32); + zext_zs(Zd); # zero upper bytes of Zd } # C7.2.100 FMADD page C7-2246 line 131323 MATCH x1f000000/mask=xff208000 @@ -7297,6 +7299,7 @@ is m=0 & b_3030=0 & s=0 & b_2428=0x1f & ftype=0 & b_21=0 & Rm_FPR32 & b_15=0 & R is m=0 & b_3030=0 & s=0 & b_2428=0x1f & ftype=3 & b_21=0 & Rm_FPR16 & b_15=0 & Ra_FPR16 & Rn_FPR16 & Rd_FPR16 & Zd { Rd_FPR16 = Ra_FPR16 f+ (Rm_FPR16 f* Rn_FPR16); #NEON_fmadd(Rn_FPR16, Rm_FPR16, Ra_FPR16); + zext_zh(Zd); # zero upper bytes of Zd } # C7.2.101 FMAX (vector) page C7-2248 line 131451 MATCH x0e20f400/mask=xbfa0fc00 @@ -9562,6 +9565,7 @@ is m=0 & b_3030=0 & s=0 & b_2428=0x1e & ftype=3 & b_2121=1 & Imm8_fmov16_operand is m=0 & b_3030=0 & s=0 & b_2428=0x1f & ftype=1 & b_21=0 & Rm_FPR64 & b_15=1 & Ra_FPR64 & Rn_FPR64 & Rd_FPR64 & Zd { Rd_FPR64 = Ra_FPR64 f- (Rm_FPR64 f* Rn_FPR64); + zext_zd(Zd); # zero upper bytes of Zd } @@ -9574,6 +9578,7 @@ is m=0 & b_3030=0 & s=0 & b_2428=0x1f & ftype=1 & b_21=0 & Rm_FPR64 & b_15=1 & R is m=0 & b_3030=0 & s=0 & b_2428=0x1f & ftype=0 & b_21=0 & Rm_FPR32 & b_15=1 & Ra_FPR32 & Rn_FPR32 & Rd_FPR32 & Zd { Rd_FPR32 = Ra_FPR32 f- (Rm_FPR32 f* Rn_FPR32); + zext_zs(Zd); # zero upper bytes of Zd } # C7.2.133 FMSUB page C7-2318 line 135582 MATCH x1f008000/mask=xff208000 @@ -9585,6 +9590,7 @@ is m=0 & b_3030=0 & s=0 & b_2428=0x1f & ftype=0 & b_21=0 & Rm_FPR32 & b_15=1 & R is m=0 & b_3030=0 & s=0 & b_2428=0x1f & ftype=3 & b_21=0 & Rm_FPR16 & b_15=1 & Ra_FPR16 & Rn_FPR16 & Rd_FPR16 & Zd { Rd_FPR16 = Ra_FPR16 f- (Rm_FPR16 f* Rn_FPR16); + zext_zh(Zd); # zero upper bytes of Zd } # C7.2.134 FMUL (by element) page C7-2320 line 135711 MATCH x5f009000/mask=xffc0f400 @@ -17093,6 +17099,7 @@ is b_3131=0 & q=1 & u=0 & b_2428=0xe & advSIMD3.size=1 & b_2121=1 & Rm_VPR128.8H is b_3131=0 & q=1 & u=0 & b_2428=0xe & advSIMD3.size=0 & b_1721=0x18 & b_1216=0xa & b_1011=2 & Rn_VPR128.16B & Rd_FPR8 & Zd { Rd_FPR8 = NEON_smaxv(Rn_VPR128.16B, 1:1); + zext_zb(Zd); # zero upper bytes of Zd } # C7.2.270 SMAXV page C7-2616 line 152715 MATCH x0e30a800/mask=xbf3ffc00 @@ -17104,6 +17111,7 @@ is b_3131=0 & q=1 & u=0 & b_2428=0xe & advSIMD3.size=0 & b_1721=0x18 & b_1216=0x is b_3131=0 & q=0 & u=0 & b_2428=0xe & advSIMD3.size=0 & b_1721=0x18 & b_1216=0xa & b_1011=2 & Rn_VPR64.8B & Rd_FPR8 & Zd { Rd_FPR8 = NEON_smaxv(Rn_VPR64.8B, 1:1); + zext_zb(Zd); # zero upper bytes of Zd } # C7.2.270 SMAXV page C7-2616 line 152715 MATCH x0e30a800/mask=xbf3ffc00 @@ -17115,6 +17123,7 @@ is b_3131=0 & q=0 & u=0 & b_2428=0xe & advSIMD3.size=0 & b_1721=0x18 & b_1216=0x is b_3131=0 & q=0 & u=0 & b_2428=0xe & advSIMD3.size=1 & b_1721=0x18 & b_1216=0xa & b_1011=2 & Rn_VPR64.4H & Rd_FPR16 & Zd { Rd_FPR16 = NEON_smaxv(Rn_VPR64.4H, 2:1); + zext_zh(Zd); # zero upper bytes of Zd } # C7.2.270 SMAXV page C7-2616 line 152715 MATCH x0e30a800/mask=xbf3ffc00 @@ -17126,6 +17135,7 @@ is b_3131=0 & q=0 & u=0 & b_2428=0xe & advSIMD3.size=1 & b_1721=0x18 & b_1216=0x is b_3131=0 & q=1 & u=0 & b_2428=0xe & advSIMD3.size=1 & b_1721=0x18 & b_1216=0xa & b_1011=2 & Rn_VPR128.8H & Rd_FPR16 & Zd { Rd_FPR16 = NEON_smaxv(Rn_VPR128.8H, 2:1); + zext_zh(Zd); # zero upper bytes of Zd } # C7.2.270 SMAXV page C7-2616 line 152715 MATCH x0e30a800/mask=xbf3ffc00 @@ -17137,6 +17147,7 @@ is b_3131=0 & q=1 & u=0 & b_2428=0xe & advSIMD3.size=1 & b_1721=0x18 & b_1216=0x is b_3131=0 & q=1 & u=0 & b_2428=0xe & advSIMD3.size=2 & b_1721=0x18 & b_1216=0xa & b_1011=2 & Rn_VPR128.4S & Rd_FPR32 & Zd { Rd_FPR32 = NEON_smaxv(Rn_VPR128.4S, 4:1); + zext_zs(Zd); # zero upper bytes of Zd } # C7.2.271 SMIN page C7-2618 line 152818 MATCH x0e206c00/mask=xbf20fc00 @@ -17280,6 +17291,7 @@ is b_3131=0 & q=1 & u=0 & b_2428=0xe & advSIMD3.size=1 & b_2121=1 & Rm_VPR128.8H is b_3131=0 & q=1 & u=0 & b_2428=0xe & advSIMD3.size=0 & b_1721=0x18 & b_1216=0x1a & b_1011=2 & Rn_VPR128.16B & Rd_FPR8 & Zd { Rd_FPR8 = NEON_sminv(Rn_VPR128.16B, 1:1); + zext_zb(Zd); # zero upper bytes of Zd } # C7.2.273 SMINV page C7-2622 line 153024 MATCH x0e31a800/mask=xbf3ffc00 @@ -17291,6 +17303,7 @@ is b_3131=0 & q=1 & u=0 & b_2428=0xe & advSIMD3.size=0 & b_1721=0x18 & b_1216=0x is b_3131=0 & q=0 & u=0 & b_2428=0xe & advSIMD3.size=0 & b_1721=0x18 & b_1216=0x1a & b_1011=2 & Rn_VPR64.8B & Rd_FPR8 & Zd { Rd_FPR8 = NEON_sminv(Rn_VPR64.8B, 1:1); + zext_zb(Zd); # zero upper bytes of Zd } # C7.2.273 SMINV page C7-2622 line 153024 MATCH x0e31a800/mask=xbf3ffc00 @@ -17302,6 +17315,7 @@ is b_3131=0 & q=0 & u=0 & b_2428=0xe & advSIMD3.size=0 & b_1721=0x18 & b_1216=0x is b_3131=0 & q=0 & u=0 & b_2428=0xe & advSIMD3.size=1 & b_1721=0x18 & b_1216=0x1a & b_1011=2 & Rn_VPR64.4H & Rd_FPR16 & Zd { Rd_FPR16 = NEON_sminv(Rn_VPR64.4H, 2:1); + zext_zh(Zd); # zero upper bytes of Zd } # C7.2.273 SMINV page C7-2622 line 153024 MATCH x0e31a800/mask=xbf3ffc00 @@ -17313,6 +17327,7 @@ is b_3131=0 & q=0 & u=0 & b_2428=0xe & advSIMD3.size=1 & b_1721=0x18 & b_1216=0x is b_3131=0 & q=1 & u=0 & b_2428=0xe & advSIMD3.size=1 & b_1721=0x18 & b_1216=0x1a & b_1011=2 & Rn_VPR128.8H & Rd_FPR16 & Zd { Rd_FPR16 = NEON_sminv(Rn_VPR128.8H, 2:1); + zext_zh(Zd); # zero upper bytes of Zd } # C7.2.273 SMINV page C7-2622 line 153024 MATCH x0e31a800/mask=xbf3ffc00 @@ -17324,6 +17339,7 @@ is b_3131=0 & q=1 & u=0 & b_2428=0xe & advSIMD3.size=1 & b_1721=0x18 & b_1216=0x is b_3131=0 & q=1 & u=0 & b_2428=0xe & advSIMD3.size=2 & b_1721=0x18 & b_1216=0x1a & b_1011=2 & Rn_VPR128.4S & Rd_FPR32 & Zd { Rd_FPR32 = NEON_sminv(Rn_VPR128.4S, 4:1); + zext_zs(Zd); # zero upper bytes of Zd } # C7.2.274 SMLAL, SMLAL2 (by element) page C7-2624 line 153127 MATCH x0f002000/mask=xbf00f400 @@ -26673,6 +26689,7 @@ is b_3131=0 & q=1 & u=1 & b_2428=0xe & advSIMD3.size=1 & b_2121=1 & Rm_VPR128.8H is b_3131=0 & q=1 & u=1 & b_2428=0xe & advSIMD3.size=0 & b_1721=0x18 & b_1216=0xa & b_1011=2 & Rn_VPR128.16B & Rd_FPR8 & Zd { Rd_FPR8 = NEON_umaxv(Rn_VPR128.16B, 1:1); + zext_zb(Zd); # zero upper bytes of Zd } # C7.2.362 UMAXV page C7-2849 line 166369 MATCH x2e30a800/mask=xbf3ffc00 @@ -26684,6 +26701,7 @@ is b_3131=0 & q=1 & u=1 & b_2428=0xe & advSIMD3.size=0 & b_1721=0x18 & b_1216=0x is b_3131=0 & q=0 & u=1 & b_2428=0xe & advSIMD3.size=0 & b_1721=0x18 & b_1216=0xa & b_1011=2 & Rn_VPR64.8B & Rd_FPR8 & Zd { Rd_FPR8 = NEON_umaxv(Rn_VPR64.8B, 1:1); + zext_zb(Zd); # zero upper bytes of Zd } # C7.2.362 UMAXV page C7-2849 line 166369 MATCH x2e30a800/mask=xbf3ffc00 @@ -26695,6 +26713,7 @@ is b_3131=0 & q=0 & u=1 & b_2428=0xe & advSIMD3.size=0 & b_1721=0x18 & b_1216=0x is b_3131=0 & q=0 & u=1 & b_2428=0xe & advSIMD3.size=1 & b_1721=0x18 & b_1216=0xa & b_1011=2 & Rn_VPR64.4H & Rd_FPR16 & Zd { Rd_FPR16 = NEON_umaxv(Rn_VPR64.4H, 2:1); + zext_zh(Zd); # zero upper bytes of Zd } # C7.2.362 UMAXV page C7-2849 line 166369 MATCH x2e30a800/mask=xbf3ffc00 @@ -26706,6 +26725,7 @@ is b_3131=0 & q=0 & u=1 & b_2428=0xe & advSIMD3.size=1 & b_1721=0x18 & b_1216=0x is b_3131=0 & q=1 & u=1 & b_2428=0xe & advSIMD3.size=1 & b_1721=0x18 & b_1216=0xa & b_1011=2 & Rn_VPR128.8H & Rd_FPR16 & Zd { Rd_FPR16 = NEON_umaxv(Rn_VPR128.8H, 2:1); + zext_zh(Zd); # zero upper bytes of Zd } # C7.2.362 UMAXV page C7-2849 line 166369 MATCH x2e30a800/mask=xbf3ffc00 @@ -26717,6 +26737,7 @@ is b_3131=0 & q=1 & u=1 & b_2428=0xe & advSIMD3.size=1 & b_1721=0x18 & b_1216=0x is b_3131=0 & q=1 & u=1 & b_2428=0xe & advSIMD3.size=2 & b_1721=0x18 & b_1216=0xa & b_1011=2 & Rn_VPR128.4S & Rd_FPR32 & Zd { Rd_FPR32 = NEON_umaxv(Rn_VPR128.4S, 4:1); + zext_zs(Zd); # zero upper bytes of Zd } # C7.2.363 UMIN page C7-2851 line 166472 MATCH x2e206c00/mask=xbf20fc00 @@ -26860,6 +26881,7 @@ is b_3131=0 & q=1 & u=1 & b_2428=0xe & advSIMD3.size=1 & b_2121=1 & Rm_VPR128.8H is b_3131=0 & q=1 & u=1 & b_2428=0xe & advSIMD3.size=0 & b_1721=0x18 & b_1216=0x1a & b_1011=2 & Rn_VPR128.16B & Rd_FPR8 & Zd { Rd_FPR8 = NEON_uminv(Rn_VPR128.16B, 1:1); + zext_zb(Zd); # zero upper bytes of Zd } # C7.2.365 UMINV page C7-2855 line 166678 MATCH x2e31a800/mask=xbf3ffc00 @@ -26871,6 +26893,7 @@ is b_3131=0 & q=1 & u=1 & b_2428=0xe & advSIMD3.size=0 & b_1721=0x18 & b_1216=0x is b_3131=0 & q=0 & u=1 & b_2428=0xe & advSIMD3.size=0 & b_1721=0x18 & b_1216=0x1a & b_1011=2 & Rn_VPR64.8B & Rd_FPR8 & Zd { Rd_FPR8 = NEON_uminv(Rn_VPR64.8B, 1:1); + zext_zb(Zd); # zero upper bytes of Zd } # C7.2.365 UMINV page C7-2855 line 166678 MATCH x2e31a800/mask=xbf3ffc00 @@ -26882,6 +26905,7 @@ is b_3131=0 & q=0 & u=1 & b_2428=0xe & advSIMD3.size=0 & b_1721=0x18 & b_1216=0x is b_3131=0 & q=0 & u=1 & b_2428=0xe & advSIMD3.size=1 & b_1721=0x18 & b_1216=0x1a & b_1011=2 & Rn_VPR64.4H & Rd_FPR16 & Zd { Rd_FPR16 = NEON_uminv(Rn_VPR64.4H, 2:1); + zext_zh(Zd); # zero upper bytes of Zd } # C7.2.365 UMINV page C7-2855 line 166678 MATCH x2e31a800/mask=xbf3ffc00 @@ -26893,6 +26917,7 @@ is b_3131=0 & q=0 & u=1 & b_2428=0xe & advSIMD3.size=1 & b_1721=0x18 & b_1216=0x is b_3131=0 & q=1 & u=1 & b_2428=0xe & advSIMD3.size=1 & b_1721=0x18 & b_1216=0x1a & b_1011=2 & Rn_VPR128.8H & Rd_FPR16 & Zd { Rd_FPR16 = NEON_uminv(Rn_VPR128.8H, 2:1); + zext_zh(Zd); # zero upper bytes of Zd } # C7.2.365 UMINV page C7-2855 line 166678 MATCH x2e31a800/mask=xbf3ffc00 @@ -26904,6 +26929,7 @@ is b_3131=0 & q=1 & u=1 & b_2428=0xe & advSIMD3.size=1 & b_1721=0x18 & b_1216=0x is b_3131=0 & q=1 & u=1 & b_2428=0xe & advSIMD3.size=2 & b_1721=0x18 & b_1216=0x1a & b_1011=2 & Rn_VPR128.4S & Rd_FPR32 & Zd { Rd_FPR32 = NEON_uminv(Rn_VPR128.4S, 4:1); + zext_zs(Zd); # zero upper bytes of Zd } # C7.2.366 UMLAL, UMLAL2 (by element) page C7-2857 line 166781 MATCH x2f002000/mask=xbf00f400 diff --git a/pypcode/processors/ARM/data/languages/ARMTHUMBinstructions.sinc b/pypcode/processors/ARM/data/languages/ARMTHUMBinstructions.sinc index 1f6b9f8..26a34b4 100644 --- a/pypcode/processors/ARM/data/languages/ARMTHUMBinstructions.sinc +++ b/pypcode/processors/ARM/data/languages/ARMTHUMBinstructions.sinc @@ -2775,7 +2775,7 @@ mrsipsr: "i" is thc0000=1 & Rd0811 { b:1 = isCurrentModePrivileged(); if (!b) goto ; ipsr:4 = getCurrentExceptionNumber(); - Rd0811 = Rd0811 | (ipsr & 0x1f); + Rd0811 = Rd0811 | (ipsr & 0x1ff); } mrsipsr: is thc0000=0 { } @@ -2931,12 +2931,12 @@ define pcodeop getProcessStackPointerLimit; @if defined(VERSION_7M) -msripsr: "i" is thc0000=1 { } -msripsr: is thc0000=0 { } -msrepsr: "e" is thc0101=1 { } -msrepsr: is thc0101=0 { } -msrapsr: is thc0202=1 { } -msrapsr: "a" is thc0202=0 & Rn0003 { +msripsr: "i" is Rn0003; thc0000=1 { } +msripsr: is Rn0003; thc0000=0 { } +msrepsr: "e" is Rn0003; thc0101=1 { } +msrepsr: is Rn0003; thc0101=0 { } +msrapsr: is Rn0003; thc0202=1 { } +msrapsr: "a" is Rn0003; thc0202=0 { cpsr = cpsr | (Rn0003 & 0xf8000000); writeAPSR_nzcvq(cpsr); } @@ -2944,11 +2944,11 @@ msrapsr: "a" is thc0202=0 & Rn0003 { msrpsr: msripsr^msrepsr^msrapsr^"psr" is msripsr & msrepsr & msrapsr { build msrapsr; } -msrpsr: "xpsr" is sysm02=3 & msrapsr { +msrpsr: "xpsr" is (Rn0003 ; sysm02=3) & msrapsr { build msrapsr; } -:msr^ItCond msrpsr,Rn0003 is TMode=1 & ItCond & op4=0xf38 & Rn0003; op12=0x8 & th_psrmask=8 & sysm37=0 & msrpsr +:msr^ItCond msrpsr,Rn0003 is TMode=1 & ItCond & (op4=0xf38 & Rn0003; op12=0x8 & th_psrmask=8 & sysm37=0) & msrpsr { build ItCond; build msrpsr; @@ -4358,7 +4358,7 @@ thumbEndianNess: "BE" is op0=0xb658 { export 1:1; } build ItCond; } -:sev^ItCond^".w" is TMode=1 & ItCond & op0=0xf3af; op0=8004 +:sev^ItCond^".w" is TMode=1 & ItCond & op0=0xf3af; op0=0x8004 { build ItCond; } diff --git a/pypcode/processors/HCS12/data/languages/HCS_HC12.sinc b/pypcode/processors/HCS12/data/languages/HCS_HC12.sinc index 26ff2c0..646d9d4 100644 --- a/pypcode/processors/HCS12/data/languages/HCS_HC12.sinc +++ b/pypcode/processors/HCS12/data/languages/HCS_HC12.sinc @@ -271,7 +271,7 @@ macro setHCSphysPage(addr) { (zext(isPpage) * (0x400000 | ((zext(PPAGE) << 14 ) ^ 0x8000))) + (zext(isPpage_FF) * (0x400000 | ((0x3FC000) ^ 0xC000))) ; } -@elif defined(HCS12) && SIZE=="3" +@elif defined(HCS12) && SIZE=="3" macro setHCSphysPage(addr) { local a3:3 = zext(addr); @@ -1961,11 +1961,9 @@ with : XGATE=0 { } # branch never is a two-byte nop -SkipNextInstr: dest is epsilon [ dest = inst_next + 1; ] { export *[RAM]:1 dest; } -:BRN SkipNextInstr is Prefix18=0 & op8=0x21 & SkipNextInstr +:BRN rel8 is Prefix18=0 & op8=0x21; rel8 { - goto SkipNextInstr; } :BRSET opr8a_8, msk8, rel8 is Prefix18=0 & op8=0x4E; opr8a_8; msk8; rel8 diff --git a/pypcode/processors/Hexagon/data/languages/hexagon.ldefs b/pypcode/processors/Hexagon/data/languages/hexagon.ldefs index 0c21cea..c6bcc4f 100755 --- a/pypcode/processors/Hexagon/data/languages/hexagon.ldefs +++ b/pypcode/processors/Hexagon/data/languages/hexagon.ldefs @@ -5,7 +5,7 @@ endian="little" size="32" variant="default" - version="2.4" + version="2.5" slafile="hexagon.sla" processorspec="hexagon.pspec" id="Hexagon:LE:32:default"> diff --git a/pypcode/processors/Hexagon/data/languages/hexagon.sinc b/pypcode/processors/Hexagon/data/languages/hexagon.sinc index de29be0..525f324 100755 --- a/pypcode/processors/Hexagon/data/languages/hexagon.sinc +++ b/pypcode/processors/Hexagon/data/languages/hexagon.sinc @@ -1,4 +1,4 @@ -# Qualcomm Hexagon (V73) General Instruction Set +# Qualcomm Hexagon (V60-V81) General Instruction Set # # Custom pcode-op @@ -327,6 +327,7 @@ Uimm1_05: "#"^i5 is i5 { export *[const]:1 i5; } Uimm8_0408_shift3: "#"^val is i0408 [ val = i0408 << 3; ] { export *[const]:1 val; } Uimm8_0409_shift2: "#"^val is i0409 [ val = i0409 << 2; ] { export *[const]:1 val; } Uimm16_0010_shift3: "#"^val is i0010 [ val = i0010 << 3; ] { export *[const]:2 val; } +Uimm8_2024_shift3: "#"^val is i2024 [ val = i2024 << 3; ] { export *[const]:1 val; } Uimm8_2025_shift2: "#"^val is i2025 [ val = i2025 << 2; ] { export *[const]:1 val; } Uimm32_2122_13_0507_shift2: "#"^val is i2122 & i13 & i0507 [ val = ((i2122 << 4) | (i13 << 3) | i0507) << 2; ] { export *[const]:4 val; } @@ -454,6 +455,14 @@ Taken12: ":nt" is op12=0 { } NotTaken01: ":nt" is op1=1 { } NotTaken01: is op1=0 { } +# Non-temporal memory hint (decoration only). + +MemNt13: is op13=0 { } +MemNt13: ":nt" is op13=1 { } + +StNt24: is op24=1 { } +StNt24: ":nt" is op24=0 { } + # Predicate Register Condition for jump/call (least significant bit only) FlowCondUU: ".if("pu0809name")" is op21=0 & pu0809name & pu0809 { condition:1 = (pu0809 & 1); @@ -469,57 +478,122 @@ FlowCondUU: ".if(!"pu0809name")" is op21=1 & pu0809name & pu0809 { # .new Predicate Register Condition for jump/call (least significant bit only) FlowCondNewUU: ".if("pu0809name".new)" is op21=0 & pu0809name & pu0809 { <> - ConditionReg = (pu0809 & 1); # predicate will already be comitted + ConditionReg = (pu0809 & 1); # predicate will already be committed } FlowCondNewUU: ".if(!"pu0809name".new)" is op21=1 & pu0809name & pu0809 { <> - ConditionReg = !(pu0809 & 1); # predicate will already be comitted + ConditionReg = !(pu0809 & 1); # predicate will already be committed } -# Predicate Register Condition for dealloc_return (least significant bit only) +# Predicate Register Condition for deallocframe / dealloc_return (least significant bit only) +# Expected to use DeallocFrameRddRsRawCond which has both <> and <> FlowCond0809_N11_S13: ".if("pu0809name")" is op13=0 & op11=0 & pu0809 & pu0809name { condition:1 = (pu0809 & 1); + <> + ConditionReg = condition; <> ConditionReg = condition; } FlowCond0809_N11_S13: ".if(!"pu0809name")" is op13=1 & op11=0 & pu0809 & pu0809name { condition:1 = !(pu0809 & 1); + <> + ConditionReg = condition; <> ConditionReg = condition; } FlowCond0809_N11_S13: ".if("pu0809name".new)" is op13=0 & op11=1 & pu0809 & pu0809name { + condition:1 = 0; + <> + condition = (pu0809 & 1); # predicate will already be committed + ConditionReg = condition; <> - ConditionReg = (pu0809 & 1); # predicate will already be comitted + ConditionReg = condition; } FlowCond0809_N11_S13: ".if(!"pu0809name".new)" is op13=1 & op11=1 & pu0809 & pu0809name { + condition:1 = 0; + <> + condition = !(pu0809 & 1); # predicate will already be committed + ConditionReg = condition; <> - ConditionReg = !(pu0809 & 1); # predicate will already be comitted + ConditionReg = condition; } -# Predicate Register Condition for Right Packed EE jumpr (least significant bit only, includes .new handling) +# Predicate Register Condition for Right Packed EE jumpr / dealloc_return (least significant bit +# only, includes .new handling). +# Expected to use DeallocFrameRawCond which has both <> and <> FlowP0Cond_N01_S00: ".if(P0)" is op0=0 & op1=0 { condition:1 = (P0 & 1); + <> + ConditionReg = condition; <> ConditionReg = condition; } FlowP0Cond_N01_S00: ".if(!P0)" is op0=1 & op1=0 { condition:1 = !(P0 & 1); + <> + ConditionReg = condition; <> ConditionReg = condition; } FlowP0Cond_N01_S00: ".if(P0.new)" is op0=0 & op1=1 { + condition:1 = 0; + <> + condition = (P0 & 1); # P0 will already be committed + ConditionReg = condition; <> - ConditionReg = (P0 & 1); # P0 will already be comitted + ConditionReg = condition; } FlowP0Cond_N01_S00: ".if(!P0.new)" is op0=1 & op1=1 { + condition:1 = 0; + <> + condition = !(P0 & 1); # P0 will already be committed + ConditionReg = condition; <> - ConditionReg = !(P0 & 1); # P0 will already be comitted + ConditionReg = condition; } + +# Predicate Register Condition for Left Packed EE dealloc_return (least significant bit only, +# includes .new handling). Left-slot counterpart of FlowP0Cond_N01_S00: the sense and .new +# selectors sit at bits 16 and 17, and op1617 encodes both, so a separate NotTaken subtable is +# not needed -- the ":nt" suffix is folded into the display text of the .new alternatives. +# Expected to use DeallocFrameRawCond which has both <> and <> + +FlowP0Cond_N17_S16: ".if(P0)" is op1617=0 { + condition:1 = (P0 & 1); + <> + ConditionReg = condition; + <> + ConditionReg = condition; +} +FlowP0Cond_N17_S16: ".if(!P0)" is op1617=1 { + condition:1 = !(P0 & 1); + <> + ConditionReg = condition; + <> + ConditionReg = condition; +} +FlowP0Cond_N17_S16: ".if(P0.new):nt" is op1617=2 { + condition:1 = 0; + <> + condition = (P0 & 1); # P0 will already be committed + ConditionReg = condition; + <> + ConditionReg = condition; +} +FlowP0Cond_N17_S16: ".if(!P0.new):nt" is op1617=3 { + condition:1 = 0; + <> + condition = !(P0 & 1); # P0 will already be committed + ConditionReg = condition; + <> + ConditionReg = condition; +} + # Predicate Register Condition for Right Packed EE conditional ops (least significant bit only, includes .new handling) P0Cond_N05_S04: ".if(P0)" is op4=0 & op5=1 { @@ -977,8 +1051,6 @@ AddrRsRelShiftC3: "("^rs5^"+"^rt5^")" is rs5 & rt5 & op13=0 & op7=0 { export tmp; } AddrRsRelShiftC3: "("^rs5^"+"^rt5^"<<"^Uimm2_13_07^")" is rs5 & rt5 & Uimm2_13_07 { - # TODO: verify order of operation - # TODO: Is there an alignment shift? tmp:4 = rs5 + (rt5 << Uimm2_13_07); export tmp; } @@ -1070,7 +1142,6 @@ LdMemRsRelC9w: LdAddrRsRelC9 is LdAddrRsRelC9 { export *[ram]:4 LdAddrRsRelC9; } # Class-9 Load Memory: Rf=#U6x LdAddrRsAssignxC9: "("^rf5^"="^Uimm32_0811_0506x^")" is rf5 & rf5_ & Uimm32_0811_0506x { - # TODO: Need to verify behavior !! rf5_ = Uimm32_0811_0506x; export Uimm32_0811_0506x; <> @@ -1096,8 +1167,6 @@ LdAddrRsRelShiftxC9: "("^rs5^"+"^Uimm32_0811_0506x^")" is rs5 & op13=0 & op7=0 & export tmp; } LdAddrRsRelShiftxC9: "("^rs5^"<<"^Uimm2_13_07^"+"^Uimm32_0811_0506x^")" is rs5 & Uimm2_13_07 & Uimm32_0811_0506x { - # TODO: verify order of operation - # TODO: Is there an alignment shift? tmp:4 = (rs5 << Uimm2_13_07) + Uimm32_0811_0506x; export tmp; } @@ -1176,14 +1245,14 @@ LdMemAIS4CircMuC9b2: LdAddrAIS4CircMuC9 is LdAddrAIS4CircMuC9 [ shift = 2; ] { e # Class-9 Load Memory: Rx++I:circ(Mu) -- 'cond=1' context must be set by conditional instructions! LdAddrAIICircMuC9: "("^rx5^"++I:circ("^mu^"))" is cond=0 & rx5 & rx5_ & mu { - i = (mu[28,4] << 7) | mu[17,7]; # Isolate I value from specified M0/M1 reg + local i = (mu[28,4] << 7) | mu[17,7]; # Isolate I value from specified M0/M1 reg tmp:4 = circularAdd(rx5, i, mu); export rx5; <> rx5 = tmp; } LdAddrAIICircMuC9: "("^rx5^"++I:circ("^mu^"))" is cond=1 & rx5 & rx5_ & mu { - i = (mu[28,4] << 7) | mu[17,7]; # Isolate I value from specified M0/M1 reg + local i = (mu[28,4] << 7) | mu[17,7]; # Isolate I value from specified M0/M1 reg tmp:4 = circularAdd(rx5, i, mu); export rx5; <> @@ -1261,16 +1330,14 @@ StMemRsRelPdC9d: StAddrRsRelPdC9 is StAddrRsRelPdC9 { export *[ram]:8 StAddrRsRe # Class-10 Store Memory: Rf=#U6x -- 'cond=1' context must be set by conditional instructions! StAddrRsAssignxC10: "("^rf5^"="^Uimm32_0005x^")" is cond=0 & rf5 & rf5_ & Uimm32_0005x { - # TODO: Need to verify behavior !! rf5_ = Uimm32_0005x; - export rf5_; + export Uimm32_0005x; <> rf5 = rf5_; } StAddrRsAssignxC10: "("^rf5^"="^Uimm32_0005x^")" is cond=1 & rf5 & rf5_ & Uimm32_0005x { - # TODO: Need to verify behavior !! rf5_ = Uimm32_0005x; - export rf5_; + export Uimm32_0005x; <> if (ConditionReg == 0) goto ; rf5 = rf5_; @@ -1295,8 +1362,6 @@ StAddrRsRelShiftxC10: "("^rs5^"+"^Uimm32_0005x^")" is rs5 & op13=0 & op6=0 & Uim export tmp; } StAddrRsRelShiftxC10: "("^rs5^"<<"^Uimm2_13_06^"+"^Uimm32_0005x^")" is rs5 & Uimm2_13_06 & Uimm32_0005x { - # TODO: verify order of operation - # TODO: Is there an alignment shift? tmp:4 = (rs5 << Uimm2_13_06) + Uimm32_0005x; export tmp; } @@ -1374,7 +1439,7 @@ StMemAIS4CircMuC10b: StAddrAIS4CircMuC10 is StAddrAIS4CircMuC10 [ shift = 0; ] { # Class-10 Store Memory: Rx++I:circ(Mu) -- 'cond=1' context must be set by conditional instructions! StAddrAIICircMuC10: "("^rx5^"++I:circ("^mu^"))" is cond=0 & op2527=4 & rx5 & rx5_ & mu & i1=1 { - i = (mu[28,4] << 7) | mu[17,7]; # Isolate I value from specified M0/M1 reg + local i = (mu[28,4] << 7) | mu[17,7]; # Isolate I value from specified M0/M1 reg tmp:4 = circularAdd(rx5, i, mu); ptr:4 = rx5; export ptr; @@ -1382,7 +1447,7 @@ StAddrAIICircMuC10: "("^rx5^"++I:circ("^mu^"))" is cond=0 & op2527=4 & rx5 & rx5 rx5 = tmp; } StAddrAIICircMuC10: "("^rx5^"++I:circ("^mu^"))" is cond=1 & op2527=4 & rx5 & rx5_ & mu & i1=1 { - i = (mu[28,4] << 7) | mu[17,7]; # Isolate I value from specified M0/M1 reg + local i = (mu[28,4] << 7) | mu[17,7]; # Isolate I value from specified M0/M1 reg tmp:4 = circularAdd(rx5, i, mu); ptr:4 = rx5; export ptr; @@ -1724,8 +1789,8 @@ ResetPacketBits: is epsilon { } # # Sample: # -# :deallocframe EndPackedRight is op0612=0x7c & op2=0 & $(END_PACKED_RIGHT) { -# deallocframe(); +# :deallocframe EndPackedRight is op0612=0x7c & op2=0 & DeallocFrameRddRsRaw & $(END_PACKED_RIGHT) { +# build DeallocFrameRddRsRaw; # build EndPackedRight; # } # @@ -1873,41 +1938,140 @@ EndPackedRight: is EndPacket [ phase = 6; ] { build EndPacket; } # resume EndPa # | | (initial SP) # -# NOTE: allocframe and dealloc_frame macro should be invoked from the -# <>, <> or <> pcode section only +# allocframe ( Rx32, #u11:3 ) +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# - - - - - - - - - - - x x x x x - - - - - i i i i i i i i i i i -macro deallocframe(reg) { - ptr:4 = reg; - FP = *[ram]:4 ptr; - ptr = ptr + 4; - LR = (*[ram]:4 ptr) ^ FRAMEKEY; - SP = ptr + 4; +AllocFrameRxU11x8: is rx5 & Uimm16_0010_shift3 { + local ptr:4 = rx5 - 4; + local tmpFP = FP; + local tmpLR = LR ^ FRAMEKEY; + <> + *[ram]:4 ptr = tmpLR; + ptr = ptr - 4; + *[ram]:4 ptr = tmpFP; + FP = ptr; + rx5 = ptr - zext(Uimm16_0010_shift3); +} + +# allocframe ( SP, #u5:3 ) +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# - - - - - - - i i i i i - - - - - - - - - - - - - - - - - - - - + +AllocFrameSPU5x8Left: is Uimm8_2024_shift3 { + local ptr:4 = SP - 4; + local tmpFP = FP; + local tmpLR = LR ^ FRAMEKEY; + <> + *[ram]:4 ptr = tmpLR; + ptr = ptr - 4; + *[ram]:4 ptr = tmpFP; + FP = ptr; + SP = ptr - zext(Uimm8_2024_shift3); } -macro allocframe(reg,sze) { - ptr:4 = reg - 4; - *[ram]:4 ptr = (LR ^ FRAMEKEY); +# allocframe ( SP, #u5:3 ) +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# - - - - - - - - - - - - - - - - - - - - - - - i i i i i - - - - + +AllocFrameSPU5x8Right: is Uimm8_0408_shift3 { + local ptr:4 = SP - 4; + local tmpFP = FP; + local tmpLR = LR ^ FRAMEKEY; + <> + *[ram]:4 ptr = tmpLR; ptr = ptr - 4; - *[ram]:4 ptr = FP; + *[ram]:4 ptr = tmpFP; FP = ptr; - reg = ptr - zext(sze); + SP = ptr - zext(Uimm8_0408_shift3); +} + +# Rdd = deallocFrameRaw(Rs32) +# NOTE: Provides delayed commit - favored over macro use +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# - - - - - - - - - - - s s s s s - - - - - - - - - - - d d d d d + +DeallocFrameRddRsRaw: is rs5 & rdd5h & rd5 { + local ptr:4 = rs5; + local FPnew = *[ram]:4 ptr; + ptr = ptr + 4; + local LRnew = (*[ram]:4 ptr) ^ FRAMEKEY; + <> + rd5 = FPnew; + rdd5h = LRnew; + SP = ptr + 4; +} + +# Rdd = deallocFrameRaw(Rs32) - conditional execution based on FlowCond0809_N11_S13 use +# NOTE: Provides delayed conditional commit - favored over macro use +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# +DeallocFrameRddRsRawCond: is rs5 & rdd5h & rd5 { + local ptr:4 = rs5; + local FPnew = *[ram]:4 ptr; + ptr = ptr + 4; + local LRnew = (*[ram]:4 ptr) ^ FRAMEKEY; + <> + if (ConditionReg == 0) goto ; + rd5 = FPnew; + rdd5h = LRnew; + SP = ptr + 4; + +} + +# LR:FP = deallocFrameRaw(FP) +# NOTE: Provides delayed commit + +DeallocFrameRaw: is epsilon { + local ptr:4 = FP; + local FPnew = *[ram]:4 ptr; + ptr = ptr + 4; + local LRnew = (*[ram]:4 ptr) ^ FRAMEKEY; + <> + FP = FPnew; + LR = LRnew; + SP = ptr + 4; +} + +# LR:FP = deallocFrameRaw(FP) - conditional execution based on FlowCond0809_N11_S13 use +# NOTE: Provides delayed conditional commit + +DeallocFrameRawCond: is epsilon { + local ptr:4 = FP; + local FPnew = *[ram]:4 ptr; + ptr = ptr + 4; + local LRnew = (*[ram]:4 ptr) ^ FRAMEKEY; + <> + if (ConditionReg == 0) goto ; + FP = FPnew; + LR = LRnew; + SP = ptr + 4; + } # # INSTRUCTIONS # # Pattern convention: -# '-' indicates don't-care bit (bit should not be constrained) -# '+' indicates don't care bit (bit should be constrained as '0') +# '-' indicates don't-care bit (bit is not constrained by the pattern) +# +# Don't-care bits are ignored by the hardware decoder and are not +# constrained by the Sleigh patterns. Assemblers (binutils/LLVM) always +# emit 0 in these bit positions, but any value must decode. # # (v2,8) abs -- "Rd32 = abs ( Rs32 )" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 1 0 0 0 1 1 0 0 1 0 0 s s s s s P P + + + + + + 1 0 0 d d d d d +# 1 0 0 0 1 1 0 0 1 0 0 s s s s s P P - - - - - - 1 0 0 d d d d d -:abs Rd5,rs5 EndPacket is iclass=8 & op2127=0x64 & op0513=0x04 & Rd5 & rs5 & $(END_PACKET) { +:abs Rd5,rs5 EndPacket is iclass=8 & op2127=0x64 & op0507=0x4 & Rd5 & rs5 & $(END_PACKET) { neg:1 = (rs5 s< 0); Rd5 = (zext(neg) * -rs5) + (zext(!neg) * rs5); build EndPacket; @@ -1916,11 +2080,11 @@ macro allocframe(reg,sze) { # (v2,8) abs -- "Rd32 = abs ( Rs32 ) :sat" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 1 0 0 0 1 1 0 0 1 0 0 s s s s s P P + + + + + + 1 0 1 d d d d d +# 1 0 0 0 1 1 0 0 1 0 0 s s s s s P P - - - - - - 1 0 1 d d d d d define pcodeop absSat; -:abs":sat" Rd5,rs5 EndPacket is iclass=8 & op2127=0x64 & op0513=0x05 & Rd5 & rs5 & $(END_PACKET) { +:abs":sat" Rd5,rs5 EndPacket is iclass=8 & op2127=0x64 & op0507=0x5 & Rd5 & rs5 & $(END_PACKET) { pos:1 = (rs5 s>= 0); toobig:1 = (rs5 == 0x80000000); # Only one saturation case @@ -1933,9 +2097,9 @@ define pcodeop absSat; # (v2,8) abs -- "Rdd32 = abs ( Rss32 )" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 1 0 0 0 0 0 0 0 1 0 + s s s s s P P + + + + + + 1 1 0 d d d d d +# 1 0 0 0 0 0 0 0 1 0 0 s s s s s P P - - - - - - 1 1 0 d d d d d -:abs Rdd5,rss5 EndPacket is iclass=0x8 & op2127=0x04 & op0513=0x06 & Rdd5 & rss5 & $(END_PACKET) +:abs Rdd5,rss5 EndPacket is iclass=0x8 & op2227=0x2 & op21=0 & op0507=0x6 & Rdd5 & rss5 & $(END_PACKET) { neg:1 = (rss5 s< 0); Rdd5 = (zext(neg) * -rss5) + (zext(!neg) * rss5); @@ -1955,9 +2119,9 @@ define pcodeop absSat; # (v2,15) add -- "Rd32 = add ( Rs32 , Rt32 )" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 1 1 1 1 0 0 1 1 0 0 0 s s s s s P P + t t t t t + + + d d d d d +# 1 1 1 1 0 0 1 1 0 0 0 s s s s s P P - t t t t t - - - d d d d d -:add Rd5,rs5,rt5 EndPacket is iclass=0xf & op2127=0x18 & op13=0 & op0507=0 & Rd5 & rs5 & rt5 & $(END_PACKET) { +:add Rd5,rs5,rt5 EndPacket is iclass=0xf & op2127=0x18 & Rd5 & rs5 & rt5 & $(END_PACKET) { Rd5 = rs5 + rt5; build EndPacket; } @@ -1965,9 +2129,9 @@ define pcodeop absSat; # (v4,15) add -- "Rd32 = add ( Rs32 , Rt32 ) :sat" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 1 1 1 1 0 1 1 0 0 1 0 s s s s s P P + t t t t t + + + d d d d d +# 1 1 1 1 0 1 1 0 0 1 0 s s s s s P P - t t t t t - - - d d d d d -:add^":sat" Rd5,rs5,rt5 EndPacket is iclass=0xf & op2127=0x32 & rs5 & op13=0 & rt5 & op0507=0x0 & Rd5 & $(END_PACKET) +:add^":sat" Rd5,rs5,rt5 EndPacket is iclass=0xf & op2127=0x32 & rs5 & rt5 & Rd5 & $(END_PACKET) { sat:1 = scarry(rs5, rt5); addSat32(Rd5, rs5, rt5); @@ -1979,9 +2143,9 @@ define pcodeop absSat; # (v2,13) add -- "Rd32 = add ( Rs32 , Rt32 ) :sat :deprecated" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 1 1 0 1 0 1 0 1 1 0 0 s s s s s P P + t t t t t 0 + + d d d d d +# 1 1 0 1 0 1 0 1 1 0 0 s s s s s P P - t t t t t 0 - - d d d d d -:add^":sat:deprecated" Rd5,rs5,rt5 EndPacket is iclass=0xd & op2127=0x2c & rs5 & op13=0 & rt5 & op0507=0x0 & Rd5 & $(END_PACKET) +:add^":sat:deprecated" Rd5,rs5,rt5 EndPacket is iclass=0xd & op2127=0x2c & op7=0x0 & rs5 & rt5 & Rd5 & $(END_PACKET) { sat:1 = scarry(rs5, rt5); addSat32(Rd5, rs5, rt5); @@ -2071,14 +2235,14 @@ MpyiRs32Rt32: "mpyi("rs5,rt5")" is rs5 & rt5 { # (v2,13) add -- "Rd32 = add ( Rt32.l , Rs32.h )" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 1 1 0 1 0 1 0 1 0 0 0 s s s s s P P + t t t t t 0 1 + d d d d d +# 1 1 0 1 0 1 0 1 0 0 0 s s s s s P P - t t t t t 0 1 - d d d d d # # (v2,13) add -- "Rd32 = add ( Rt32.l , Rs32.l )" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 1 1 0 1 0 1 0 1 0 0 0 s s s s s P P + t t t t t 0 0 + d d d d d +# 1 1 0 1 0 1 0 1 0 0 0 s s s s s P P - t t t t t 0 0 - d d d d d -:add Rd5,rt5L,Rs5HL06 EndPacket is iclass=0xd & op2127=0x28 & op13=0 & op7=0 & op5=0 & rt5L & Rs5HL06 & Rd5 & $(END_PACKET) +:add Rd5,rt5L,Rs5HL06 EndPacket is iclass=0xd & op2127=0x28 & op7=0 & rt5L & Rs5HL06 & Rd5 & $(END_PACKET) { Rd5 = sext(rt5L + Rs5HL06); build EndPacket; @@ -2087,24 +2251,24 @@ MpyiRs32Rt32: "mpyi("rs5,rt5")" is rs5 & rt5 { # (v2,13) add -- "Rd32 = add ( Rt32.h , Rs32.h ) :<<16" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 1 1 0 1 0 1 0 1 0 1 0 s s s s s P P + t t t t t 0 1 1 d d d d d +# 1 1 0 1 0 1 0 1 0 1 0 s s s s s P P - t t t t t 0 1 1 d d d d d # # (v2,13) add -- "Rd32 = add ( Rt32.h , Rs32.l ) :<<16" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 1 1 0 1 0 1 0 1 0 1 0 s s s s s P P + t t t t t 0 1 0 d d d d d +# 1 1 0 1 0 1 0 1 0 1 0 s s s s s P P - t t t t t 0 1 0 d d d d d # # (v2,13) add -- "Rd32 = add ( Rt32.l , Rs32.h ) :<<16" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 1 1 0 1 0 1 0 1 0 1 0 s s s s s P P + t t t t t 0 0 1 d d d d d +# 1 1 0 1 0 1 0 1 0 1 0 s s s s s P P - t t t t t 0 0 1 d d d d d # # (v2,13) add -- "Rd32 = add ( Rt32.l , Rs32.l ) :<<16" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 1 1 0 1 0 1 0 1 0 1 0 s s s s s P P + t t t t t 0 0 0 d d d d d +# 1 1 0 1 0 1 0 1 0 1 0 s s s s s P P - t t t t t 0 0 0 d d d d d -:add^":<<16" Rd5,Rt5HL06,Rs5HL05 EndPacket is iclass=0xd & op2127=0x2a & op13=0 & op7=0 & Rs5HL05 & Rt5HL06 & Rd5 & $(END_PACKET) +:add^":<<16" Rd5,Rt5HL06,Rs5HL05 EndPacket is iclass=0xd & op2127=0x2a & op7=0 & Rs5HL05 & Rt5HL06 & Rd5 & $(END_PACKET) { Rd5 = zext(Rs5HL05 + Rt5HL06) << 16; build EndPacket; @@ -2113,24 +2277,24 @@ MpyiRs32Rt32: "mpyi("rs5,rt5")" is rs5 & rt5 { # (v2,13) add -- "Rd32 = add ( Rt32.h , Rs32.h ) :sat :<<16" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 1 1 0 1 0 1 0 1 0 1 0 s s s s s P P + t t t t t 1 1 1 d d d d d +# 1 1 0 1 0 1 0 1 0 1 0 s s s s s P P - t t t t t 1 1 1 d d d d d # # (v2,13) add -- "Rd32 = add ( Rt32.h , Rs32.l ) :sat :<<16" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 1 1 0 1 0 1 0 1 0 1 0 s s s s s P P + t t t t t 1 1 0 d d d d d +# 1 1 0 1 0 1 0 1 0 1 0 s s s s s P P - t t t t t 1 1 0 d d d d d # # (v2,13) add -- "Rd32 = add ( Rt32.l , Rs32.h ) :sat :<<16" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 1 1 0 1 0 1 0 1 0 1 0 s s s s s P P + t t t t t 1 0 1 d d d d d +# 1 1 0 1 0 1 0 1 0 1 0 s s s s s P P - t t t t t 1 0 1 d d d d d # # (v2,13) add -- "Rd32 = add ( Rt32.l , Rs32.l ) :sat :<<16" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 1 1 0 1 0 1 0 1 0 1 0 s s s s s P P + t t t t t 1 0 0 d d d d d +# 1 1 0 1 0 1 0 1 0 1 0 s s s s s P P - t t t t t 1 0 0 d d d d d -:add^":sat:<<16" Rd5,Rt5HL06,Rs5HL05 EndPacket is iclass=0xd & op2127=0x2a & op13=0 & op7=1 & Rs5HL05 & Rt5HL06 & Rd5 & $(END_PACKET) +:add^":sat:<<16" Rd5,Rt5HL06,Rs5HL05 EndPacket is iclass=0xd & op2127=0x2a & op7=1 & Rs5HL05 & Rt5HL06 & Rd5 & $(END_PACKET) { temp:2 = 0; addSat16(temp, Rs5HL05, Rt5HL06); @@ -2144,14 +2308,14 @@ MpyiRs32Rt32: "mpyi("rs5,rt5")" is rs5 & rt5 { # (v2,13) add -- "Rd32 = add ( Rt32.l , Rs32.h ) :sat" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 1 1 0 1 0 1 0 1 0 0 0 s s s s s P P + t t t t t 1 1 + d d d d d +# 1 1 0 1 0 1 0 1 0 0 0 s s s s s P P - t t t t t 1 1 - d d d d d # # (v2,13) add -- "Rd32 = add ( Rt32.l , Rs32.l ) :sat" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 1 1 0 1 0 1 0 1 0 0 0 s s s s s P P + t t t t t 1 0 + d d d d d +# 1 1 0 1 0 1 0 1 0 0 0 s s s s s P P - t t t t t 1 0 - d d d d d -:add^":sat" Rd5,rt5L,Rs5HL06 EndPacket is iclass=0xd & op2127=0x28 & op13=0 & op7=1 & op5=0 & Rs5HL06 & rt5L & Rd5 & $(END_PACKET) +:add^":sat" Rd5,rt5L,Rs5HL06 EndPacket is iclass=0xd & op2127=0x28 & op7=1 & Rs5HL06 & rt5L & Rd5 & $(END_PACKET) { temp:2 = 0; addSat16(temp, Rs5HL06, rt5L); @@ -2178,11 +2342,11 @@ ClbRs: "clb("^rs5")" is rs5 { cnt:4 = countLeadingBits(rs5); export cnt; } # (v4,8) add -- "Rd32 = add ( clb ( Rss32 ) , #s6 )" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 1 0 0 0 1 0 0 0 0 1 1 s s s s s P P i i i i i i 0 1 + d d d d d +# 1 0 0 0 1 0 0 0 0 1 1 s s s s s P P i i i i i i 0 1 0 d d d d d ClbRss: "clb("^rss5")" is rss5 { cnt:4 = countLeadingBits(rss5); export cnt; } -:add Rd5,ClbRss,Simm8_0813 EndPacket is iclass=8 & op2127=0x43 & op0507=2 & Rd5 & ClbRss & Simm8_0813 & $(END_PACKET) +:add Rd5,ClbRss,Simm8_0813 EndPacket is iclass=8 & op2127=0x43 & op0607=1 & op5=0 & Rd5 & ClbRss & Simm8_0813 & $(END_PACKET) { Rd5 = ClbRss + sext(Simm8_0813); build EndPacket; @@ -2191,26 +2355,27 @@ ClbRss: "clb("^rss5")" is rss5 { cnt:4 = countLeadingBits(rss5); export cnt; } # (v4,6) add -- "Rd32 = add ( pc , #u6x )" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 0 1 1 0 1 0 1 0 0 1 0 0 1 0 0 1 P P + i i i i i i + + d d d d d +# 0 1 1 0 1 0 1 0 0 1 0 0 1 0 0 1 P P - i i i i i i - - d d d d d -:assign Rd5,PacketPC EndPacket is iclass=6 & op2127=0x52 & op1620=0x9 & op13=0 & op0506=0 & i0712=0 & immext=0 & Rd5 & PacketPC & $(END_PACKET) +:add Rd5,PacketPC,Uimm32_0712x EndPacket is iclass=6 & op2127=0x52 & op1620=0x9 & Rd5 & PacketPC & Uimm32_0712x & $(END_PACKET) { - Rd5 = PacketPC; + Rd5 = PacketPC + Uimm32_0712x; build EndPacket; } -:add Rd5,PacketPC,Uimm32_0712x EndPacket is iclass=6 & op2127=0x52 & op1620=0x9 & op13=0 & op0506=0 & Rd5 & PacketPC & Uimm32_0712x & $(END_PACKET) +# Simplification when adding zero constant to packet PC +:assign Rd5,PacketPC EndPacket is iclass=6 & op2127=0x52 & op1620=0x9 & i0712=0 & immext=0 & Rd5 & PacketPC & $(END_PACKET) { - Rd5 = PacketPC + Uimm32_0712x; + Rd5 = PacketPC; build EndPacket; } # (v2,13) add -- "Rdd32 = add ( Rss32 , Rtt32 )" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 1 1 0 1 0 0 1 1 0 0 0 s s s s s P P + t t t t t 1 1 1 d d d d d +# 1 1 0 1 0 0 1 1 0 0 0 s s s s s P P - t t t t t 1 1 1 d d d d d -:add Rdd5,rss5,rtt5 EndPacket is iclass=0xd & op2127=0x18 & rss5 & op13=0 & rtt5 & op0507=0x7 & Rdd5 & $(END_PACKET) +:add Rdd5,rss5,rtt5 EndPacket is iclass=0xd & op2127=0x18 & op0507=0x7 & rss5 & rtt5 & Rdd5 & $(END_PACKET) { Rdd5 = rss5 + rtt5; build EndPacket; @@ -2219,11 +2384,11 @@ ClbRss: "clb("^rss5")" is rss5 { cnt:4 = countLeadingBits(rss5); export cnt; } # (v4,13) add -- "Rdd32 = add ( Rss32 , Rtt32 ) :raw :hi" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 1 1 0 1 0 0 1 1 0 1 1 s s s s s P P + t t t t t 1 1 1 d d d d d +# 1 1 0 1 0 0 1 1 0 1 1 s s s s s P P - t t t t t 1 1 1 d d d d d define pcodeop addRawHi; -:add":raw:hi" Rdd5,rss5,rtt5 EndPacket is iclass=0xd & op2127=0x1b & rss5 & op13=0 & rtt5 & op0507=0x7 & Rdd5 & $(END_PACKET) +:add":raw:hi" Rdd5,rss5,rtt5 EndPacket is iclass=0xd & op2127=0x1b & op0507=0x7 & rss5 & rtt5 & Rdd5 & $(END_PACKET) { Rdd5 = rtt5 + sext(rss5[32,32]); build EndPacket; @@ -2232,11 +2397,11 @@ define pcodeop addRawHi; # (v4,13) add -- "Rdd32 = add ( Rss32 , Rtt32 ) :raw :lo" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 1 1 0 1 0 0 1 1 0 1 1 s s s s s P P + t t t t t 1 1 0 d d d d d +# 1 1 0 1 0 0 1 1 0 1 1 s s s s s P P - t t t t t 1 1 0 d d d d d define pcodeop addRawLo; -:add":raw:lo" Rdd5,rss5,rtt5 EndPacket is iclass=0xd & op2127=0x1b & rss5 & op13=0 & rtt5 & op0507=0x6 & Rdd5 & $(END_PACKET) +:add":raw:lo" Rdd5,rss5,rtt5 EndPacket is iclass=0xd & op2127=0x1b & op0507=0x6 & rss5 & rtt5 & Rdd5 & $(END_PACKET) { Rdd5 = rtt5 + sext(rss5[0,32]); build EndPacket; @@ -2245,11 +2410,11 @@ define pcodeop addRawLo; # (v4,13) add -- "Rdd32 = add ( Rss32 , Rtt32 ) :sat" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 1 1 0 1 0 0 1 1 0 1 1 s s s s s P P + t t t t t 1 0 1 d d d d d +# 1 1 0 1 0 0 1 1 0 1 1 s s s s s P P - t t t t t 1 0 1 d d d d d define pcodeop addSat; -:add":sat" Rdd5,rss5,rtt5 EndPacket is iclass=0xd & op2127=0x1b & rss5 & op13=0 & rtt5 & op0507=0x5 & Rdd5 & $(END_PACKET) +:add":sat" Rdd5,rss5,rtt5 EndPacket is iclass=0xd & op2127=0x1b & op0507=0x5 & rss5 & rtt5 & Rdd5 & $(END_PACKET) { Rdd5 = addSat(rss5, rtt5); build EndPacket; @@ -2258,17 +2423,26 @@ define pcodeop addSat; # (v4,12) add -- "Rdd32 = add ( Rss32 , Rtt32 , Px4 ) :carry" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 1 1 0 0 0 0 1 0 1 1 0 s s s s s P P + t t t t t + x x d d d d d +# 1 1 0 0 0 0 1 0 1 1 0 s s s s s P P - t t t t t - x x d d d d d -:add":carry" Rdd5,rss5,rtt5,pu0506 EndPacket is iclass=0xc & op2127=0x16 & rss5 & op13=0 & rtt5 & op7=0 & Rdd5 & pu0506 & pu0506_ & $(END_PACKET) -unimpl +:add":carry" Rdd5,rss5,rtt5,pu0506 EndPacket is iclass=0xc & op2127=0x16 & rss5 & rtt5 & Rdd5 & pu0506 & pu0506_ & $(END_PACKET) { + cin:8 = zext(pu0506 & 1); # carry-in: bit 0 of predicate + partial:8 = rss5 + rtt5; + c1:1 = carry(rss5, rtt5); # carry from Rss + Rtt + c2:1 = carry(partial, cin); # carry from adding carry-in + Rdd5 = partial + cin; + pu0506_ = (c1 | c2) * 0xff; # carry-out: 0xff if carry, 0x00 otherwise + build EndPacket; + <> + pu0506 = pu0506_; +} # (v2,14) add -- "Rx32 += add ( Rs32 , #s8x )" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 1 1 1 0 0 0 1 0 0 + + s s s s s P P + i i i i i i i i x x x x x +# 1 1 1 0 0 0 1 0 0 - - s s s s s P P 0 i i i i i i i i x x x x x -:add+= Rd5,rs5,Simm32_0512x EndPacket is iclass=0xe & op2127=0x10 & rs5 & op13=0 & Simm32_0512x & rd5 & Rd5 & $(END_PACKET) +:add+= Rd5,rs5,Simm32_0512x EndPacket is iclass=0xe & op2327=0x4 & op13=0 & rs5 & Simm32_0512x & rd5 & Rd5 & $(END_PACKET) { Rd5 = rd5 + rs5 + Simm32_0512x; build EndPacket; @@ -2277,9 +2451,9 @@ unimpl # (v2,14) add -- "Rx32 += add ( Rs32 , Rt32 )" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 1 1 1 0 1 1 1 1 0 0 0 s s s s s P P + t t t t t + 0 1 x x x x x +# 1 1 1 0 1 1 1 1 0 0 0 s s s s s P P - t t t t t - 0 1 x x x x x -:add+= Rd5,rs5,rt5 EndPacket is iclass=0xe & op2127=0x78 & rs5 & op13=0 & op0507=0x1 & rt5 & rd5 & Rd5 & $(END_PACKET) +:add+= Rd5,rs5,rt5 EndPacket is iclass=0xe & op2127=0x78 & op0506=0x1 & rs5 & rt5 & rd5 & Rd5 & $(END_PACKET) { Rd5 = rd5 + rs5 + rt5; build EndPacket; @@ -2288,9 +2462,9 @@ unimpl # (v2,14) add -- "Rx32 -= add ( Rs32 , #s8x )" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 1 1 1 0 0 0 1 0 1 + + s s s s s P P + i i i i i i i i x x x x x +# 1 1 1 0 0 0 1 0 1 - - s s s s s P P 0 i i i i i i i i x x x x x -:add-= Rd5,rs5,Simm32_0512x EndPacket is iclass=0xe & op2127=0x14 & op13=0 & rs5 & Simm32_0512x & rd5 & Rd5 & $(END_PACKET) +:add-= Rd5,rs5,Simm32_0512x EndPacket is iclass=0xe & op2327=0x5 & op13=0 & rs5 & Simm32_0512x & rd5 & Rd5 & $(END_PACKET) { Rd5 = rd5 - rs5 + Simm32_0512x; build EndPacket; @@ -2299,9 +2473,9 @@ unimpl # (v2,14) add -- "Rx32 -= add ( Rs32 , Rt32 )" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 1 1 1 0 1 1 1 1 1 0 0 s s s s s P P + t t t t t + 0 1 x x x x x +# 1 1 1 0 1 1 1 1 1 0 0 s s s s s P P 0 t t t t t 0 0 1 x x x x x -:add-= Rd5,rs5,rt5 EndPacket is iclass=0xe & op2127=0x7c & rs5 & op13=0 & rt5 & op0507=0x1 & rd5 & Rd5 & $(END_PACKET) +:add-= Rd5,rs5,rt5 EndPacket is iclass=0xe & op2127=0x7c & op13=0 & op7=0 & op0506=0x1 & rs5 & rt5 & rd5 & Rd5 & $(END_PACKET) { Rd5 = rd5 - ( rs5 + rt5 ); build EndPacket; @@ -2310,14 +2484,14 @@ unimpl # (v4,13) add -- "Rx32 = add ( #u8x , asl ( Rx32 , #U5 ) )" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 1 1 0 1 1 1 1 0 i i i x x x x x P P i I I I I I i i i 0 i 1 0 + +# 1 1 0 1 1 1 1 0 i i i x x x x x P P i I I I I I i i i 0 i 1 0 - # # (v4,13) add -- "Rx32 = add ( #u8x , lsr ( Rx32 , #U5 ) )" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 1 1 0 1 1 1 1 0 i i i x x x x x P P i I I I I I i i i 1 i 1 0 + +# 1 1 0 1 1 1 1 0 i i i x x x x x P P i I I I I I i i i 1 i 1 0 - -:add Rx5,Uimm32_2123_13_0507_03x,ShiftRx_D04_I0812 EndPacket is iclass=13 & op2427=14 & op0002=4 & Uimm32_2123_13_0507_03x & ShiftRx_D04_I0812 & Rx5 & $(END_PACKET) +:add Rx5,Uimm32_2123_13_0507_03x,ShiftRx_D04_I0812 EndPacket is iclass=13 & op2427=14 & op0102=2 & Uimm32_2123_13_0507_03x & ShiftRx_D04_I0812 & Rx5 & $(END_PACKET) { Rx5 = Uimm32_2123_13_0507_03x + ShiftRx_D04_I0812; build EndPacket; @@ -2326,14 +2500,14 @@ unimpl # (v4,14) add -- "Rx32 = add ( Ru32 , mpyi ( Rx32 , Rs32 ) )" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 1 1 1 0 0 0 1 1 0 0 0 s s s s s P P + x x x x x + + + u u u u u +# 1 1 1 0 0 0 1 1 0 0 0 s s s s s P P - x x x x x - - - u u u u u MpyiRx32Rs32: "mpyi("rt5,rs5")" is rs5 & rt5 { tmp:4 = rs5 * rt5; export tmp; } -:add Rd0812,ru5,MpyiRx32Rs32 EndPacket is iclass=14 & op2127=0x18 & op13=0 & op0507=0 & Rd0812 & MpyiRx32Rs32 & ru5 & $(END_PACKET) +:add Rd0812,ru5,MpyiRx32Rs32 EndPacket is iclass=14 & op2127=0x18 & Rd0812 & MpyiRx32Rs32 & ru5 & $(END_PACKET) { Rd0812 = ru5 + MpyiRx32Rs32; build EndPacket; @@ -2363,24 +2537,33 @@ MpyiRx32Rs32: "mpyi("rt5,rs5")" is rs5 & rt5 { build PuCond2122_N13_S23; build EndPacket; <> + build PuCond2122_N13_S23; if (ConditionReg == 0) goto ; rd5_ = rs5 + Simm32_0512x; <> + build PuCond2122_N13_S23; if (ConditionReg == 0) goto ; rd5 = rd5_; } # if ([!]Pu4[.new]) Rd32 = Rs32 ( simplification of if ([!]Pu4[.new]) Rd32 = add(Rs32,#0) -:assign^PuCond2122_N13_S23 rd5,rs5 EndPacket is iclass=7 & op2427=4 & PuCond2122_N13_S23 & rs5 & op0512=0 & immexted=0 & rd5 & rd5_ & SetNRegRd5 & $(END_PACKET) { +# (v2,7) assign -- "if ([!]Pu4[.new]) Rd32 = Rs32" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 1 1 1 0 1 0 0 N n s s s s s s P P N 0 0 0 0 0 0 0 0 d d d d d + +:assign^PuCond2122_N13_S23 rd5,rs5 EndPacket is iclass=7 & op2427=4 & op0512=0 & PuCond2122_N13_S23 & rs5 & immexted=0 & rd5 & rd5_ & SetNRegRd5 & $(END_PACKET) { build PuCond2122_N13_S23; build EndPacket; <> + build PuCond2122_N13_S23; if (ConditionReg == 0) goto ; rd5_ = rs5; <> + build PuCond2122_N13_S23; if (ConditionReg == 0) goto ; rd5 = rd5_; @@ -2406,14 +2589,16 @@ MpyiRx32Rs32: "mpyi("rt5,rs5")" is rs5 & rt5 { # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| # 1 1 1 1 1 0 1 1 0 - 0 s s s s s P P 1 t t t t t 1 u u d d d d d -:add^PuCond0506_N13_S07 rd5,rs5,rt5 EndPacket is iclass=15 & op2327=0x16 & op22=0 & op21=0 & PuCond0506_N13_S07 & rs5 & rt5 & rd5 & rd5_ & SetNRegRd5 & $(END_PACKET) { +:add^PuCond0506_N13_S07 rd5,rs5,rt5 EndPacket is iclass=15 & op2327=0x16 & op21=0 & PuCond0506_N13_S07 & rs5 & rt5 & rd5 & rd5_ & SetNRegRd5 & $(END_PACKET) { build PuCond0506_N13_S07; build EndPacket; <> + build PuCond0506_N13_S07; if (ConditionReg == 0) goto ; rd5_ = rs5 + rt5; <> + build PuCond0506_N13_S07; if (ConditionReg == 0) goto ; rd5 = rd5_; @@ -2435,7 +2620,7 @@ MpyiRx32Rs32: "mpyi("rt5,rs5")" is rs5 & rt5 { # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| # 0 1 1 0 1 0 1 1 1 0 1 0 - - s s P P 0 - - - - - - - - - - - d d -:all8 Pd2,pu1617 EndPacket is iclass=6 & op2127=0x5d & op1820=0 & op0213=0 & pu1617 & Pd2 & $(END_PACKET) { +:all8 Pd2,pu1617 EndPacket is iclass=6 & op2127=0x5d & op20=0 & op13=0 & pu1617 & Pd2 & $(END_PACKET) { Pd2 = Pd2 & ((pu1617 == 0xff) * 0xff); build EndPacket; } @@ -2445,8 +2630,8 @@ MpyiRx32Rs32: "mpyi("rt5,rs5")" is rs5 & rt5 { # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| # 1 0 1 0 0 0 0 0 1 0 0 1 1 1 0 1 P P 0 0 0 i i i i i i i i i i i -:allocframe Uimm16_0010_shift3 EndPacket is iclass=10 & op2527=0 & op2224=2 & op21=0 & op1620=0x1d & op1113=0 & Uimm16_0010_shift3 & $(END_PACKET) { - allocframe(SP, Uimm16_0010_shift3); +:allocframe Uimm16_0010_shift3 EndPacket is iclass=10 & op2527=0 & op2224=2 & op21=0 & op1620=0x1d & op1113=0 & Uimm16_0010_shift3 & AllocFrameRxU11x8 & $(END_PACKET) { + build AllocFrameRxU11x8; # allocframe(SP, #u11:3) build EndPacket; } @@ -2455,32 +2640,32 @@ MpyiRx32Rs32: "mpyi("rt5,rs5")" is rs5 & rt5 { # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| # 1 0 1 0 0 0 0 0 1 0 0 x x x x x P P 0 0 0 i i i i i i i i i i i -:allocframe rx5, Uimm16_0010_shift3 EndPacket is iclass=10 & op2527=0 & op2224=2 & op21=0 & rx5 & op1113=0 & Uimm16_0010_shift3 & $(END_PACKET) { - allocframe(rx5, Uimm16_0010_shift3); +:allocframe rx5, Uimm16_0010_shift3 EndPacket is iclass=10 & op2527=0 & op2224=2 & op21=0 & op1113=0 & rx5 & Uimm16_0010_shift3 & AllocFrameRxU11x8 & $(END_PACKET) { + build AllocFrameRxU11x8; build EndPacket; } # (v4,6) and -- "Pd4 = and ( Ps4 , and ( Pt4 , Pu4 ) )" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 0 1 1 0 1 0 1 1 0 0 0 1 + + s s P P 0 - - - t t u u - - - - d d +# 0 1 1 0 1 0 1 1 0 0 0 1 - - s s P P 0 - - - t t u u - - - - d d # # (v4,6) and -- "Pd4 = and ( Ps4 , and ( Pt4 , ! Pu4 ) )" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 0 1 1 0 1 0 1 1 1 0 0 1 + + s s P P 0 - - - t t u u - - - - d d +# 0 1 1 0 1 0 1 1 1 0 0 1 - - s s P P 0 - - - t t u u - - - - d d # # (v4,6) and -- "Pd4 = and ( Ps4 , or ( Pt4 , Pu4 ) )" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 0 1 1 0 1 0 1 1 0 0 1 1 + + s s P P 0 - - - t t u u - - - - d d +# 0 1 1 0 1 0 1 1 0 0 1 1 - - s s P P 0 - - - t t u u - - - - d d # # (v4,6) and -- "Pd4 = and ( Ps4 , or ( Pt4 , ! Pu4 ) )" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 0 1 1 0 1 0 1 1 1 0 1 1 + + s s P P 0 - - - t t u u - - - - d d +# 0 1 1 0 1 0 1 1 1 0 1 1 - - s s P P 0 - - - t t u u - - - - d d -:and Pd2,pu1617,PredLogic_L21_S23_P0809_P0607 EndPacket is iclass=6 & op2427=0xb & op22=0 & op1820=4 & pu1617 & Pd2 & PredLogic_L21_S23_P0809_P0607 & $(END_PACKET) { +:and Pd2,pu1617,PredLogic_L21_S23_P0809_P0607 EndPacket is iclass=6 & op2427=0xb & op22=0 & op20=1 & pu1617 & Pd2 & PredLogic_L21_S23_P0809_P0607 & $(END_PACKET) { Pd2 = Pd2 & (pu1617 & PredLogic_L21_S23_P0809_P0607); build EndPacket; } @@ -2490,7 +2675,7 @@ MpyiRx32Rs32: "mpyi("rt5,rs5")" is rs5 & rt5 { # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| # 0 1 1 0 1 0 1 1 0 0 0 0 - - s s P P 0 - - - t t - - - - - - d d -:and Pd2,pu0809,pu1617 EndPacket is iclass=6 & op2127=0x58 & op1820=0 & op1013=0 & op0207=0 & pu0809 & pu1617 & Pd2 & $(END_PACKET) { +:and Pd2,pu0809,pu1617 EndPacket is iclass=6 & op2127=0x58 & op20=0 & op13=0 & pu0809 & pu1617 & Pd2 & $(END_PACKET) { Pd2 = Pd2 & (pu1617 & pu0809); build EndPacket; } @@ -2500,7 +2685,7 @@ MpyiRx32Rs32: "mpyi("rt5,rs5")" is rs5 & rt5 { # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| # 0 1 1 0 1 0 1 1 0 1 1 0 - - s s P P 0 - - - t t - - - - - - d d -:and Pd2,pu0809,NotPs2 EndPacket is iclass=6 & op2127=0x5b & op1820=0 & op1013=0 & op0207=0 & pu0809 & NotPs2 & Pd2 & $(END_PACKET) { +:and Pd2,pu0809,NotPs2 EndPacket is iclass=6 & op2127=0x5b & op20=0 & op13=0 & pu0809 & NotPs2 & Pd2 & $(END_PACKET) { Pd2 = Pd2 & (NotPs2 & pu0809); build EndPacket; } @@ -2558,9 +2743,9 @@ MpyiRx32Rs32: "mpyi("rt5,rs5")" is rs5 & rt5 { # (v4,14) and -- "Rx32 &= and ( Rs32 , Rt32 )" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 1 1 1 0 1 1 1 1 0 1 0 s s s s s P P + t t t t t + 0 0 x x x x x +# 1 1 1 0 1 1 1 1 0 1 0 s s s s s P P 0 t t t t t 0 0 0 x x x x x -:and&= Rd5,rs5,rt5 EndPacket is iclass=0xe & op2127=0x7a & op13=0 & op0507=0 & rs5 & rt5 & rd5 & Rd5 & $(END_PACKET) +:and&= Rd5,rs5,rt5 EndPacket is iclass=0xe & op2127=0x7a & op13=0 & op7=0 & op0506=0 & rs5 & rt5 & rd5 & Rd5 & $(END_PACKET) { Rd5 = rd5 & rs5 & rt5; build EndPacket; @@ -2569,9 +2754,9 @@ MpyiRx32Rs32: "mpyi("rt5,rs5")" is rs5 & rt5 { # (v4,14) and -- "Rx32 &= and ( Rs32 , ~ Rt32 )" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 1 1 1 0 1 1 1 1 0 0 1 s s s s s P P + t t t t t + 0 1 x x x x x +# 1 1 1 0 1 1 1 1 0 0 1 s s s s s P P 0 t t t t t 0 0 1 x x x x x -:and&= Rd5,rs5,OnesCompRt5 EndPacket is iclass=0xe & op2127=0x79 & op13=0 & op0507=1 & rs5 & OnesCompRt5 & rd5 & Rd5 & $(END_PACKET) +:and&= Rd5,rs5,OnesCompRt5 EndPacket is iclass=0xe & op2127=0x79 & op13=0 & op7=0 & op0506=1 & rs5 & OnesCompRt5 & rd5 & Rd5 & $(END_PACKET) { Rd5 = rd5 & rs5 & OnesCompRt5; build EndPacket; @@ -2585,9 +2770,9 @@ MpyiRx32Rs32: "mpyi("rt5,rs5")" is rs5 & rt5 { # (v4,13) and -- "Rx32 = and ( #u8x , lsr ( Rx32 , #U5 ) )" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 1 1 0 1 1 1 1 0 i i i x x x x x P P i I I I I I i i i 1 i 0 0 + +# 1 1 0 1 1 1 1 0 i i i x x x x x P P i I I I I I i i i 1 i 0 0 - -:and Rx5,Uimm32_2123_13_0507_03x,ShiftRx_D04_I0812 EndPacket is iclass=13 & op2427=14 & op0002=0 & Uimm32_2123_13_0507_03x & ShiftRx_D04_I0812 & Rx5 & $(END_PACKET) +:and Rx5,Uimm32_2123_13_0507_03x,ShiftRx_D04_I0812 EndPacket is iclass=13 & op2427=14 & op0102=0 & Uimm32_2123_13_0507_03x & ShiftRx_D04_I0812 & Rx5 & $(END_PACKET) { Rx5 = Uimm32_2123_13_0507_03x & ShiftRx_D04_I0812; build EndPacket; @@ -2596,9 +2781,9 @@ MpyiRx32Rs32: "mpyi("rt5,rs5")" is rs5 & rt5 { # (v4,14) and -- "Rx32 ^= and ( Rs32 , Rt32 )" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 1 1 1 0 1 1 1 1 1 1 0 s s s s s P P + t t t t t + 1 0 x x x x x +# 1 1 1 0 1 1 1 1 1 1 0 s s s s s P P 0 t t t t t 0 1 0 x x x x x -:and"^=" Rd5,rs5,rt5 EndPacket is iclass=0xe & op2127=0x7e & op13=0 & op0507=2 & rs5 & rt5 & rd5 & Rd5 & $(END_PACKET) +:and"^=" Rd5,rs5,rt5 EndPacket is iclass=0xe & op2127=0x7e & op13=0 & op7=0 & op0506=2 & rs5 & rt5 & rd5 & Rd5 & $(END_PACKET) { Rd5 = rd5 ^ (rs5 & rt5); build EndPacket; @@ -2607,9 +2792,9 @@ MpyiRx32Rs32: "mpyi("rt5,rs5")" is rs5 & rt5 { # (v4,14) and -- "Rx32 ^= and ( Rs32 , ~ Rt32 )" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 1 1 1 0 1 1 1 1 0 0 1 s s s s s P P + t t t t t + 1 0 x x x x x +# 1 1 1 0 1 1 1 1 0 0 1 s s s s s P P 0 t t t t t 0 1 0 x x x x x -:and"^=" Rd5,rs5,OnesCompRt5 EndPacket is iclass=0xe & op2127=0x79 & op13=0 & op0507=2 & rs5 & OnesCompRt5 & rd5 & Rd5 & $(END_PACKET) +:and"^=" Rd5,rs5,OnesCompRt5 EndPacket is iclass=0xe & op2127=0x79 & op13=0 & op7=0 & op0506=2 & rs5 & OnesCompRt5 & rd5 & Rd5 & $(END_PACKET) { Rd5 = rd5 ^ (rs5 & OnesCompRt5); build EndPacket; @@ -2628,9 +2813,9 @@ MpyiRx32Rs32: "mpyi("rt5,rs5")" is rs5 & rt5 { # (v4,14) and -- "Rx32 |= and ( Rs32 , Rt32 )" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 1 1 1 0 1 1 1 1 0 1 0 s s s s s P P + t t t t t + 1 1 x x x x x +# 1 1 1 0 1 1 1 1 0 1 0 s s s s s P P 0 t t t t t 0 1 1 x x x x x -:and|= Rd5,rs5,rt5 EndPacket is iclass=0xe & op2127=0x7a & op13=0 & op0507=3 & rs5 & rt5 & rd5 & Rd5 & $(END_PACKET) +:and|= Rd5,rs5,rt5 EndPacket is iclass=0xe & op2127=0x7a & op13=0 & op7=0 & op0506=3 & rs5 & rt5 & rd5 & Rd5 & $(END_PACKET) { Rd5 = rd5 | (rs5 & rt5); build EndPacket; @@ -2639,9 +2824,9 @@ MpyiRx32Rs32: "mpyi("rt5,rs5")" is rs5 & rt5 { # (v4,14) and -- "Rx32 |= and ( Rs32 , ~ Rt32 )" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 1 1 1 0 1 1 1 1 0 0 1 s s s s s P P + t t t t t + 0 0 x x x x x +# 1 1 1 0 1 1 1 1 0 0 1 s s s s s P P 0 t t t t t 0 0 0 x x x x x -:and|= Rd5,rs5,OnesCompRt5 EndPacket is iclass=0xe & op2127=0x79 & op13=0 & op0507=0 & rs5 & OnesCompRt5 & rd5 & Rd5 & $(END_PACKET) +:and|= Rd5,rs5,OnesCompRt5 EndPacket is iclass=0xe & op2127=0x79 & op13=0 & op7=0 & op0506=0 & rs5 & OnesCompRt5 & rd5 & Rd5 & $(END_PACKET) { Rd5 = rd5 | (rs5 & OnesCompRt5); build EndPacket; @@ -2650,31 +2835,33 @@ MpyiRx32Rs32: "mpyi("rt5,rs5")" is rs5 & rt5 { # (v2,15) and -- "if ( Pu4 ) Rd32 = and ( Rs32 , Rt32 )" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 1 1 1 1 1 0 0 1 + 0 0 s s s s s P P 0 t t t t t 0 u u d d d d d +# 1 1 1 1 1 0 0 1 - 0 0 s s s s s P P 0 t t t t t 0 u u d d d d d # # (v2,15) and -- "if ( ! Pu4 ) Rd32 = and ( Rs32 , Rt32 )" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 1 1 1 1 1 0 0 1 + 0 0 s s s s s P P 0 t t t t t 1 u u d d d d d +# 1 1 1 1 1 0 0 1 - 0 0 s s s s s P P 0 t t t t t 1 u u d d d d d # # (v2,15) and -- "if ( Pu4 .new ) Rd32 = and ( Rs32 , Rt32 )" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 1 1 1 1 1 0 0 1 + 0 0 s s s s s P P 1 t t t t t 0 u u d d d d d +# 1 1 1 1 1 0 0 1 - 0 0 s s s s s P P 1 t t t t t 0 u u d d d d d # # (v2,15) and -- "if ( ! Pu4 .new ) Rd32 = and ( Rs32 , Rt32 )" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 1 1 1 1 1 0 0 1 + 0 0 s s s s s P P 1 t t t t t 1 u u d d d d d +# 1 1 1 1 1 0 0 1 - 0 0 s s s s s P P 1 t t t t t 1 u u d d d d d -:and^PuCond0506_N13_S07 rd5,rs5,rt5 EndPacket is iclass=15 & op2327=0x12 & op22=0 & op21=0 & PuCond0506_N13_S07 & rs5 & rt5 & rd5 & rd5_ & SetNRegRd5 & $(END_PACKET) { +:and^PuCond0506_N13_S07 rd5,rs5,rt5 EndPacket is iclass=15 & op2427=0x9 & op22=0 & op21=0 & PuCond0506_N13_S07 & rs5 & rt5 & rd5 & rd5_ & SetNRegRd5 & $(END_PACKET) { build PuCond0506_N13_S07; build EndPacket; <> + build PuCond0506_N13_S07; if (ConditionReg == 0) goto ; rd5_ = rs5 & rt5; <> + build PuCond0506_N13_S07; if (ConditionReg == 0) goto ; rd5 = rd5_; @@ -2683,23 +2870,23 @@ MpyiRx32Rs32: "mpyi("rt5,rs5")" is rs5 & rt5 { # (v2,6) any8 -- "Pd4 = any8 ( Ps4 )" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 0 1 1 0 1 0 1 1 1 0 0 0 + + s s P P 0 + + + + + + + + + + + d d +# 0 1 1 0 1 0 1 1 1 0 0 0 - - s s P P 0 - - - - - - - - - - - d d -:any8 Pd2,pu1617 EndPacket is iclass=6 & op2127=0x5c & op1820=0 & op0213=0 & pu1617 & Pd2 & $(END_PACKET) { +:any8 Pd2,pu1617 EndPacket is iclass=6 & op2127=0x5c & op20=0 & op13=0 & pu1617 & Pd2 & $(END_PACKET) { Pd2 = Pd2 & ((pu1617 != 0) * 0xff); build EndPacket; } -# any8 -- "Pd4 = any8 ( vcmpb.eq ( Rss32 , Rtt32 ) )" +# (v4,13) any8 -- "Pd4 = any8 ( vcmpb.eq ( Rss32 , Rtt32 ) )" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 1 1 0 1 0 0 1 0 0 + + s s s s s P P 1 t t t t t 0 0 0 + + + d d +# 1 1 0 1 0 0 1 0 0 - - s s s s s P P 1 t t t t t 0 0 0 - - - d d define pcodeop vcmpb.eq; VcmpbEq: "vcmpb.eq("^rss5,rtt5^")" is rss5 & rtt5 { tmp:1 = vcmpb.eq(rss5,rtt5); export tmp; } -:any8 Pd2,VcmpbEq EndPacket is iclass=13 & op2127=0x10 & op13=1 & op0207=0 & rss5 & rtt5 & Pd2 & VcmpbEq & $(END_PACKET) { +:any8 Pd2,VcmpbEq EndPacket is iclass=13 & op2327=0x4 & op13=1 & op0507=0 & rss5 & rtt5 & Pd2 & VcmpbEq & $(END_PACKET) { Pd2 = Pd2 & ((VcmpbEq != 0) * 0xff); build EndPacket; } @@ -2709,19 +2896,18 @@ VcmpbEq: "vcmpb.eq("^rss5,rtt5^")" is rss5 & rtt5 { tmp:1 = vcmpb.eq(rss5,rtt5) # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| # 1 1 0 1 0 0 1 0 0 - - s s s s s P P 1 t t t t t 0 0 1 - - - d d -:any8! Pd2,VcmpbEq EndPacket is iclass=13 & op2127=0x10 & op13=1 & op0207=8 & rss5 & rtt5 & Pd2 & VcmpbEq & $(END_PACKET) { +:any8! Pd2,VcmpbEq EndPacket is iclass=13 & op2327=0x4 & op13=1 & op0507=1 & rss5 & rtt5 & Pd2 & VcmpbEq & $(END_PACKET) { Pd2 = Pd2 & ~((VcmpbEq != 0) * 0xff); build EndPacket; } - # (v2,8) rol -- "Rd32 = rol ( Rs32 , #u5 )" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| # 1 0 0 0 1 1 0 0 0 0 0 s s s s s P P 0 i i i i i 0 1 1 d d d d d :rol Rd5,rs5,Uimm8_0812 EndPacket is iclass=8 & op2127=0x60 & op13=0 & op0507=3 & Rd5 & rs5 & Uimm8_0812 & $(END_PACKET) { - Rd5 = (rs5 << Uimm8_0812) | zext((rs5 s< 0) * 1); + Rd5 = (rs5 << Uimm8_0812) | (rs5 >> (32 - Uimm8_0812)); build EndPacket; } @@ -2750,20 +2936,21 @@ define pcodeop aslSat; # (v2,12) asl -- "Rd32 = asl ( Rs32 , Rt32 )" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 1 1 0 0 0 1 1 0 0 1 + s s s s s P P + t t t t t 1 0 + d d d d d +# 1 1 0 0 0 1 1 0 0 1 - s s s s s P P - t t t t t 1 0 - d d d d d -:asl Rd5,rs5,rt5 EndPacket is iclass=12 & op2127=0x32 & op13=0 & op0507=4 & Rd5 & rs5 & rt5 & $(END_PACKET) { - right:1 = rt5 s< 0; - Rd5 = (zext(right) * (rs5 s>> -rt5)) + (zext(!right) * (rs5 << rt5)); +:asl Rd5,rs5,rt5 EndPacket is iclass=12 & op2227=0x19 & op0607=2 & Rd5 & rs5 & rt5 & $(END_PACKET) { + shamt:4 = (rt5 << 25) s>> 25; + right:1 = shamt s< 0; + Rd5 = (zext(right) * (rs5 s>> -shamt)) + (zext(!right) * (rs5 << shamt)); build EndPacket; } # (v2,12) asl -- "Rd32 = asl ( Rs32 , Rt32 ) :sat" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 1 1 0 0 0 1 1 0 0 0 + s s s s s P P + t t t t t 1 0 + d d d d d +# 1 1 0 0 0 1 1 0 0 0 - s s s s s P P - t t t t t 1 0 - d d d d d -:asl":sat" Rd5,rs5,rt5 EndPacket is iclass=12 & op2127=0x30 & op13=0 & op0507=4 & Rd5 & rs5 & rt5 & $(END_PACKET) { +:asl":sat" Rd5,rs5,rt5 EndPacket is iclass=12 & op2227=0x18 & op0607=2 & Rd5 & rs5 & rt5 & $(END_PACKET) { Rd5 = aslSat(rs5, rt5); build EndPacket; } @@ -2771,9 +2958,9 @@ define pcodeop aslSat; # (v2,8) asl -- "Rdd32 = asl ( Rss32 , #u6 )" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 1 0 0 0 0 0 0 0 0 0 + s s s s s P P i i i i i i 0 1 0 d d d d d +# 1 0 0 0 0 0 0 0 0 0 0 s s s s s P P i i i i i i 0 1 0 d d d d d -:asl Rdd5,rss5,Uimm8_0813 EndPacket is iclass=8 & op2127=0x00 & op0507=2 & Rdd5 & rss5 & Uimm8_0813 & $(END_PACKET) { +:asl Rdd5,rss5,Uimm8_0813 EndPacket is iclass=8 & op2227=0x0 & op21=0 & op0507=2 & Rdd5 & rss5 & Uimm8_0813 & $(END_PACKET) { Rdd5 = rss5 << Uimm8_0813; build EndPacket; } @@ -2781,30 +2968,31 @@ define pcodeop aslSat; # (v2,8) rol -- "Rdd32 = rol ( Rss32 , #u6 )" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 1 0 0 0 0 0 0 0 0 0 + s s s s s P P i i i i i i 0 1 1 d d d d d +# 1 0 0 0 0 0 0 0 0 0 0 s s s s s P P i i i i i i 0 1 1 d d d d d -:rol Rdd5,rss5,Uimm8_0813 EndPacket is iclass=8 & op2127=0x00 & op0507=3 & Rdd5 & rss5 & Uimm8_0813 & $(END_PACKET) { - Rdd5 = (rss5 << Uimm8_0813) | zext((rss5 s< 0) * 1); +:rol Rdd5,rss5,Uimm8_0813 EndPacket is iclass=8 & op2227=0x0 & op21=0 & op0507=3 & Rdd5 & rss5 & Uimm8_0813 & $(END_PACKET) { + Rdd5 = (rss5 << Uimm8_0813) | (rss5 >> (64 - Uimm8_0813)); build EndPacket; } # (v2,12) asl -- "Rdd32 = asl ( Rss32 , Rt32 )" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 1 1 0 0 0 0 1 1 1 0 + s s s s s P P + t t t t t 1 0 + d d d d d +# 1 1 0 0 0 0 1 1 1 0 - s s s s s P P - t t t t t 1 0 - d d d d d -:asl Rdd5,rss5,rt5 EndPacket is iclass=12 & op2127=0x1c & op13=0 & op0507=4 & Rdd5 & rss5 & rt5 & $(END_PACKET) { - right:1 = rt5 s< 0; - Rdd5 = (zext(right) * (rss5 s>> -rt5)) + (zext(!right) * (rss5 << rt5)); +:asl Rdd5,rss5,rt5 EndPacket is iclass=12 & op2227=0xe & op0607=2 & Rdd5 & rss5 & rt5 & $(END_PACKET) { + shamt:4 = (rt5 << 25) s>> 25; + right:1 = shamt s< 0; + Rdd5 = (zext(right) * (rss5 s>> -shamt)) + (zext(!right) * (rss5 << shamt)); build EndPacket; } # (v2,8) asl -- "Rx32 &= asl ( Rs32 , #u5 )" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 1 0 0 0 1 1 1 0 0 1 + s s s s s P P 0 i i i i i 0 1 0 x x x x x +# 1 0 0 0 1 1 1 0 0 1 - s s s s s P P 0 i i i i i 0 1 0 x x x x x -:asl&= Rd5,rs5,Uimm8_0812 EndPacket is iclass=8 & op2127=0x72 & op13=0 & op0507=2 & Rd5 & rd5 & rs5 & Uimm8_0812 & $(END_PACKET) { +:asl&= Rd5,rs5,Uimm8_0812 EndPacket is iclass=8 & op2227=0x39 & op13=0 & op0507=2 & Rd5 & rd5 & rs5 & Uimm8_0812 & $(END_PACKET) { Rd5 = rd5 & (rs5 << Uimm8_0812); build EndPacket; } @@ -2812,21 +3000,22 @@ define pcodeop aslSat; # (v2,8) rol -- "Rx32 &= rol ( Rs32 , #u5 )" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 1 0 0 0 1 1 1 0 0 1 + s s s s s P P 0 i i i i i 0 1 1 x x x x x +# 1 0 0 0 1 1 1 0 0 1 - s s s s s P P 0 i i i i i 0 1 1 x x x x x -:rol&= Rd5,rs5,Uimm8_0812 EndPacket is iclass=8 & op2127=0x72 & op13=0 & op0507=3 & Rd5 & rd5 & rs5 & Uimm8_0812 & $(END_PACKET) { - Rd5 = rd5 & ((rs5 << Uimm8_0812) | zext((rs5 s<0) * 1)); +:rol&= Rd5,rs5,Uimm8_0812 EndPacket is iclass=8 & op2227=0x39 & op13=0 & op0507=3 & Rd5 & rd5 & rs5 & Uimm8_0812 & $(END_PACKET) { + Rd5 = rd5 & ((rs5 << Uimm8_0812) | (rs5 >> (32 - Uimm8_0812))); build EndPacket; } # (v2,12) asl -- "Rx32 &= asl ( Rs32 , Rt32 )" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 1 1 0 0 1 1 0 0 0 1 + s s s s s P P + t t t t t 1 0 + x x x x x +# 1 1 0 0 1 1 0 0 0 1 - s s s s s P P - t t t t t 1 0 - x x x x x -:asl&= Rd5,rs5,rt5 EndPacket is iclass=12 & op2127=0x62 & op13=0 & op0507=4 & Rd5 & rd5 & rs5 & rt5 & $(END_PACKET) { - right:1 = rt5 s< 0; - result:4 = (zext(right) * (rs5 s>> -rt5)) + (zext(!right) * (rs5 << rt5)); +:asl&= Rd5,rs5,rt5 EndPacket is iclass=12 & op2227=0x31 & op0607=2 & Rd5 & rd5 & rs5 & rt5 & $(END_PACKET) { + shamt:4 = (rt5 << 25) s>> 25; + right:1 = shamt s< 0; + result:4 = (zext(right) * (rs5 s>> -shamt)) + (zext(!right) * (rs5 << shamt)); Rd5 = rd5 & result; build EndPacket; } @@ -2834,9 +3023,9 @@ define pcodeop aslSat; # (v2,8) asl -- "Rx32 += asl ( Rs32 , #u5 )" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 1 0 0 0 1 1 1 0 0 0 + s s s s s P P 0 i i i i i 1 1 0 x x x x x +# 1 0 0 0 1 1 1 0 0 0 - s s s s s P P 0 i i i i i 1 1 0 x x x x x -:asl+= Rd5,rs5,Uimm8_0812 EndPacket is iclass=8 & op2127=0x70 & op13=0 & op0507=6 & Rd5 & rd5 & rs5 & Uimm8_0812 & $(END_PACKET) { +:asl+= Rd5,rs5,Uimm8_0812 EndPacket is iclass=8 & op2227=0x38 & op13=0 & op0507=6 & Rd5 & rd5 & rs5 & Uimm8_0812 & $(END_PACKET) { Rd5 = rd5 + (rs5 << Uimm8_0812); build EndPacket; } @@ -2844,21 +3033,22 @@ define pcodeop aslSat; # (v2,8) rol -- "Rx32 += rol ( Rs32 , #u5 )" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 1 0 0 0 1 1 1 0 0 0 + s s s s s P P 0 i i i i i 1 1 1 x x x x x +# 1 0 0 0 1 1 1 0 0 0 - s s s s s P P 0 i i i i i 1 1 1 x x x x x -:rol+= Rd5,rs5,Uimm8_0812 EndPacket is iclass=8 & op2127=0x70 & op13=0 & op0507=7 & Rd5 & rd5 & rs5 & Uimm8_0812 & $(END_PACKET) { - Rd5 = rd5 + ((rs5 << Uimm8_0812) | zext((rs5 s< 0) * 1)); +:rol+= Rd5,rs5,Uimm8_0812 EndPacket is iclass=8 & op2227=0x38 & op13=0 & op0507=7 & Rd5 & rd5 & rs5 & Uimm8_0812 & $(END_PACKET) { + Rd5 = rd5 + ((rs5 << Uimm8_0812) | (rs5 >> (32 - Uimm8_0812))); build EndPacket; } # (v2,12) asl -- "Rx32 += asl ( Rs32 , Rt32 )" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 1 1 0 0 1 1 0 0 1 1 + s s s s s P P + t t t t t 1 0 + x x x x x +# 1 1 0 0 1 1 0 0 1 1 - s s s s s P P - t t t t t 1 0 - x x x x x -:asl+= Rd5,rs5,rt5 EndPacket is iclass=12 & op2127=0x66 & op13=0 & op0507=4 & Rd5 & rd5 & rs5 & rt5 & $(END_PACKET) { - right:1 = rt5 s< 0; - result:4 = (zext(right) * (rs5 s>> -rt5)) + (zext(!right) * (rs5 << rt5)); +:asl+= Rd5,rs5,rt5 EndPacket is iclass=12 & op2227=0x33 & op0607=2 & Rd5 & rd5 & rs5 & rt5 & $(END_PACKET) { + shamt:4 = (rt5 << 25) s>> 25; + right:1 = shamt s< 0; + result:4 = (zext(right) * (rs5 s>> -shamt)) + (zext(!right) * (rs5 << shamt)); Rd5 = rd5 + result; build EndPacket; } @@ -2866,9 +3056,9 @@ define pcodeop aslSat; # (v2,8) asl -- "Rx32 -= asl ( Rs32 , #u5 )" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 1 0 0 0 1 1 1 0 0 0 + s s s s s P P 0 i i i i i 0 1 0 x x x x x +# 1 0 0 0 1 1 1 0 0 0 - s s s s s P P 0 i i i i i 0 1 0 x x x x x -:asl-= Rd5,rs5,Uimm8_0812 EndPacket is iclass=8 & op2127=0x70 & op13=0 & op0507=2 & Rd5 & rd5 & rs5 & Uimm8_0812 & $(END_PACKET) { +:asl-= Rd5,rs5,Uimm8_0812 EndPacket is iclass=8 & op2227=0x38 & op13=0 & op0507=2 & Rd5 & rd5 & rs5 & Uimm8_0812 & $(END_PACKET) { Rd5 = rd5 - (rs5 << Uimm8_0812); build EndPacket; } @@ -2876,21 +3066,22 @@ define pcodeop aslSat; # (v2,8) rol -- "Rx32 -= rol ( Rs32 , #u5 )" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 1 0 0 0 1 1 1 0 0 0 + s s s s s P P 0 i i i i i 0 1 1 x x x x x +# 1 0 0 0 1 1 1 0 0 0 - s s s s s P P 0 i i i i i 0 1 1 x x x x x -:rol-= Rd5,rs5,Uimm8_0812 EndPacket is iclass=8 & op2127=0x70 & op13=0 & op0507=3 & Rd5 & rd5 & rs5 & Uimm8_0812 & $(END_PACKET) { - Rd5 = rd5 - ((rs5 << Uimm8_0812) | zext((rs5 s< 0) * 1)); +:rol-= Rd5,rs5,Uimm8_0812 EndPacket is iclass=8 & op2227=0x38 & op13=0 & op0507=3 & Rd5 & rd5 & rs5 & Uimm8_0812 & $(END_PACKET) { + Rd5 = rd5 - ((rs5 << Uimm8_0812) | (rs5 >> (32 - Uimm8_0812))); build EndPacket; } # (v2,12) asl -- "Rx32 -= asl ( Rs32 , Rt32 )" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 1 1 0 0 1 1 0 0 1 0 + s s s s s P P + t t t t t 1 0 + x x x x x +# 1 1 0 0 1 1 0 0 1 0 - s s s s s P P - t t t t t 1 0 - x x x x x -:asl-= Rd5,rs5,rt5 EndPacket is iclass=12 & op2127=0x64 & op13=0 & op0507=4 & Rd5 & rd5 & rs5 & rt5 & $(END_PACKET) { - right:1 = rt5 s< 0; - result:4 = (zext(right) * (rs5 s>> -rt5)) + (zext(!right) * (rs5 << rt5)); +:asl-= Rd5,rs5,rt5 EndPacket is iclass=12 & op2227=0x32 & op0607=2 & Rd5 & rd5 & rs5 & rt5 & $(END_PACKET) { + shamt:4 = (rt5 << 25) s>> 25; + right:1 = shamt s< 0; + result:4 = (zext(right) * (rs5 s>> -shamt)) + (zext(!right) * (rs5 << shamt)); Rd5 = rd5 - result; build EndPacket; } @@ -2898,9 +3089,9 @@ define pcodeop aslSat; # (v2,8) asl -- "Rx32 ^= asl ( Rs32 , #u5 )" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 1 0 0 0 1 1 1 0 1 0 + s s s s s P P 0 i i i i i 0 1 0 x x x x x +# 1 0 0 0 1 1 1 0 1 0 - s s s s s P P 0 i i i i i 0 1 0 x x x x x -:asl"^=" Rd5,rs5,Uimm8_0812 EndPacket is iclass=8 & op2127=0x74 & op13=0 & op0507=2 & Rd5 & rd5 & rs5 & Uimm8_0812 & $(END_PACKET) { +:asl"^=" Rd5,rs5,Uimm8_0812 EndPacket is iclass=8 & op2227=0x3a & op13=0 & op0507=2 & Rd5 & rd5 & rs5 & Uimm8_0812 & $(END_PACKET) { Rd5 = rd5 ^ (rs5 << Uimm8_0812); build EndPacket; } @@ -2908,19 +3099,19 @@ define pcodeop aslSat; # (v2,8) rol -- "Rx32 ^= rol ( Rs32 , #u5 )" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 1 0 0 0 1 1 1 0 1 0 + s s s s s P P 0 i i i i i 0 1 1 x x x x x +# 1 0 0 0 1 1 1 0 1 0 - s s s s s P P 0 i i i i i 0 1 1 x x x x x -:rol"^=" Rd5,rs5,Uimm8_0812 EndPacket is iclass=8 & op2127=0x74 & op13=0 & op0507=3 & Rd5 & rd5 & rs5 & Uimm8_0812 & $(END_PACKET) { - Rd5 = rd5 ^ ((rs5 << Uimm8_0812) | zext((rs5 s< 0) * 1)); +:rol"^=" Rd5,rs5,Uimm8_0812 EndPacket is iclass=8 & op2227=0x3a & op13=0 & op0507=3 & Rd5 & rd5 & rs5 & Uimm8_0812 & $(END_PACKET) { + Rd5 = rd5 ^ ((rs5 << Uimm8_0812) | (rs5 >> (32 - Uimm8_0812))); build EndPacket; } # (v2,8) asl -- "Rx32 |= asl ( Rs32 , #u5 )" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 1 0 0 0 1 1 1 0 0 1 + s s s s s P P 0 i i i i i 1 1 0 x x x x x +# 1 0 0 0 1 1 1 0 0 1 - s s s s s P P 0 i i i i i 1 1 0 x x x x x -:asl|= Rd5,rs5,Uimm8_0812 EndPacket is iclass=8 & op2127=0x72 & op13=0 & op0507=6 & Rd5 & rd5 & rs5 & Uimm8_0812 & $(END_PACKET) { +:asl|= Rd5,rs5,Uimm8_0812 EndPacket is iclass=8 & op2227=0x39 & op13=0 & op0507=6 & Rd5 & rd5 & rs5 & Uimm8_0812 & $(END_PACKET) { Rd5 = rd5 | (rs5 << Uimm8_0812); build EndPacket; } @@ -2928,21 +3119,22 @@ define pcodeop aslSat; # (v2,8) rol -- "Rx32 |= rol ( Rs32 , #u5 )" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 1 0 0 0 1 1 1 0 0 1 + s s s s s P P 0 i i i i i 1 1 1 x x x x x +# 1 0 0 0 1 1 1 0 0 1 - s s s s s P P 0 i i i i i 1 1 1 x x x x x -:rol|= Rd5,rs5,Uimm8_0812 EndPacket is iclass=8 & op2127=0x72 & op13=0 & op0507=7 & Rd5 & rd5 & rs5 & Uimm8_0812 & $(END_PACKET) { - Rd5 = rd5 | ((rs5 << Uimm8_0812) | zext((rs5 s< 0) * 1)); +:rol|= Rd5,rs5,Uimm8_0812 EndPacket is iclass=8 & op2227=0x39 & op13=0 & op0507=7 & Rd5 & rd5 & rs5 & Uimm8_0812 & $(END_PACKET) { + Rd5 = rd5 | ((rs5 << Uimm8_0812) | (rs5 >> (32 - Uimm8_0812))); build EndPacket; } # (v2,12) asl -- "Rx32 |= asl ( Rs32 , Rt32 )" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 1 1 0 0 1 1 0 0 0 0 + s s s s s P P + t t t t t 1 0 + x x x x x +# 1 1 0 0 1 1 0 0 0 0 - s s s s s P P - t t t t t 1 0 - x x x x x -:asl|= Rd5,rs5,rt5 EndPacket is iclass=12 & op2127=0x60 & op13=0 & op0507=4 & Rd5 & rd5 & rs5 & rt5 & $(END_PACKET) { - right:1 = rt5 s< 0; - result:4 = (zext(right) * (rs5 s>> -rt5)) + (zext(!right) * (rs5 << rt5)); +:asl|= Rd5,rs5,rt5 EndPacket is iclass=12 & op2227=0x30 & op0607=2 & Rd5 & rd5 & rs5 & rt5 & $(END_PACKET) { + shamt:4 = (rt5 << 25) s>> 25; + right:1 = shamt s< 0; + result:4 = (zext(right) * (rs5 s>> -shamt)) + (zext(!right) * (rs5 << shamt)); Rd5 = rd5 | result; build EndPacket; } @@ -2950,9 +3142,9 @@ define pcodeop aslSat; # (v2,8) asl -- "Rxx32 &= asl ( Rss32 , #u6 )" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 1 0 0 0 0 0 1 0 0 1 + s s s s s P P i i i i i i 0 1 0 x x x x x +# 1 0 0 0 0 0 1 0 0 1 - s s s s s P P i i i i i i 0 1 0 x x x x x -:asl&= Rdd5,rss5,Uimm8_0813 EndPacket is iclass=8 & op2127=0x12 & op0507=2 & Rdd5 & rdd5 & rss5 & Uimm8_0813 & $(END_PACKET) { +:asl&= Rdd5,rss5,Uimm8_0813 EndPacket is iclass=8 & op2227=0x9 & op0507=2 & Rdd5 & rdd5 & rss5 & Uimm8_0813 & $(END_PACKET) { Rdd5 = rdd5 & (rss5 << Uimm8_0813); build EndPacket; } @@ -2960,21 +3152,22 @@ define pcodeop aslSat; # (v2,8) rol -- "Rxx32 &= rol ( Rss32 , #u6 )" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 1 0 0 0 0 0 1 0 0 1 + s s s s s P P i i i i i i 0 1 1 x x x x x +# 1 0 0 0 0 0 1 0 0 1 - s s s s s P P i i i i i i 0 1 1 x x x x x -:rol&= Rdd5,rss5,Uimm8_0813 EndPacket is iclass=8 & op2127=0x12 & op0507=3 & Rdd5 & rdd5 & rss5 & Uimm8_0813 & $(END_PACKET) { - Rdd5 = rdd5 & ((rss5 << Uimm8_0813) | zext((rss5 s< 0) * 1)); +:rol&= Rdd5,rss5,Uimm8_0813 EndPacket is iclass=8 & op2227=0x9 & op0507=3 & Rdd5 & rdd5 & rss5 & Uimm8_0813 & $(END_PACKET) { + Rdd5 = rdd5 & ((rss5 << Uimm8_0813) | (rss5 >> (64 - Uimm8_0813))); build EndPacket; } # (v2,12) asl -- "Rxx32 &= asl ( Rss32 , Rt32 )" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 1 1 0 0 1 0 1 1 0 1 0 s s s s s P P + t t t t t 1 0 + x x x x x +# 1 1 0 0 1 0 1 1 0 1 0 s s s s s P P - t t t t t 1 0 - x x x x x -:asl&= Rdd5,rss5,rt5 EndPacket is iclass=12 & op2127=0x5a & op13=0 & op0507=4 & Rdd5 & rdd5 & rss5 & rt5 & $(END_PACKET) { - right:1 = rt5 s< 0; - result:8 = (zext(right) * (rss5 s>> -rt5)) + (zext(!right) * (rss5 << rt5)); +:asl&= Rdd5,rss5,rt5 EndPacket is iclass=12 & op2127=0x5a & op0607=2 & Rdd5 & rdd5 & rss5 & rt5 & $(END_PACKET) { + shamt:4 = (rt5 << 25) s>> 25; + right:1 = shamt s< 0; + result:8 = (zext(right) * (rss5 s>> -shamt)) + (zext(!right) * (rss5 << shamt)); Rdd5 = rdd5 & result; build EndPacket; } @@ -2982,9 +3175,9 @@ define pcodeop aslSat; # (v2,8) asl -- "Rxx32 += asl ( Rss32 , #u6 )" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 1 0 0 0 0 0 1 0 0 0 + s s s s s P P i i i i i i 1 1 0 x x x x x +# 1 0 0 0 0 0 1 0 0 0 - s s s s s P P i i i i i i 1 1 0 x x x x x -:asl+= Rdd5,rss5,Uimm8_0813 EndPacket is iclass=8 & op2127=0x10 & op0507=6 & Rdd5 & rdd5 & rss5 & Uimm8_0813 & $(END_PACKET) { +:asl+= Rdd5,rss5,Uimm8_0813 EndPacket is iclass=8 & op2227=0x8 & op0507=6 & Rdd5 & rdd5 & rss5 & Uimm8_0813 & $(END_PACKET) { Rdd5 = rdd5 + (rss5 << Uimm8_0813); build EndPacket; } @@ -2992,21 +3185,22 @@ define pcodeop aslSat; # (v2,8) rol -- "Rxx32 += rol ( Rss32 , #u6 )" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 1 0 0 0 0 0 1 0 0 0 + s s s s s P P i i i i i i 1 1 1 x x x x x +# 1 0 0 0 0 0 1 0 0 0 - s s s s s P P i i i i i i 1 1 1 x x x x x -:rol+= Rdd5,rss5,Uimm8_0813 EndPacket is iclass=8 & op2127=0x10 & op0507=7 & Rdd5 & rdd5 & rss5 & Uimm8_0813 & $(END_PACKET) { - Rdd5 = rdd5 + ((rss5 << Uimm8_0813) | zext((rss5 s< 0) * 1)); +:rol+= Rdd5,rss5,Uimm8_0813 EndPacket is iclass=8 & op2227=0x8 & op0507=7 & Rdd5 & rdd5 & rss5 & Uimm8_0813 & $(END_PACKET) { + Rdd5 = rdd5 + ((rss5 << Uimm8_0813) | (rss5 >> (64 - Uimm8_0813))); build EndPacket; } # (v2,12) asl -- "Rxx32 += asl ( Rss32 , Rt32 )" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 1 1 0 0 1 0 1 1 1 1 0 s s s s s P P + t t t t t 1 0 + x x x x x +# 1 1 0 0 1 0 1 1 1 1 0 s s s s s P P - t t t t t 1 0 - x x x x x -:asl+= Rdd5,rss5,rt5 EndPacket is iclass=12 & op2127=0x5e & op13=0 & op0507=4 & Rdd5 & rdd5 & rss5 & rt5 & $(END_PACKET) { - right:1 = rt5 s< 0; - result:8 = (zext(right) * (rss5 s>> -rt5)) + (zext(!right) * (rss5 << rt5)); +:asl+= Rdd5,rss5,rt5 EndPacket is iclass=12 & op2127=0x5e & op0607=2 & Rdd5 & rdd5 & rss5 & rt5 & $(END_PACKET) { + shamt:4 = (rt5 << 25) s>> 25; + right:1 = shamt s< 0; + result:8 = (zext(right) * (rss5 s>> -shamt)) + (zext(!right) * (rss5 << shamt)); Rdd5 = rdd5 + result; build EndPacket; } @@ -3014,9 +3208,9 @@ define pcodeop aslSat; # (v2,8) asl -- "Rxx32 -= asl ( Rss32 , #u6 )" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 1 0 0 0 0 0 1 0 0 0 + s s s s s P P i i i i i i 0 1 0 x x x x x +# 1 0 0 0 0 0 1 0 0 0 - s s s s s P P i i i i i i 0 1 0 x x x x x -:asl-= Rdd5,rss5,Uimm8_0813 EndPacket is iclass=8 & op2127=0x10 & op0507=2 & Rdd5 & rdd5 & rss5 & Uimm8_0813 & $(END_PACKET) { +:asl-= Rdd5,rss5,Uimm8_0813 EndPacket is iclass=8 & op2227=0x8 & op0507=2 & Rdd5 & rdd5 & rss5 & Uimm8_0813 & $(END_PACKET) { Rdd5 = rdd5 - (rss5 << Uimm8_0813); build EndPacket; } @@ -3024,21 +3218,22 @@ define pcodeop aslSat; # (v2,8) rol -- "Rxx32 -= rol ( Rss32 , #u6 )" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 1 0 0 0 0 0 1 0 0 0 + s s s s s P P i i i i i i 0 1 1 x x x x x +# 1 0 0 0 0 0 1 0 0 0 - s s s s s P P i i i i i i 0 1 1 x x x x x -:rol-= Rdd5,rss5,Uimm8_0813 EndPacket is iclass=8 & op2127=0x10 & op0507=3 & Rdd5 & rdd5 & rss5 & Uimm8_0813 & $(END_PACKET) { - Rdd5 = rdd5 - ((rss5 << Uimm8_0813) | zext((rss5 s< 0) * 1)); +:rol-= Rdd5,rss5,Uimm8_0813 EndPacket is iclass=8 & op2227=0x8 & op0507=3 & Rdd5 & rdd5 & rss5 & Uimm8_0813 & $(END_PACKET) { + Rdd5 = rdd5 - ((rss5 << Uimm8_0813) | (rss5 >> (64 - Uimm8_0813))); build EndPacket; } # (v2,12) asl -- "Rxx32 -= asl ( Rss32 , Rt32 )" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 1 1 0 0 1 0 1 1 1 0 0 s s s s s P P + t t t t t 1 0 + x x x x x +# 1 1 0 0 1 0 1 1 1 0 0 s s s s s P P - t t t t t 1 0 - x x x x x -:asl-= Rdd5,rss5,rt5 EndPacket is iclass=12 & op2127=0x5c & op13=0 & op0507=4 & Rdd5 & rdd5 & rss5 & rt5 & $(END_PACKET) { - right:1 = rt5 s< 0; - result:8 = (zext(right) * (rss5 s>> -rt5)) + (zext(!right) * (rss5 << rt5)); +:asl-= Rdd5,rss5,rt5 EndPacket is iclass=12 & op2127=0x5c & op0607=2 & Rdd5 & rdd5 & rss5 & rt5 & $(END_PACKET) { + shamt:4 = (rt5 << 25) s>> 25; + right:1 = shamt s< 0; + result:8 = (zext(right) * (rss5 s>> -shamt)) + (zext(!right) * (rss5 << shamt)); Rdd5 = rdd5 - result; build EndPacket; } @@ -3046,9 +3241,9 @@ define pcodeop aslSat; # (v2,8) asl -- "Rxx32 ^= asl ( Rss32 , #u6 )" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 1 0 0 0 0 0 1 0 1 0 + s s s s s P P i i i i i i 0 1 0 x x x x x +# 1 0 0 0 0 0 1 0 1 0 - s s s s s P P i i i i i i 0 1 0 x x x x x -:asl"^=" Rdd5,rss5,Uimm8_0813 EndPacket is iclass=8 & op2127=0x14 & op0507=2 & Rdd5 & rdd5 & rss5 & Uimm8_0813 & $(END_PACKET) { +:asl"^=" Rdd5,rss5,Uimm8_0813 EndPacket is iclass=8 & op2227=0xa & op0507=2 & Rdd5 & rdd5 & rss5 & Uimm8_0813 & $(END_PACKET) { Rdd5 = rdd5 ^ (rss5 << Uimm8_0813); build EndPacket; } @@ -3056,21 +3251,22 @@ define pcodeop aslSat; # (v2,8) rol -- "Rxx32 ^= rol ( Rss32 , #u6 )" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 1 0 0 0 0 0 1 0 1 0 + s s s s s P P i i i i i i 0 1 1 x x x x x +# 1 0 0 0 0 0 1 0 1 0 - s s s s s P P i i i i i i 0 1 1 x x x x x -:rol"^=" Rdd5,rss5,Uimm8_0813 EndPacket is iclass=8 & op2127=0x14 & op0507=3 & Rdd5 & rdd5 & rss5 & Uimm8_0813 & $(END_PACKET) { - Rdd5 = rdd5 ^ ((rss5 << Uimm8_0813) | zext((rss5 s< 0) * 1)); +:rol"^=" Rdd5,rss5,Uimm8_0813 EndPacket is iclass=8 & op2227=0xa & op0507=3 & Rdd5 & rdd5 & rss5 & Uimm8_0813 & $(END_PACKET) { + Rdd5 = rdd5 ^ ((rss5 << Uimm8_0813) | (rss5 >> (64 - Uimm8_0813))); build EndPacket; } # (v4,12) asl -- "Rxx32 ^= asl ( Rss32 , Rt32 )" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 1 1 0 0 1 0 1 1 0 1 1 s s s s s P P + t t t t t 1 0 + x x x x x +# 1 1 0 0 1 0 1 1 0 1 1 s s s s s P P - t t t t t 1 0 - x x x x x -:asl"^=" Rdd5,rss5,rt5 EndPacket is iclass=12 & op2127=0x5b & op13=0 & op0507=4 & Rdd5 & rdd5 & rss5 & rt5 & $(END_PACKET) { - right:1 = rt5 s< 0; - result:8 = (zext(right) * (rss5 s>> -rt5)) + (zext(!right) * (rss5 << rt5)); +:asl"^=" Rdd5,rss5,rt5 EndPacket is iclass=12 & op2127=0x5b & op0607=2 & Rdd5 & rdd5 & rss5 & rt5 & $(END_PACKET) { + shamt:4 = (rt5 << 25) s>> 25; + right:1 = shamt s< 0; + result:8 = (zext(right) * (rss5 s>> -shamt)) + (zext(!right) * (rss5 << shamt)); Rdd5 = rdd5 ^ result; build EndPacket; } @@ -3078,9 +3274,9 @@ define pcodeop aslSat; # (v2,8) asl -- "Rxx32 |= asl ( Rss32 , #u6 )" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 1 0 0 0 0 0 1 0 0 1 + s s s s s P P i i i i i i 1 1 0 x x x x x +# 1 0 0 0 0 0 1 0 0 1 - s s s s s P P i i i i i i 1 1 0 x x x x x -:asl|= Rdd5,rss5,Uimm8_0813 EndPacket is iclass=8 & op2127=0x12 & op0507=6 & Rdd5 & rdd5 & rss5 & Uimm8_0813 & $(END_PACKET) { +:asl|= Rdd5,rss5,Uimm8_0813 EndPacket is iclass=8 & op2227=0x9 & op0507=6 & Rdd5 & rdd5 & rss5 & Uimm8_0813 & $(END_PACKET) { Rdd5 = rdd5 | (rss5 << Uimm8_0813); build EndPacket; } @@ -3088,21 +3284,22 @@ define pcodeop aslSat; # (v2,8) rol -- "Rxx32 |= rol ( Rss32 , #u6 )" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 1 0 0 0 0 0 1 0 0 1 + s s s s s P P i i i i i i 1 1 1 x x x x x +# 1 0 0 0 0 0 1 0 0 1 - s s s s s P P i i i i i i 1 1 1 x x x x x -:rol|= Rdd5,rss5,Uimm8_0813 EndPacket is iclass=8 & op2127=0x12 & op0507=7 & Rdd5 & rdd5 & rss5 & Uimm8_0813 & $(END_PACKET) { - Rdd5 = rdd5 | ((rss5 << Uimm8_0813) | zext((rss5 s< 0) * 1)); +:rol|= Rdd5,rss5,Uimm8_0813 EndPacket is iclass=8 & op2227=0x9 & op0507=7 & Rdd5 & rdd5 & rss5 & Uimm8_0813 & $(END_PACKET) { + Rdd5 = rdd5 | ((rss5 << Uimm8_0813) | (rss5 >> (64 - Uimm8_0813))); build EndPacket; } # (v2,12) asl -- "Rxx32 |= asl ( Rss32 , Rt32 )" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 1 1 0 0 1 0 1 1 0 0 0 s s s s s P P + t t t t t 1 0 + x x x x x +# 1 1 0 0 1 0 1 1 0 0 0 s s s s s P P - t t t t t 1 0 - x x x x x -:asl|= Rdd5,rss5,rt5 EndPacket is iclass=12 & op2127=0x58 & op13=0 & op0507=4 & Rdd5 & rdd5 & rss5 & rt5 & $(END_PACKET) { - right:1 = rt5 s< 0; - result:8 = (zext(right) * (rss5 s>> -rt5)) + (zext(!right) * (rss5 << rt5)); +:asl|= Rdd5,rss5,rt5 EndPacket is iclass=12 & op2127=0x58 & op0607=2 & Rdd5 & rdd5 & rss5 & rt5 & $(END_PACKET) { + shamt:4 = (rt5 << 25) s>> 25; + right:1 = shamt s< 0; + result:8 = (zext(right) * (rss5 s>> -shamt)) + (zext(!right) * (rss5 << shamt)); Rdd5 = rdd5 | result; build EndPacket; } @@ -3110,9 +3307,9 @@ define pcodeop aslSat; # (v2,7) aslh -- "Rd32 = aslh ( Rs32 )" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 0 1 1 1 0 0 0 0 0 0 0 s s s s s P P 0 + + + + + + + + d d d d d +# 0 1 1 1 0 0 0 0 0 0 0 s s s s s P P 0 - - - - - - - - d d d d d -:aslh Rd5,rs5 EndPacket is iclass=7 & op2127=0 & op13=0 & op0512=0 & Rd5 & rs5 & $(END_PACKET) { +:aslh Rd5,rs5 EndPacket is iclass=7 & op2127=0 & op13=0 & Rd5 & rs5 & $(END_PACKET) { Rd5 = rs5 << 16; build EndPacket; } @@ -3141,10 +3338,12 @@ define pcodeop aslSat; build PuCond0809_N10_S11; build EndPacket; <> + build PuCond0809_N10_S11; if (ConditionReg == 0) goto ; rd5_ = rs5 << 16; <> + build PuCond0809_N10_S11; if (ConditionReg == 0) goto ; rd5 = rd5_; @@ -3183,22 +3382,23 @@ define pcodeop aslSat; # (v2,12) asr -- "Rd32 = asr ( Rs32 , Rt32 )" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 1 1 0 0 0 1 1 0 0 1 + s s s s s P P + t t t t t 0 0 + d d d d d +# 1 1 0 0 0 1 1 0 0 1 - s s s s s P P - t t t t t 0 0 - d d d d d -:asr Rd5,rs5,rt5 EndPacket is iclass=12 & op2127=0x32 & op13=0 & op0507=0 & Rd5 & rs5 & rt5 & $(END_PACKET) { - left:1 = rt5 s< 0; - Rd5 = (zext(!left) * (rs5 s>> rt5)) + (zext(left) * (rs5 << -rt5)); +:asr Rd5,rs5,rt5 EndPacket is iclass=12 & op2227=0x19 & op0607=0 & Rd5 & rs5 & rt5 & $(END_PACKET) { + shamt:4 = (rt5 << 25) s>> 25; + left:1 = shamt s< 0; + Rd5 = (zext(!left) * (rs5 s>> shamt)) + (zext(left) * (rs5 << -shamt)); build EndPacket; } # (v2,12) asr -- "Rd32 = asr ( Rs32 , Rt32 ) :sat" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 1 1 0 0 0 1 1 0 0 0 + s s s s s P P + t t t t t 0 0 + d d d d d +# 1 1 0 0 0 1 1 0 0 0 - s s s s s P P - t t t t t 0 0 - d d d d d define pcodeop asrSat; -:asr":sat" Rd5,rs5,rt5 EndPacket is iclass=12 & op2127=0x30 & op13=0 & op0507=0 & Rd5 & rs5 & rt5 & $(END_PACKET) { +:asr":sat" Rd5,rs5,rt5 EndPacket is iclass=12 & op2227=0x18 & op0607=0 & Rd5 & rs5 & rt5 & $(END_PACKET) { Rd5 = asrSat(rs5, rt5); build EndPacket; } @@ -3206,9 +3406,9 @@ define pcodeop asrSat; # (v2,8) asr -- "Rdd32 = asr ( Rss32 , #u6 )" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 1 0 0 0 0 0 0 0 0 0 + s s s s s P P i i i i i i 0 0 0 d d d d d +# 1 0 0 0 0 0 0 0 0 0 0 s s s s s P P i i i i i i 0 0 0 d d d d d -:asr Rdd5,rss5,Uimm8_0813 EndPacket is iclass=8 & op2127=0x00 & op0507=0 & Rdd5 & rss5 & Uimm8_0813 & $(END_PACKET) { +:asr Rdd5,rss5,Uimm8_0813 EndPacket is iclass=8 & op2227=0x0 & op21=0 & op0507=0 & Rdd5 & rss5 & Uimm8_0813 & $(END_PACKET) { Rdd5 = rss5 s>> Uimm8_0813; build EndPacket; } @@ -3216,20 +3416,21 @@ define pcodeop asrSat; # (v2,12) asr -- "Rdd32 = asr ( Rss32 , Rt32 )" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 1 1 0 0 0 0 1 1 1 0 + s s s s s P P + t t t t t 0 0 + d d d d d +# 1 1 0 0 0 0 1 1 1 0 - s s s s s P P - t t t t t 0 0 - d d d d d -:asr Rdd5,rss5,rt5 EndPacket is iclass=12 & op2127=0x1c & op13=0 & op0507=0 & Rdd5 & rss5 & rt5 & $(END_PACKET) { - left:1 = rt5 s< 0; - Rdd5 = (zext(!left) * (rss5 s>> rt5)) + (zext(left) * (rss5 << -rt5)); +:asr Rdd5,rss5,rt5 EndPacket is iclass=12 & op2227=0xe & op0607=0 & Rdd5 & rss5 & rt5 & $(END_PACKET) { + shamt:4 = (rt5 << 25) s>> 25; + left:1 = shamt s< 0; + Rdd5 = (zext(!left) * (rss5 s>> shamt)) + (zext(left) * (rss5 << -shamt)); build EndPacket; } # (v2,8) asr -- "Rx32 &= asr ( Rs32 , #u5 )" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 1 0 0 0 1 1 1 0 0 1 + s s s s s P P 0 i i i i i 0 0 0 x x x x x +# 1 0 0 0 1 1 1 0 0 1 - s s s s s P P 0 i i i i i 0 0 0 x x x x x -:asr&= Rd5,rs5,Uimm8_0812 EndPacket is iclass=8 & op2127=0x72 & op13=0 & op0507=0 & Rd5 & rd5 & rs5 & Uimm8_0812 & $(END_PACKET) { +:asr&= Rd5,rs5,Uimm8_0812 EndPacket is iclass=8 & op2227=0x39 & op13=0 & op0507=0 & Rd5 & rd5 & rs5 & Uimm8_0812 & $(END_PACKET) { Rd5 = rd5 & (rs5 s>> Uimm8_0812); build EndPacket; } @@ -3237,11 +3438,12 @@ define pcodeop asrSat; # (v2,12) asr -- "Rx32 &= asr ( Rs32 , Rt32 )" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 1 1 0 0 1 1 0 0 0 1 + s s s s s P P + t t t t t 0 0 + x x x x x +# 1 1 0 0 1 1 0 0 0 1 - s s s s s P P - t t t t t 0 0 - x x x x x -:asr&= Rd5,rs5,rt5 EndPacket is iclass=12 & op2127=0x62 & op13=0 & op0507=0 & Rd5 & rd5 & rs5 & rt5 & $(END_PACKET) { - left:1 = rt5 s< 0; - result:4 = (zext(!left) * (rs5 s>> rt5)) + (zext(left) * (rs5 << -rt5)); +:asr&= Rd5,rs5,rt5 EndPacket is iclass=12 & op2227=0x31 & op0607=0 & Rd5 & rd5 & rs5 & rt5 & $(END_PACKET) { + shamt:4 = (rt5 << 25) s>> 25; + left:1 = shamt s< 0; + result:4 = (zext(!left) * (rs5 s>> shamt)) + (zext(left) * (rs5 << -shamt)); Rd5 = rd5 & result; build EndPacket; } @@ -3249,9 +3451,9 @@ define pcodeop asrSat; # (v2,8) asr -- "Rx32 += asr ( Rs32 , #u5 )" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 1 0 0 0 1 1 1 0 0 0 + s s s s s P P 0 i i i i i 1 0 0 x x x x x +# 1 0 0 0 1 1 1 0 0 0 - s s s s s P P 0 i i i i i 1 0 0 x x x x x -:asr+= Rd5,rs5,Uimm8_0812 EndPacket is iclass=8 & op2127=0x70 & op13=0 & op0507=4 & Rd5 & rd5 & rs5 & Uimm8_0812 & $(END_PACKET) { +:asr+= Rd5,rs5,Uimm8_0812 EndPacket is iclass=8 & op2227=0x38 & op13=0 & op0507=4 & Rd5 & rd5 & rs5 & Uimm8_0812 & $(END_PACKET) { Rd5 = rd5 + (rs5 s>> Uimm8_0812); build EndPacket; } @@ -3259,11 +3461,12 @@ define pcodeop asrSat; # (v2,12) asr -- "Rx32 += asr ( Rs32 , Rt32 )" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 1 1 0 0 1 1 0 0 1 1 + s s s s s P P + t t t t t 0 0 + x x x x x +# 1 1 0 0 1 1 0 0 1 1 - s s s s s P P - t t t t t 0 0 - x x x x x -:asr+= Rd5,rs5,rt5 EndPacket is iclass=12 & op2127=0x66 & op13=0 & op0507=0 & Rd5 & rd5 & rs5 & rt5 & $(END_PACKET) { - left:1 = rt5 s< 0; - result:4 = (zext(!left) * (rs5 s>> rt5)) + (zext(left) * (rs5 << -rt5)); +:asr+= Rd5,rs5,rt5 EndPacket is iclass=12 & op2227=0x33 & op0607=0 & Rd5 & rd5 & rs5 & rt5 & $(END_PACKET) { + shamt:4 = (rt5 << 25) s>> 25; + left:1 = shamt s< 0; + result:4 = (zext(!left) * (rs5 s>> shamt)) + (zext(left) * (rs5 << -shamt)); Rd5 = rd5 + result; build EndPacket; } @@ -3271,9 +3474,9 @@ define pcodeop asrSat; # (v2,8) asr -- "Rx32 -= asr ( Rs32 , #u5 )" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 1 0 0 0 1 1 1 0 0 0 + s s s s s P P 0 i i i i i 0 0 0 x x x x x +# 1 0 0 0 1 1 1 0 0 0 - s s s s s P P 0 i i i i i 0 0 0 x x x x x -:asr-= Rd5,rs5,Uimm8_0812 EndPacket is iclass=8 & op2127=0x70 & op13=0 & op0507=0 & Rd5 & rd5 & rs5 & Uimm8_0812 & $(END_PACKET) { +:asr-= Rd5,rs5,Uimm8_0812 EndPacket is iclass=8 & op2227=0x38 & op13=0 & op0507=0 & Rd5 & rd5 & rs5 & Uimm8_0812 & $(END_PACKET) { Rd5 = rd5 - (rs5 s>> Uimm8_0812); build EndPacket; } @@ -3281,11 +3484,12 @@ define pcodeop asrSat; # (v2,12) asr -- "Rx32 -= asr ( Rs32 , Rt32 )" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 1 1 0 0 1 1 0 0 1 0 + s s s s s P P + t t t t t 0 0 + x x x x x +# 1 1 0 0 1 1 0 0 1 0 - s s s s s P P - t t t t t 0 0 - x x x x x -:asr-= Rd5,rs5,rt5 EndPacket is iclass=12 & op2127=0x64 & op13=0 & op0507=0 & Rd5 & rd5 & rs5 & rt5 & $(END_PACKET) { - left:1 = rt5 s< 0; - result:4 = (zext(!left) * (rs5 s>> rt5)) + (zext(left) * (rs5 << -rt5)); +:asr-= Rd5,rs5,rt5 EndPacket is iclass=12 & op2227=0x32 & op0607=0 & Rd5 & rd5 & rs5 & rt5 & $(END_PACKET) { + shamt:4 = (rt5 << 25) s>> 25; + left:1 = shamt s< 0; + result:4 = (zext(!left) * (rs5 s>> shamt)) + (zext(left) * (rs5 << -shamt)); Rd5 = rd5 - result; build EndPacket; } @@ -3293,9 +3497,9 @@ define pcodeop asrSat; # (v2,8) asr -- "Rx32 |= asr ( Rs32 , #u5 )" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 1 0 0 0 1 1 1 0 0 1 + s s s s s P P 0 i i i i i 1 0 0 x x x x x +# 1 0 0 0 1 1 1 0 0 1 - s s s s s P P 0 i i i i i 1 0 0 x x x x x -:asr|= Rd5,rs5,Uimm8_0812 EndPacket is iclass=8 & op2127=0x72 & op13=0 & op0507=4 & Rd5 & rd5 & rs5 & Uimm8_0812 & $(END_PACKET) { +:asr|= Rd5,rs5,Uimm8_0812 EndPacket is iclass=8 & op2227=0x39 & op13=0 & op0507=4 & Rd5 & rd5 & rs5 & Uimm8_0812 & $(END_PACKET) { Rd5 = rd5 | (rs5 s>> Uimm8_0812); build EndPacket; } @@ -3303,11 +3507,12 @@ define pcodeop asrSat; # (v2,12) asr -- "Rx32 |= asr ( Rs32 , Rt32 )" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 1 1 0 0 1 1 0 0 0 0 + s s s s s P P + t t t t t 0 0 + x x x x x +# 1 1 0 0 1 1 0 0 0 0 - s s s s s P P - t t t t t 0 0 - x x x x x -:asr|= Rd5,rs5,rt5 EndPacket is iclass=12 & op2127=0x60 & op13=0 & op0507=0 & Rd5 & rd5 & rs5 & rt5 & $(END_PACKET) { - left:1 = rt5 s< 0; - result:4 = (zext(!left) * (rs5 s>> rt5)) + (zext(left) * (rs5 << -rt5)); +:asr|= Rd5,rs5,rt5 EndPacket is iclass=12 & op2227=0x30 & op0607=0 & Rd5 & rd5 & rs5 & rt5 & $(END_PACKET) { + shamt:4 = (rt5 << 25) s>> 25; + left:1 = shamt s< 0; + result:4 = (zext(!left) * (rs5 s>> shamt)) + (zext(left) * (rs5 << -shamt)); Rd5 = rd5 | result; build EndPacket; } @@ -3315,9 +3520,9 @@ define pcodeop asrSat; # (v2,8) asr -- "Rxx32 &= asr ( Rss32 , #u6 )" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 1 0 0 0 0 0 1 0 0 1 + s s s s s P P i i i i i i 0 0 0 x x x x x +# 1 0 0 0 0 0 1 0 0 1 - s s s s s P P i i i i i i 0 0 0 x x x x x -:asr&= Rdd5,rss5,Uimm8_0813 EndPacket is iclass=8 & op2127=0x12 & op0507=0 & Rdd5 & rdd5 & rss5 & Uimm8_0813 & $(END_PACKET) { +:asr&= Rdd5,rss5,Uimm8_0813 EndPacket is iclass=8 & op2227=0x9 & op0507=0 & Rdd5 & rdd5 & rss5 & Uimm8_0813 & $(END_PACKET) { Rdd5 = rdd5 & (rss5 s>> Uimm8_0813); build EndPacket; } @@ -3325,11 +3530,12 @@ define pcodeop asrSat; # (v2,12) asr -- "Rxx32 &= asr ( Rss32 , Rt32 )" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 1 1 0 0 1 0 1 1 0 1 0 s s s s s P P + t t t t t 0 0 + x x x x x +# 1 1 0 0 1 0 1 1 0 1 0 s s s s s P P - t t t t t 0 0 - x x x x x -:asr&= Rdd5,rss5,rt5 EndPacket is iclass=12 & op2127=0x5a & op13=0 & op0507=0 & Rdd5 & rdd5 & rss5 & rt5 & $(END_PACKET) { - left:1 = rt5 s< 0; - result:8 = (zext(!left) * (rss5 s>> rt5)) + (zext(left) * (rss5 << -rt5)); +:asr&= Rdd5,rss5,rt5 EndPacket is iclass=12 & op2127=0x5a & op0607=0 & Rdd5 & rdd5 & rss5 & rt5 & $(END_PACKET) { + shamt:4 = (rt5 << 25) s>> 25; + left:1 = shamt s< 0; + result:8 = (zext(!left) * (rss5 s>> shamt)) + (zext(left) * (rss5 << -shamt)); Rdd5 = rdd5 & result; build EndPacket; } @@ -3337,9 +3543,9 @@ define pcodeop asrSat; # (v2,8) asr -- "Rxx32 += asr ( Rss32 , #u6 )" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 1 0 0 0 0 0 1 0 0 0 + s s s s s P P i i i i i i 1 0 0 x x x x x +# 1 0 0 0 0 0 1 0 0 0 - s s s s s P P i i i i i i 1 0 0 x x x x x -:asr+= Rdd5,rss5,Uimm8_0813 EndPacket is iclass=8 & op2127=0x10 & op0507=4 & Rdd5 & rdd5 & rss5 & Uimm8_0813 & $(END_PACKET) { +:asr+= Rdd5,rss5,Uimm8_0813 EndPacket is iclass=8 & op2227=0x8 & op0507=4 & Rdd5 & rdd5 & rss5 & Uimm8_0813 & $(END_PACKET) { Rdd5 = rdd5 + (rss5 s>> Uimm8_0813); build EndPacket; } @@ -3347,11 +3553,12 @@ define pcodeop asrSat; # (v2,12) asr -- "Rxx32 += asr ( Rss32 , Rt32 )" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 1 1 0 0 1 0 1 1 1 1 0 s s s s s P P + t t t t t 0 0 + x x x x x +# 1 1 0 0 1 0 1 1 1 1 0 s s s s s P P - t t t t t 0 0 - x x x x x -:asr+= Rdd5,rss5,rt5 EndPacket is iclass=12 & op2127=0x5e & op13=0 & op0507=0 & Rdd5 & rdd5 & rss5 & rt5 & $(END_PACKET) { - left:1 = rt5 s< 0; - result:8 = (zext(!left) * (rss5 s>> rt5)) + (zext(left) * (rss5 << -rt5)); +:asr+= Rdd5,rss5,rt5 EndPacket is iclass=12 & op2127=0x5e & op0607=0 & Rdd5 & rdd5 & rss5 & rt5 & $(END_PACKET) { + shamt:4 = (rt5 << 25) s>> 25; + left:1 = shamt s< 0; + result:8 = (zext(!left) * (rss5 s>> shamt)) + (zext(left) * (rss5 << -shamt)); Rdd5 = rdd5 + result; build EndPacket; } @@ -3359,9 +3566,9 @@ define pcodeop asrSat; # (v2,8) asr -- "Rxx32 -= asr ( Rss32 , #u6 )" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 1 0 0 0 0 0 1 0 0 0 + s s s s s P P i i i i i i 0 0 0 x x x x x +# 1 0 0 0 0 0 1 0 0 0 - s s s s s P P i i i i i i 0 0 0 x x x x x -:asr-= Rdd5,rss5,Uimm8_0813 EndPacket is iclass=8 & op2127=0x10 & op0507=0 & Rdd5 & rdd5 & rss5 & Uimm8_0813 & $(END_PACKET) { +:asr-= Rdd5,rss5,Uimm8_0813 EndPacket is iclass=8 & op2227=0x8 & op0507=0 & Rdd5 & rdd5 & rss5 & Uimm8_0813 & $(END_PACKET) { Rdd5 = rdd5 - (rss5 s>> Uimm8_0813); build EndPacket; } @@ -3369,11 +3576,12 @@ define pcodeop asrSat; # (v2,12) asr -- "Rxx32 -= asr ( Rss32 , Rt32 )" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 1 1 0 0 1 0 1 1 1 0 0 s s s s s P P + t t t t t 0 0 + x x x x x +# 1 1 0 0 1 0 1 1 1 0 0 s s s s s P P - t t t t t 0 0 - x x x x x -:asr-= Rdd5,rss5,rt5 EndPacket is iclass=12 & op2127=0x5c & op13=0 & op0507=0 & Rdd5 & rdd5 & rss5 & rt5 & $(END_PACKET) { - left:1 = rt5 s< 0; - result:8 = (zext(!left) * (rss5 s>> rt5)) + (zext(left) * (rss5 << -rt5)); +:asr-= Rdd5,rss5,rt5 EndPacket is iclass=12 & op2127=0x5c & op0607=0 & Rdd5 & rdd5 & rss5 & rt5 & $(END_PACKET) { + shamt:4 = (rt5 << 25) s>> 25; + left:1 = shamt s< 0; + result:8 = (zext(!left) * (rss5 s>> shamt)) + (zext(left) * (rss5 << -shamt)); Rdd5 = rdd5 - result; build EndPacket; } @@ -3381,11 +3589,12 @@ define pcodeop asrSat; # (v4,12) asr -- "Rxx32 ^= asr ( Rss32 , Rt32 )" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 1 1 0 0 1 0 1 1 0 1 1 s s s s s P P + t t t t t 0 0 + x x x x x +# 1 1 0 0 1 0 1 1 0 1 1 s s s s s P P - t t t t t 0 0 - x x x x x -:asr"^=" Rdd5,rss5,rt5 EndPacket is iclass=12 & op2127=0x5b & op13=0 & op0507=0 & Rdd5 & rdd5 & rss5 & rt5 & $(END_PACKET) { - left:1 = rt5 s< 0; - result:8 = (zext(!left) * (rss5 s>> rt5)) + (zext(left) * (rss5 << -rt5)); +:asr"^=" Rdd5,rss5,rt5 EndPacket is iclass=12 & op2127=0x5b & op0607=0 & Rdd5 & rdd5 & rss5 & rt5 & $(END_PACKET) { + shamt:4 = (rt5 << 25) s>> 25; + left:1 = shamt s< 0; + result:8 = (zext(!left) * (rss5 s>> shamt)) + (zext(left) * (rss5 << -shamt)); Rdd5 = rdd5 ^ result; build EndPacket; } @@ -3393,9 +3602,9 @@ define pcodeop asrSat; # (v2,8) asr -- "Rxx32 |= asr ( Rss32 , #u6 )" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 1 0 0 0 0 0 1 0 0 1 + s s s s s P P i i i i i i 1 0 0 x x x x x +# 1 0 0 0 0 0 1 0 0 1 - s s s s s P P i i i i i i 1 0 0 x x x x x -:asr|= Rdd5,rss5,Uimm8_0813 EndPacket is iclass=8 & op2127=0x12 & op0507=4 & Rdd5 & rdd5 & rss5 & Uimm8_0813 & $(END_PACKET) { +:asr|= Rdd5,rss5,Uimm8_0813 EndPacket is iclass=8 & op2227=0x9 & op0507=4 & Rdd5 & rdd5 & rss5 & Uimm8_0813 & $(END_PACKET) { Rdd5 = rdd5 | (rss5 s>> Uimm8_0813); build EndPacket; } @@ -3403,11 +3612,12 @@ define pcodeop asrSat; # (v2,12) asr -- "Rxx32 |= asr ( Rss32 , Rt32 )" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 1 1 0 0 1 0 1 1 0 0 0 s s s s s P P + t t t t t 0 0 + x x x x x +# 1 1 0 0 1 0 1 1 0 0 0 s s s s s P P - t t t t t 0 0 - x x x x x -:asr|= Rdd5,rss5,rt5 EndPacket is iclass=12 & op2127=0x58 & op13=0 & op0507=0 & Rdd5 & rdd5 & rss5 & rt5 & $(END_PACKET) { - left:1 = rt5 s< 0; - result:8 = (zext(!left) * (rss5 s>> rt5)) + (zext(left) * (rss5 << -rt5)); +:asr|= Rdd5,rss5,rt5 EndPacket is iclass=12 & op2127=0x58 & op0607=0 & Rdd5 & rdd5 & rss5 & rt5 & $(END_PACKET) { + shamt:4 = (rt5 << 25) s>> 25; + left:1 = shamt s< 0; + result:8 = (zext(!left) * (rss5 s>> shamt)) + (zext(left) * (rss5 << -shamt)); Rdd5 = rdd5 | result; build EndPacket; } @@ -3415,9 +3625,9 @@ define pcodeop asrSat; # (v2,7) asrh -- "Rd32 = asrh ( Rs32 )" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 0 1 1 1 0 0 0 0 0 0 1 s s s s s P P 0 + + + + + + + + d d d d d +# 0 1 1 1 0 0 0 0 0 0 1 s s s s s P P 0 - - - - - - - - d d d d d -:asrh Rd5,rs5 EndPacket is iclass=7 & op2127=1 & op13=0 & op0512=0 & Rd5 & rs5 & $(END_PACKET) { +:asrh Rd5,rs5 EndPacket is iclass=7 & op2127=1 & op13=0 & Rd5 & rs5 & $(END_PACKET) { Rd5 = rs5 s>> 16; build EndPacket; } @@ -3446,10 +3656,12 @@ define pcodeop asrSat; build PuCond0809_N10_S11; build EndPacket; <> + build PuCond0809_N10_S11; if (ConditionReg == 0) goto ; rd5_ = rs5 s>> 16; <> + build PuCond0809_N10_S11; if (ConditionReg == 0) goto ; rd5 = rd5_; @@ -3458,9 +3670,9 @@ define pcodeop asrSat; # (v2,6) assign -- "Cd32 = Rs32" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 0 1 1 0 0 0 1 0 0 0 1 s s s s s P P + + + + + + + + + d d d d d +# 0 1 1 0 0 0 1 0 0 0 1 s s s s s P P - - - - - - - - - d d d d d -:assign Cd5,rs5 EndPacket is iclass=6 & op2127=0x11 & op0513=0 & Cd5 & rs5 & $(END_PACKET) { +:assign Cd5,rs5 EndPacket is iclass=6 & op2127=0x11 & Cd5 & rs5 & $(END_PACKET) { # NOTE: Assuming that PC will not be directly assigned Cd5 = rs5; build EndPacket; @@ -3469,9 +3681,9 @@ define pcodeop asrSat; # (v4,6) assign -- "Cdd32 = Rss32" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 0 1 1 0 0 0 1 1 0 0 1 s s s s s P P + + + + + + + + + d d d d d +# 0 1 1 0 0 0 1 1 0 0 1 s s s s s P P - - - - - - - - - d d d d d -:assign Cdd5,rss5 EndPacket is iclass=6 & op2127=0x19 & op0513=0 & Cdd5 & rss5 & $(END_PACKET) { +:assign Cdd5,rss5 EndPacket is iclass=6 & op2127=0x19 & Cdd5 & rss5 & $(END_PACKET) { # NOTE: Assuming that PC will not be directly assigned Cdd5 = rss5; build EndPacket; @@ -3480,9 +3692,9 @@ define pcodeop asrSat; # (v4,6) assign -- "Gd32 = Rs32" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 0 1 1 0 0 0 1 0 0 0 0 s s s s s P P + + + + + + + + + d d d d d +# 0 1 1 0 0 0 1 0 0 0 0 s s s s s P P - - - - - - - - - d d d d d -:assign Gd5,rs5 EndPacket is iclass=6 & op2127=0x10 & op0513=0 & Gd5 & rs5 & $(END_PACKET) { +:assign Gd5,rs5 EndPacket is iclass=6 & op2127=0x10 & Gd5 & rs5 & $(END_PACKET) { Gd5 = rs5; build EndPacket; } @@ -3490,9 +3702,9 @@ define pcodeop asrSat; # (v4,6) assign -- "Gdd32 = Rss32" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 0 1 1 0 0 0 1 1 0 0 0 s s s s s P P + + + + + + + + + d d d d d +# 0 1 1 0 0 0 1 1 0 0 0 s s s s s P P - - - - - - - - - d d d d d -:assign Gdd5,rss5 EndPacket is iclass=6 & op2127=0x18 & op0513=0 & Gdd5 & rss5 & $(END_PACKET) { +:assign Gdd5,rss5 EndPacket is iclass=6 & op2127=0x18 & Gdd5 & rss5 & $(END_PACKET) { Gdd5 = rss5; build EndPacket; } @@ -3500,9 +3712,9 @@ define pcodeop asrSat; # (v2,8) assign -- "Pd4 = Rs32" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 1 0 0 0 0 1 0 1 0 1 + s s s s s P P + + + + + + + + + + + + d d +# 1 0 0 0 0 1 0 1 0 1 0 s s s s s P P - - - - - - - - - - - - d d -:assign Pd2,rs5 EndPacket is iclass=8 & op2127=0x2a & rs5 & op0213=0 & Pd2 & $(END_PACKET) { +:assign Pd2,rs5 EndPacket is iclass=8 & op2227=0x15 & op21=0 & rs5 & Pd2 & $(END_PACKET) { Pd2 = Pd2 & rs5:1; build EndPacket; } @@ -3512,7 +3724,7 @@ define pcodeop asrSat; # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| # 0 1 1 1 1 0 0 0 i i - i i i i i P P i i i i i i i i i d d d d d -:assign Rd5,Simm32_2223_1620_0513x EndPacket is iclass=7 & op2427=8 & op21=0 & Rd5 & Simm32_2223_1620_0513x & $(END_PACKET) { +:assign Rd5,Simm32_2223_1620_0513x EndPacket is iclass=7 & op2427=8 & Rd5 & Simm32_2223_1620_0513x & $(END_PACKET) { Rd5 = Simm32_2223_1620_0513x; build EndPacket; } @@ -3520,9 +3732,9 @@ define pcodeop asrSat; # (v2,6) assign -- "Rd32 = Cs32" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 0 1 1 0 1 0 1 0 0 0 0 s s s s s P P + + + + + + + + + d d d d d +# 0 1 1 0 1 0 1 0 0 0 0 s s s s s P P - - - - - - - - - d d d d d -:assign Rd5,Cs5 EndPacket is iclass=6 & op2127=0x50 & op0513=0 & Rd5 & Cs5 & $(END_PACKET) { +:assign Rd5,Cs5 EndPacket is iclass=6 & op2127=0x50 & Rd5 & Cs5 & $(END_PACKET) { Rd5 = Cs5; build EndPacket; } @@ -3530,9 +3742,9 @@ define pcodeop asrSat; # (v4,6) assign -- "Rd32 = Gs32" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 0 1 1 0 1 0 1 0 0 0 1 s s s s s P P + + + + + + + + + d d d d d +# 0 1 1 0 1 0 1 0 0 0 1 s s s s s P P - - - - - - - - - d d d d d -:assign Rd5,gs5 EndPacket is iclass=6 & op2127=0x51 & op0513=0 & Rd5 & gs5 & $(END_PACKET) { +:assign Rd5,gs5 EndPacket is iclass=6 & op2127=0x51 & Rd5 & gs5 & $(END_PACKET) { Rd5 = gs5; build EndPacket; } @@ -3540,9 +3752,9 @@ define pcodeop asrSat; # (v2,8) assign -- "Rd32 = Ps4" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 1 0 0 0 1 0 0 1 + 1 + + + + s s P P + + + + + + + + + d d d d d +# 1 0 0 0 1 0 0 1 - 1 - - - - s s P P - - - - - - - - - d d d d d -:assign Rd5,pu1617 EndPacket is iclass=8 & op1827=0x250 & pu1617 & op0513=0 & Rd5 & $(END_PACKET) { +:assign Rd5,pu1617 EndPacket is iclass=8 & op2427=0x9 & op22=0x1 & pu1617 & Rd5 & $(END_PACKET) { Rd5 = zext( pu1617 ); build EndPacket; } @@ -3552,7 +3764,7 @@ define pcodeop asrSat; # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| # 0 1 1 1 0 0 0 0 0 1 1 s s s s s P P 0 - - - - - - - - d d d d d -:assign Rd5,rs5 EndPacket is iclass=7 & op2127=0x03 & op0513=0 & Rd5 & rs5 & $(END_PACKET) { +:assign Rd5,rs5 EndPacket is iclass=7 & op2127=0x03 & op13=0 & Rd5 & rs5 & $(END_PACKET) { Rd5 = rs5; build EndPacket; } @@ -3560,9 +3772,9 @@ define pcodeop asrSat; # (v2,6) assign -- "Rd32 = Ss64" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 0 1 1 0 1 1 1 0 1 + s s s s s s P P + + + + + + + + + d d d d d +# 0 1 1 0 1 1 1 0 1 - s s s s s s P P - - - - - - - - - d d d d d -:assign Rd5,ss6 EndPacket is iclass=6 & op2227=0x3a & op0513=0 & Rd5 & ss6 & $(END_PACKET) { +:assign Rd5,ss6 EndPacket is iclass=6 & op2327=0x1d & Rd5 & ss6 & $(END_PACKET) { Rd5 = ss6; build EndPacket; } @@ -3570,9 +3782,9 @@ define pcodeop asrSat; # (v4,6) assign -- "Rdd32 = Css32" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 0 1 1 0 1 0 0 0 0 0 0 s s s s s P P + + + + + + + + + d d d d d +# 0 1 1 0 1 0 0 0 0 0 0 s s s s s P P - - - - - - - - - d d d d d -:assign Rdd5,css5 EndPacket is iclass=6 & op2127=0x40 & op0513=0 & Rdd5 & css5 & $(END_PACKET) { +:assign Rdd5,css5 EndPacket is iclass=6 & op2127=0x40 & Rdd5 & css5 & $(END_PACKET) { Rdd5 = css5; build EndPacket; } @@ -3580,9 +3792,9 @@ define pcodeop asrSat; # (v4,6) assign -- "Rdd32 = Gss32" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 0 1 1 0 1 0 0 0 0 0 1 s s s s s P P + + + + + + + + + d d d d d +# 0 1 1 0 1 0 0 0 0 0 1 s s s s s P P - - - - - - - - - d d d d d -:assign Rdd5,gss5 EndPacket is iclass=6 & op2127=0x41 & op0513=0 & Rdd5 & gss5 & $(END_PACKET) { +:assign Rdd5,gss5 EndPacket is iclass=6 & op2127=0x41 & Rdd5 & gss5 & $(END_PACKET) { Rdd5 = gss5; build EndPacket; } @@ -3590,9 +3802,9 @@ define pcodeop asrSat; # (v4,6) assign -- "Rdd32 = Sss64" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 0 1 1 0 1 1 1 1 + + s s s s s s P P + + + + + + + + + d d d d d +# 0 1 1 0 1 1 1 1 - - s s s s s s P P - - - - - - - - - d d d d d -:assign Rdd5,sss6 EndPacket is iclass=6 & op2227=0x3c & op0513=0 & Rdd5 & sss6 & $(END_PACKET) { +:assign Rdd5,sss6 EndPacket is iclass=6 & op2427=0xf & Rdd5 & sss6 & $(END_PACKET) { Rdd5 = sss6; build EndPacket; } @@ -3620,9 +3832,9 @@ define pcodeop asrSat; # (v2,6) assign -- "Sd64 = Rs32" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 0 1 1 0 0 1 1 1 0 0 + s s s s s P P + + + + + + + + d d d d d d +# 0 1 1 0 0 1 1 1 0 0 - s s s s s P P - - - - - - - - d d d d d d -:assign Sd6,rs5 EndPacket is iclass=6 & op2127=0x38 & op0613=0 & Sd6 & rs5 & $(END_PACKET) { +:assign Sd6,rs5 EndPacket is iclass=6 & op2227=0x1c & Sd6 & rs5 & $(END_PACKET) { Sd6 = rs5; build EndPacket; } @@ -3630,9 +3842,9 @@ define pcodeop asrSat; # (v4,6) assign -- "Sdd64 = Rss32" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 0 1 1 0 1 1 0 1 0 + + s s s s s P P + + + + + + + + d d d d d d +# 0 1 1 0 1 1 0 1 0 - - s s s s s P P - - - - - - - - d d d d d d -:assign Sdd6,rss5 EndPacket is iclass=6 & op2127=0x68 & op0613=0 & Sdd6 & rss5 & $(END_PACKET) { +:assign Sdd6,rss5 EndPacket is iclass=6 & op2327=0x1a & Sdd6 & rss5 & $(END_PACKET) { Sdd6 = rss5; build EndPacket; } @@ -3661,10 +3873,12 @@ define pcodeop asrSat; build PuCond2122_N13_S23; build EndPacket; <> + build PuCond2122_N13_S23; if (ConditionReg == 0) goto ; rd5_ = Simm32_1619_0512x; <> + build PuCond2122_N13_S23; if (ConditionReg == 0) goto ; rd5 = rd5_; @@ -3673,11 +3887,11 @@ define pcodeop asrSat; # (v2,10) barrier -- "barrier" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 1 0 1 0 1 0 0 0 0 0 0 + + + + + P P + + + + + + + + + + + + + + +# 1 0 1 0 1 0 0 0 0 0 0 - - - - - P P - - - - - - 0 0 0 - - - - - define pcodeop barrier; -:barrier EndPacket is iclass=10 & op2127=0x40 & op1620=0 & op0013=0 & $(END_PACKET) { +:barrier EndPacket is iclass=10 & op2127=0x40 & op7=0 & op6=0 & op5=0 & $(END_PACKET) { barrier(); build EndPacket; } @@ -3685,9 +3899,9 @@ define pcodeop barrier; # (v2,8) bitsclr -- "Pd4 = bitsclr ( Rs32 , #u6 )" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 1 0 0 0 0 1 0 1 1 0 0 s s s s s P P i i i i i i + + + + + + d d +# 1 0 0 0 0 1 0 1 1 0 0 s s s s s P P i i i i i i - - - - - - d d -:bitsclr Pd2,rs5,Uimm8_0813 EndPacket is iclass=8 & op2127=0x2c & op0207=0 & rs5 & Uimm8_0813 & Pd2 & $(END_PACKET) { +:bitsclr Pd2,rs5,Uimm8_0813 EndPacket is iclass=8 & op2127=0x2c & rs5 & Uimm8_0813 & Pd2 & $(END_PACKET) { isClr:1 = (rs5 & zext(Uimm8_0813)) == 0; Pd2 = Pd2 & (isClr * 0xff); build EndPacket; @@ -3696,9 +3910,9 @@ define pcodeop barrier; # (v4,8) bitsclr -- "Pd4 = ! bitsclr ( Rs32 , #u6 )" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 1 0 0 0 0 1 0 1 1 0 1 s s s s s P P i i i i i i + + + + + + d d +# 1 0 0 0 0 1 0 1 1 0 1 s s s s s P P i i i i i i - - - - - - d d -:bitsclr! Pd2,rs5,Uimm8_0813 EndPacket is iclass=8 & op2127=0x2d & op0207=0 & rs5 & Uimm8_0813 & Pd2 & $(END_PACKET) { +:bitsclr! Pd2,rs5,Uimm8_0813 EndPacket is iclass=8 & op2127=0x2d & rs5 & Uimm8_0813 & Pd2 & $(END_PACKET) { notClr:1 = (rs5 & zext(Uimm8_0813)) != 0; Pd2 = Pd2 & (notClr * 0xff); build EndPacket; @@ -3707,9 +3921,9 @@ define pcodeop barrier; # (v2,12) bitsclr -- "Pd4 = bitsclr ( Rs32 , Rt32 )" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 1 1 0 0 0 1 1 1 1 0 0 s s s s s P P + t t t t t + + + + + + d d +# 1 1 0 0 0 1 1 1 1 0 0 s s s s s P P - t t t t t - - - - - - d d -:bitsclr Pd2,rs5,rt5 EndPacket is iclass=12 & op2127=0x3c & op13=0 & op0207=0 & rs5 & rt5 & Pd2 & $(END_PACKET) { +:bitsclr Pd2,rs5,rt5 EndPacket is iclass=12 & op2127=0x3c & rs5 & rt5 & Pd2 & $(END_PACKET) { isClr:1 = (rs5 & rt5) == 0; Pd2 = Pd2 & (isClr * 0xff); build EndPacket; @@ -3718,9 +3932,9 @@ define pcodeop barrier; # (v4,12) bitsclr -- "Pd4 = ! bitsclr ( Rs32 , Rt32 )" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 1 1 0 0 0 1 1 1 1 0 1 s s s s s P P + t t t t t + + + + + + d d +# 1 1 0 0 0 1 1 1 1 0 1 s s s s s P P - t t t t t - - - - - - d d -:bitsclr! Pd2,rs5,rt5 EndPacket is iclass=12 & op2127=0x3d & op13=0 & op0207=0 & rs5 & rt5 & Pd2 & $(END_PACKET) { +:bitsclr! Pd2,rs5,rt5 EndPacket is iclass=12 & op2127=0x3d & rs5 & rt5 & Pd2 & $(END_PACKET) { notClr:1 = (rs5 & rt5) != 0; Pd2 = Pd2 & (notClr * 0xff); build EndPacket; @@ -3729,9 +3943,9 @@ define pcodeop barrier; # (v4,8) bitsplit -- "Rdd32 = bitsplit ( Rs32 , #u5 )" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 1 0 0 0 1 0 0 0 1 1 0 s s s s s P P 0 i i i i i 1 0 + d d d d d +# 1 0 0 0 1 0 0 0 1 1 0 s s s s s P P 0 i i i i i 1 0 - d d d d d -:bitsplit Rdd5,rs5,Uimm8_0812 EndPacket is iclass=8 & op2127=0x46 & op13=0 & op0507=4 & Rdd5 & rdd5h_ & rd5_ & rs5 & Uimm8_0812 & $(END_PACKET) { +:bitsplit Rdd5,rs5,Uimm8_0812 EndPacket is iclass=8 & op2127=0x46 & op13=0 & op0607=2 & Rdd5 & rdd5h_ & rd5_ & rs5 & Uimm8_0812 & $(END_PACKET) { build Rdd5; # build Rdd5 and assign hi/lo words separately to aid analysis rdd5h_ = rs5 >> Uimm8_0812; mask:4 = ~(-1 << Uimm8_0812); @@ -3742,9 +3956,9 @@ define pcodeop barrier; # (v4,13) bitsplit -- "Rdd32 = bitsplit ( Rs32 , Rt32 )" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 1 1 0 1 0 1 0 0 + + 1 s s s s s P P + t t t t t + + + d d d d d +# 1 1 0 1 0 1 0 0 - - 1 s s s s s P P - t t t t t - - - d d d d d -:bitsplit Rdd5,rs5,rt5 EndPacket is iclass=13 & op2127=0x21 & op13=0 & op0507=0 & Rdd5 & rdd5h_ & rd5_ & rs5 & rt5 & $(END_PACKET) { +:bitsplit Rdd5,rs5,rt5 EndPacket is iclass=13 & op2427=0x4 & op21=0x1 & Rdd5 & rdd5h_ & rd5_ & rs5 & rt5 & $(END_PACKET) { build Rdd5; # build Rdd5 and assign hi/lo words separately to aid analysis cnt:4 = rt5 & 0x1f; rdd5h_ = rs5 >> cnt; @@ -3756,9 +3970,9 @@ define pcodeop barrier; # (v2,12) bitsset -- "Pd4 = bitsset ( Rs32 , Rt32 )" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 1 1 0 0 0 1 1 1 0 1 0 s s s s s P P + t t t t t + + + + + + d d +# 1 1 0 0 0 1 1 1 0 1 0 s s s s s P P - t t t t t - - - - - - d d -:bitsset Pd2,rs5,rt5 EndPacket is iclass=12 & op2127=0x3a & op13=0 & op0207=0 & rs5 & rt5 & Pd2 & $(END_PACKET) { +:bitsset Pd2,rs5,rt5 EndPacket is iclass=12 & op2127=0x3a & rs5 & rt5 & Pd2 & $(END_PACKET) { isSet:1 = (rs5 & rt5) == rt5; Pd2 = Pd2 & (isSet * 0xff); build EndPacket; @@ -3767,9 +3981,9 @@ define pcodeop barrier; # (v4,12) bitsset -- "Pd4 = ! bitsset ( Rs32 , Rt32 )" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 1 1 0 0 0 1 1 1 0 1 1 s s s s s P P + t t t t t + + + + + + d d +# 1 1 0 0 0 1 1 1 0 1 1 s s s s s P P - t t t t t - - - - - - d d -:bitsset! Pd2,rs5,rt5 EndPacket is iclass=12 & op2127=0x3b & op13=0 & op0207=0 & rs5 & rt5 & Pd2 & $(END_PACKET) { +:bitsset! Pd2,rs5,rt5 EndPacket is iclass=12 & op2127=0x3b & rs5 & rt5 & Pd2 & $(END_PACKET) { notSet:1 = (rs5 & rt5) != rt5; Pd2 = Pd2 & (notSet * 0xff); build EndPacket; @@ -3778,13 +3992,12 @@ define pcodeop barrier; # (v4,13) boundscheck -- "Pd4 = boundscheck ( Rss32 , Rtt32 ) :raw :hi" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 1 1 0 1 0 0 1 0 0 + + s s s s s P P 1 t t t t t 1 0 1 + + + d d +# 1 1 0 1 0 0 1 0 0 - - s s s s s P P 1 t t t t t 1 0 1 - - - d d -:boundscheck":raw:hi" Pd2,rss5,rtt5 EndPacket is iclass=13 & op2127=0x10 & op13=1 & op0207=0x28 & rss5 & rtt5 & Pd2 & $(END_PACKET) { +:boundscheck":raw:hi" Pd2,rss5,rtt5 EndPacket is iclass=13 & op2327=0x4 & op13=1 & op0507=0x5 & rss5 & rtt5 & Pd2 & $(END_PACKET) { upper:4 = rtt5(4); lower:4 = rtt5:4; src:4 = rss5(4); - # TODO: unclear if comparison should be signed or unsigned bool:1 = (src >= lower) && (src < upper); Pd2 = Pd2 & (bool * 0xff); build EndPacket; @@ -3793,13 +4006,12 @@ define pcodeop barrier; # (v4,13) boundscheck -- "Pd4 = boundscheck ( Rss32 , Rtt32 ) :raw :lo" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 1 1 0 1 0 0 1 0 0 + + s s s s s P P 1 t t t t t 1 0 0 + + + d d +# 1 1 0 1 0 0 1 0 0 - - s s s s s P P 1 t t t t t 1 0 0 - - - d d -:boundscheck":raw:lo" Pd2,rss5,rtt5 EndPacket is iclass=13 & op2127=0x10 & op13=1 & op0207=0x20 & rss5 & rtt5 & Pd2 & $(END_PACKET) { +:boundscheck":raw:lo" Pd2,rss5,rtt5 EndPacket is iclass=13 & op2327=0x4 & op13=1 & op0507=0x4 & rss5 & rtt5 & Pd2 & $(END_PACKET) { upper:4 = rtt5(4); lower:4 = rtt5:4; src:4 = rss5:4; - # TODO: unclear if comparison should be signed or unsigned bool:1 = (src >= lower) && (src < upper); Pd2 = Pd2 & (bool * 0xff); build EndPacket; @@ -3808,9 +4020,9 @@ define pcodeop barrier; # (v2,8) brev -- "Rd32 = brev ( Rs32 )" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 1 0 0 0 1 1 0 0 0 1 0 s s s s s P P + + + + + + 1 1 0 d d d d d +# 1 0 0 0 1 1 0 0 0 1 0 s s s s s P P - - - - - - 1 1 0 d d d d d -:brev Rd5,rs5 EndPacket is iclass=8 & op2127=0x62 & op0513=0x06 & Rd5 & rs5 & $(END_PACKET) { +:brev Rd5,rs5 EndPacket is iclass=8 & op2127=0x62 & op0507=0x6 & Rd5 & rs5 & $(END_PACKET) { Rd5 = bitReverse(rs5); build EndPacket; } @@ -3818,9 +4030,9 @@ define pcodeop barrier; # (v4,8) brev -- "Rdd32 = brev ( Rss32 )" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 1 0 0 0 0 0 0 0 1 1 + s s s s s P P + + + + + + 1 1 0 d d d d d +# 1 0 0 0 0 0 0 0 1 1 - s s s s s P P - - - - - - 1 1 0 d d d d d -:brev Rdd5,rss5 EndPacket is iclass=8 & op2127=0x06 & op0513=0x06 & Rdd5 & rss5 & $(END_PACKET) { +:brev Rdd5,rss5 EndPacket is iclass=8 & op2227=0x3 & op0507=0x6 & Rdd5 & rss5 & $(END_PACKET) { Rdd5 = bitReverse(rss5); build EndPacket; } @@ -3852,17 +4064,18 @@ define pcodeop brkpt; # (v2,5) call -- "if ( Pu4 ) call #r15:2x" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 0 1 0 1 1 1 0 1 i i 0 i i i i i P P i 0 0 + u u i i i i i i i + +# 0 1 0 1 1 1 0 1 i i 0 i i i i i P P i 0 0 - u u i i i i i i i - # # (v2,5) call -- "if ( ! Pu4 ) call #r15:2x" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 0 1 0 1 1 1 0 1 i i 1 i i i i i P P i 0 0 + u u i i i i i i i + +# 0 1 0 1 1 1 0 1 i i 1 i i i i i P P i - 0 - u u i i i i i i i - -:call^FlowCondUU RelDest15x EndPacket is iclass=5 & op2427=0xd & op1112=0 & op10=0 & op0=0 & FlowCondUU & RelDest15x & $(END_PACKET) { +:call^FlowCondUU RelDest15x EndPacket is iclass=5 & op2427=0xd & op11=0 & FlowCondUU & RelDest15x & $(END_PACKET) { build FlowCondUU; build EndPacket; <> + build FlowCondUU; if (ConditionReg == 0) goto ; LR = ReturnAddr; call RelDest15x; @@ -3872,9 +4085,9 @@ define pcodeop brkpt; # (v2,5) callr -- "callr Rs32" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 0 1 0 1 0 0 0 0 1 0 1 s s s s s P P + + + + + + + + + + + + + + +# 0 1 0 1 0 0 0 0 1 0 1 s s s s s P P - - - - - - - - - - - - - - -:callr rs5 EndPacket is iclass=5 & op2127=0x05 & op0013=0 & rs5 & $(END_PACKET) { +:callr rs5 EndPacket is iclass=5 & op2127=0x05 & rs5 & $(END_PACKET) { dest:4 = rs5; build EndPacket; <> @@ -3885,9 +4098,14 @@ define pcodeop brkpt; # callrh -- "callrh Rs32" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 0 1 0 1 0 0 0 0 1 1 0 s s s s s P P + + + + + + + + + + + + + + +# 0 1 0 1 0 0 0 0 1 1 0 s s s s s P P - - - - - - - - - - - - - - -:callrh rs5 EndPacket is iclass=5 & op2127=0x06 & op0013=0 & rs5 & $(END_PACKET) { +# (v73,5) callrh -- "callrh ( Rs32 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 1 0 1 0 0 0 0 1 1 0 s s s s s P P - - - - - - - - - - - - - - + +:callrh rs5 EndPacket is iclass=5 & op2127=0x06 & rs5 & $(END_PACKET) { dest:4 = rs5; build EndPacket; <> @@ -3898,18 +4116,19 @@ define pcodeop brkpt; # (v2,5) callr -- "if ( Pu4 ) callr Rs32" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 0 1 0 1 0 0 0 1 0 0 0 s s s s s P P + + + + u u + + + + + + + + +# 0 1 0 1 0 0 0 1 0 0 0 s s s s s P P - - - - u u - - - - - - - - # # (v2,5) callr -- "if ( ! Pu4 ) callr Rs32" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 0 1 0 1 0 0 0 1 0 0 1 s s s s s P P + + + + u u + + + + + + + + +# 0 1 0 1 0 0 0 1 0 0 1 s s s s s P P - - - - u u - - - - - - - - -:callr^FlowCondUU rs5 EndPacket is iclass=5 & op2227=0x04 & op1013=0 & op0007=0 & rs5 & FlowCondUU & $(END_PACKET) { +:callr^FlowCondUU rs5 EndPacket is iclass=5 & op2227=0x04 & rs5 & FlowCondUU & $(END_PACKET) { dest:4 = rs5; build FlowCondUU; build EndPacket; <> + build FlowCondUU; if (ConditionReg == 0) goto ; LR = ReturnAddr; call [dest]; @@ -3919,7 +4138,7 @@ define pcodeop brkpt; # (v2,6) ciad -- "ciad ( Rs32 )" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 0 1 1 0 0 1 0 0 0 0 0 s s s s s P P + + + + + + 0 1 1 + + + + + +# 0 1 1 0 0 1 0 0 0 0 0 s s s s s P P - - - - - - 0 1 1 - - - - - :ciad rs5 EndPacket is iclass=6 & op2127=0x20 & op0507=3 & rs5 & $(END_PACKET) { S22 = S22 & ~(rs5); @@ -3929,7 +4148,7 @@ define pcodeop brkpt; # (v2,8) cl0 -- "Rd32 = cl0 ( Rs32 )" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 1 0 0 0 1 1 0 0 0 0 0 s s s s s P P + + + + + + 1 0 1 d d d d d +# 1 0 0 0 1 1 0 0 0 0 0 s s s s s P P - - - - - - 1 0 1 d d d d d :cl0 Rd5,rs5 EndPacket is iclass=8 & op2127=0x60 & op0507=5 & rs5 & Rd5 & $(END_PACKET) { Rd5 = lzcount(rs5); @@ -3939,7 +4158,7 @@ define pcodeop brkpt; # (v2,8) cl0 -- "Rd32 = cl0 ( Rss32 )" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 1 0 0 0 1 0 0 0 0 1 0 s s s s s P P + + + + + + 0 1 0 d d d d d +# 1 0 0 0 1 0 0 0 0 1 0 s s s s s P P - - - - - - 0 1 0 d d d d d :cl0 Rd5,rss5 EndPacket is iclass=8 & op2127=0x42 & op0507=2 & rss5 & Rd5 & $(END_PACKET) { Rd5 = lzcount(rss5); @@ -3949,7 +4168,7 @@ define pcodeop brkpt; # (v2,8) cl1 -- "Rd32 = cl1 ( Rs32 )" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 1 0 0 0 1 1 0 0 0 0 0 s s s s s P P + + + + + + 1 1 0 d d d d d +# 1 0 0 0 1 1 0 0 0 0 0 s s s s s P P - - - - - - 1 1 0 d d d d d :cl1 Rd5,rs5 EndPacket is iclass=8 & op2127=0x60 & op0507=6 & rs5 & Rd5 & $(END_PACKET) { Rd5 = lzcount(~rs5); @@ -3959,7 +4178,7 @@ define pcodeop brkpt; # (v2,8) cl1 -- "Rd32 = cl1 ( Rss32 )" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 1 0 0 0 1 0 0 0 0 1 0 s s s s s P P + + + + + + 1 0 0 d d d d d +# 1 0 0 0 1 0 0 0 0 1 0 s s s s s P P - - - - - - 1 0 0 d d d d d :cl1 Rd5,rss5 EndPacket is iclass=8 & op2127=0x42 & op0507=4 & rss5 & Rd5 & $(END_PACKET) { Rd5 = lzcount(~rss5); @@ -3969,7 +4188,7 @@ define pcodeop brkpt; # (v2,8) clb -- "Rd32 = clb ( Rs32 )" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 1 0 0 0 1 1 0 0 0 0 0 s s s s s P P + + + + + + 1 0 0 d d d d d +# 1 0 0 0 1 1 0 0 0 0 0 s s s s s P P - - - - - - 1 0 0 d d d d d :clb Rd5,rs5 EndPacket is iclass=8 & op2127=0x60 & op0507=4 & rs5 & Rd5 & $(END_PACKET) { Rd5 = countLeadingBits(rs5); @@ -3979,7 +4198,7 @@ define pcodeop brkpt; # (v2,8) clb -- "Rd32 = clb ( Rss32 )" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 1 0 0 0 1 0 0 0 0 1 0 s s s s s P P + + + + + + 0 0 0 d d d d d +# 1 0 0 0 1 0 0 0 0 1 0 s s s s s P P - - - - - - 0 0 0 d d d d d :clb Rd5,rss5 EndPacket is iclass=8 & op2127=0x42 & op0507=0 & rss5 & Rd5 & $(END_PACKET) { Rd5 = countLeadingBits(rss5); @@ -3989,7 +4208,7 @@ define pcodeop brkpt; # (v66,8) clip -- "Rd32 = clip ( Rs32 , #u5 )" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 1 0 0 0 1 0 0 0 1 1 0 s s s s s P P 0 + + + + + 1 0 1 d d d d d +# 1 0 0 0 1 0 0 0 1 1 0 s s s s s P P 0 - - - - - 1 0 1 d d d d d define pcodeop clip; :clip Rd5,rs5,Uimm8_0812 EndPacket is iclass=8 & op2127=0x46 & op13=0 & op0507=5 & rs5 & Rd5 & Uimm8_0812 & $(END_PACKET) { @@ -4011,10 +4230,11 @@ define pcodeop clip; # (v2,12) clrbit -- "Rd32 = clrbit ( Rs32 , Rt32 )" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 1 1 0 0 0 1 1 0 1 0 + s s s s s P P + t t t t t 0 1 + d d d d d +# 1 1 0 0 0 1 1 0 1 0 - s s s s s P P - t t t t t 0 1 - d d d d d -:clrbit Rd5,rs5,rt5 EndPacket is iclass=12 & op2127=0x34 & op13=0 & op0507=2 & Rd5 & rs5 & rt5 & $(END_PACKET) { - mask:4 = 1 << rt5; +:clrbit Rd5,rs5,rt5 EndPacket is iclass=12 & op2227=0x1a & op0607=1 & Rd5 & rs5 & rt5 & $(END_PACKET) { + shamt:4 = (rt5 << 25) s>> 25; + mask:4 = zext(shamt s>= 0) * (1 << shamt); Rd5 = rs5 & ~mask; build EndPacket; } @@ -4035,7 +4255,7 @@ define pcodeop clip; # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| # 0 1 1 1 0 1 0 1 0 0 i s s s s s P P i i i i i i i i i 1 0 0 d d -:cmp.eq! Pd2,rs5,Simm32_21_0513x EndPacket is iclass=7 & op2227=0x14 & op0204=4 & rs5 & Simm32_21_0513x & Pd2 & $(END_PACKET) { +:"!cmp.eq" Pd2,rs5,Simm32_21_0513x EndPacket is iclass=7 & op2227=0x14 & op0204=4 & rs5 & Simm32_21_0513x & Pd2 & $(END_PACKET) { bool:1 = (rs5 != Simm32_21_0513x); Pd2 = Pd2 & (bool * 0xff); build EndPacket; @@ -4044,9 +4264,9 @@ define pcodeop clip; # (v2,15) cmp.eq -- "Pd4 = cmp.eq ( Rs32 , Rt32 )" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 1 1 1 1 0 0 1 0 + 0 0 s s s s s P P + t t t t t + + + 0 0 0 d d +# 1 1 1 1 0 0 1 0 - 0 0 s s s s s P P - t t t t t - - - 0 0 0 d d -:cmp.eq Pd2,rs5,rt5 EndPacket is iclass=15 & op2127=0x10 & op13=0 & op0207=0 & rs5 & rt5 & Pd2 & $(END_PACKET) { +:cmp.eq Pd2,rs5,rt5 EndPacket is iclass=15 & op2427=0x2 & op2122=0x0 & op0204=0 & rs5 & rt5 & Pd2 & $(END_PACKET) { bool:1 = (rs5 == rt5); Pd2 = Pd2 & (bool * 0xff); build EndPacket; @@ -4055,9 +4275,9 @@ define pcodeop clip; # (v4,15) cmp.eq -- "Pd4 = ! cmp.eq ( Rs32 , Rt32 )" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 1 1 1 1 0 0 1 0 + 0 0 s s s s s P P + t t t t t + + + 1 0 0 d d +# 1 1 1 1 0 0 1 0 - 0 0 s s s s s P P - t t t t t - - - 1 0 0 d d -:cmp.eq! Pd2,rs5,rt5 EndPacket is iclass=15 & op2127=0x10 & op13=0 & op0207=4 & rs5 & rt5 & Pd2 & $(END_PACKET) { +:"!cmp.eq" Pd2,rs5,rt5 EndPacket is iclass=15 & op2427=0x2 & op2122=0x0 & op0204=4 & rs5 & rt5 & Pd2 & $(END_PACKET) { bool:1 = (rs5 != rt5); Pd2 = Pd2 & (bool * 0xff); build EndPacket; @@ -4066,9 +4286,9 @@ define pcodeop clip; # (v2,13) cmp.eq -- "Pd4 = cmp.eq ( Rss32 , Rtt32 )" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 1 1 0 1 0 0 1 0 1 + + s s s s s P P + t t t t t 0 0 + + + + d d +# 1 1 0 1 0 0 1 0 1 - - s s s s s P P - t t t t t 0 0 - - - - d d -:cmp.eq Pd2,rss5,rtt5 EndPacket is iclass=13 & op2127=0x14 & op13=0 & op0207=0 & rss5 & rtt5 & Pd2 & $(END_PACKET) { +:cmp.eq Pd2,rss5,rtt5 EndPacket is iclass=13 & op2327=0x5 & op0607=0 & rss5 & rtt5 & Pd2 & $(END_PACKET) { bool:1 = (rss5 == rtt5); Pd2 = Pd2 & (bool * 0xff); build EndPacket; @@ -4090,7 +4310,7 @@ define pcodeop clip; # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| # 0 1 1 1 0 1 0 1 0 1 i s s s s s P P i i i i i i i i i 1 0 0 d d -:cmp.gt! Pd2,rs5,Simm32_21_0513x EndPacket is iclass=7 & op2227=0x15 & op0204=4 & rs5 & Simm32_21_0513x & Pd2 & $(END_PACKET) { +:"!cmp.gt" Pd2,rs5,Simm32_21_0513x EndPacket is iclass=7 & op2227=0x15 & op0204=4 & rs5 & Simm32_21_0513x & Pd2 & $(END_PACKET) { bool:1 = (rs5 s<= Simm32_21_0513x); Pd2 = Pd2 & (bool * 0xff); build EndPacket; @@ -4099,9 +4319,9 @@ define pcodeop clip; # (v2,15) cmp.gt -- "Pd4 = cmp.gt ( Rs32 , Rt32 )" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 1 1 1 1 0 0 1 0 + 1 0 s s s s s P P + t t t t t + + + 0 0 0 d d +# 1 1 1 1 0 0 1 0 - 1 0 s s s s s P P - t t t t t - - - 0 0 0 d d -:cmp.gt Pd2,rs5,rt5 EndPacket is iclass=15 & op2127=0x12 & op13=0 & op0207=0 & rs5 & rt5 & Pd2 & $(END_PACKET) { +:cmp.gt Pd2,rs5,rt5 EndPacket is iclass=15 & op2427=0x2 & op2122=0x2 & op0204=0 & rs5 & rt5 & Pd2 & $(END_PACKET) { bool:1 = (rs5 s> rt5); Pd2 = Pd2 & (bool * 0xff); build EndPacket; @@ -4110,9 +4330,9 @@ define pcodeop clip; # (v4,15) cmp.gt -- "Pd4 = ! cmp.gt ( Rs32 , Rt32 )" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 1 1 1 1 0 0 1 0 + 1 0 s s s s s P P + t t t t t + + + 1 0 0 d d +# 1 1 1 1 0 0 1 0 - 1 0 s s s s s P P - t t t t t - - - 1 0 0 d d -:cmp.gt! Pd2,rs5,rt5 EndPacket is iclass=15 & op2127=0x12 & op13=0 & op0207=4 & rs5 & rt5 & Pd2 & $(END_PACKET) { +:"!cmp.gt" Pd2,rs5,rt5 EndPacket is iclass=15 & op2427=0x2 & op2122=0x2 & op0204=4 & rs5 & rt5 & Pd2 & $(END_PACKET) { bool:1 = (rs5 s<= rt5); Pd2 = Pd2 & (bool * 0xff); build EndPacket; @@ -4121,9 +4341,9 @@ define pcodeop clip; # (v2,13) cmp.gt -- "Pd4 = cmp.gt ( Rss32 , Rtt32 )" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 1 1 0 1 0 0 1 0 1 + + s s s s s P P + t t t t t 0 1 + + + + d d +# 1 1 0 1 0 0 1 0 1 - - s s s s s P P - t t t t t 0 1 - - - - d d -:cmp.gt Pd2,rss5,rtt5 EndPacket is iclass=13 & op2127=0x14 & op13=0 & op0207=0x10 & rss5 & rtt5 & Pd2 & $(END_PACKET) { +:cmp.gt Pd2,rss5,rtt5 EndPacket is iclass=13 & op2327=0x5 & op0607=0x1 & rss5 & rtt5 & Pd2 & $(END_PACKET) { bool:1 = (rss5 s> rtt5); Pd2 = Pd2 & (bool * 0xff); build EndPacket; @@ -4145,7 +4365,7 @@ define pcodeop clip; # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| # 0 1 1 1 0 1 0 1 1 0 0 s s s s s P P i i i i i i i i i 1 0 0 d d -:cmp.gtu! Pd2,rs5,Uimm32_0513x EndPacket is iclass=7 & op2127=0x2c & op0204=4 & rs5 & Uimm32_0513x & Pd2 & $(END_PACKET) { +:"!cmp.gtu" Pd2,rs5,Uimm32_0513x EndPacket is iclass=7 & op2127=0x2c & op0204=4 & rs5 & Uimm32_0513x & Pd2 & $(END_PACKET) { bool:1 = (rs5 <= Uimm32_0513x); Pd2 = Pd2 & (bool * 0xff); build EndPacket; @@ -4154,9 +4374,9 @@ define pcodeop clip; # (v2,15) cmp.gtu -- "Pd4 = cmp.gtu ( Rs32 , Rt32 )" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 1 1 1 1 0 0 1 0 + 1 1 s s s s s P P + t t t t t + + + 0 0 0 d d +# 1 1 1 1 0 0 1 0 - 1 1 s s s s s P P - t t t t t - - - 0 0 0 d d -:cmp.gtu Pd2,rs5,rt5 EndPacket is iclass=15 & op2127=0x13 & op0207=0 & rs5 & rt5 & Pd2 & $(END_PACKET) { +:cmp.gtu Pd2,rs5,rt5 EndPacket is iclass=15 & op2427=0x2 & op2122=0x3 & op0204=0 & rs5 & rt5 & Pd2 & $(END_PACKET) { bool:1 = (rs5 > rt5); Pd2 = Pd2 & (bool * 0xff); build EndPacket; @@ -4165,9 +4385,9 @@ define pcodeop clip; # (v4,15) cmp.gtu -- "Pd4 = ! cmp.gtu ( Rs32 , Rt32 )" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 1 1 1 1 0 0 1 0 + 1 1 s s s s s P P + t t t t t + + + 1 0 0 d d +# 1 1 1 1 0 0 1 0 - 1 1 s s s s s P P - t t t t t - - - 1 0 0 d d -:cmp.gtu! Pd2,rs5,rt5 EndPacket is iclass=15 & op2127=0x13 & op0207=4 & rs5 & rt5 & Pd2 & $(END_PACKET) { +:"!cmp.gtu" Pd2,rs5,rt5 EndPacket is iclass=15 & op2427=0x2 & op2122=0x3 & op0204=4 & rs5 & rt5 & Pd2 & $(END_PACKET) { bool:1 = (rs5 <= rt5); Pd2 = Pd2 & (bool * 0xff); build EndPacket; @@ -4176,9 +4396,9 @@ define pcodeop clip; # (v2,13) cmp.gtu -- "Pd4 = cmp.gtu ( Rss32 , Rtt32 )" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 1 1 0 1 0 0 1 0 1 + + s s s s s P P + t t t t t 1 0 + + + + d d +# 1 1 0 1 0 0 1 0 1 0 0 s s s s s P P - t t t t t 1 0 0 - - - d d -:cmp.gtu Pd2,rss5,rtt5 EndPacket is iclass=13 & op2127=0x14 & op13=0 & op0207=0x20 & rss5 & rtt5 & Pd2 & $(END_PACKET) { +:cmp.gtu Pd2,rss5,rtt5 EndPacket is iclass=13 & op2327=0x5 & op22=0 & op21=0 & op0607=0x2 & op5=0 & rss5 & rtt5 & Pd2 & $(END_PACKET) { bool:1 = (rss5 > rtt5); Pd2 = Pd2 & (bool * 0xff); build EndPacket; @@ -4187,10 +4407,9 @@ define pcodeop clip; # (v4,7) cmp.eq -- "Rd32 = cmp.eq ( Rs32 , #s8x )" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 0 1 1 1 0 0 1 1 + 1 0 s s s s s P P 1 i i i i i i i i d d d d d +# 0 1 1 1 0 0 1 1 - 1 0 s s s s s P P 1 i i i i i i i i d d d d d -:cmp.eq Rd5,rs5,Simm32_0512x EndPacket is iclass=7 & op2127=0x1a & op13=1 & rs5 & Rd5 & Simm32_0512x & $(END_PACKET) { - # TODO: Verify output value - assuming 0/1 boolean +:cmp.eq Rd5,rs5,Simm32_0512x EndPacket is iclass=7 & op2427=0x3 & op2122=0x2 & op13=1 & rs5 & Rd5 & Simm32_0512x & $(END_PACKET) { Rd5 = zext(rs5 == Simm32_0512x); build EndPacket; } @@ -4198,10 +4417,9 @@ define pcodeop clip; # (v4,7) cmp.eq -- "Rd32 = ! cmp.eq ( Rs32 , #s8x )" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 0 1 1 1 0 0 1 1 + 1 1 s s s s s P P 1 i i i i i i i i d d d d d +# 0 1 1 1 0 0 1 1 - 1 1 s s s s s P P 1 i i i i i i i i d d d d d -:cmp.eq! Rd5,rs5,Simm32_0512x EndPacket is iclass=7 & op2127=0x1b & op13=1 & rs5 & Rd5 & Simm32_0512x & $(END_PACKET) { - # TODO: Verify output value - assuming 0/1 boolean +:"!cmp.eq" Rd5,rs5,Simm32_0512x EndPacket is iclass=7 & op2427=0x3 & op2122=0x3 & op13=1 & rs5 & Rd5 & Simm32_0512x & $(END_PACKET) { Rd5 = zext(rs5 != Simm32_0512x); build EndPacket; } @@ -4209,9 +4427,9 @@ define pcodeop clip; # (v4,15) cmp.eq -- "Rd32 = cmp.eq ( Rs32 , Rt32 )" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 1 1 1 1 0 0 1 1 0 1 0 s s s s s P P + t t t t t + + + d d d d d +# 1 1 1 1 0 0 1 1 0 1 0 s s s s s P P - t t t t t - - - d d d d d -:cmp.eq Rd5,rs5,rt5 EndPacket is iclass=15 & op2127=0x1a & op13=0 & op0507=0 & rs5 & rt5 & Rd5 & $(END_PACKET) { +:cmp.eq Rd5,rs5,rt5 EndPacket is iclass=15 & op2127=0x1a & rs5 & rt5 & Rd5 & $(END_PACKET) { Rd5 = zext(rs5 == rt5); build EndPacket; } @@ -4219,9 +4437,9 @@ define pcodeop clip; # (v4,15) cmp.eq -- "Rd32 = ! cmp.eq ( Rs32 , Rt32 )" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 1 1 1 1 0 0 1 1 0 1 1 s s s s s P P + t t t t t + + + d d d d d +# 1 1 1 1 0 0 1 1 0 1 1 s s s s s P P - t t t t t - - - d d d d d -:cmp.eq! Rd5,rs5,rt5 EndPacket is iclass=15 & op2127=0x1b & op13=0 & op0507=0 & rs5 & rt5 & Rd5 & $(END_PACKET) { +:"!cmp.eq" Rd5,rs5,rt5 EndPacket is iclass=15 & op2127=0x1b & rs5 & rt5 & Rd5 & $(END_PACKET) { Rd5 = zext(rs5 != rt5); build EndPacket; } @@ -4229,9 +4447,9 @@ define pcodeop clip; # (v4,13) cmpb.eq -- "Pd4 = cmpb.eq ( Rs32 , #u8 )" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 1 1 0 1 1 1 0 1 + 0 0 s s s s s P P + i i i i i i i i 0 0 + d d +# 1 1 0 1 1 1 0 1 - 0 0 s s s s s P P - i i i i i i i i 0 0 - d d -:cmpb.eq Pd2,rs5,Uimm8_0512 EndPacket is iclass=13 & op2127=0x68 & op13=0 & op0204=0 & rs5 & Uimm8_0512 & Pd2 & $(END_PACKET) { +:cmpb.eq Pd2,rs5,Uimm8_0512 EndPacket is iclass=13 & op2427=0xd & op2122=0x0 & op0304=0 & rs5 & Uimm8_0512 & Pd2 & $(END_PACKET) { bool:1 = (rs5:1 == Uimm8_0512); Pd2 = Pd2 & (bool * 0xff); build EndPacket; @@ -4240,9 +4458,9 @@ define pcodeop clip; # (v4,12) cmpb.eq -- "Pd4 = cmpb.eq ( Rs32 , Rt32 )" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 1 1 0 0 0 1 1 1 1 1 + s s s s s P P + t t t t t 1 1 0 + + + d d +# 1 1 0 0 0 1 1 1 1 1 0 s s s s s P P - t t t t t 1 1 0 - - - d d -:cmpb.eq Pd2,rs5,rt5 EndPacket is iclass=12 & op2127=0x3e & op13=0 & op0207=0x30 & rs5 & rt5 & Pd2 & $(END_PACKET) { +:cmpb.eq Pd2,rs5,rt5 EndPacket is iclass=12 & op2227=0x1f & op21=0 & op0507=0x6 & rs5 & rt5 & Pd2 & $(END_PACKET) { bool:1 = (rs5:1 == rt5:1); Pd2 = Pd2 & (bool * 0xff); build EndPacket; @@ -4251,9 +4469,9 @@ define pcodeop clip; # (v4,13) cmpb.gt -- "Pd4 = cmpb.gt ( Rs32 , #s8 )" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 1 1 0 1 1 1 0 1 + 0 1 s s s s s P P + i i i i i i i i 0 0 + d d +# 1 1 0 1 1 1 0 1 - 0 1 s s s s s P P - i i i i i i i i 0 0 - d d -:cmpb.gt Pd2,rs5,Simm8_0512 EndPacket is iclass=13 & op2127=0x69 & op13=0 & op0204=0 & rs5 & Simm8_0512 & Pd2 & $(END_PACKET) { +:cmpb.gt Pd2,rs5,Simm8_0512 EndPacket is iclass=13 & op2427=0xd & op2122=0x1 & op0304=0 & rs5 & Simm8_0512 & Pd2 & $(END_PACKET) { bool:1 = (rs5:1 s> Simm8_0512); Pd2 = Pd2 & (bool * 0xff); build EndPacket; @@ -4262,9 +4480,9 @@ define pcodeop clip; # (v4,12) cmpb.gt -- "Pd4 = cmpb.gt ( Rs32 , Rt32 )" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 1 1 0 0 0 1 1 1 1 1 + s s s s s P P + t t t t t 0 1 0 + + + d d +# 1 1 0 0 0 1 1 1 1 1 0 s s s s s P P - t t t t t 0 1 0 - - - d d -:cmpb.gt Pd2,rs5,rt5 EndPacket is iclass=12 & op2127=0x3e & op13=0 & op0207=0x10 & rs5 & rt5 & Pd2 & $(END_PACKET) { +:cmpb.gt Pd2,rs5,rt5 EndPacket is iclass=12 & op2227=0x1f & op21=0 & op0507=0x2 & rs5 & rt5 & Pd2 & $(END_PACKET) { bool:1 = (rs5:1 s> rt5:1); Pd2 = Pd2 & (bool * 0xff); build EndPacket; @@ -4273,9 +4491,9 @@ define pcodeop clip; # (v4,13) cmpb.gtu -- "Pd4 = cmpb.gtu ( Rs32 , #u7x )" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 1 1 0 1 1 1 0 1 + 1 0 s s s s s P P + 0 i i i i i i i 0 0 + d d +# 1 1 0 1 1 1 0 1 - 1 0 s s s s s P P - 0 i i i i i i i 0 0 - d d -:cmpb.gtu Pd2,rs5,Uimm8_0511x EndPacket is iclass=13 & op2127=0x6a & op1213=0 & op0204=0 & rs5 & Uimm8_0511x & Pd2 & $(END_PACKET) { +:cmpb.gtu Pd2,rs5,Uimm8_0511x EndPacket is iclass=13 & op2427=0xd & op2122=0x2 & op12=0 & op0304=0 & rs5 & Uimm8_0511x & Pd2 & $(END_PACKET) { bool:1 = (rs5:1 > Uimm8_0511x); Pd2 = Pd2 & (bool * 0xff); build EndPacket; @@ -4284,9 +4502,9 @@ define pcodeop clip; # (v4,12) cmpb.gtu -- "Pd4 = cmpb.gtu ( Rs32 , Rt32 )" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 1 1 0 0 0 1 1 1 1 1 + s s s s s P P + t t t t t 1 1 1 + + + d d +# 1 1 0 0 0 1 1 1 1 1 0 s s s s s P P - t t t t t 1 1 1 - - - d d -:cmpb.gtu Pd2,rs5,rt5 EndPacket is iclass=12 & op2127=0x3e & op13=0 & op0207=0x38 & rs5 & rt5 & Pd2 & $(END_PACKET) { +:cmpb.gtu Pd2,rs5,rt5 EndPacket is iclass=12 & op2227=0x1f & op21=0 & op0507=0x7 & rs5 & rt5 & Pd2 & $(END_PACKET) { bool:1 = (rs5:1 > rt5:1); Pd2 = Pd2 & (bool * 0xff); build EndPacket; @@ -4295,9 +4513,9 @@ define pcodeop clip; # (v4,13) cmph.eq -- "Pd4 = cmph.eq ( Rs32 , #s8x )" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 1 1 0 1 1 1 0 1 + 0 0 s s s s s P P + i i i i i i i i 0 1 + d d +# 1 1 0 1 1 1 0 1 - 0 0 s s s s s P P - i i i i i i i i 0 1 - d d -:cmph.eq Pd2,rs5,Simm16_0512x EndPacket is iclass=13 & op2127=0x68 & op13=0 & op0204=2 & rs5 & Simm16_0512x & Pd2 & $(END_PACKET) { +:cmph.eq Pd2,rs5,Simm16_0512x EndPacket is iclass=13 & op2427=0xd & op2122=0x0 & op0304=1 & rs5 & Simm16_0512x & Pd2 & $(END_PACKET) { bool:1 = (rs5:2 == Simm16_0512x); Pd2 = Pd2 & (bool * 0xff); build EndPacket; @@ -4306,9 +4524,9 @@ define pcodeop clip; # (v4,12) cmph.eq -- "Pd4 = cmph.eq ( Rs32 , Rt32 )" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 1 1 0 0 0 1 1 1 1 1 + s s s s s P P + t t t t t 0 1 1 + + + d d +# 1 1 0 0 0 1 1 1 1 1 - s s s s s P P - t t t t t 0 1 1 - - - d d -:cmph.eq Pd2,rs5,rt5 EndPacket is iclass=12 & op2127=0x3e & op13=0 & op0207=0x18 & rs5 & rt5 & Pd2 & $(END_PACKET) { +:cmph.eq Pd2,rs5,rt5 EndPacket is iclass=12 & op2227=0x1f & op0507=0x3 & rs5 & rt5 & Pd2 & $(END_PACKET) { bool:1 = (rs5:2 == rt5:2); Pd2 = Pd2 & (bool * 0xff); build EndPacket; @@ -4317,9 +4535,9 @@ define pcodeop clip; # (v4,13) cmph.gt -- "Pd4 = cmph.gt ( Rs32 , #s8x )" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 1 1 0 1 1 1 0 1 + 0 1 s s s s s P P + i i i i i i i i 0 1 + d d +# 1 1 0 1 1 1 0 1 - 0 1 s s s s s P P - i i i i i i i i 0 1 - d d -:cmph.gt Pd2,rs5,Simm16_0512x EndPacket is iclass=13 & op2127=0x69 & op13=0 & op0204=2 & rs5 & Simm16_0512x & Pd2 & $(END_PACKET) { +:cmph.gt Pd2,rs5,Simm16_0512x EndPacket is iclass=13 & op2427=0xd & op2122=0x1 & op0304=1 & rs5 & Simm16_0512x & Pd2 & $(END_PACKET) { bool:1 = (rs5:2 s> Simm16_0512x); Pd2 = Pd2 & (bool * 0xff); build EndPacket; @@ -4328,9 +4546,9 @@ define pcodeop clip; # (v4,12) cmph.gt -- "Pd4 = cmph.gt ( Rs32 , Rt32 )" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 1 1 0 0 0 1 1 1 1 1 + s s s s s P P + t t t t t 1 0 0 + + + d d +# 1 1 0 0 0 1 1 1 1 1 - s s s s s P P - t t t t t 1 0 0 - - - d d -:cmph.gt Pd2,rs5,rt5 EndPacket is iclass=12 & op2127=0x3e & op13=0 & op0207=0x20 & rs5 & rt5 & Pd2 & $(END_PACKET) { +:cmph.gt Pd2,rs5,rt5 EndPacket is iclass=12 & op2227=0x1f & op0507=0x4 & rs5 & rt5 & Pd2 & $(END_PACKET) { bool:1 = (rs5:2 s> rt5:2); Pd2 = Pd2 & (bool * 0xff); build EndPacket; @@ -4339,9 +4557,9 @@ define pcodeop clip; # (v4,13) cmph.gtu -- "Pd4 = cmph.gtu ( Rs32 , #u7x )" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 1 1 0 1 1 1 0 1 + 1 0 s s s s s P P + 0 i i i i i i i 0 1 + d d +# 1 1 0 1 1 1 0 1 - 1 0 s s s s s P P - 0 i i i i i i i 0 1 - d d -:cmph.gtu Pd2,rs5,Uimm16_0511x EndPacket is iclass=13 & op2127=0x6a & op1213=0 & op0204=2 & rs5 & Uimm16_0511x & Pd2 & $(END_PACKET) { +:cmph.gtu Pd2,rs5,Uimm16_0511x EndPacket is iclass=13 & op2427=0xd & op2122=0x2 & op12=0 & op0304=1 & rs5 & Uimm16_0511x & Pd2 & $(END_PACKET) { bool:1 = (rs5:2 > Uimm16_0511x); Pd2 = Pd2 & (bool * 0xff); build EndPacket; @@ -4350,9 +4568,9 @@ define pcodeop clip; # (v4,12) cmph.gtu -- "Pd4 = cmph.gtu ( Rs32 , Rt32 )" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 1 1 0 0 0 1 1 1 1 1 + s s s s s P P + t t t t t 1 0 1 + + + d d +# 1 1 0 0 0 1 1 1 1 1 0 s s s s s P P - t t t t t 1 0 1 - - - d d -:cmph.gtu Pd2,rs5,rt5 EndPacket is iclass=12 & op2127=0x3e & op13=0 & op0207=0x28 & rs5 & rt5 & Pd2 & $(END_PACKET) { +:cmph.gtu Pd2,rs5,rt5 EndPacket is iclass=12 & op2227=0x1f & op21=0 & op0507=0x5 & rs5 & rt5 & Pd2 & $(END_PACKET) { bool:1 = (rs5:2 > rt5:2); Pd2 = Pd2 & (bool * 0xff); build EndPacket; @@ -4361,7 +4579,7 @@ define pcodeop clip; # (v2,14) cmpy -- "Rd32 = cmpy ( Rs32 , Rt32 ) :<<1 :rnd :sat" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 1 1 1 0 1 1 0 1 1 0 1 s s s s s P P + t t t t t 1 1 0 d d d d d +# 1 1 1 0 1 1 0 1 1 0 1 s s s s s P P 0 t t t t t 1 1 0 d d d d d define pcodeop cmpyX2RndSat; @@ -4373,7 +4591,7 @@ define pcodeop cmpyX2RndSat; # (v2,14) cmpy -- "Rd32 = cmpy ( Rs32 , Rt32 ) :rnd :sat" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 1 1 1 0 1 1 0 1 0 0 1 s s s s s P P + t t t t t 1 1 0 d d d d d +# 1 1 1 0 1 1 0 1 0 0 1 s s s s s P P 0 t t t t t 1 1 0 d d d d d define pcodeop cmpyRndSat; @@ -4385,7 +4603,7 @@ define pcodeop cmpyRndSat; # (v2,14) cmpy -- "Rd32 = cmpy ( Rs32 , Rt32 * ) :<<1 :rnd :sat" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 1 1 1 0 1 1 0 1 1 1 1 s s s s s P P + t t t t t 1 1 0 d d d d d +# 1 1 1 0 1 1 0 1 1 1 1 s s s s s P P 0 t t t t t 1 1 0 d d d d d :cmpy":<<1:rnd:sat" Rd5,rs5,Rt5Conjugate EndPacket is iclass=14 & op2127=0x6f & op13=0 & op0507=6 & rs5 & Rt5Conjugate & Rd5 & $(END_PACKET) { Rd5 = cmpyX2RndSat(rs5,Rt5Conjugate); @@ -4395,7 +4613,7 @@ define pcodeop cmpyRndSat; # (v2,14) cmpy -- "Rd32 = cmpy ( Rs32 , Rt32 * ) :rnd :sat" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 1 1 1 0 1 1 0 1 0 1 1 s s s s s P P + t t t t t 1 1 0 d d d d d +# 1 1 1 0 1 1 0 1 0 1 1 s s s s s P P 0 t t t t t 1 1 0 d d d d d :cmpy":rnd:sat" Rd5,rs5,Rt5Conjugate EndPacket is iclass=14 & op2127=0x6b & op13=0 & op0507=6 & rs5 & Rt5Conjugate & Rd5 & $(END_PACKET) { Rd5 = cmpyRndSat(rs5,Rt5Conjugate); @@ -4405,7 +4623,7 @@ define pcodeop cmpyRndSat; # (v2,14) cmpy -- "Rdd32 = cmpy ( Rs32 , Rt32 ) :<<1 :sat" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 1 1 1 0 0 1 0 1 1 0 0 s s s s s P P + t t t t t 1 1 0 d d d d d +# 1 1 1 0 0 1 0 1 1 0 0 s s s s s P P 0 t t t t t 1 1 0 d d d d d define pcodeop cmpyX2Sat; @@ -4417,7 +4635,7 @@ define pcodeop cmpyX2Sat; # (v2,14) cmpy -- "Rdd32 = cmpy ( Rs32 , Rt32 ) :sat" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 1 1 1 0 0 1 0 1 0 0 0 s s s s s P P + t t t t t 1 1 0 d d d d d +# 1 1 1 0 0 1 0 1 0 0 0 s s s s s P P 0 t t t t t 1 1 0 d d d d d define pcodeop cmpySat; @@ -4429,7 +4647,7 @@ define pcodeop cmpySat; # (v2,14) cmpy -- "Rdd32 = cmpy ( Rs32 , Rt32 * ) :<<1 :sat" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 1 1 1 0 0 1 0 1 1 1 0 s s s s s P P + t t t t t 1 1 0 d d d d d +# 1 1 1 0 0 1 0 1 1 1 0 s s s s s P P 0 t t t t t 1 1 0 d d d d d :cmpy":<<1:sat" Rdd5,rs5,Rt5Conjugate EndPacket is iclass=14 & op2127=0x2e & op13=0 & op0507=6 & rs5 & Rt5Conjugate & Rdd5 & $(END_PACKET) { Rdd5 = cmpyX2Sat(rs5,Rt5Conjugate); @@ -4439,7 +4657,7 @@ define pcodeop cmpySat; # (v2,14) cmpy -- "Rdd32 = cmpy ( Rs32 , Rt32 * ) :sat" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 1 1 1 0 0 1 0 1 0 1 0 s s s s s P P + t t t t t 1 1 0 d d d d d +# 1 1 1 0 0 1 0 1 0 1 0 s s s s s P P 0 t t t t t 1 1 0 d d d d d :cmpy":sat" Rdd5,rs5,Rt5Conjugate EndPacket is iclass=14 & op2127=0x2a & op13=0 & op0507=6 & rs5 & Rt5Conjugate & Rdd5 & $(END_PACKET) { Rdd5 = cmpySat(rs5,Rt5Conjugate); @@ -4449,7 +4667,7 @@ define pcodeop cmpySat; # (v2,14) cmpy -- "Rxx32 += cmpy ( Rs32 , Rt32 ) :<<1 :sat" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 1 1 1 0 0 1 1 1 1 0 0 s s s s s P P + t t t t t 1 1 0 x x x x x +# 1 1 1 0 0 1 1 1 1 0 0 s s s s s P P 0 t t t t t 1 1 0 x x x x x define pcodeop cmpyX2SatAdd; @@ -4461,7 +4679,7 @@ define pcodeop cmpyX2SatAdd; # (v2,14) cmpy -- "Rxx32 += cmpy ( Rs32 , Rt32 ) :sat" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 1 1 1 0 0 1 1 1 0 0 0 s s s s s P P + t t t t t 1 1 0 x x x x x +# 1 1 1 0 0 1 1 1 0 0 0 s s s s s P P 0 t t t t t 1 1 0 x x x x x define pcodeop cmpySatAdd; @@ -4473,7 +4691,7 @@ define pcodeop cmpySatAdd; # (v2,14) cmpy -- "Rxx32 += cmpy ( Rs32 , Rt32 * ) :<<1 :sat" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 1 1 1 0 0 1 1 1 1 1 0 s s s s s P P + t t t t t 1 1 0 x x x x x +# 1 1 1 0 0 1 1 1 1 1 0 s s s s s P P 0 t t t t t 1 1 0 x x x x x :cmpy+=":<<1:sat" Rdd5,rs5,Rt5Conjugate EndPacket is iclass=14 & op2127=0x3e & op13=0 & op0507=6 & rs5 & Rt5Conjugate & rdd5 & Rdd5 & $(END_PACKET) { Rdd5 = cmpyX2SatAdd(rs5,Rt5Conjugate,rdd5); @@ -4483,7 +4701,7 @@ define pcodeop cmpySatAdd; # (v2,14) cmpy -- "Rxx32 += cmpy ( Rs32 , Rt32 * ) :sat" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 1 1 1 0 0 1 1 1 0 1 0 s s s s s P P + t t t t t 1 1 0 x x x x x +# 1 1 1 0 0 1 1 1 0 1 0 s s s s s P P 0 t t t t t 1 1 0 x x x x x :cmpy+=":sat" Rdd5,rs5,Rt5Conjugate EndPacket is iclass=14 & op2127=0x3a & op13=0 & op0507=6 & rs5 & Rt5Conjugate & rdd5 & Rdd5 & $(END_PACKET) { Rdd5 = cmpySatAdd(rs5,Rt5Conjugate,rdd5); @@ -4493,7 +4711,7 @@ define pcodeop cmpySatAdd; # (v2,14) cmpy -- "Rxx32 -= cmpy ( Rs32 , Rt32 ) :<<1 :sat" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 1 1 1 0 0 1 1 1 1 0 0 s s s s s P P + t t t t t 1 1 1 x x x x x +# 1 1 1 0 0 1 1 1 1 0 0 s s s s s P P 0 t t t t t 1 1 1 x x x x x define pcodeop cmpyX2SatSub; @@ -4505,7 +4723,7 @@ define pcodeop cmpyX2SatSub; # (v2,14) cmpy -- "Rxx32 -= cmpy ( Rs32 , Rt32 ) :sat" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 1 1 1 0 0 1 1 1 0 0 0 s s s s s P P + t t t t t 1 1 1 x x x x x +# 1 1 1 0 0 1 1 1 0 0 0 s s s s s P P 0 t t t t t 1 1 1 x x x x x define pcodeop cmpySatSub; @@ -4517,7 +4735,7 @@ define pcodeop cmpySatSub; # (v2,14) cmpy -- "Rxx32 -= cmpy ( Rs32 , Rt32 * ) :<<1 :sat" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 1 1 1 0 0 1 1 1 1 1 0 s s s s s P P + t t t t t 1 1 1 x x x x x +# 1 1 1 0 0 1 1 1 1 1 0 s s s s s P P 0 t t t t t 1 1 1 x x x x x :cmpy-=":<<1:sat" Rdd5,rs5,Rt5Conjugate EndPacket is iclass=14 & op2127=0x3e & op13=0 & op0507=7 & rs5 & Rt5Conjugate & rdd5 & Rdd5 & $(END_PACKET) { Rdd5 = cmpyX2SatSub(rs5,Rt5Conjugate,rdd5); @@ -4527,7 +4745,7 @@ define pcodeop cmpySatSub; # (v2,14) cmpy -- "Rxx32 -= cmpy ( Rs32 , Rt32 * ) :sat" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 1 1 1 0 0 1 1 1 0 1 0 s s s s s P P + t t t t t 1 1 1 x x x x x +# 1 1 1 0 0 1 1 1 0 1 0 s s s s s P P 0 t t t t t 1 1 1 x x x x x :cmpy-=":sat" Rdd5,rs5,Rt5Conjugate EndPacket is iclass=14 & op2127=0x3a & op13=0 & op0507=7 & rs5 & Rt5Conjugate & rdd5 & Rdd5 & $(END_PACKET) { Rdd5 = cmpySatSub(rs5,Rt5Conjugate,rdd5); @@ -4537,7 +4755,7 @@ define pcodeop cmpySatSub; # (v2,14) cmpyi -- "Rdd32 = cmpyi ( Rs32 , Rt32 )" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 1 1 1 0 0 1 0 1 0 0 0 s s s s s P P + t t t t t 0 0 1 d d d d d +# 1 1 1 0 0 1 0 1 0 0 0 s s s s s P P 0 t t t t t 0 0 1 d d d d d :cmpyi Rdd5,rs5,rt5 EndPacket is iclass=14 & op2127=0x28 & op13=0 & op0507=1 & rs5 & rt5 & Rdd5 & $(END_PACKET) { # Rdd = (Rs.h[1] * Rt.h[0]) - (Rs.h[0] * Rt.h[1]); @@ -4554,7 +4772,7 @@ define pcodeop cmpySatSub; # (v2,14) cmpyi -- "Rxx32 += cmpyi ( Rs32 , Rt32 )" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 1 1 1 0 0 1 1 1 0 0 0 s s s s s P P + t t t t t 0 0 1 x x x x x +# 1 1 1 0 0 1 1 1 0 0 0 s s s s s P P 0 t t t t t 0 0 1 x x x x x :cmpyi+= Rdd5,rs5,rt5 EndPacket is iclass=14 & op2127=0x38 & op13=0 & op0507=1 & rs5 & rt5 & Rdd5 & rdd5 & $(END_PACKET) { # Rdd = (Rs.h[1] * Rt.h[0]) - (Rs.h[0] * Rt.h[1]); @@ -4614,6 +4832,7 @@ define pcodeop cmpyiwX2Sat; # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| # 1 1 1 0 1 0 0 1 1 0 0 s s s s s P P 0 t t t t t 1 0 0 d d d d d + define pcodeop cmpyiwX2RndSat; :cmpyiw":<<1:rnd:sat" Rdd5,rss5,rtt5 EndPacket is iclass=0xe & op2127=0x4c & op13=0 & op0507=4 & rss5 & rtt5 & Rdd5 & $(END_PACKET) { @@ -4631,12 +4850,14 @@ define pcodeop cmpyiwX2RndSat; build EndPacket; } -define pcodeop cmpyiwAdd; # (v4,12) cmpyiw -- "Rxx32 += cmpyiw ( Rss32 , Rtt32 )" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| # 1 1 1 0 1 0 1 0 0 1 1 s s s s s P P 0 t t t t t 0 1 0 x x x x x -:cmpyiw Rdd5,rss5,rtt5 EndPacket is iclass=0xe & op2127=0x53 & op13=0 & op0507=2 & rss5 & rtt5 & Rdd5 & rdd5 & $(END_PACKET) { + +define pcodeop cmpyiwAdd; + +:cmpyiw+= Rdd5,rss5,rtt5 EndPacket is iclass=0xe & op2127=0x53 & op13=0 & op0507=2 & rss5 & rtt5 & Rdd5 & rdd5 & $(END_PACKET) { Rdd5 = cmpyiwAdd(rdd5,rss5,rtt5); build EndPacket; } @@ -4646,7 +4867,7 @@ define pcodeop cmpyiwAdd; # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| # 1 1 1 0 1 0 1 0 0 1 0 s s s s s P P 0 t t t t t 1 1 0 x x x x x -:cmpyiw Rdd5,rss5,Rtt5Conjugate^"*" EndPacket is iclass=0xe & op2127=0x52 & op13=0 & op0507=6 & rss5 & Rtt5Conjugate & Rdd5 & rdd5 & $(END_PACKET) { +:cmpyiw+= Rdd5,rss5,Rtt5Conjugate^"*" EndPacket is iclass=0xe & op2127=0x52 & op13=0 & op0507=6 & rss5 & Rtt5Conjugate & Rdd5 & rdd5 & $(END_PACKET) { Rdd5 = cmpyiwAdd(rdd5,rss5,Rtt5Conjugate); build EndPacket; } @@ -4658,7 +4879,7 @@ define pcodeop cmpyiwAdd; define pcodeop cmpyiwhX2RndSat; -:cmpyiwh":<<1:rnd:sat" Rd5,rss5,rt5 EndPacket is iclass=12 & op2127=0x28 & op13=0 & op0507=4 & rss5 & rt5 & Rd5 & rd5 & $(END_PACKET) { +:cmpyiwh":<<1:rnd:sat" Rd5,rss5,rt5 EndPacket is iclass=12 & op2427=0x5 & op0507=4 & rss5 & rt5 & Rd5 & rd5 & $(END_PACKET) { Rd5 = cmpyiwhX2RndSat(rd5,rss5,rt5); build EndPacket; } @@ -4666,9 +4887,9 @@ define pcodeop cmpyiwhX2RndSat; # (v5,12) cmpyiwh -- "Rd32 = cmpyiwh ( Rss32 , Rt32 * ) :<<1 :rnd :sat" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 1 1 0 0 0 1 0 1 + + + s s s s s P P + t t t t t 1 0 1 d d d d d +# 1 1 0 0 0 1 0 1 - - - s s s s s P P - t t t t t 1 0 1 d d d d d -:cmpyiwh":<<1:rnd:sat" Rd5,rss5,Rt5Conjugate EndPacket is iclass=12 & op2127=0x28 & op13=0 & op0507=5 & rss5 & Rt5Conjugate & Rd5 & rd5 & $(END_PACKET) { +:cmpyiwh":<<1:rnd:sat" Rd5,rss5,Rt5Conjugate EndPacket is iclass=12 & op2427=0x5 & op0507=5 & rss5 & Rt5Conjugate & Rd5 & rd5 & $(END_PACKET) { Rd5 = cmpyiwhX2RndSat(rd5,rss5,Rt5Conjugate); build EndPacket; } @@ -4676,7 +4897,7 @@ define pcodeop cmpyiwhX2RndSat; # (v2,14) cmpyr -- "Rdd32 = cmpyr ( Rs32 , Rt32 )" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 1 1 1 0 0 1 0 1 0 0 0 s s s s s P P + t t t t t 0 1 0 d d d d d +# 1 1 1 0 0 1 0 1 0 0 0 s s s s s P P 0 t t t t t 0 1 0 d d d d d :cmpyr Rdd5,rs5,rt5 EndPacket is iclass=14 & op2127=0x28 & op13=0 & op0507=2 & rs5 & rt5 & Rdd5 & $(END_PACKET) { # Rdd = (Rs.h[0] * Rt.h[0]) - (Rs.h[1] * Rt.h[1]); @@ -4693,7 +4914,7 @@ define pcodeop cmpyiwhX2RndSat; # (v2,14) cmpyr -- "Rxx32 += cmpyr ( Rs32 , Rt32 )" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 1 1 1 0 0 1 1 1 0 0 0 s s s s s P P + t t t t t 0 1 0 x x x x x +# 1 1 1 0 0 1 1 1 0 0 0 s s s s s P P 0 t t t t t 0 1 0 x x x x x :cmpyr+= Rdd5,rs5,rt5 EndPacket is iclass=14 & op2127=0x38 & op13=0 & op0507=2 & rs5 & rt5 & rdd5 & Rdd5 & $(END_PACKET) { # Rdd += (Rs.h[0] * Rt.h[0]) - (Rs.h[1] * Rt.h[1]); @@ -4707,18 +4928,19 @@ define pcodeop cmpyiwhX2RndSat; build EndPacket; } -define pcodeop cmpyrw; -# cmpyrw -- "Rdd32 = cmpyrw ( Rss32 , Rtt32 )" +# (v2,14) cmpyrw -- "Rdd32 = cmpyrw ( Rss32 , Rtt32 )" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| # 1 1 1 0 1 0 0 0 1 0 0 s s s s s P P 0 t t t t t 0 1 0 d d d d d +define pcodeop cmpyrw; + :cmpyrw Rdd5,rss5,rtt5 EndPacket is iclass=0xe & op2127=0x44 & op13=0 & op0507=2 & rss5 & rtt5 & Rdd5 & $(END_PACKET) { Rdd5 = cmpyrw(rss5,rtt5); build EndPacket; } -# cmpyrw -- "Rdd32 = cmpyrw ( Rss32 , Rtt32* )" +# (v2,14) cmpyrw -- "Rdd32 = cmpyrw ( Rss32 , Rtt32* )" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| # 1 1 1 0 1 0 0 0 1 1 0 s s s s s P P 0 t t t t t 0 1 0 d d d d d @@ -4728,7 +4950,7 @@ define pcodeop cmpyrw; build EndPacket; } -# cmpyrw -- "Rdd32 = cmpyrw ( Rss32 , Rtt32 ) :<<1 :sat" +# (v2,14) cmpyrw -- "Rdd32 = cmpyrw ( Rss32 , Rtt32 ) :<<1 :sat" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| # 1 1 1 0 1 0 0 1 0 1 0 s s s s s P P 0 t t t t t 0 0 0 d d d d d @@ -4739,7 +4961,7 @@ define pcodeop cmpyrwX2Sat; build EndPacket; } -# cmpyrw -- "Rdd32 = cmpyrw ( Rss32 , Rtt32* ) :<<1 :sat" +# (v2,14) cmpyrw -- "Rdd32 = cmpyrw ( Rss32 , Rtt32* ) :<<1 :sat" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| # 1 1 1 0 1 0 0 1 0 1 1 s s s s s P P 0 t t t t t 0 0 0 d d d d d @@ -4749,7 +4971,7 @@ define pcodeop cmpyrwX2Sat; build EndPacket; } -# cmpyrw -- "Rdd32 = cmpyrw ( Rss32 , Rtt32 ) :<<1 :rnd :sat" +# (v2,14) cmpyrw -- "Rdd32 = cmpyrw ( Rss32 , Rtt32 ) :<<1 :rnd :sat" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| # 1 1 1 0 1 0 0 1 1 1 0 s s s s s P P 0 t t t t t 0 0 0 d d d d d @@ -4760,7 +4982,7 @@ define pcodeop cmpyrwX2RndSat; build EndPacket; } -# cmpyrw -- "Rdd32 = cmpyrw ( Rss32 , Rtt32* ) :<<1 :rnd :sat" +# (v2,14) cmpyrw -- "Rdd32 = cmpyrw ( Rss32 , Rtt32* ) :<<1 :rnd :sat" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| # 1 1 1 0 1 0 0 1 1 1 1 s s s s s P P 0 t t t t t 0 0 0 d d d d d @@ -4770,23 +4992,23 @@ define pcodeop cmpyrwX2RndSat; build EndPacket; } -# cmpyrw -- "Rxx32 += cmpyrw ( Rss32 , Rtt32 )" +# (v2,14) cmpyrw -- "Rxx32 += cmpyrw ( Rss32 , Rtt32 )" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| # 1 1 1 0 1 0 1 0 1 0 0 s s s s s P P 0 t t t t t 0 1 0 x x x x x define pcodeop cmpyrwAdd; -:cmpyrw Rdd5,rss5,rtt5 EndPacket is iclass=0xe & op2127=0x54 & op13=0 & op0507=2 & rss5 & rtt5 & Rdd5 & rdd5 & $(END_PACKET) { +:cmpyrw+= Rdd5,rss5,rtt5 EndPacket is iclass=0xe & op2127=0x54 & op13=0 & op0507=2 & rss5 & rtt5 & Rdd5 & rdd5 & $(END_PACKET) { Rdd5 = cmpyrwAdd(rdd5,rss5,rtt5); build EndPacket; } -# cmpyrw -- "Rxx32 += cmpyrw ( Rss32 , Rtt32* )" +# (v2,14) cmpyrw -- "Rxx32 += cmpyrw ( Rss32 , Rtt32* )" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| # 1 1 1 0 1 0 1 0 1 1 0 s s s s s P P 0 t t t t t 0 1 0 x x x x x -:cmpyrw Rdd5,rss5,Rtt5Conjugate^"*" EndPacket is iclass=0xe & op2127=0x56 & op13=0 & op0507=2 & rss5 & Rtt5Conjugate & Rdd5 & rdd5 & $(END_PACKET) { +:cmpyrw+= Rdd5,rss5,Rtt5Conjugate^"*" EndPacket is iclass=0xe & op2127=0x56 & op13=0 & op0507=2 & rss5 & Rtt5Conjugate & Rdd5 & rdd5 & $(END_PACKET) { Rdd5 = cmpyrwAdd(rdd5,rss5,Rtt5Conjugate); build EndPacket; } @@ -4795,19 +5017,19 @@ define pcodeop cmpyrwAdd; # (v4,12) cmpyrwh -- "Rd32 = cmpyrwh ( Rss32 , Rt32 ) :<<1 :rnd :sat" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 1 1 0 0 0 1 0 1 + + + s s s s s P P + t t t t t 1 1 0 d d d d d +# 1 1 0 0 0 1 0 1 - - - s s s s s P P - t t t t t 1 1 0 d d d d d define pcodeop cmpyrwhX2RndSat; -:cmpyrwh":<<1:rnd:sat" Rd5,rss5,rt5 EndPacket is iclass=12 & op2127=0x28 & op13=0 & op0507=6 & rss5 & rt5 & Rd5 & rd5 & $(END_PACKET) { +:cmpyrwh":<<1:rnd:sat" Rd5,rss5,rt5 EndPacket is iclass=12 & op2427=0x5 & op0507=6 & rss5 & rt5 & Rd5 & rd5 & $(END_PACKET) { Rd5 = cmpyrwhX2RndSat(rd5,rss5,rt5); build EndPacket; } # (v5,12) cmpyrwh -- "Rd32 = cmpyrwh ( Rss32 , Rt32 * ) :<<1 :rnd :sat" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 1 1 0 0 0 1 0 1 + + + s s s s s P P + t t t t t 1 1 1 d d d d d +# 1 1 0 0 0 1 0 1 - - - s s s s s P P - t t t t t 1 1 1 d d d d d -:cmpyrwh":<<1:rnd:sat" Rd5,rss5,Rt5Conjugate EndPacket is iclass=12 & op2127=0x28 & op13=0 & op0507=7 & rss5 & Rt5Conjugate & Rd5 & rd5 & $(END_PACKET) { +:cmpyrwh":<<1:rnd:sat" Rd5,rss5,Rt5Conjugate EndPacket is iclass=12 & op2427=0x5 & op0507=7 & rss5 & Rt5Conjugate & Rd5 & rd5 & $(END_PACKET) { Rd5 = cmpyrwhX2RndSat(rd5,rss5,Rt5Conjugate); build EndPacket; } @@ -4817,7 +5039,7 @@ define pcodeop cmpyrwhX2RndSat; # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| # 1 1 1 1 0 0 1 1 1 0 0 s s s s s P P - t t t t t - - - d d d d d -:combine Rd5,rt5H,rs5H EndPacket is iclass=0xf & op2127=0x1c & op13=0 & op0507=0 & Rd5 & rt5H & rs5H & $(END_PACKET) { +:combine Rd5,rt5H,rs5H EndPacket is iclass=0xf & op2127=0x1c & Rd5 & rt5H & rs5H & $(END_PACKET) { Rd5 = (zext(rt5H) << 16) + zext(rs5H); build EndPacket; } @@ -4827,7 +5049,7 @@ define pcodeop cmpyrwhX2RndSat; # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| # 1 1 1 1 0 0 1 1 1 0 1 s s s s s P P - t t t t t - - - d d d d d -:combine Rd5,rt5H,rs5L EndPacket is iclass=0xf & op2127=0x1d & op13=0 & op0507=0 & Rd5 & rt5H & rs5L & $(END_PACKET) { +:combine Rd5,rt5H,rs5L EndPacket is iclass=0xf & op2127=0x1d & Rd5 & rt5H & rs5L & $(END_PACKET) { Rd5 = (zext(rt5H) << 16) + zext(rs5L); build EndPacket; } @@ -4837,7 +5059,7 @@ define pcodeop cmpyrwhX2RndSat; # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| # 1 1 1 1 0 0 1 1 1 1 0 s s s s s P P - t t t t t - - - d d d d d -:combine Rd5,rt5L,rs5H EndPacket is iclass=0xf & op2127=0x1e & op13=0 & op0507=0 & Rd5 & rt5L & rs5H & $(END_PACKET) { +:combine Rd5,rt5L,rs5H EndPacket is iclass=0xf & op2127=0x1e & Rd5 & rt5L & rs5H & $(END_PACKET) { Rd5 = (zext(rt5L) << 16) + zext(rs5H); build EndPacket; } @@ -4847,7 +5069,7 @@ define pcodeop cmpyrwhX2RndSat; # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| # 1 1 1 1 0 0 1 1 1 1 1 s s s s s P P - t t t t t - - - d d d d d -:combine Rd5,rt5L,rs5L EndPacket is iclass=0xf & op2127=0x1f & op13=0 & op0507=0 & Rd5 & rt5L & rs5L & $(END_PACKET) { +:combine Rd5,rt5L,rs5L EndPacket is iclass=0xf & op2127=0x1f & Rd5 & rt5L & rs5L & $(END_PACKET) { Rd5 = (zext(rt5L) << 16) + zext(rs5L); build EndPacket; } @@ -4855,9 +5077,9 @@ define pcodeop cmpyrwhX2RndSat; # (v4,7) combine -- "Rdd32 = combine ( #s8 , #U6x )" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 0 1 1 1 1 1 0 0 1 + + I I I I I P P I i i i i i i i i d d d d d +# 0 1 1 1 1 1 0 0 1 - - I I I I I P P I i i i i i i i i d d d d d -:combine Rdd5,Simm8_0512,Uimm32_1620_13x EndPacket is iclass=7 & op2127=0x64 & Rdd5 & rdd5h_ & rd5_ & Simm8_0512 & Uimm32_1620_13x & $(END_PACKET) { +:combine Rdd5,Simm8_0512,Uimm32_1620_13x EndPacket is iclass=7 & op2327=0x19 & Rdd5 & rdd5h_ & rd5_ & Simm8_0512 & Uimm32_1620_13x & $(END_PACKET) { build Rdd5; # build Rdd5 and assign hi/lo words separately to aid analysis rdd5h_ = sext(Simm8_0512); rd5_ = Uimm32_1620_13x; @@ -4875,23 +5097,13 @@ define pcodeop cmpyrwhX2RndSat; rd5_ = sext(Simm8_1622_13); build EndPacket; } -# Special case (no immext): Rdd=combine(#-1,#s8) where s8 < 0 (maps to Rdd=#s8) -:assign Rdd5,Simm8_1622_13 EndPacket is iclass=7 & op2427=0xc & op23=0 & Rdd5 & Simm8_1622_13 & s0512=0xff & s22=1 & immext=0 & $(END_PACKET) { - Rdd5 = sext(Simm8_1622_13); - build EndPacket; -} -# Special case (no immext): Rdd=combine(#0,#s8) where s8 > 0 (maps to Rdd=#s8) -:assign Rdd5,Simm8_1622_13 EndPacket is iclass=7 & op2427=0xc & op23=0 & Rdd5 & Simm8_1622_13 & s0512=0 & s22=0 & immext=0 & $(END_PACKET) { - Rdd5 = zext(Simm8_1622_13); - build EndPacket; -} # (v4,7) combine -- "Rdd32 = combine ( #s8x , Rs32 )" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 0 1 1 1 0 0 1 1 + 0 1 s s s s s P P 1 i i i i i i i i d d d d d +# 0 1 1 1 0 0 1 1 - 0 1 s s s s s P P 1 i i i i i i i i d d d d d -:combine Rdd5,Simm32_0512x,rs5 EndPacket is iclass=7 & op2127=0x19 & op13=1 & Rdd5 & rdd5h_ & rd5_ & rs5 & Simm32_0512x & $(END_PACKET) { +:combine Rdd5,Simm32_0512x,rs5 EndPacket is iclass=7 & op2427=0x3 & op2122=0x1 & op13=1 & Rdd5 & rdd5h_ & rd5_ & rs5 & Simm32_0512x & $(END_PACKET) { build Rdd5; # build Rdd5 and assign hi/lo words separately to aid analysis rdd5h_ = Simm32_0512x; rd5_ = rs5; @@ -4901,9 +5113,9 @@ define pcodeop cmpyrwhX2RndSat; # (v4,7) combine -- "Rdd32 = combine ( Rs32 , #s8x )" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 0 1 1 1 0 0 1 1 + 0 0 s s s s s P P 1 i i i i i i i i d d d d d +# 0 1 1 1 0 0 1 1 - 0 0 s s s s s P P 1 i i i i i i i i d d d d d -:combine Rdd5,rs5,Simm32_0512x EndPacket is iclass=7 & op2127=0x18 & op13=1 & Rdd5 & rdd5h_ & rd5_ & rs5 & Simm32_0512x & $(END_PACKET) { +:combine Rdd5,rs5,Simm32_0512x EndPacket is iclass=7 & op2427=0x3 & op2122=0x0 & op13=1 & Rdd5 & rdd5h_ & rd5_ & rs5 & Simm32_0512x & $(END_PACKET) { build Rdd5; # build Rdd5 and assign hi/lo words separately to aid analysis rdd5h_ = rs5; rd5_ = Simm32_0512x; @@ -4915,7 +5127,7 @@ define pcodeop cmpyrwhX2RndSat; # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| # 1 1 1 1 0 1 0 1 0 - - s s s s s P P - t t t t t - - - d d d d d -:combine Rdd5,rs5,rt5 EndPacket is iclass=0xf & op2427=5 & op2123=0 & op13=0 & op0507=0 & Rdd5 & rdd5h_ & rd5_ & rs5 & rt5 & $(END_PACKET) { +:combine Rdd5,rs5,rt5 EndPacket is iclass=0xf & op2427=5 & op23=0 & Rdd5 & rdd5h_ & rd5_ & rs5 & rt5 & $(END_PACKET) { build Rdd5; # build Rdd5 and assign hi/lo words separately to aid analysis rdd5h_ = rs5; rd5_ = rt5; @@ -4940,14 +5152,15 @@ define pcodeop cmpyrwhX2RndSat; # (v2,15) combine -- "if ( ! Pu4 .new ) Rdd32 = combine ( Rs32 , Rt32 )" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 1 1 1 1 1 1 0 1 + + + s s s s s P P 1 t t t t t 1 u u d d d d d +# 1 1 1 1 1 1 0 1 0 0 0 s s s s s P P 1 t t t t t 1 u u d d d d d -:combine^PuCond0506_N13_S07 rdd5,rs5,rt5 EndPacket is iclass=15 & op2127=0x68 & PuCond0506_N13_S07 & rs5 & rt5 & rdd5 & rdd5h & rd5 & $(END_PACKET) { +:combine^PuCond0506_N13_S07 rdd5,rs5,rt5 EndPacket is iclass=15 & op2427=0xd & op23=0 & op22=0 & op21=0 & PuCond0506_N13_S07 & rs5 & rt5 & rdd5 & rdd5h & rd5 & $(END_PACKET) { hi:4 = rs5; lo:4 = rt5; build PuCond0506_N13_S07; build EndPacket; <> + build PuCond0506_N13_S07; if (ConditionReg == 0) goto ; # Write hi/lo regs separately to simplify analysis rdd5h = hi; @@ -4955,29 +5168,22 @@ define pcodeop cmpyrwhX2RndSat; } -# if ([!]Pu4[.new]) Rdd32 = Rs32:Rt32 ( simplification of if ([!]Pu4[.new]) Rdd32 = combine ( Rs32 , Rt32 ) -# where Rs32 is odd and Rt32 is the corresponding low reg -:assign^PuCond0506_N13_S07 rdd5,rtt5 EndPacket is iclass=15 & op2127=0x68 & op16=1 & op8=0 & op0912=op1720 & PuCond0506_N13_S07 & rtt5 & rdd5 & $(END_PACKET) { - tmp:8 = rtt5; - build PuCond0506_N13_S07; - build EndPacket; - <> - if (ConditionReg == 0) goto ; - rdd5 = tmp; - -} - # (v4,8) cround -- "Rd32 = cround ( Rs32 , #u5 )" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 1 0 0 0 1 1 0 0 1 1 1 s s s s s P P 0 i i i i i 0 0 + d d d d d +# 1 0 0 0 1 1 0 0 1 1 1 s s s s s P P 0 i i i i i 0 0 - d d d d d -:cround Rd5,rs5,Uimm8_0812 EndPacket is iclass=8 & op2127=0x67 & op13=0 & op0507=0 & Rd5 & rs5 & Uimm8_0812 & $(END_PACKET) { +:cround Rd5,rs5,Uimm8_0812 EndPacket is iclass=8 & op2127=0x67 & op13=0 & op0607=0 & Rd5 & rs5 & Uimm8_0812 & $(END_PACKET) { Rd5 = roundConvergent(rs5, Uimm8_0812); build EndPacket; } -:cround Rdd5,rss5,Uimm8_0813 EndPacket is iclass=8 & op2127=0x67 & op13=0 & op0507=2 & Rdd5 & rss5 & Uimm8_0813 & $(END_PACKET) { +# (v67,8) cround -- "Rdd32 = cround ( Rss32 , #u6 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 0 0 1 1 0 0 1 1 1 s s s s s P P i i i i i i 0 1 - d d d d d + +:cround Rdd5,rss5,Uimm8_0813 EndPacket is iclass=8 & op2127=0x67 & op0607=1 & Rdd5 & rss5 & Uimm8_0813 & $(END_PACKET) { Rdd5 = roundConvergent(rss5, Uimm8_0813); build EndPacket; } @@ -4986,14 +5192,19 @@ define pcodeop cmpyrwhX2RndSat; # (v4,12) cround -- "Rd32 = cround ( Rs32 , Rt32 )" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 1 1 0 0 0 1 1 0 1 1 + s s s s s P P + t t t t t 0 0 + d d d d d +# 1 1 0 0 0 1 1 0 1 1 - s s s s s P P - t t t t t 0 0 - d d d d d -:cround Rd5,rs5,rt5 EndPacket is iclass=12 & op2127=0x36 & op13=0 & op0507=0 & Rd5 & rs5 & rt5 & $(END_PACKET) { +:cround Rd5,rs5,rt5 EndPacket is iclass=12 & op2227=0x1b & op0607=0 & Rd5 & rs5 & rt5 & $(END_PACKET) { Rd5 = roundConvergent(rs5, rt5); build EndPacket; } -:cround Rdd5,rss5,rt5 EndPacket is iclass=12 & op2127=0x36 & op13=0 & op0507=2 & Rdd5 & rss5 & rt5 & $(END_PACKET) { +# (v67,12) cround -- "Rdd32 = cround ( Rss32 , Rt32 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 0 0 0 1 1 0 1 1 - s s s s s P P - t t t t t 0 1 - d d d d d + +:cround Rdd5,rss5,rt5 EndPacket is iclass=12 & op2227=0x1b & op0607=1 & Rdd5 & rss5 & rt5 & $(END_PACKET) { Rdd5 = roundConvergent(rss5, rt5); build EndPacket; } @@ -5001,9 +5212,9 @@ define pcodeop cmpyrwhX2RndSat; # (v2,6) crswap -- "crswap ( Rx32 , sgp0 )" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 0 1 1 0 0 1 0 1 0 0 0 x x x x x P P + + + + + + + + + + + + + + +# 0 1 1 0 0 1 0 1 0 0 0 x x x x x P P - - - - - - - - - - - - - - -:crswap Rx5,S0 EndPacket is iclass=6 & op2127=0x28 & op0013=0x00 & Rx5 & rx5 & S0 & $(END_PACKET) { +:crswap Rx5,S0 EndPacket is iclass=6 & op2127=0x28 & Rx5 & rx5 & S0 & $(END_PACKET) { # TODO: Verify semantics - this was a guess based upon mnemonic tmp:4 = S0; S0 = rx5; @@ -5014,9 +5225,9 @@ define pcodeop cmpyrwhX2RndSat; # (v4,6) crswap -- "crswap ( Rx32 , sgp1 )" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 0 1 1 0 0 1 0 1 0 0 1 x x x x x P P + + + + + + + + + + + + + + +# 0 1 1 0 0 1 0 1 0 0 1 x x x x x P P - - - - - - - - - - - - - - -:crswap Rx5,S1 EndPacket is iclass=6 & op2127=0x29 & op0013=0x00 & Rx5 & rx5 & S1 & $(END_PACKET) { +:crswap Rx5,S1 EndPacket is iclass=6 & op2127=0x29 & Rx5 & rx5 & S1 & $(END_PACKET) { # TODO: Verify semantics - this was a guess based upon mnemonic tmp:4 = S1; S1 = rx5; @@ -5027,9 +5238,9 @@ define pcodeop cmpyrwhX2RndSat; # (v4,6) crswap -- "crswap ( Rxx32 , sgp1:0 )" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 0 1 1 0 1 1 0 1 1 + + x x x x x P P + + + + + + + + + 0 0 0 0 0 +# 0 1 1 0 1 1 0 1 1 - - x x x x x P P - - - - - - - - - 0 0 0 0 0 -:crswap Rxx5,S1S0 EndPacket is iclass=6 & op2127=0x6c & op0013=0x00 & Rxx5 & rxx5 & S1S0 & $(END_PACKET) { +:crswap Rxx5,S1S0 EndPacket is iclass=6 & op2327=0x1b & op0004=0x0 & Rxx5 & rxx5 & S1S0 & $(END_PACKET) { # TODO: Verify semantics - this was a guess based upon mnemonic tmp:8 = S1S0; S1S0 = rxx5; @@ -5040,11 +5251,11 @@ define pcodeop cmpyrwhX2RndSat; # (v2,6) cswi -- "cswi ( Rs32 )" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 0 1 1 0 0 1 0 0 0 0 0 s s s s s P P + + + + + + 0 0 1 + + + + + +# 0 1 1 0 0 1 0 0 0 0 0 s s s s s P P - - - - - - 0 0 1 - - - - - define pcodeop cswi; -:cswi rs5 EndPacket is iclass=6 & op2127=0x20 & op0013=0x20 & rs5 & $(END_PACKET) { +:cswi rs5 EndPacket is iclass=6 & op2127=0x20 & op0507=0x1 & rs5 & $(END_PACKET) { cswi(rs5); build EndPacket; } @@ -5052,9 +5263,9 @@ define pcodeop cswi; # (v2,8) ct0 -- "Rd32 = ct0 ( Rs32 )" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 1 0 0 0 1 1 0 0 0 1 0 s s s s s P P + + + + + + 1 0 0 d d d d d +# 1 0 0 0 1 1 0 0 0 1 0 s s s s s P P - - - - - - 1 0 0 d d d d d -:ct0 Rd5,rs5 EndPacket is iclass=8 & op2127=0x62 & op0513=4 & Rd5 & rs5 & $(END_PACKET) { +:ct0 Rd5,rs5 EndPacket is iclass=8 & op2127=0x62 & op0507=4 & Rd5 & rs5 & $(END_PACKET) { Rd5 = countTrailingZeros(rs5); build EndPacket; } @@ -5062,9 +5273,9 @@ define pcodeop cswi; # (v4,8) ct0 -- "Rd32 = ct0 ( Rss32 )" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 1 0 0 0 1 0 0 0 1 1 1 s s s s s P P + + + + + + 0 1 + d d d d d +# 1 0 0 0 1 0 0 0 1 1 1 s s s s s P P - - - - - - 0 1 0 d d d d d -:ct0 Rd5,rss5 EndPacket is iclass=8 & op2127=0x47 & op0513=2 & Rd5 & rss5 & $(END_PACKET) { +:ct0 Rd5,rss5 EndPacket is iclass=8 & op2127=0x47 & op0607=1 & op5=0 & Rd5 & rss5 & $(END_PACKET) { Rd5 = countTrailingZeros(rss5); build EndPacket; } @@ -5072,9 +5283,9 @@ define pcodeop cswi; # (v2,8) ct1 -- "Rd32 = ct1 ( Rs32 )" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 1 0 0 0 1 1 0 0 0 1 0 s s s s s P P + + + + + + 1 0 1 d d d d d +# 1 0 0 0 1 1 0 0 0 1 0 s s s s s P P - - - - - - 1 0 1 d d d d d -:ct1 Rd5,rs5 EndPacket is iclass=8 & op2127=0x62 & op0513=5 & Rd5 & rs5 & $(END_PACKET) { +:ct1 Rd5,rs5 EndPacket is iclass=8 & op2127=0x62 & op0507=5 & Rd5 & rs5 & $(END_PACKET) { Rd5 = countTrailingOnes(rs5); build EndPacket; } @@ -5082,9 +5293,9 @@ define pcodeop cswi; # (v4,8) ct1 -- "Rd32 = ct1 ( Rss32 )" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 1 0 0 0 1 0 0 0 1 1 1 s s s s s P P + + + + + + 1 0 + d d d d d +# 1 0 0 0 1 0 0 0 1 1 1 s s s s s P P - - - - - - 1 0 0 d d d d d -:ct1 Rd5,rss5 EndPacket is iclass=8 & op2127=0x47 & op0513=0x04 & Rd5 & rss5 & $(END_PACKET) { +:ct1 Rd5,rss5 EndPacket is iclass=8 & op2127=0x47 & op0607=0x2 & op5=0 & Rd5 & rss5 & $(END_PACKET) { Rd5 = countTrailingOnes(rss5); build EndPacket; } @@ -5092,7 +5303,7 @@ define pcodeop cswi; # (v65,6) ctlbw -- "Rd32 = ctlbw ( Rss32 , Rt32 )" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 0 1 1 0 1 1 0 0 1 1 0 s s s s s P P 0 t t t t t + + + d d d d d +# 0 1 1 0 1 1 0 0 1 1 0 s s s s s P P 0 t t t t t - - - d d d d d define pcodeop ctlbw; :ctlbw Rd5,rss5,rt5 EndPacket is iclass=6 & op2127=0x66 & op13=0 & rss5 & rt5 & Rd5 & $(END_PACKET) { @@ -5103,11 +5314,11 @@ define pcodeop ctlbw; # (v2,10) dccleana -- "dccleana ( Rs32 )" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 1 0 1 0 0 0 0 0 0 0 0 s s s s s P P + + + + + + + + + + + + + + +# 1 0 1 0 0 0 0 0 0 0 0 s s s s s P P - - - - - - - - - - - - - - define pcodeop dccleana; -:dccleana rs5 EndPacket is iclass=10 & op2127=0 & op0013=0 & rs5 & $(END_PACKET) { +:dccleana rs5 EndPacket is iclass=10 & op2127=0 & rs5 & $(END_PACKET) { dccleana(rs5); build EndPacket; } @@ -5115,11 +5326,11 @@ define pcodeop dccleana; # (v2,10) dccleanidx -- "dccleanidx ( Rs32 )" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 1 0 1 0 0 0 1 0 0 0 1 s s s s s P P + + + + + + + + + + + + + + +# 1 0 1 0 0 0 1 0 0 0 1 s s s s s P P - - - - - - - - - - - - - - define pcodeop dccleanidx; -:dccleanidx rs5 EndPacket is iclass=10 & op2127=0x11 & op0013=0 & rs5 & $(END_PACKET) { +:dccleanidx rs5 EndPacket is iclass=10 & op2127=0x11 & rs5 & $(END_PACKET) { dccleanidx(rs5); build EndPacket; } @@ -5127,11 +5338,11 @@ define pcodeop dccleanidx; # (v2,10) dccleaninva -- "dccleaninva ( Rs32 )" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 1 0 1 0 0 0 0 0 0 1 0 s s s s s P P + + + + + + + + + + + + + + +# 1 0 1 0 0 0 0 0 0 1 0 s s s s s P P - - - - - - - - - - - - - - define pcodeop dccleaninva; -:dccleaninva rs5 EndPacket is iclass=10 & op2127=0x02 & op0013=0 & rs5 & $(END_PACKET) { +:dccleaninva rs5 EndPacket is iclass=10 & op2127=0x02 & rs5 & $(END_PACKET) { dccleaninva(rs5); build EndPacket; } @@ -5139,11 +5350,11 @@ define pcodeop dccleaninva; # (v2,10) dccleaninvidx -- "dccleaninvidx ( Rs32 )" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 1 0 1 0 0 0 1 0 0 1 1 s s s s s P P + + + + + + + + + + + + + + +# 1 0 1 0 0 0 1 0 0 1 1 s s s s s P P - - - - - - - - - - - - - - define pcodeop dccleaninvidx; -:dccleaninvidx rs5 EndPacket is iclass=10 & op2127=0x13 & op0013=0 & rs5 & $(END_PACKET) { +:dccleaninvidx rs5 EndPacket is iclass=10 & op2127=0x13 & rs5 & $(END_PACKET) { dccleaninvidx(rs5); build EndPacket; } @@ -5151,14 +5362,14 @@ define pcodeop dccleaninvidx; # (v2,9) dcfetch -- "dcfetch ( Rs32 + #u11:3 )" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 1 0 0 1 0 1 0 0 0 0 0 s s s s s P P 0 + + i i i i i i i i i i i +# 1 0 0 1 0 1 0 0 0 0 0 s s s s s P P 0 - - i i i i i i i i i i i FetchAddrRsReld: "("^rs5^"+"^Uimm16_0010_shift3^")" is rs5 & Uimm16_0010_shift3 { ptr:4 = rs5 + zext(Uimm16_0010_shift3); export *[ram]:8 ptr; } FetchAddrRsReld: "("^rs5^")" is rs5 & i0010=0 { export *[ram]:8 rs5; } define pcodeop dcfetch; -:dcfetch FetchAddrRsReld EndPacket is iclass=9 & op2127=0x20 & op1112=0 & FetchAddrRsReld & $(END_PACKET) { +:dcfetch^MemNt13 FetchAddrRsReld EndPacket is iclass=9 & op2127=0x20 & FetchAddrRsReld & MemNt13 & $(END_PACKET) { dcfetch(FetchAddrRsReld); build EndPacket; } @@ -5166,11 +5377,11 @@ define pcodeop dcfetch; # (v2,10) dcinva -- "dcinva ( Rs32 )" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 1 0 1 0 0 0 0 0 0 0 1 s s s s s P P + + + + + + + + + + + + + + +# 1 0 1 0 0 0 0 0 0 0 1 s s s s s P P - - - - - - - - - - - - - - define pcodeop dcinva; -:dcinva rs5 EndPacket is iclass=10 & op2127=0x01 & op0013=0 & rs5 & $(END_PACKET) { +:dcinva rs5 EndPacket is iclass=10 & op2127=0x01 & rs5 & $(END_PACKET) { dcinva(rs5); build EndPacket; } @@ -5178,11 +5389,11 @@ define pcodeop dcinva; # (v2,10) dcinvidx -- "dcinvidx ( Rs32 )" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 1 0 1 0 0 0 1 0 0 1 0 s s s s s P P + + + + + + + + + + + + + + +# 1 0 1 0 0 0 1 0 0 1 0 s s s s s P P - - - - - - - - - - - - - - define pcodeop dcinvidx; -:dcinvidx rs5 EndPacket is iclass=10 & op2127=0x12 & op0013=0 & rs5 & $(END_PACKET) { +:dcinvidx rs5 EndPacket is iclass=10 & op2127=0x12 & rs5 & $(END_PACKET) { dcinvidx(rs5); build EndPacket; } @@ -5190,11 +5401,11 @@ define pcodeop dcinvidx; # (v2,10) dckill -- "dckill" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 1 0 1 0 0 0 1 0 0 0 0 + + + + + P P + + + + + + + + + + + + + + +# 1 0 1 0 0 0 1 0 0 0 0 - - - - - P P - - - - - - - - - - - - - - define pcodeop dckill; -:dckill EndPacket is iclass=10 & op2127=0x10 & op1620=0 & op0013=0 & $(END_PACKET) { +:dckill EndPacket is iclass=10 & op2127=0x10 & $(END_PACKET) { dckill(); build EndPacket; } @@ -5202,11 +5413,11 @@ define pcodeop dckill; # (v2,10) dctagr -- "Rd32 = dctagr ( Rs32 )" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 1 0 1 0 0 1 0 0 0 0 1 s s s s s P P + + + + + + + + + d d d d d +# 1 0 1 0 0 1 0 0 0 0 1 s s s s s P P - - - - - - - - - d d d d d define pcodeop dctagr; -:dctagr Rd5,rs5 EndPacket is iclass=10 & op2127=0x21 & op0513=0 & rs5 & Rd5 & $(END_PACKET) { +:dctagr Rd5,rs5 EndPacket is iclass=10 & op2127=0x21 & rs5 & Rd5 & $(END_PACKET) { Rd5 = dctagr(rs5); build EndPacket; } @@ -5214,154 +5425,165 @@ define pcodeop dctagr; # (v2,10) dctagw -- "dctagw ( Rs32 , Rt32 )" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 1 0 1 0 0 1 0 0 0 0 0 s s s s s P P + t t t t t + + + + + + + + +# 1 0 1 0 0 1 0 0 0 0 0 s s s s s P P - t t t t t - - - - - - - - define pcodeop dctagw; -:dctagw rs5,rt5 EndPacket is iclass=10 & op2127=0x20 & op13=0 & op0007=0 & rs5 & rt5 & $(END_PACKET) { +:dctagw rs5,rt5 EndPacket is iclass=10 & op2127=0x20 & rs5 & rt5 & $(END_PACKET) { dctagw(rs5,rt5); build EndPacket; } -# (v2,10) dczeroa -- "dczeroa ( Rs32 )" +# (v2,10) dczeroa -- "dczeroa ( Rs32 )" (bit13=1 selects the ":nt" hint) # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 1 0 1 0 0 0 0 0 1 1 0 s s s s s P P 0 + + + + + + + + + + + + + +# 1 0 1 0 0 0 0 0 1 1 0 s s s s s P P - - - - - - - - - - - - - - define pcodeop dczeroa; -:dczeroa rs5 EndPacket is iclass=10 & op2127=0x06 & op0013=0 & rs5 & $(END_PACKET) { +:dczeroa^MemNt13 rs5 EndPacket is iclass=10 & op2127=0x06 & rs5 & MemNt13 & $(END_PACKET) { dczeroa(rs5); build EndPacket; } -# (v4,9) dealloc_return -- "dealloc_return" +# (v65,9) dealloc_return -- "Rdd32 = dealloc_return ( Rs32 ):raw" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 1 0 0 1 0 1 1 0 0 0 0 1 1 1 1 0 P P 0 0 0 0 + + + + + 1 1 1 1 0 +# 1 0 0 1 0 1 1 0 0 0 0 s s s s s P P 0 0 0 0 - - - - - d d d d d -:dealloc_return EndPacket is iclass=9 & op2127=0x30 & op1620=0x1e & op0013=0x001e & $(END_PACKET) { +:dealloc_return^":raw" rdd5,rs5 EndPacket is iclass=9 & op2127=0x30 & op1013=0x0 & rs5 & rdd5 & rdd5h & DeallocFrameRddRsRaw & $(END_PACKET) { + build DeallocFrameRddRsRaw; # consumes rs5 and updates rdd5, and SP during <> build EndPacket; <> - deallocframe(FP); - return [LR]; + return [rdd5h]; } # (v4,9) dealloc_return -- "dealloc_return" +# LR:FP = dealloc_return(FP):raw # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 1 0 0 1 0 1 1 0 0 0 0 s s s s s P P 0 0 0 0 + + + + + 1 1 1 1 0 +# 1 0 0 1 0 1 1 0 0 0 0 1 1 1 1 0 P P 0 0 0 0 - - - - - 1 1 1 1 0 -:dealloc_return rs5 EndPacket is iclass=9 & op2127=0x30 & rs5 & op0013=0x001e & $(END_PACKET) { +:dealloc_return EndPacket is iclass=9 & op2127=0x30 & op1620=0x1e & op1013=0x0 & op0004=0x1e & DeallocFrameRddRsRaw & $(END_PACKET) { + build DeallocFrameRddRsRaw; # consumes FP and updates LR, FP, and SP during <> build EndPacket; <> - deallocframe(rs5); return [LR]; } -# dealloc_return -- "if ( Ps4 ) dealloc_return" +# (v4,9) dealloc_return -- "if ( Ps4 ) dealloc_return" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 1 0 0 1 0 1 1 0 0 0 0 1 1 1 1 0 P P 0 1 0 0 s s + + + 1 1 1 1 0 +# 1 0 0 1 0 1 1 0 0 0 0 1 1 1 1 0 P P 0 1 0 0 s s - - - 1 1 1 1 0 # -# dealloc_return -- "if ( ! Ps4 ) dealloc_return" +# (v4,9) dealloc_return -- "if ( ! Ps4 ) dealloc_return" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 1 0 0 1 0 1 1 0 0 0 0 1 1 1 1 0 P P 1 1 0 0 s s + + + 1 1 1 1 0 +# 1 0 0 1 0 1 1 0 0 0 0 1 1 1 1 0 P P 1 1 0 0 s s - - - 1 1 1 1 0 # -# dealloc_return:nt -- "if ( Ps4 .new ) dealloc_return:nt" +# (v4,9) dealloc_return:nt -- "if ( Ps4 .new ) dealloc_return:nt" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 1 0 0 1 0 1 1 0 0 0 0 1 1 1 1 0 P P 0 0 1 0 s s + + + 1 1 1 1 0 +# 1 0 0 1 0 1 1 0 0 0 0 1 1 1 1 0 P P 0 0 1 0 s s - - - 1 1 1 1 0 # -# dealloc_return:nt -- "if ( ! Ps4 .new ) dealloc_return:nt" +# (v4,9) dealloc_return:nt -- "if ( ! Ps4 .new ) dealloc_return:nt" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 1 0 0 1 0 1 1 0 0 0 0 1 1 1 1 0 P P 1 0 1 0 s s + + + 1 1 1 1 0 +# 1 0 0 1 0 1 1 0 0 0 0 1 1 1 1 0 P P 1 0 1 0 s s - - - 1 1 1 1 0 # -# dealloc_return:t -- "if ( Ps4 .new ) dealloc_return:t" +# (v4,9) dealloc_return:t -- "if ( Ps4 .new ) dealloc_return:t" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 1 0 0 1 0 1 1 0 0 0 0 1 1 1 1 0 P P 0 1 1 0 s s + + + 1 1 1 1 0 +# 1 0 0 1 0 1 1 0 0 0 0 1 1 1 1 0 P P 0 1 1 0 s s - - - 1 1 1 1 0 # -# dealloc_return:t -- "if ( ! Ps4 .new ) dealloc_return:t" +# (v4,9) dealloc_return:t -- "if ( ! Ps4 .new ) dealloc_return:t" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 1 0 0 1 0 1 1 0 0 0 0 1 1 1 1 0 P P 1 1 1 0 s s + + + 1 1 1 1 0 +# 1 0 0 1 0 1 1 0 0 0 0 1 1 1 1 0 P P 1 1 1 0 s s - - - 1 1 1 1 0 DRTaken12: is op11=0 & op12=1 { } DRTaken12: ":t" is op11=1 & op12=1 { } DRTaken12: ":nt" is op11=1 & op12=0 { } -:dealloc_return^FlowCond0809_N11_S13^DRTaken12 EndPacket is iclass=9 & op2127=0x30 & op1620=0x1e & (op1112=2 | op11=1) & op0007=0x1e & FlowCond0809_N11_S13 & DRTaken12 & $(END_PACKET) { - build FlowCond0809_N11_S13; +:dealloc_return^FlowCond0809_N11_S13^DRTaken12 EndPacket is iclass=9 & op2127=0x30 & op1620=0x1e & op0004=0x1e & (op1112=2 | op11=1) & FlowCond0809_N11_S13 & DeallocFrameRddRsRawCond & DRTaken12 & $(END_PACKET) { + build FlowCond0809_N11_S13; # Establishes ConditionReg during <> and <> + build DeallocFrameRddRsRawCond; # consumes FP and conditionally updates LR, FP, and SP during <> build EndPacket; <> + build FlowCond0809_N11_S13; if (ConditionReg == 0) goto ; - deallocframe(FP); return [LR]; } -# (v4,9) dealloc_return -- "if ( Ps4 ) dealloc_return" +# (v4,9) dealloc_return -- "if ( Ps4 ) Rdd32 = dealloc_return (Rs32 ):raw" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 1 0 0 1 0 1 1 0 0 0 0 s s s s s P P 0 1 0 0 s s + + + 1 1 1 1 0 +# 1 0 0 1 0 1 1 0 0 0 0 s s s s s P P 0 1 0 0 s s - - - d d d d d # -# (v4,9) dealloc_return -- "if ( ! Ps4 ) dealloc_return" +# (v4,9) dealloc_return -- "if ( ! Ps4 ) Rdd32 = dealloc_return (Rs32 ):raw" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 1 0 0 1 0 1 1 0 0 0 0 s s s s s P P 1 1 0 0 s s + + + 1 1 1 1 0 +# 1 0 0 1 0 1 1 0 0 0 0 s s s s s P P 1 1 0 0 s s - - - d d d d d # -# (v4,9) dealloc_return:nt -- "if ( Ps4 .new ) dealloc_return:nt" +# (v4,9) dealloc_return:nt -- "if ( Ps4 .new ) Rdd32 = dealloc_return:nt (Rs32 ):raw" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 1 0 0 1 0 1 1 0 0 0 0 s s s s s P P 0 0 1 0 s s + + + 1 1 1 1 0 +# 1 0 0 1 0 1 1 0 0 0 0 s s s s s P P 0 0 1 0 s s - - - d d d d d # -# (v4,9) dealloc_return:nt -- "if ( ! Ps4 .new ) dealloc_return:nt" +# (v4,9) dealloc_return:nt -- "if ( ! Ps4 .new ) Rdd32 = dealloc_return:nt (Rs32 ):raw" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 1 0 0 1 0 1 1 0 0 0 0 s s s s s P P 1 0 1 0 s s + + + 1 1 1 1 0 +# 1 0 0 1 0 1 1 0 0 0 0 s s s s s P P 1 0 1 0 s s - - - d d d d d # -# (v4,9) dealloc_return:t -- "if ( Ps4 .new ) dealloc_return:t" +# (v4,9) dealloc_return:t -- "if ( Ps4 .new ) Rdd32 = dealloc_return:t (Rs32 ):raw" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 1 0 0 1 0 1 1 0 0 0 0 s s s s s P P 0 1 1 0 s s + + + 1 1 1 1 0 +# 1 0 0 1 0 1 1 0 0 0 0 s s s s s P P 0 1 1 0 s s - - - d d d d d # -# (v4,9) dealloc_return:t -- "if ( ! Ps4 .new ) dealloc_return:t" +# (v4,9) dealloc_return:t -- "if ( ! Ps4 .new ) Rdd32 = dealloc_return:t (Rs32 ):raw" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 1 0 0 1 0 1 1 0 0 0 0 s s s s s P P 1 1 1 0 s s + + + 1 1 1 1 0 +# 1 0 0 1 0 1 1 0 0 0 0 s s s s s P P 1 1 1 0 s s - - - d d d d d -:dealloc_return^FlowCond0809_N11_S13^DRTaken12 rs5 EndPacket is iclass=9 & op2127=0x30 & rs5 & (op1112=2 | op11=1) & op0007=0x1e & FlowCond0809_N11_S13 & DRTaken12 & $(END_PACKET) { - build FlowCond0809_N11_S13; +:dealloc_return^FlowCond0809_N11_S13^DRTaken12^":raw" rdd5,rs5 EndPacket is iclass=9 & op2127=0x30 & rdd5 & rdd5h & rs5 & (op1112=2 | op11=1) & FlowCond0809_N11_S13 & DeallocFrameRddRsRawCond & DRTaken12 & $(END_PACKET) { + build FlowCond0809_N11_S13; # Establishes ConditionReg during <> and <> + build DeallocFrameRddRsRawCond; # # consumes rs5 and updates rdd5, and SP during <> build EndPacket; <> + build FlowCond0809_N11_S13; if (ConditionReg == 0) goto ; - deallocframe(rs5); - return [LR]; + return [rdd5h]; } - # (v2,9) deallocframe -- "deallocframe" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 1 0 0 1 0 0 0 0 0 0 0 1 1 1 1 0 P P 0 - - - - - - - - 1 1 1 1 0 +# 1 0 0 1 0 0 0 0 0 0 0 1 1 1 1 0 P P 0 - - - - - - - - 1 1 1 1 0 -:deallocframe EndPacket is iclass=9 & op2527=0 & op2224=0 & op21=0 & op1620=0x1e & op13=0 & op0512=0 & op0004=0x1e & $(END_PACKET) { +:deallocframe EndPacket is iclass=9 & op2527=0 & op2224=0 & op21=0 & op1620=0x1e & op13=0 & op0004=0x1e & DeallocFrameRddRsRaw & $(END_PACKET) { + build DeallocFrameRddRsRaw; # consumes FP and updates LR, FP, and SP during <> + build EndPacket; +} + +# (v65,9) deallocframe -- "Rdd32 = deallocframe ( Rs32 ):raw" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 0 1 0 0 0 0 0 0 0 s s s s s P P 0 - - - - - - - - d d d d d + +:deallocframe^":raw" rdd5,rs5 EndPacket is iclass=9 & op2127=0x0 & op13=0 & rdd5 & rs5 & DeallocFrameRddRsRaw & $(END_PACKET) { + build DeallocFrameRddRsRaw; # consumes rs5 and updates rdd5, and SP during <> build EndPacket; - <> - deallocframe(FP); } # (v4,12) decbin -- "Rdd32 = decbin ( Rss32 , Rtt32 )" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 1 1 0 0 0 0 0 1 1 1 + s s s s s P P + t t t t t 1 1 + d d d d d +# 1 1 0 0 0 0 0 1 1 1 - s s s s s P P - t t t t t 1 1 - d d d d d define pcodeop decbin; -:decbin Rdd5,rss5,rtt5 EndPacket is iclass=12 & op2127=0x0e & op13=0 & op0507=6 & Rdd5 & rss5 & rtt5 & $(END_PACKET) { +:decbin Rdd5,rss5,rtt5 EndPacket is iclass=12 & op2227=0x7 & op0607=3 & Rdd5 & rss5 & rtt5 & $(END_PACKET) { Rdd5 = decbin(rss5, rtt5); build EndPacket; } @@ -5369,9 +5591,9 @@ define pcodeop decbin; # (v2,8) deinterleave -- "Rdd32 = deinterleave ( Rss32 )" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 1 0 0 0 0 0 0 0 1 1 + s s s s s P P + + + + + + 1 0 0 d d d d d +# 1 0 0 0 0 0 0 0 1 1 0 s s s s s P P - - - - - - 1 0 0 d d d d d define pcodeop deinterleave; -:deinterleave Rdd5,rss5 EndPacket is iclass=8 & op2127=0x06 & op0513=0x04 & Rdd5 & rss5 & $(END_PACKET) { +:deinterleave Rdd5,rss5 EndPacket is iclass=8 & op2227=0x3 & op21=0 & op0507=0x4 & Rdd5 & rss5 & $(END_PACKET) { Rdd5 = deinterleave(rss5); build EndPacket; } @@ -5379,7 +5601,7 @@ define pcodeop deinterleave; # (v69,6) diag -- "diag ( Rs32 )" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 0 1 1 0 0 0 1 0 0 1 0 s s s s s P P + + + + + + 0 0 1 + + + + + +# 0 1 1 0 0 0 1 0 0 1 0 s s s s s P P - - - - - - 0 0 1 - - - - - define pcodeop diag; :diag rs5 EndPacket is iclass=6 & op2127=0x12 & op0507=1 & rs5 & $(END_PACKET) { @@ -5390,7 +5612,7 @@ define pcodeop diag; # (v69,6) diag0 -- "diag0 ( Rss32 , Rtt32 )" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 0 1 1 0 0 0 1 0 0 1 0 s s s s s P P + t t t t t 0 1 0 + + + + + +# 0 1 1 0 0 0 1 0 0 1 0 s s s s s P P - t t t t t 0 1 0 - - - - - define pcodeop diag0; :diag0 rss5,rtt5 EndPacket is iclass=6 & op2127=0x12 & op0507=2 & rss5 & rtt5 & $(END_PACKET) { @@ -5401,7 +5623,7 @@ define pcodeop diag0; # (v69,6) diag1 -- "diag1 ( Rss32 , Rtt32 )" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 0 1 1 0 0 0 1 0 0 1 0 s s s s s P P + t t t t t 0 1 1 + + + + + +# 0 1 1 0 0 0 1 0 0 1 0 s s s s s P P - t t t t t 0 1 1 - - - - - define pcodeop diag1; :diag1 rss5,rtt5 EndPacket is iclass=6 & op2127=0x12 & op0507=3 & rss5 & rtt5 & $(END_PACKET) { @@ -5420,6 +5642,72 @@ define pcodeop dmsyncht; build EndPacket; } +# (v68,10) dmstart -- "dmstart ( Rs32 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 1 0 0 1 1 0 0 0 0 s s s s s P P 0 0 0 0 0 0 0 0 1 0 0 0 0 0 + +define pcodeop dma_start; +:dmstart rs5 EndPacket is iclass=10 & op2127=0x30 & op13=0 & op0812=0 & op0507=1 & op0004=0 & rs5 & $(END_PACKET) { + dma_start(rs5); # Rs = pointer to DMA descriptor + build EndPacket; +} + +# (v68,10) dmlink -- "dmlink ( Rs32 , Rt32 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 1 0 0 1 1 0 0 0 0 s s s s s P P 0 t t t t t 0 1 0 0 0 0 0 0 + +define pcodeop dma_link; +:dmlink rs5,rt5 EndPacket is iclass=10 & op2127=0x30 & op13=0 & op0507=2 & op0004=0 & rs5 & rt5 & $(END_PACKET) { + dma_link(rs5, rt5); # append descriptor Rt to tail Rs + build EndPacket; +} + +# (v68,10) dmresume -- "dmresume ( Rs32 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 1 0 0 1 1 0 0 0 0 s s s s s P P 0 0 0 0 0 0 1 0 0 0 0 0 0 0 + +define pcodeop dma_resume; +:dmresume rs5 EndPacket is iclass=10 & op2127=0x30 & op13=0 & op0812=0 & op0507=4 & op0004=0 & rs5 & $(END_PACKET) { + dma_resume(rs5); # resume paused DMA using status pointer Rs + build EndPacket; +} + +# (v68,10) dmwait -- "Rd32 = dmwait" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 1 0 1 0 0 0 0 0 0 - - - - - P P - - - - - 0 0 0 1 d d d d d + +define pcodeop dma_wait; +:dmwait Rd5 EndPacket is iclass=10 & op2127=0x40 & op0508=1 & Rd5 & $(END_PACKET) { + Rd5 = dma_wait(); # block until all DMAs idle; Rd = status + build EndPacket; +} + +# (v68,10) dmpoll -- "Rd32 = dmpoll" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 1 0 1 0 0 0 0 0 0 - - - - - P P - - - - - 0 0 1 0 d d d d d + +define pcodeop dma_poll; +:dmpoll Rd5 EndPacket is iclass=10 & op2127=0x40 & op0508=2 & Rd5 & $(END_PACKET) { + Rd5 = dma_poll(); # sample DMA status without blocking + build EndPacket; +} + +# (v68,10) dmpause -- "Rd32 = dmpause" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 1 0 1 0 0 0 0 0 0 - - - - - P P - - - - - 0 0 1 1 d d d d d + +define pcodeop dma_pause; +:dmpause Rd5 EndPacket is iclass=10 & op2127=0x40 & op0508=3 & Rd5 & $(END_PACKET) { + Rd5 = dma_pause(); # pause all DMAs; Rd = status pointer + build EndPacket; +} + # (v4,8) extract -- "Rd32 = extract ( Rs32 , #u5 , #U5 )" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| @@ -5439,9 +5727,9 @@ define pcodeop dmsyncht; # (v4,12) extract -- "Rd32 = extract ( Rs32 , Rtt32 )" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 1 1 0 0 1 0 0 1 0 0 + s s s s s P P + t t t t t 0 1 + d d d d d +# 1 1 0 0 1 0 0 1 0 0 - s s s s s P P - t t t t t 0 1 - d d d d d -:extract Rd5,rs5,rtt5 EndPacket is iclass=12 & op2127=0x48 & op13=0 & op0507=2 & Rd5 & rs5 & rtt5 & rtt5h & rt5 & $(END_PACKET) { +:extract Rd5,rs5,rtt5 EndPacket is iclass=12 & op2227=0x24 & op0607=1 & Rd5 & rs5 & rtt5 & rtt5h & rt5 & $(END_PACKET) { # width: rtt5h (hi-word of rtt5) # offset: rt5 (lo-word of rtt5) mask:4 = ~(-1 << rtt5h); @@ -5471,9 +5759,9 @@ define pcodeop dmsyncht; # (v4,12) extract -- "Rdd32 = extract ( Rss32 , Rtt32 )" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 1 1 0 0 0 0 0 1 1 1 + s s s s s P P + t t t t t 1 0 + d d d d d +# 1 1 0 0 0 0 0 1 1 1 - s s s s s P P - t t t t t 1 0 - d d d d d -:extract Rdd5,rss5,rtt5 EndPacket is iclass=12 & op2127=0x0e & op13=0 & op0507=4 & Rdd5 & rss5 & rtt5 & rtt5h & rt5 & $(END_PACKET) { +:extract Rdd5,rss5,rtt5 EndPacket is iclass=12 & op2227=0x7 & op0607=2 & Rdd5 & rss5 & rtt5 & rtt5h & rt5 & $(END_PACKET) { # width: rtt5h (hi-word of rtt5) # offset: rt5 (lo-word of rtt5) mask:8 = ~(-1 << rtt5h); @@ -5500,9 +5788,9 @@ define pcodeop dmsyncht; # (v2,12) extractu -- "Rd32 = extractu ( Rs32 , Rtt32 )" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 1 1 0 0 1 0 0 1 0 0 + s s s s s P P + t t t t t 0 0 + d d d d d +# 1 1 0 0 1 0 0 1 0 0 - s s s s s P P - t t t t t 0 0 - d d d d d -:extractu Rd5,rs5,rtt5 EndPacket is iclass=12 & op2127=0x48 & op13=0 & op0507=0 & Rd5 & rs5 & rtt5 & rtt5h & rt5 & $(END_PACKET) { +:extractu Rd5,rs5,rtt5 EndPacket is iclass=12 & op2227=0x24 & op0607=0 & Rd5 & rs5 & rtt5 & rtt5h & rt5 & $(END_PACKET) { # width: rtt5h (hi-word of rtt5) # offset: rt5 (lo-word of rtt5) mask:4 = ~(-1 << rtt5h); @@ -5526,9 +5814,9 @@ define pcodeop dmsyncht; # (v2,12) extractu -- "Rdd32 = extractu ( Rss32 , Rtt32 )" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 1 1 0 0 0 0 0 1 0 0 + s s s s s P P + t t t t t 0 0 + d d d d d +# 1 1 0 0 0 0 0 1 0 0 - s s s s s P P - t t t t t 0 0 - d d d d d -:extractu Rdd5,rss5,rtt5 EndPacket is iclass=12 & op2127=0x08 & op13=0 & op0507=0 & Rdd5 & rss5 & rtt5 & rtt5h & rt5 & $(END_PACKET) { +:extractu Rdd5,rss5,rtt5 EndPacket is iclass=12 & op2227=0x4 & op0607=0 & Rdd5 & rss5 & rtt5 & rtt5h & rt5 & $(END_PACKET) { # width: rtt5h (hi-word of rtt5) # offset: rt5 (lo-word of rtt5) mask:8 = ~(-1 << rtt5h); @@ -5539,11 +5827,11 @@ define pcodeop dmsyncht; # (v4,6) fastcorner9 -- "Pd4 = fastcorner9 ( Ps4 , Pt4 )" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 0 1 1 0 1 0 1 1 0 0 0 0 + + s s P P 1 + + + t t 1 + + 1 + + d d +# 0 1 1 0 1 0 1 1 0 0 0 0 - - s s P P 1 - - - t t 1 - - 1 - - d d define pcodeop fastcorner9; -:fastcorner9 Pd2,pu1617,pu0809 EndPacket is iclass=6 & op2127=0x58 & op1820=0 & op13=1 & op1012=0 & op0207=0x24 & Pd2 & pu1617 & pu0809 & $(END_PACKET) { +:fastcorner9 Pd2,pu1617,pu0809 EndPacket is iclass=6 & op2127=0x58 & op20=0 & op13=1 & op7=0x1 & op4=0x1 & Pd2 & pu1617 & pu0809 & $(END_PACKET) { Pd2 = Pd2 & fastcorner9(pu1617,pu0809); build EndPacket; } @@ -5551,9 +5839,9 @@ define pcodeop fastcorner9; # (v4,6) fastcorner9 -- "Pd4 = ! fastcorner9 ( Ps4 , Pt4 )" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 0 1 1 0 1 0 1 1 0 0 0 1 + + s s P P 1 + + + t t 1 + + 1 + + d d +# 0 1 1 0 1 0 1 1 0 0 0 1 - - s s P P 1 - - - t t 1 - - 1 - - d d -:fastcorner9! Pd2,pu1617,pu0809 EndPacket is iclass=6 & op2127=0x58 & op1820=4 & op13=1 & op1012=0 & op0207=0x24 & Pd2 & pu1617 & pu0809 & $(END_PACKET) { +:fastcorner9! Pd2,pu1617,pu0809 EndPacket is iclass=6 & op2127=0x58 & op20=1 & op13=1 & op7=0x1 & op4=0x1 & Pd2 & pu1617 & pu0809 & $(END_PACKET) { Pd2 = Pd2 & ~fastcorner9(pu1617,pu0809); build EndPacket; } @@ -5561,11 +5849,11 @@ define pcodeop fastcorner9; # (v4,6) getimask -- "Rd32 = getimask ( Rs32 )" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 0 1 1 0 0 1 1 0 0 0 0 s s s s s P P + + + + + + + + + d d d d d +# 0 1 1 0 0 1 1 0 0 0 0 s s s s s P P - - - - - - - - - d d d d d define pcodeop getimask; -:getimask Rd5,rs5 EndPacket is iclass=6 & op2127=0x30 & op0513=0 & Rd5 & rs5 & $(END_PACKET) { +:getimask Rd5,rs5 EndPacket is iclass=6 & op2127=0x30 & Rd5 & rs5 & $(END_PACKET) { Rd5 = getimask(rs5); build EndPacket; } @@ -5573,21 +5861,21 @@ define pcodeop getimask; # (v4,5) hintjr -- "hintjr ( Rs32 )" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 0 1 0 1 0 0 1 0 1 0 1 s s s s s P P + + + + + + + + + + + + + + +# 0 1 0 1 0 0 1 0 1 0 1 s s s s s P P - - - - - - - - - - - - - - -:hintjr rs5 EndPacket is iclass=5 & op2127=0x15 & op0013=0 & rs5 & $(END_PACKET) { - # TODO: appears in decomp compilation - not sure what it does +:hintjr rs5 EndPacket is iclass=5 & op2127=0x15 & rs5 & $(END_PACKET) { + # branch hint - intentionally no-op build EndPacket; } # (v2,6) iassignr -- "Rd32 = iassignr ( Rs32 )" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 0 1 1 0 0 1 1 0 0 1 1 s s s s s P P + + + + + + + + + d d d d d +# 0 1 1 0 0 1 1 0 0 1 1 s s s s s P P - - - - - - - - - d d d d d define pcodeop iassignr; -:iassignr Rd5,rs5 EndPacket is iclass=6 & op2127=0x33 & op0513=0 & rs5 & Rd5 & $(END_PACKET) { +:iassignr Rd5,rs5 EndPacket is iclass=6 & op2127=0x33 & rs5 & Rd5 & $(END_PACKET) { Rd5 = iassignr(rs5); build EndPacket; } @@ -5595,11 +5883,11 @@ define pcodeop iassignr; # (v2,6) iassignw -- "iassignw ( Rs32 )" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 0 1 1 0 0 1 0 0 0 0 0 s s s s s P P + + + + + + 0 1 0 + + + + + +# 0 1 1 0 0 1 0 0 0 0 0 s s s s s P P - - - - - - 0 1 0 - - - - - define pcodeop iassignw; # TODO: What affect does this have -:iassignw rs5 EndPacket is iclass=6 & op2127=0x20 & op0013=0x40 & rs5 & $(END_PACKET) { +:iassignw rs5 EndPacket is iclass=6 & op2127=0x20 & op0507=0x2 & rs5 & $(END_PACKET) { iassignw(rs5); build EndPacket; } @@ -5607,11 +5895,11 @@ define pcodeop iassignw; # TODO: What affect does this have # (v4,5) icdatar -- "Rd32 = icdatar ( Rs32 )" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 0 1 0 1 0 1 0 1 1 0 1 s s s s s P P + + + + + + + + + d d d d d +# 0 1 0 1 0 1 0 1 1 0 1 s s s s s P P - - - - - - - - - d d d d d define pcodeop icdatar; -:icdatar Rd5,rs5 EndPacket is iclass=5 & op2127=0x2d & op0513=0 & rs5 & Rd5 & $(END_PACKET) { +:icdatar Rd5,rs5 EndPacket is iclass=5 & op2127=0x2d & rs5 & Rd5 & $(END_PACKET) { Rd5 = icdatar(rs5); build EndPacket; } @@ -5619,11 +5907,11 @@ define pcodeop icdatar; # (v66,5) icdataw -- "icdataw ( Rs32 , Rt32 )" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 0 1 0 1 0 1 0 1 1 1 0 s s s s s P P + t t t t t + + + + + + + + +# 0 1 0 1 0 1 0 1 1 1 0 s s s s s P P 1 t t t t t - - - - - - - - define pcodeop icache_data_write; # TODO: What affect does this have -:icdataw rs5, rt5 EndPacket is iclass=5 & op2127=0x36 & rs5 & rt5 & $(END_PACKET) { +:icdataw rs5, rt5 EndPacket is iclass=5 & op2127=0x2e & op13=1 & rs5 & rt5 & $(END_PACKET) { icache_data_write(rs5, rt5); build EndPacket; } @@ -5631,11 +5919,11 @@ define pcodeop icache_data_write; # TODO: What affect does this have # (v2,5) icinva -- "icinva ( Rs32 )" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 0 1 0 1 0 1 1 0 1 1 0 s s s s s P P 0 0 0 + + + + + + + + + + + +# 0 1 0 1 0 1 1 0 1 1 0 s s s s s P P 0 0 0 - - - - - - - - - - - define pcodeop icache_inv_addr; -:icinva rs5 EndPacket is iclass=5 & op2127=0x36 & op0013=0 & rs5 & $(END_PACKET) { +:icinva rs5 EndPacket is iclass=5 & op2127=0x36 & op1113=0 & rs5 & $(END_PACKET) { icache_inv_addr(rs5); build EndPacket; } @@ -5643,11 +5931,11 @@ define pcodeop icache_inv_addr; # (v2,5) icinvidx -- "icinvidx ( Rs32 )" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 0 1 0 1 0 1 1 0 1 1 0 s s s s s P P 0 0 1 + + + + + + + + + + + +# 0 1 0 1 0 1 1 0 1 1 0 s s s s s P P 0 0 1 - - - - - - - - - - - define pcodeop icinvidx; # TODO: What affect does this have -:icinvidx rs5 EndPacket is iclass=5 & op2127=0x36 & op0013=0x800 & rs5 & $(END_PACKET) { +:icinvidx rs5 EndPacket is iclass=5 & op2127=0x36 & op1113=0x1 & rs5 & $(END_PACKET) { icinvidx(rs5); build EndPacket; } @@ -5655,7 +5943,7 @@ define pcodeop icinvidx; # TODO: What affect does this have # (v2,5) ickill -- "ickill" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 0 1 0 1 0 1 1 0 1 1 0 + + + + + P P 0 1 0 + + + + + + + + + + + +# 0 1 0 1 0 1 1 0 1 1 0 - - - - - P P 0 1 0 - - - - - - - - - - - define pcodeop ickill; @@ -5667,11 +5955,11 @@ define pcodeop ickill; # (v2,5) ictagr -- "Rd32 = ictagr ( Rs32 )" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 0 1 0 1 0 1 0 1 1 1 1 s s s s s P P + + + + + + + + + d d d d d +# 0 1 0 1 0 1 0 1 1 1 1 s s s s s P P - - - - - - - - - d d d d d define pcodeop ictagr; -:ictagr Rd5,rs5 EndPacket is iclass=5 & op2127=0x2f & op0513=0 & Rd5 & rs5 & $(END_PACKET) { +:ictagr Rd5,rs5 EndPacket is iclass=5 & op2127=0x2f & Rd5 & rs5 & $(END_PACKET) { Rd5 = ictagr(rs5); build EndPacket; } @@ -5679,11 +5967,11 @@ define pcodeop ictagr; # (v4,5) ictagw -- "ictagw ( Rs32 , Rt32 )" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 0 1 0 1 0 1 0 1 1 1 0 s s s s s P P + t t t t t + + + + + + + + +# 0 1 0 1 0 1 0 1 1 1 0 s s s s s P P 0 t t t t t 0 0 0 0 0 0 0 0 define pcodeop ictagw; -:ictagw rs5,rt5 EndPacket is iclass=5 & op2127=0x2e & op13=0 & op0007=0 & Rd5 & rs5 & rt5 & $(END_PACKET) { +:ictagw rs5,rt5 EndPacket is iclass=5 & op2127=0x2e & op13=0 & op0007=0 & rs5 & rt5 & $(END_PACKET) { ictagw(rs5, rt5); build EndPacket; } @@ -5719,9 +6007,9 @@ Uimm32_1627_0013_6: "#"^val is i1627 & i0013 [ val = (i1627 << 20) | (i0013 << # (v2,12) insert -- "Rx32 = insert ( Rs32 , Rtt32 )" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 1 1 0 0 1 0 0 0 + + + s s s s s P P + t t t t t + + + x x x x x +# 1 1 0 0 1 0 0 0 - - - s s s s s P P - t t t t t - - - x x x x x -:insert Rd5,rs5,rtt5 EndPacket is iclass=12 & op2127=0x40 & op13=0 & op0507=0 & Rd5 & rd5 & rs5 & rtt5 & rtt5h & rt5 & $(END_PACKET) { +:insert Rd5,rs5,rtt5 EndPacket is iclass=12 & op2427=0x8 & Rd5 & rd5 & rs5 & rtt5 & rtt5h & rt5 & $(END_PACKET) { # width: rtt5h (hi-word of rtt5) # offset: rt5 (lo-word of rtt5) clrMask:4 = ~(((1 << rtt5h) - 1) << rt5); @@ -5747,9 +6035,9 @@ Uimm32_1627_0013_6: "#"^val is i1627 & i0013 [ val = (i1627 << 20) | (i0013 << # (v2,12) insert -- "Rxx32 = insert ( Rss32 , Rtt32 )" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 1 1 0 0 1 0 1 0 0 + + s s s s s P P + t t t t t + + + x x x x x +# 1 1 0 0 1 0 1 0 0 - - s s s s s P P 0 t t t t t - - - x x x x x -:insert Rdd5,rss5,rtt5 EndPacket is iclass=12 & op2127=0x50 & op13=0 & op0507=0 & Rdd5 & rdd5 & rss5 & rtt5 & rtt5h & rt5 & $(END_PACKET) { +:insert Rdd5,rss5,rtt5 EndPacket is iclass=12 & op2327=0x14 & op13=0 & Rdd5 & rdd5 & rss5 & rtt5 & rtt5h & rt5 & $(END_PACKET) { # width: rtt5h (hi-word of rtt5) # offset: rt5 (lo-word of rtt5) clrMask:8 = ~(((1 << rtt5h) - 1) << rt5); @@ -5761,9 +6049,9 @@ Uimm32_1627_0013_6: "#"^val is i1627 & i0013 [ val = (i1627 << 20) | (i0013 << # (v2,8) interleave -- "Rdd32 = interleave ( Rss32 )" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 1 0 0 0 0 0 0 0 1 1 + s s s s s P P + + + + + + 1 0 1 d d d d d +# 1 0 0 0 0 0 0 0 1 1 0 s s s s s P P - - - - - - 1 0 1 d d d d d define pcodeop interleave; -:interleave Rdd5,rss5 EndPacket is iclass=8 & op2127=0x06 & op0513=0x05 & Rdd5 & rss5 & $(END_PACKET) { +:interleave Rdd5,rss5 EndPacket is iclass=8 & op2227=0x3 & op21=0 & op0507=0x5 & Rdd5 & rss5 & $(END_PACKET) { Rdd5 = interleave(rss5); build EndPacket; } @@ -5785,7 +6073,7 @@ define pcodeop isync; # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| # 0 1 0 1 1 0 0 i i i i i i i i i P P i i i i i i i i i i i i i - -:jump RelDest22x EndPacket is iclass=5 & op2527=4 & op0=0 & RelDest22x & $(END_PACKET) { +:jump RelDest22x EndPacket is iclass=5 & op2527=4 & RelDest22x & $(END_PACKET) { build EndPacket; <> goto RelDest22x; @@ -5794,17 +6082,18 @@ define pcodeop isync; # (v2,5) jump -- "if ( Pu4 ) jump #r15:2x" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 0 1 0 1 1 1 0 0 i i 0 i i i i i P P i - 0 - u u i i i i i i i - +# 0 1 0 1 1 1 0 0 i i 0 i i i i i P P i 0 0 - u u i i i i i i i - # # (v2,5) jump -- "if ( ! Pu4 ) jump #r15:2x" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 0 1 0 1 1 1 0 0 i i 1 i i i i i P P i - 0 - u u i i i i i i i - +# 0 1 0 1 1 1 0 0 i i 1 i i i i i P P i 0 0 - u u i i i i i i i - -:jump^FlowCondUU RelDest15x EndPacket is iclass=5 & op2427=0xc & op1112=0 & op10=0 & op0=0 & FlowCondUU & RelDest15x & $(END_PACKET) { +:jump^FlowCondUU RelDest15x EndPacket is iclass=5 & op2427=0xc & op1112=0 & FlowCondUU & RelDest15x & $(END_PACKET) { build FlowCondUU; build EndPacket; <> + build FlowCondUU; if (ConditionReg == 0) goto ; goto RelDest15x; @@ -5813,27 +6102,28 @@ define pcodeop isync; # (v60,5) jump:nt -- "if ( Pu4 ) jump:nt #r15:2x" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 0 1 0 1 1 1 0 0 i i 0 i i i i i P P i 0 0 + u u i i i i i i i + +# 0 1 0 1 1 1 0 0 i i 0 i i i i i P P i 0 0 - u u i i i i i i i - # # (v60,5) jump:nt -- "if ( ! Pu4 ) jump:nt #r15:2x" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 0 1 0 1 1 1 0 0 i i 1 i i i i i P P i 0 0 + u u i i i i i i i + +# 0 1 0 1 1 1 0 0 i i 1 i i i i i P P i 0 0 - u u i i i i i i i - # # (v60,5) jump:t -- "if ( Pu4 ) jump:t #r15:2x" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 0 1 0 1 1 1 0 0 i i 0 i i i i i P P i 1 0 + u u i i i i i i i + +# 0 1 0 1 1 1 0 0 i i 0 i i i i i P P i 1 0 - u u i i i i i i i - # # (v60,5) jump:t -- "if ( ! Pu4 ) jump:t #r15:2x" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 0 1 0 1 1 1 0 0 i i 1 i i i i i P P i 1 0 + u u i i i i i i i + +# 0 1 0 1 1 1 0 0 i i 1 i i i i i P P i 1 0 - u u i i i i i i i - -:jump^FlowCondUU^Taken12 RelDest15x EndPacket is iclass=5 & op2427=0xc & op1011=0 & op0=0 & Taken12 & FlowCondUU & RelDest15x & $(END_PACKET) { +:jump^FlowCondUU^Taken12 RelDest15x EndPacket is iclass=5 & op2427=0xc & op11=0 & Taken12 & FlowCondUU & RelDest15x & $(END_PACKET) { build FlowCondUU; build EndPacket; <> + build FlowCondUU; if (ConditionReg == 0) goto ; goto RelDest15x; @@ -5842,27 +6132,28 @@ define pcodeop isync; # (v2,5) jump:nt -- "if ( Pu4 .new ) jump:nt #r15:2x" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 0 1 0 1 1 1 0 0 i i 0 i i i i i P P i 0 1 + u u i i i i i i i + +# 0 1 0 1 1 1 0 0 i i 0 i i i i i P P i 0 1 - u u i i i i i i i - # # (v2,5) jump:nt -- "if ( ! Pu4 .new ) jump:nt #r15:2x" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 0 1 0 1 1 1 0 0 i i 1 i i i i i P P i 0 1 + u u i i i i i i i + +# 0 1 0 1 1 1 0 0 i i 1 i i i i i P P i 0 1 - u u i i i i i i i - # # (v2,5) jump:t -- "if ( Pu4 .new ) jump:t #r15:2x" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 0 1 0 1 1 1 0 0 i i 0 i i i i i P P i 1 1 + u u i i i i i i i + +# 0 1 0 1 1 1 0 0 i i 0 i i i i i P P i 1 1 - u u i i i i i i i - # # (v2,5) jump:t -- "if ( ! Pu4 .new ) jump:t #r15:2x" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 0 1 0 1 1 1 0 0 i i 1 i i i i i P P i 1 1 + u u i i i i i i i + +# 0 1 0 1 1 1 0 0 i i 1 i i i i i P P i 1 1 - u u i i i i i i i - -:jump^FlowCondNewUU^Taken12 RelDest15x EndPacket is iclass=5 & op2427=0xc & op1011=2 & op0=0 & Taken12 & FlowCondNewUU & RelDest15x & $(END_PACKET) { +:jump^FlowCondNewUU^Taken12 RelDest15x EndPacket is iclass=5 & op2427=0xc & op11=1 & Taken12 & FlowCondNewUU & RelDest15x & $(END_PACKET) { build FlowCondNewUU; build EndPacket; <> + build FlowCondNewUU; if (ConditionReg == 0) goto ; goto RelDest15x; @@ -5871,49 +6162,49 @@ define pcodeop isync; # (v4,6) jump:nt -- "if ( Rs32 != #0 ) jump:nt #r13:2" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 0 1 1 0 0 0 0 1 0 0 i s s s s s P P i 0 i i i i i i i i i i i + +# 0 1 1 0 0 0 0 1 0 0 i s s s s s P P i 0 i i i i i i i i i i i - # # (v4,6) jump:t -- "if ( Rs32 != #0 ) jump:t #r13:2" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 0 1 1 0 0 0 0 1 0 0 i s s s s s P P i 1 i i i i i i i i i i i + +# 0 1 1 0 0 0 0 1 0 0 i s s s s s P P i 1 i i i i i i i i i i i - # # (v4,6) jump:nt -- "if ( Rs32 <= #0 ) jump:nt #r13:2" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 0 1 1 0 0 0 0 1 1 1 i s s s s s P P i 0 i i i i i i i i i i i + +# 0 1 1 0 0 0 0 1 1 1 i s s s s s P P i 0 i i i i i i i i i i i - # # (v4,6) jump:t -- "if ( Rs32 <= #0 ) jump:t #r13:2" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 0 1 1 0 0 0 0 1 1 1 i s s s s s P P i 1 i i i i i i i i i i i + +# 0 1 1 0 0 0 0 1 1 1 i s s s s s P P i 1 i i i i i i i i i i i - # # (v4,6) jump:nt -- "if ( Rs32 == #0 ) jump:nt #r13:2" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 0 1 1 0 0 0 0 1 1 0 i s s s s s P P i 0 i i i i i i i i i i i + +# 0 1 1 0 0 0 0 1 1 0 i s s s s s P P i 0 i i i i i i i i i i i - # # (v4,6) jump:t -- "if ( Rs32 == #0 ) jump:t #r13:2" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 0 1 1 0 0 0 0 1 1 0 i s s s s s P P i 1 i i i i i i i i i i i + +# 0 1 1 0 0 0 0 1 1 0 i s s s s s P P i 1 i i i i i i i i i i i - # # (v4,6) jump:nt -- "if ( Rs32 >= #0 ) jump:nt #r13:2" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 0 1 1 0 0 0 0 1 0 1 i s s s s s P P i 0 i i i i i i i i i i i + +# 0 1 1 0 0 0 0 1 0 1 i s s s s s P P i 0 i i i i i i i i i i i - # # (v4,6) jump:t -- "if ( Rs32 >= #0 ) jump:t #r13:2" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 0 1 1 0 0 0 0 1 0 1 i s s s s s P P i 1 i i i i i i i i i i i + +# 0 1 1 0 0 0 0 1 0 1 i s s s s s P P i 1 i i i i i i i i i i i - JmpRsCmp_2223: "("^rs5^"!=#0)" is op2223=0 & rs5 { tmp:1 = rs5 != 0; export tmp; } JmpRsCmp_2223: "("^rs5^">=#0)" is op2223=1 & rs5 { tmp:1 = rs5 s>= 0; export tmp; } JmpRsCmp_2223: "("^rs5^"==#0)" is op2223=2 & rs5 { tmp:1 = rs5 == 0; export tmp; } JmpRsCmp_2223: "("^rs5^"<=#0)" is op2223=3 & rs5 { tmp:1 = rs5 s<= 0; export tmp; } -:jump.if^Taken12 JmpRsCmp_2223,RelDest13 EndPacket is iclass=6 & op2427=1 & op0=0 & Taken12 & JmpRsCmp_2223 & RelDest13 & $(END_PACKET) { +:jump.if^Taken12 JmpRsCmp_2223,RelDest13 EndPacket is iclass=6 & op2427=1 & Taken12 & JmpRsCmp_2223 & RelDest13 & $(END_PACKET) { build EndPacket; <> if (JmpRsCmp_2223 == 0) goto ; @@ -6218,7 +6509,7 @@ JumpIf_2326_S22: "!"^JumpCmp_2326 is op22=1 & JumpCmp_2326 { # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| # 0 1 0 1 0 0 1 0 1 0 0 s s s s s P P - - - - - - - - - - - - - - -:jumpr rs5 EndPacket is iclass=5 & op2127=0x14 & op0013=0 & rs5 & $(END_PACKET) { +:jumpr rs5 EndPacket is iclass=5 & op2127=0x14 & rs5 & $(END_PACKET) { dest:4 = rs5; build EndPacket; <> @@ -6226,6 +6517,11 @@ JumpIf_2326_S22: "!"^JumpCmp_2326 is op22=1 & JumpCmp_2326 { } # jumpr LR (special case: treat as return) +# (v2,5) jumpr -- "jumpr LR" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 1 0 1 0 0 0 1 0 0 0 1 1 1 1 1 P P 0 0 0 0 0 0 0 0 0 0 0 0 0 0 + :jumpr LR EndPacket is iclass=5 & op2127=0x14 & op1620=31 & op0013=0 & LR & $(END_PACKET) { dest:4 = LR; build EndPacket; @@ -6238,7 +6534,12 @@ JumpIf_2326_S22: "!"^JumpCmp_2326 is op22=1 & JumpCmp_2326 { # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| # 0 1 0 1 0 0 1 0 1 1 0 s s s s s P P - - - - - - - - - - - - - - -:jumprh rs5 EndPacket is iclass=5 & op2127=0x16 & op0013=0 & rs5 & $(END_PACKET) { +# (v2,5) jumprh -- "jumprh ( Rs32 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 1 0 1 0 0 0 1 0 1 1 s s s s s P P 0 0 0 0 0 0 0 0 0 0 0 0 0 0 + +:jumprh rs5 EndPacket is iclass=5 & op2127=0x16 & rs5 & $(END_PACKET) { dest:4 = rs5; build EndPacket; <> @@ -6273,22 +6574,24 @@ JumpIf_2326_S22: "!"^JumpCmp_2326 is op22=1 & JumpCmp_2326 { # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| # 0 1 0 1 0 0 1 1 0 1 1 s s s s s P P - 1 0 - u u - - - - - - - - -:jumpr^FlowCondUU^Taken12 rs5 EndPacket is iclass=5 & op2227=0xd & Taken12 & op11=0 & op0007=0 & rs5 & FlowCondUU & $(END_PACKET) { +:jumpr^FlowCondUU^Taken12 rs5 EndPacket is iclass=5 & op2227=0xd & op11=0 & Taken12 & rs5 & FlowCondUU & $(END_PACKET) { dest:4 = rs5; build FlowCondUU; build EndPacket; <> + build FlowCondUU; if (ConditionReg == 0) goto ; goto [dest]; } # if ([!]Pu) jumpr LR (special case: treat as conditional return) -:jumpr^FlowCondUU^Taken12 LR EndPacket is iclass=5 & op2227=0xd & op1620=31 & Taken12 & op11=0 & op0007=0 & LR & FlowCondUU & $(END_PACKET) { +:jumpr^FlowCondUU^Taken12 LR EndPacket is iclass=5 & op2227=0xd & op1620=31 & op11=0 & op0007=0 & Taken12 & LR & FlowCondUU & $(END_PACKET) { dest:4 = LR; build FlowCondUU; build EndPacket; <> + build FlowCondUU; if (ConditionReg == 0) goto ; return [dest]; @@ -6314,22 +6617,29 @@ JumpIf_2326_S22: "!"^JumpCmp_2326 is op22=1 & JumpCmp_2326 { # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| # 0 1 0 1 0 0 1 1 0 1 1 s s s s s P P - 1 1 - u u - - - - - - - - -:jumpr^FlowCondNewUU^Taken12 rs5 EndPacket is iclass=5 & op2227=0xd & Taken12 & op11=1 & rs5 & FlowCondNewUU & $(END_PACKET) { +:jumpr^FlowCondNewUU^Taken12 rs5 EndPacket is iclass=5 & op2227=0xd & op11=1 & Taken12 & rs5 & FlowCondNewUU & $(END_PACKET) { dest:4 = rs5; build FlowCondNewUU; build EndPacket; <> + build FlowCondNewUU; if (ConditionReg == 0) goto ; goto [dest]; } # if ([!]Pu.new) jumpr LR (special case: treat as conditional return) -:jumpr^FlowCondNewUU LR EndPacket is iclass=5 & op2227=0xd & op1620=31 & Taken12 & op11=1 & LR & FlowCondNewUU & $(END_PACKET) { +# (v2,5) jumpr -- "if ([!]Pu4) jumpr:t LR" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 1 0 1 0 0 1 1 0 N - 1 1 1 1 1 P P 1 - - - - - 1 T - - - - - - + +:jumpr^FlowCondNewUU LR EndPacket is iclass=5 & op2227=0xd & op1620=31 & op11=1 & Taken12 & LR & FlowCondNewUU & $(END_PACKET) { dest:4 = LR; build FlowCondNewUU; build EndPacket; <> + build FlowCondNewUU; if (ConditionReg == 0) goto ; return [dest]; @@ -6386,21 +6696,21 @@ define pcodeop l2cleaninvidx; # (v4,10) l2fetch -- "l2fetch ( Rs32 , Rt32 )" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 1 0 1 0 0 1 1 0 0 + + s s s s s P P - t t t t t - - - - - - - - +# 1 0 1 0 0 1 1 0 0 0 0 s s s s s P P - t t t t t 0 0 0 - - - - - define pcodeop l2fetch; -:l2fetch rs5,rt5 EndPacket is iclass=10 & op2127=0x30 & rs5 & rt5 & op13=0 & op0007=0 & $(END_PACKET) { +:l2fetch rs5,rt5 EndPacket is iclass=10 & op2327=0xc & op22=0 & op21=0 & op7=0 & op6=0 & op5=0 & rs5 & rt5 & $(END_PACKET) { l2fetch(rs5,rt5); build EndPacket; } -# (v?,10) l2fetch -- "l2fetch ( Rs32 , Rtt32 )" +# (v5,10) l2fetch -- "l2fetch ( Rs32 , Rtt32 )" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 1 0 1 0 0 1 1 0 1 + + s s s s s P P - t t t t t - - - - - - - - +# 1 0 1 0 0 1 1 0 1 0 0 s s s s s P P - t t t t t - - - - - - - - -:l2fetch rs5,rtt5 EndPacket is iclass=10 & op2127=0x34 & rs5 & rtt5 & $(END_PACKET) { +:l2fetch rs5,rtt5 EndPacket is iclass=10 & op2327=0xd & op22=0 & op21=0 & rs5 & rtt5 & $(END_PACKET) { l2fetch(rs5,rtt5); build EndPacket; } @@ -6408,7 +6718,7 @@ define pcodeop l2fetch; # (v65,10) l2gclean -- "l2gclean" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 1 0 1 0 1 0 0 0 0 0 1 + + + + + P P - 1 0 0 - - - - - - - - - - +# 1 0 1 0 1 0 0 0 0 0 1 - - - - - P P - 1 0 0 - - - - - - - - - - define pcodeop l2gclean; @@ -6420,7 +6730,7 @@ define pcodeop l2gclean; # (v65,10) l2gclean -- "l2gclean ( Rtt32 )" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 1 0 1 0 0 1 1 0 1 0 1 + + + + + P P - t t t t t - - - - - - - - +# 1 0 1 0 0 1 1 0 1 0 1 - - - - - P P - t t t t t - - - - - - - - :l2gclean rtt5 EndPacket is iclass=10 & op2127=0x35 & rtt5 & $(END_PACKET) { l2gclean(rtt5); @@ -6430,7 +6740,7 @@ define pcodeop l2gclean; # (v65,10) l2gcleaninv -- "l2gcleaninv" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 1 0 1 0 1 0 0 0 0 0 1 + + + + + P P - 1 1 0 - - - - - - - - - - +# 1 0 1 0 1 0 0 0 0 0 1 - - - - - P P - 1 1 0 - - - - - - - - - - define pcodeop l2gcleaninv; @@ -6442,7 +6752,7 @@ define pcodeop l2gcleaninv; # (v65,10) l2gcleaninv -- "l2gcleaninv ( Rtt32 )" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 1 0 1 0 0 1 1 0 1 1 0 + + + + + P P - t t t t t - - - - - - - - +# 1 0 1 0 0 1 1 0 1 1 0 - - - - - P P - t t t t t - - - - - - - - :l2gcleaninv rtt5 EndPacket is iclass=10 & op2127=0x36 & rtt5 & $(END_PACKET) { l2gcleaninv(rtt5); @@ -6452,7 +6762,7 @@ define pcodeop l2gcleaninv; # (v65,10) l2gunlock -- "l2gunlock" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 1 0 1 0 1 0 0 0 0 0 1 + + + + + P P - 0 1 0 - - - - - - - - - - +# 1 0 1 0 1 0 0 0 0 0 1 - - - - - P P - 0 1 0 - - - - - - - - - - define pcodeop l2gunlock; @@ -6536,21 +6846,21 @@ define pcodeop l2locka; # (v2,12) lfs -- "Rdd32 = lfs ( Rss32 , Rtt32 )" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 1 1 0 0 0 0 0 1 1 0 + s s s s s P P + t t t t t 1 1 + d d d d d +# 1 1 0 0 0 0 0 1 1 0 - s s s s s P P - t t t t t 1 1 0 d d d d d define pcodeop lfs; -:lfs Rdd5,rss5,rtt5 EndPacket is iclass=12 & op2127=0x0c & op13=0 & op0507=6 & Rdd5 & rss5 & rtt5 & $(END_PACKET) { +:lfs Rdd5,rss5,rtt5 EndPacket is iclass=12 & op2227=0x6 & op0607=3 & op5=0 & Rdd5 & rss5 & rtt5 & $(END_PACKET) { Rdd5 = lfs(rss5, rtt5); build EndPacket; } - # linecpy -- "Rdd32 = linecpy( Rs32 , Rtt32 )" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| # 1 0 0 1 1 0 0 1 1 1 1 t t t t t P P 0 s s s s s 0 0 1 d d d d d define pcodeop linecpy; + :linecpy Rdd5,rt5,rss5 EndPacket is iclass=0x9 & op2127=0x4f & op13=0 & op0507=1 & Rdd5 & rss5 & rt5 & $(END_PACKET) { Rdd5 = linecpy(rt5, rss5); } @@ -6572,7 +6882,7 @@ LoopUimm10: "#"^val is i1620 & i0507 & i0001 [ val = (i1620 << 5) | (i0507 << # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| # 0 1 1 0 1 0 0 1 0 0 0 I I I I I P P - i i i i i I I I i i - I I -:loop0 LoopRelMem7x,LoopUimm10 EndPacket is iclass=6 & op2127=0x48 & op13=0 & op2=0 & LoopRelMem7x & LoopRelAddr7x & LoopUimm10 & $(END_PACKET) { +:loop0 LoopRelMem7x,LoopUimm10 EndPacket is iclass=6 & op2127=0x48 & LoopRelMem7x & LoopRelAddr7x & LoopUimm10 & $(END_PACKET) { SA0_ = LoopRelAddr7x; LC0_ = LoopUimm10; build EndPacket; @@ -6587,7 +6897,7 @@ LoopUimm10: "#"^val is i1620 & i0507 & i0001 [ val = (i1620 << 5) | (i0507 << # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| # 0 1 1 0 0 0 0 0 0 0 0 s s s s s P P - i i i i i - - - i i - - - -:loop0 LoopRelMem7x,rs5 EndPacket is iclass=6 & op2127=0 & op13=0 & op0507=0 & op0002=0 & LoopRelMem7x & LoopRelAddr7x & rs5 & $(END_PACKET) { +:loop0 LoopRelMem7x,rs5 EndPacket is iclass=6 & op2127=0 & LoopRelMem7x & LoopRelAddr7x & rs5 & $(END_PACKET) { SA0_ = LoopRelAddr7x; LC0_ = rs5; build EndPacket; @@ -6602,7 +6912,7 @@ LoopUimm10: "#"^val is i1620 & i0507 & i0001 [ val = (i1620 << 5) | (i0507 << # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| # 0 1 1 0 1 0 0 1 0 0 1 I I I I I P P - i i i i i I I I i i - I I -:loop1 LoopRelMem7x,LoopUimm10 EndPacket is iclass=6 & op2127=0x49 & op13=0 & op2=0 & LoopRelMem7x & LoopRelAddr7x & LoopUimm10 & $(END_PACKET) { +:loop1 LoopRelMem7x,LoopUimm10 EndPacket is iclass=6 & op2127=0x49 & LoopRelMem7x & LoopRelAddr7x & LoopUimm10 & $(END_PACKET) { SA1_ = LoopRelAddr7x; LC1_ = LoopUimm10; build EndPacket; @@ -6617,7 +6927,7 @@ LoopUimm10: "#"^val is i1620 & i0507 & i0001 [ val = (i1620 << 5) | (i0507 << # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| # 0 1 1 0 0 0 0 0 0 0 1 s s s s s P P - i i i i i - - - i i - - - -:loop1 LoopRelMem7x,rs5 EndPacket is iclass=6 & op2127=1 & op13=0 & op0507=0 & op0002=0 & LoopRelMem7x & LoopRelAddr7x & rs5 & $(END_PACKET) { +:loop1 LoopRelMem7x,rs5 EndPacket is iclass=6 & op2127=1 & LoopRelMem7x & LoopRelAddr7x & rs5 & $(END_PACKET) { SA1_ = LoopRelAddr7x; LC1_ = rs5; build EndPacket; @@ -6630,43 +6940,48 @@ LoopUimm10: "#"^val is i1620 & i0507 & i0001 [ val = (i1620 << 5) | (i0507 << # (v4,12) lsl -- "Rd32 = lsl ( #s6 , Rt32 )" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 1 1 0 0 0 1 1 0 1 0 + i i i i i P P + t t t t t 1 1 i d d d d d +# 1 1 0 0 0 1 1 0 1 0 - i i i i i P P - t t t t t 1 1 i d d d d d -:lsl Rd5,Simm8_1620_05,rt5 EndPacket is iclass=12 & op2127=0x34 & op13=0 & op0607=3 & Rd5 & rt5 & Simm8_1620_05 & $(END_PACKET) { - Rd5 = sext(Simm8_1620_05) << rt5; +:lsl Rd5,Simm8_1620_05,rt5 EndPacket is iclass=12 & op2227=0x1a & op0607=3 & Rd5 & rt5 & Simm8_1620_05 & $(END_PACKET) { + shamt:4 = (rt5 << 25) s>> 25; + right:1 = shamt s< 0; + Rd5 = (zext(right) * (sext(Simm8_1620_05) >> -shamt)) + (zext(!right) * (sext(Simm8_1620_05) << shamt)); build EndPacket; } # (v2,12) lsl -- "Rd32 = lsl ( Rs32 , Rt32 )" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 1 1 0 0 0 1 1 0 0 1 + s s s s s P P + t t t t t 1 1 + d d d d d +# 1 1 0 0 0 1 1 0 0 1 - s s s s s P P - t t t t t 1 1 - d d d d d -:lsl Rd5,rs5,rt5 EndPacket is iclass=12 & op2127=0x32 & op13=0 & op0507=6 & Rd5 & rt5 & rs5 & $(END_PACKET) { - right:1 = rt5 s< 0; - Rd5 = (zext(right) * (rs5 >> -rt5)) + (zext(!right) * (rs5 << rt5)); +:lsl Rd5,rs5,rt5 EndPacket is iclass=12 & op2227=0x19 & op0607=3 & Rd5 & rt5 & rs5 & $(END_PACKET) { + shamt:4 = (rt5 << 25) s>> 25; + right:1 = shamt s< 0; + Rd5 = (zext(right) * (rs5 >> -shamt)) + (zext(!right) * (rs5 << shamt)); build EndPacket; } # (v2,12) lsl -- "Rdd32 = lsl ( Rss32 , Rt32 )" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 1 1 0 0 0 0 1 1 1 0 + s s s s s P P + t t t t t 1 1 + d d d d d +# 1 1 0 0 0 0 1 1 1 0 - s s s s s P P - t t t t t 1 1 - d d d d d -:lsl Rdd5,rss5,rt5 EndPacket is iclass=12 & op2127=0x1c & op13=0 & op0507=6 & Rdd5 & rt5 & rss5 & $(END_PACKET) { - right:1 = rt5 s< 0; - Rdd5 = (zext(right) * (rss5 >> -rt5)) + (zext(!right) * (rss5 << rt5)); +:lsl Rdd5,rss5,rt5 EndPacket is iclass=12 & op2227=0xe & op0607=3 & Rdd5 & rt5 & rss5 & $(END_PACKET) { + shamt:4 = (rt5 << 25) s>> 25; + right:1 = shamt s< 0; + Rdd5 = (zext(right) * (rss5 >> -shamt)) + (zext(!right) * (rss5 << shamt)); build EndPacket; } # (v2,12) lsl -- "Rx32 &= lsl ( Rs32 , Rt32 )" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 1 1 0 0 1 1 0 0 0 1 + s s s s s P P + t t t t t 1 1 + x x x x x +# 1 1 0 0 1 1 0 0 0 1 - s s s s s P P - t t t t t 1 1 - x x x x x -:lsl&= Rd5,rs5,rt5 EndPacket is iclass=12 & op2127=0x62 & op13=0 & op0507=6 & Rd5 & rd5 & rt5 & rs5 & $(END_PACKET) { - right:1 = rt5 s< 0; - result:4 = (zext(right) * (rs5 >> -rt5)) + (zext(!right) * (rs5 << rt5)); +:lsl&= Rd5,rs5,rt5 EndPacket is iclass=12 & op2227=0x31 & op0607=3 & Rd5 & rd5 & rt5 & rs5 & $(END_PACKET) { + shamt:4 = (rt5 << 25) s>> 25; + right:1 = shamt s< 0; + result:4 = (zext(right) * (rs5 >> -shamt)) + (zext(!right) * (rs5 << shamt)); Rd5 = rd5 & result; build EndPacket; } @@ -6674,11 +6989,12 @@ LoopUimm10: "#"^val is i1620 & i0507 & i0001 [ val = (i1620 << 5) | (i0507 << # (v2,12) lsl -- "Rx32 += lsl ( Rs32 , Rt32 )" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 1 1 0 0 1 1 0 0 1 1 + s s s s s P P + t t t t t 1 1 + x x x x x +# 1 1 0 0 1 1 0 0 1 1 - s s s s s P P - t t t t t 1 1 - x x x x x -:lsl+= Rd5,rs5,rt5 EndPacket is iclass=12 & op2127=0x66 & op13=0 & op0507=6 & Rd5 & rd5 & rt5 & rs5 & $(END_PACKET) { - right:1 = rt5 s< 0; - result:4 = (zext(right) * (rs5 >> -rt5)) + (zext(!right) * (rs5 << rt5)); +:lsl+= Rd5,rs5,rt5 EndPacket is iclass=12 & op2227=0x33 & op0607=3 & Rd5 & rd5 & rt5 & rs5 & $(END_PACKET) { + shamt:4 = (rt5 << 25) s>> 25; + right:1 = shamt s< 0; + result:4 = (zext(right) * (rs5 >> -shamt)) + (zext(!right) * (rs5 << shamt)); Rd5 = rd5 + result; build EndPacket; } @@ -6686,11 +7002,12 @@ LoopUimm10: "#"^val is i1620 & i0507 & i0001 [ val = (i1620 << 5) | (i0507 << # (v2,12) lsl -- "Rx32 -= lsl ( Rs32 , Rt32 )" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 1 1 0 0 1 1 0 0 1 0 + s s s s s P P + t t t t t 1 1 + x x x x x +# 1 1 0 0 1 1 0 0 1 0 - s s s s s P P - t t t t t 1 1 - x x x x x -:lsl-= Rd5,rs5,rt5 EndPacket is iclass=12 & op2127=0x64 & op13=0 & op0507=6 & Rd5 & rd5 & rt5 & rs5 & $(END_PACKET) { - right:1 = rt5 s< 0; - result:4 = (zext(right) * (rs5 >> -rt5)) + (zext(!right) * (rs5 << rt5)); +:lsl-= Rd5,rs5,rt5 EndPacket is iclass=12 & op2227=0x32 & op0607=3 & Rd5 & rd5 & rt5 & rs5 & $(END_PACKET) { + shamt:4 = (rt5 << 25) s>> 25; + right:1 = shamt s< 0; + result:4 = (zext(right) * (rs5 >> -shamt)) + (zext(!right) * (rs5 << shamt)); Rd5 = rd5 - result; build EndPacket; } @@ -6698,11 +7015,12 @@ LoopUimm10: "#"^val is i1620 & i0507 & i0001 [ val = (i1620 << 5) | (i0507 << # (v2,12) lsl -- "Rx32 |= lsl ( Rs32 , Rt32 )" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 1 1 0 0 1 1 0 0 0 0 + s s s s s P P + t t t t t 1 1 + x x x x x +# 1 1 0 0 1 1 0 0 0 0 - s s s s s P P - t t t t t 1 1 - x x x x x -:lsl|= Rd5,rs5,rt5 EndPacket is iclass=12 & op2127=0x60 & op13=0 & op0507=6 & Rd5 & rd5 & rt5 & rs5 & $(END_PACKET) { - right:1 = rt5 s< 0; - result:4 = (zext(right) * (rs5 >> -rt5)) + (zext(!right) * (rs5 << rt5)); +:lsl|= Rd5,rs5,rt5 EndPacket is iclass=12 & op2227=0x30 & op0607=3 & Rd5 & rd5 & rt5 & rs5 & $(END_PACKET) { + shamt:4 = (rt5 << 25) s>> 25; + right:1 = shamt s< 0; + result:4 = (zext(right) * (rs5 >> -shamt)) + (zext(!right) * (rs5 << shamt)); Rd5 = rd5 | result; build EndPacket; } @@ -6710,21 +7028,25 @@ LoopUimm10: "#"^val is i1620 & i0507 & i0001 [ val = (i1620 << 5) | (i0507 << # (v2,12) lsl -- "Rxx32 &= lsl ( Rss32 , Rt32 )" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 1 1 0 0 1 0 1 1 0 1 0 s s s s s P P + t t t t t 1 1 + x x x x x +# 1 1 0 0 1 0 1 1 0 1 0 s s s s s P P - t t t t t 1 1 - x x x x x -:lsl&= Rdd5,rss5,rt5 EndPacket is iclass=12 & op2127=0x5a & op13=0 & op0507=6 & Rdd5 & rdd5 & rt5 & rss5 & $(END_PACKET) { - Rdd5 = rdd5 & (rss5 << rt5); +:lsl&= Rdd5,rss5,rt5 EndPacket is iclass=12 & op2127=0x5a & op0607=3 & Rdd5 & rdd5 & rt5 & rss5 & $(END_PACKET) { + shamt:4 = (rt5 << 25) s>> 25; + right:1 = shamt s< 0; + result:8 = (zext(right) * (rss5 >> -shamt)) + (zext(!right) * (rss5 << shamt)); + Rdd5 = rdd5 & result; build EndPacket; } # (v2,12) lsl -- "Rxx32 += lsl ( Rss32 , Rt32 )" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 1 1 0 0 1 0 1 1 1 1 0 s s s s s P P + t t t t t 1 1 + x x x x x +# 1 1 0 0 1 0 1 1 1 1 0 s s s s s P P - t t t t t 1 1 - x x x x x -:lsl+= Rdd5,rss5,rt5 EndPacket is iclass=12 & op2127=0x5e & op13=0 & op0507=6 & Rdd5 & rdd5 & rt5 & rss5 & $(END_PACKET) { - right:1 = rt5 s< 0; - result:8 = (zext(right) * (rss5 >> -rt5)) + (zext(!right) * (rss5 << rt5)); +:lsl+= Rdd5,rss5,rt5 EndPacket is iclass=12 & op2127=0x5e & op0607=3 & Rdd5 & rdd5 & rt5 & rss5 & $(END_PACKET) { + shamt:4 = (rt5 << 25) s>> 25; + right:1 = shamt s< 0; + result:8 = (zext(right) * (rss5 >> -shamt)) + (zext(!right) * (rss5 << shamt)); Rdd5 = rdd5 + result; build EndPacket; } @@ -6732,11 +7054,12 @@ LoopUimm10: "#"^val is i1620 & i0507 & i0001 [ val = (i1620 << 5) | (i0507 << # (v2,12) lsl -- "Rxx32 -= lsl ( Rss32 , Rt32 )" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 1 1 0 0 1 0 1 1 1 0 0 s s s s s P P + t t t t t 1 1 + x x x x x +# 1 1 0 0 1 0 1 1 1 0 0 s s s s s P P - t t t t t 1 1 - x x x x x -:lsl-= Rdd5,rss5,rt5 EndPacket is iclass=12 & op2127=0x5c & op13=0 & op0507=6 & Rdd5 & rdd5 & rt5 & rss5 & $(END_PACKET) { - right:1 = rt5 s< 0; - result:8 = (zext(right) * (rss5 >> -rt5)) + (zext(!right) * (rss5 << rt5)); +:lsl-= Rdd5,rss5,rt5 EndPacket is iclass=12 & op2127=0x5c & op0607=3 & Rdd5 & rdd5 & rt5 & rss5 & $(END_PACKET) { + shamt:4 = (rt5 << 25) s>> 25; + right:1 = shamt s< 0; + result:8 = (zext(right) * (rss5 >> -shamt)) + (zext(!right) * (rss5 << shamt)); Rdd5 = rdd5 - result; build EndPacket; } @@ -6744,11 +7067,12 @@ LoopUimm10: "#"^val is i1620 & i0507 & i0001 [ val = (i1620 << 5) | (i0507 << # (v4,12) lsl -- "Rxx32 ^= lsl ( Rss32 , Rt32 )" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 1 1 0 0 1 0 1 1 0 1 1 s s s s s P P + t t t t t 1 1 + x x x x x +# 1 1 0 0 1 0 1 1 0 1 1 s s s s s P P - t t t t t 1 1 - x x x x x -:lsl"^=" Rdd5,rss5,rt5 EndPacket is iclass=12 & op2127=0x5b & op13=0 & op0507=6 & Rdd5 & rdd5 & rt5 & rss5 & $(END_PACKET) { - right:1 = rt5 s< 0; - result:8 = (zext(right) * (rss5 >> -rt5)) + (zext(!right) * (rss5 << rt5)); +:lsl"^=" Rdd5,rss5,rt5 EndPacket is iclass=12 & op2127=0x5b & op0607=3 & Rdd5 & rdd5 & rt5 & rss5 & $(END_PACKET) { + shamt:4 = (rt5 << 25) s>> 25; + right:1 = shamt s< 0; + result:8 = (zext(right) * (rss5 >> -shamt)) + (zext(!right) * (rss5 << shamt)); Rdd5 = rdd5 ^ result; build EndPacket; } @@ -6756,11 +7080,12 @@ LoopUimm10: "#"^val is i1620 & i0507 & i0001 [ val = (i1620 << 5) | (i0507 << # (v2,12) lsl -- "Rxx32 |= lsl ( Rss32 , Rt32 )" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 1 1 0 0 1 0 1 1 0 0 0 s s s s s P P + t t t t t 1 1 + x x x x x +# 1 1 0 0 1 0 1 1 0 0 0 s s s s s P P - t t t t t 1 1 - x x x x x -:lsl|= Rdd5,rss5,rt5 EndPacket is iclass=12 & op2127=0x58 & op13=0 & op0507=6 & Rdd5 & rdd5 & rt5 & rss5 & $(END_PACKET) { - right:1 = rt5 s< 0; - result:8 = (zext(right) * (rss5 >> -rt5)) + (zext(!right) * (rss5 << rt5)); +:lsl|= Rdd5,rss5,rt5 EndPacket is iclass=12 & op2127=0x58 & op0607=3 & Rdd5 & rdd5 & rt5 & rss5 & $(END_PACKET) { + shamt:4 = (rt5 << 25) s>> 25; + right:1 = shamt s< 0; + result:8 = (zext(right) * (rss5 >> -shamt)) + (zext(!right) * (rss5 << shamt)); Rdd5 = rdd5 | result; build EndPacket; } @@ -6778,20 +7103,21 @@ LoopUimm10: "#"^val is i1620 & i0507 & i0001 [ val = (i1620 << 5) | (i0507 << # (v2,12) lsr -- "Rd32 = lsr ( Rs32 , Rt32 )" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 1 1 0 0 0 1 1 0 0 1 + s s s s s P P + t t t t t 0 1 + d d d d d +# 1 1 0 0 0 1 1 0 0 1 - s s s s s P P - t t t t t 0 1 - d d d d d -:lsr Rd5,rs5,rt5 EndPacket is iclass=12 & op2127=0x32 & op13=0 & op0507=2 & Rd5 & rs5 & rt5 & $(END_PACKET) { - left:1 = rt5 s< 0; - Rd5 = (zext(!left) * (rs5 >> rt5)) + (zext(left) * (rs5 << -rt5)); +:lsr Rd5,rs5,rt5 EndPacket is iclass=12 & op2227=0x19 & op0607=1 & Rd5 & rs5 & rt5 & $(END_PACKET) { + shamt:4 = (rt5 << 25) s>> 25; + left:1 = shamt s< 0; + Rd5 = (zext(!left) * (rs5 >> shamt)) + (zext(left) * (rs5 << -shamt)); build EndPacket; } # (v2,8) lsr -- "Rdd32 = lsr ( Rss32 , #u6 )" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 1 0 0 0 0 0 0 0 0 0 + s s s s s P P i i i i i i 0 0 1 d d d d d +# 1 0 0 0 0 0 0 0 0 0 0 s s s s s P P i i i i i i 0 0 1 d d d d d -:lsr Rdd5,rss5,Uimm8_0813 EndPacket is iclass=8 & op2127=0x00 & op0507=1 & Rdd5 & rss5 & Uimm8_0813 & $(END_PACKET) { +:lsr Rdd5,rss5,Uimm8_0813 EndPacket is iclass=8 & op2227=0x0 & op21=0 & op0507=1 & Rdd5 & rss5 & Uimm8_0813 & $(END_PACKET) { Rdd5 = rss5 >> Uimm8_0813; build EndPacket; } @@ -6799,20 +7125,21 @@ LoopUimm10: "#"^val is i1620 & i0507 & i0001 [ val = (i1620 << 5) | (i0507 << # (v2,12) lsr -- "Rdd32 = lsr ( Rss32 , Rt32 )" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 1 1 0 0 0 0 1 1 1 0 + s s s s s P P + t t t t t 0 1 + d d d d d +# 1 1 0 0 0 0 1 1 1 0 - s s s s s P P - t t t t t 0 1 - d d d d d -:lsr Rdd5,rss5,rt5 EndPacket is iclass=12 & op2127=0x1c & op13=0 & op0507=2 & Rdd5 & rss5 & rt5 & $(END_PACKET) { - left:1 = rt5 s< 0; - Rdd5 = (zext(!left) * (rss5 >> rt5)) + (zext(left) * (rss5 << -rt5)); +:lsr Rdd5,rss5,rt5 EndPacket is iclass=12 & op2227=0xe & op0607=1 & Rdd5 & rss5 & rt5 & $(END_PACKET) { + shamt:4 = (rt5 << 25) s>> 25; + left:1 = shamt s< 0; + Rdd5 = (zext(!left) * (rss5 >> shamt)) + (zext(left) * (rss5 << -shamt)); build EndPacket; } # (v2,8) lsr -- "Rx32 &= lsr ( Rs32 , #u5 )" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 1 0 0 0 1 1 1 0 0 1 + s s s s s P P 0 i i i i i 0 0 1 x x x x x +# 1 0 0 0 1 1 1 0 0 1 - s s s s s P P 0 i i i i i 0 0 1 x x x x x -:lsr&= Rd5,rs5,Uimm8_0812 EndPacket is iclass=8 & op2127=0x72 & op13=0 & op0507=1 & Rd5 & rd5 & rs5 & Uimm8_0812 & $(END_PACKET) { +:lsr&= Rd5,rs5,Uimm8_0812 EndPacket is iclass=8 & op2227=0x39 & op13=0 & op0507=1 & Rd5 & rd5 & rs5 & Uimm8_0812 & $(END_PACKET) { Rd5 = rd5 & (rs5 >> Uimm8_0812); build EndPacket; } @@ -6820,11 +7147,12 @@ LoopUimm10: "#"^val is i1620 & i0507 & i0001 [ val = (i1620 << 5) | (i0507 << # (v2,12) lsr -- "Rx32 &= lsr ( Rs32 , Rt32 )" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 1 1 0 0 1 1 0 0 0 1 + s s s s s P P + t t t t t 0 1 + x x x x x +# 1 1 0 0 1 1 0 0 0 1 - s s s s s P P - t t t t t 0 1 - x x x x x -:lsr&= Rd5,rs5,rt5 EndPacket is iclass=12 & op2127=0x62 & op13=0 & op0507=2 & Rd5 & rd5 & rs5 & rt5 & $(END_PACKET) { - left:1 = rt5 s< 0; - result:4 = (zext(!left) * (rs5 >> rt5)) + (zext(left) * (rs5 << -rt5)); +:lsr&= Rd5,rs5,rt5 EndPacket is iclass=12 & op2227=0x31 & op0607=1 & Rd5 & rd5 & rs5 & rt5 & $(END_PACKET) { + shamt:4 = (rt5 << 25) s>> 25; + left:1 = shamt s< 0; + result:4 = (zext(!left) * (rs5 >> shamt)) + (zext(left) * (rs5 << -shamt)); Rd5 = rd5 & result; build EndPacket; } @@ -6832,9 +7160,9 @@ LoopUimm10: "#"^val is i1620 & i0507 & i0001 [ val = (i1620 << 5) | (i0507 << # (v2,8) lsr -- "Rx32 += lsr ( Rs32 , #u5 )" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 1 0 0 0 1 1 1 0 0 0 + s s s s s P P 0 i i i i i 1 0 1 x x x x x +# 1 0 0 0 1 1 1 0 0 0 - s s s s s P P 0 i i i i i 1 0 1 x x x x x -:lsr+= Rd5,rs5,Uimm8_0812 EndPacket is iclass=8 & op2127=0x70 & op13=0 & op0507=5 & Rd5 & rd5 & rs5 & Uimm8_0812 & $(END_PACKET) { +:lsr+= Rd5,rs5,Uimm8_0812 EndPacket is iclass=8 & op2227=0x38 & op13=0 & op0507=5 & Rd5 & rd5 & rs5 & Uimm8_0812 & $(END_PACKET) { Rd5 = rd5 + (rs5 >> Uimm8_0812); build EndPacket; } @@ -6842,11 +7170,12 @@ LoopUimm10: "#"^val is i1620 & i0507 & i0001 [ val = (i1620 << 5) | (i0507 << # (v2,12) lsr -- "Rx32 += lsr ( Rs32 , Rt32 )" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 1 1 0 0 1 1 0 0 1 1 + s s s s s P P + t t t t t 0 1 + x x x x x +# 1 1 0 0 1 1 0 0 1 1 - s s s s s P P - t t t t t 0 1 - x x x x x -:lsr+= Rd5,rs5,rt5 EndPacket is iclass=12 & op2127=0x66 & op13=0 & op0507=2 & Rd5 & rd5 & rs5 & rt5 & $(END_PACKET) { - left:1 = rt5 s< 0; - result:4 = (zext(!left) * (rs5 >> rt5)) + (zext(left) * (rs5 << -rt5)); +:lsr+= Rd5,rs5,rt5 EndPacket is iclass=12 & op2227=0x33 & op0607=1 & Rd5 & rd5 & rs5 & rt5 & $(END_PACKET) { + shamt:4 = (rt5 << 25) s>> 25; + left:1 = shamt s< 0; + result:4 = (zext(!left) * (rs5 >> shamt)) + (zext(left) * (rs5 << -shamt)); Rd5 = rd5 + result; build EndPacket; } @@ -6854,9 +7183,9 @@ LoopUimm10: "#"^val is i1620 & i0507 & i0001 [ val = (i1620 << 5) | (i0507 << # (v2,8) lsr -- "Rx32 -= lsr ( Rs32 , #u5 )" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 1 0 0 0 1 1 1 0 0 0 + s s s s s P P 0 i i i i i 0 0 1 x x x x x +# 1 0 0 0 1 1 1 0 0 0 - s s s s s P P 0 i i i i i 0 0 1 x x x x x -:lsr-= Rd5,rs5,Uimm8_0812 EndPacket is iclass=8 & op2127=0x70 & op13=0 & op0507=1 & Rd5 & rd5 & rs5 & Uimm8_0812 & $(END_PACKET) { +:lsr-= Rd5,rs5,Uimm8_0812 EndPacket is iclass=8 & op2227=0x38 & op13=0 & op0507=1 & Rd5 & rd5 & rs5 & Uimm8_0812 & $(END_PACKET) { Rd5 = rd5 - (rs5 >> Uimm8_0812); build EndPacket; } @@ -6864,11 +7193,12 @@ LoopUimm10: "#"^val is i1620 & i0507 & i0001 [ val = (i1620 << 5) | (i0507 << # (v2,12) lsr -- "Rx32 -= lsr ( Rs32 , Rt32 )" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 1 1 0 0 1 1 0 0 1 0 + s s s s s P P + t t t t t 0 1 + x x x x x +# 1 1 0 0 1 1 0 0 1 0 - s s s s s P P - t t t t t 0 1 - x x x x x -:lsr-= Rd5,rs5,rt5 EndPacket is iclass=12 & op2127=0x64 & op13=0 & op0507=2 & Rd5 & rd5 & rs5 & rt5 & $(END_PACKET) { - left:1 = rt5 s< 0; - result:4 = (zext(!left) * (rs5 >> rt5)) + (zext(left) * (rs5 << -rt5)); +:lsr-= Rd5,rs5,rt5 EndPacket is iclass=12 & op2227=0x32 & op0607=1 & Rd5 & rd5 & rs5 & rt5 & $(END_PACKET) { + shamt:4 = (rt5 << 25) s>> 25; + left:1 = shamt s< 0; + result:4 = (zext(!left) * (rs5 >> shamt)) + (zext(left) * (rs5 << -shamt)); Rd5 = rd5 - result; build EndPacket; } @@ -6876,9 +7206,9 @@ LoopUimm10: "#"^val is i1620 & i0507 & i0001 [ val = (i1620 << 5) | (i0507 << # (v2,8) lsr -- "Rx32 ^= lsr ( Rs32 , #u5 )" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 1 0 0 0 1 1 1 0 1 0 + s s s s s P P 0 i i i i i 0 0 1 x x x x x +# 1 0 0 0 1 1 1 0 1 0 - s s s s s P P 0 i i i i i 0 0 1 x x x x x -:lsr"^=" Rd5,rs5,Uimm8_0812 EndPacket is iclass=8 & op2127=0x74 & op13=0 & op0507=1 & Rd5 & rd5 & rs5 & Uimm8_0812 & $(END_PACKET) { +:lsr"^=" Rd5,rs5,Uimm8_0812 EndPacket is iclass=8 & op2227=0x3a & op13=0 & op0507=1 & Rd5 & rd5 & rs5 & Uimm8_0812 & $(END_PACKET) { Rd5 = rd5 ^ (rs5 >> Uimm8_0812); build EndPacket; } @@ -6886,9 +7216,9 @@ LoopUimm10: "#"^val is i1620 & i0507 & i0001 [ val = (i1620 << 5) | (i0507 << # (v2,8) lsr -- "Rx32 |= lsr ( Rs32 , #u5 )" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 1 0 0 0 1 1 1 0 0 1 + s s s s s P P 0 i i i i i 1 0 1 x x x x x +# 1 0 0 0 1 1 1 0 0 1 - s s s s s P P 0 i i i i i 1 0 1 x x x x x -:lsr|= Rd5,rs5,Uimm8_0812 EndPacket is iclass=8 & op2127=0x72 & op13=0 & op0507=5 & Rd5 & rd5 & rs5 & Uimm8_0812 & $(END_PACKET) { +:lsr|= Rd5,rs5,Uimm8_0812 EndPacket is iclass=8 & op2227=0x39 & op13=0 & op0507=5 & Rd5 & rd5 & rs5 & Uimm8_0812 & $(END_PACKET) { Rd5 = rd5 | (rs5 >> Uimm8_0812); build EndPacket; } @@ -6896,11 +7226,12 @@ LoopUimm10: "#"^val is i1620 & i0507 & i0001 [ val = (i1620 << 5) | (i0507 << # (v2,12) lsr -- "Rx32 |= lsr ( Rs32 , Rt32 )" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 1 1 0 0 1 1 0 0 0 0 + s s s s s P P + t t t t t 0 1 + x x x x x +# 1 1 0 0 1 1 0 0 0 0 - s s s s s P P - t t t t t 0 1 - x x x x x -:lsr|= Rd5,rs5,rt5 EndPacket is iclass=12 & op2127=0x60 & op13=0 & op0507=2 & Rd5 & rd5 & rs5 & rt5 & $(END_PACKET) { - left:1 = rt5 s< 0; - result:4 = (zext(!left) * (rs5 >> rt5)) + (zext(left) * (rs5 << -rt5)); +:lsr|= Rd5,rs5,rt5 EndPacket is iclass=12 & op2227=0x30 & op0607=1 & Rd5 & rd5 & rs5 & rt5 & $(END_PACKET) { + shamt:4 = (rt5 << 25) s>> 25; + left:1 = shamt s< 0; + result:4 = (zext(!left) * (rs5 >> shamt)) + (zext(left) * (rs5 << -shamt)); Rd5 = rd5 | result; build EndPacket; } @@ -6908,9 +7239,9 @@ LoopUimm10: "#"^val is i1620 & i0507 & i0001 [ val = (i1620 << 5) | (i0507 << # (v2,8) lsr -- "Rxx32 &= lsr ( Rss32 , #u6 )" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 1 0 0 0 0 0 1 0 0 1 + s s s s s P P i i i i i i 0 0 1 x x x x x +# 1 0 0 0 0 0 1 0 0 1 - s s s s s P P i i i i i i 0 0 1 x x x x x -:lsr&= Rdd5,rss5,Uimm8_0813 EndPacket is iclass=8 & op2127=0x12 & op0507=1 & Rdd5 & rdd5 & rss5 & Uimm8_0813 & $(END_PACKET) { +:lsr&= Rdd5,rss5,Uimm8_0813 EndPacket is iclass=8 & op2227=0x9 & op0507=1 & Rdd5 & rdd5 & rss5 & Uimm8_0813 & $(END_PACKET) { Rdd5 = rdd5 & (rss5 >> Uimm8_0813); build EndPacket; } @@ -6918,11 +7249,12 @@ LoopUimm10: "#"^val is i1620 & i0507 & i0001 [ val = (i1620 << 5) | (i0507 << # (v2,12) lsr -- "Rxx32 &= lsr ( Rss32 , Rt32 )" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 1 1 0 0 1 0 1 1 0 1 0 s s s s s P P + t t t t t 0 1 + x x x x x +# 1 1 0 0 1 0 1 1 0 1 0 s s s s s P P - t t t t t 0 1 - x x x x x -:lsr&= Rdd5,rss5,rt5 EndPacket is iclass=12 & op2127=0x5a & op13=0 & op0507=2 & Rdd5 & rdd5 & rss5 & rt5 & $(END_PACKET) { - left:1 = rt5 s< 0; - result:8 = (zext(!left) * (rss5 >> rt5)) + (zext(left) * (rss5 << -rt5)); +:lsr&= Rdd5,rss5,rt5 EndPacket is iclass=12 & op2127=0x5a & op0607=1 & Rdd5 & rdd5 & rss5 & rt5 & $(END_PACKET) { + shamt:4 = (rt5 << 25) s>> 25; + left:1 = shamt s< 0; + result:8 = (zext(!left) * (rss5 >> shamt)) + (zext(left) * (rss5 << -shamt)); Rdd5 = rdd5 & result; build EndPacket; } @@ -6930,9 +7262,9 @@ LoopUimm10: "#"^val is i1620 & i0507 & i0001 [ val = (i1620 << 5) | (i0507 << # (v2,8) lsr -- "Rxx32 += lsr ( Rss32 , #u6 )" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 1 0 0 0 0 0 1 0 0 0 + s s s s s P P i i i i i i 1 0 1 x x x x x +# 1 0 0 0 0 0 1 0 0 0 - s s s s s P P i i i i i i 1 0 1 x x x x x -:lsr+= Rdd5,rss5,Uimm8_0813 EndPacket is iclass=8 & op2127=0x10 & op0507=5 & Rdd5 & rdd5 & rss5 & Uimm8_0813 & $(END_PACKET) { +:lsr+= Rdd5,rss5,Uimm8_0813 EndPacket is iclass=8 & op2227=0x8 & op0507=5 & Rdd5 & rdd5 & rss5 & Uimm8_0813 & $(END_PACKET) { Rdd5 = rdd5 + (rss5 >> Uimm8_0813); build EndPacket; } @@ -6940,11 +7272,12 @@ LoopUimm10: "#"^val is i1620 & i0507 & i0001 [ val = (i1620 << 5) | (i0507 << # (v2,12) lsr -- "Rxx32 += lsr ( Rss32 , Rt32 )" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 1 1 0 0 1 0 1 1 1 1 0 s s s s s P P + t t t t t 0 1 + x x x x x +# 1 1 0 0 1 0 1 1 1 1 0 s s s s s P P - t t t t t 0 1 - x x x x x -:lsr+= Rdd5,rss5,rt5 EndPacket is iclass=12 & op2127=0x5e & op13=0 & op0507=2 & Rdd5 & rdd5 & rss5 & rt5 & $(END_PACKET) { - left:1 = rt5 s< 0; - result:8 = (zext(!left) * (rss5 >> rt5)) + (zext(left) * (rss5 << -rt5)); +:lsr+= Rdd5,rss5,rt5 EndPacket is iclass=12 & op2127=0x5e & op0607=1 & Rdd5 & rdd5 & rss5 & rt5 & $(END_PACKET) { + shamt:4 = (rt5 << 25) s>> 25; + left:1 = shamt s< 0; + result:8 = (zext(!left) * (rss5 >> shamt)) + (zext(left) * (rss5 << -shamt)); Rdd5 = rdd5 + result; build EndPacket; } @@ -6952,9 +7285,9 @@ LoopUimm10: "#"^val is i1620 & i0507 & i0001 [ val = (i1620 << 5) | (i0507 << # (v2,8) lsr -- "Rxx32 -= lsr ( Rss32 , #u6 )" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 1 0 0 0 0 0 1 0 0 0 + s s s s s P P i i i i i i 0 0 1 x x x x x +# 1 0 0 0 0 0 1 0 0 0 - s s s s s P P i i i i i i 0 0 1 x x x x x -:lsr-= Rdd5,rss5,Uimm8_0813 EndPacket is iclass=8 & op2127=0x10 & op0507=1 & Rdd5 & rdd5 & rss5 & Uimm8_0813 & $(END_PACKET) { +:lsr-= Rdd5,rss5,Uimm8_0813 EndPacket is iclass=8 & op2227=0x8 & op0507=1 & Rdd5 & rdd5 & rss5 & Uimm8_0813 & $(END_PACKET) { Rdd5 = rdd5 - (rss5 >> Uimm8_0813); build EndPacket; } @@ -6962,11 +7295,12 @@ LoopUimm10: "#"^val is i1620 & i0507 & i0001 [ val = (i1620 << 5) | (i0507 << # (v2,12) lsr -- "Rxx32 -= lsr ( Rss32 , Rt32 )" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 1 1 0 0 1 0 1 1 1 0 0 s s s s s P P + t t t t t 0 1 + x x x x x +# 1 1 0 0 1 0 1 1 1 0 0 s s s s s P P - t t t t t 0 1 - x x x x x -:lsr-= Rdd5,rss5,rt5 EndPacket is iclass=12 & op2127=0x5c & op13=0 & op0507=2 & Rdd5 & rdd5 & rss5 & rt5 & $(END_PACKET) { - left:1 = rt5 s< 0; - result:8 = (zext(!left) * (rss5 >> rt5)) + (zext(left) * (rss5 << -rt5)); +:lsr-= Rdd5,rss5,rt5 EndPacket is iclass=12 & op2127=0x5c & op0607=1 & Rdd5 & rdd5 & rss5 & rt5 & $(END_PACKET) { + shamt:4 = (rt5 << 25) s>> 25; + left:1 = shamt s< 0; + result:8 = (zext(!left) * (rss5 >> shamt)) + (zext(left) * (rss5 << -shamt)); Rdd5 = rdd5 - result; build EndPacket; } @@ -6974,9 +7308,9 @@ LoopUimm10: "#"^val is i1620 & i0507 & i0001 [ val = (i1620 << 5) | (i0507 << # (v2,8) lsr -- "Rxx32 ^= lsr ( Rss32 , #u6 )" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 1 0 0 0 0 0 1 0 1 0 + s s s s s P P i i i i i i 0 0 1 x x x x x +# 1 0 0 0 0 0 1 0 1 0 - s s s s s P P i i i i i i 0 0 1 x x x x x -:lsr"^=" Rdd5,rss5,Uimm8_0813 EndPacket is iclass=8 & op2127=0x14 & op0507=1 & Rdd5 & rdd5 & rss5 & Uimm8_0813 & $(END_PACKET) { +:lsr"^=" Rdd5,rss5,Uimm8_0813 EndPacket is iclass=8 & op2227=0xa & op0507=1 & Rdd5 & rdd5 & rss5 & Uimm8_0813 & $(END_PACKET) { Rdd5 = rdd5 ^ (rss5 >> Uimm8_0813); build EndPacket; } @@ -6984,11 +7318,12 @@ LoopUimm10: "#"^val is i1620 & i0507 & i0001 [ val = (i1620 << 5) | (i0507 << # (v4,12) lsr -- "Rxx32 ^= lsr ( Rss32 , Rt32 )" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 1 1 0 0 1 0 1 1 0 1 1 s s s s s P P + t t t t t 0 1 + x x x x x +# 1 1 0 0 1 0 1 1 0 1 1 s s s s s P P - t t t t t 0 1 - x x x x x -:lsr"^=" Rdd5,rss5,rt5 EndPacket is iclass=12 & op2127=0x5b & op13=0 & op0507=2 & Rdd5 & rdd5 & rss5 & rt5 & $(END_PACKET) { - left:1 = rt5 s< 0; - result:8 = (zext(!left) * (rss5 >> rt5)) + (zext(left) * (rss5 << -rt5)); +:lsr"^=" Rdd5,rss5,rt5 EndPacket is iclass=12 & op2127=0x5b & op0607=1 & Rdd5 & rdd5 & rss5 & rt5 & $(END_PACKET) { + shamt:4 = (rt5 << 25) s>> 25; + left:1 = shamt s< 0; + result:8 = (zext(!left) * (rss5 >> shamt)) + (zext(left) * (rss5 << -shamt)); Rdd5 = rdd5 ^ result; build EndPacket; } @@ -6996,9 +7331,9 @@ LoopUimm10: "#"^val is i1620 & i0507 & i0001 [ val = (i1620 << 5) | (i0507 << # (v2,8) lsr -- "Rxx32 |= lsr ( Rss32 , #u6 )" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 1 0 0 0 0 0 1 0 0 1 + s s s s s P P i i i i i i 1 0 1 x x x x x +# 1 0 0 0 0 0 1 0 0 1 - s s s s s P P i i i i i i 1 0 1 x x x x x -:lsr|= Rdd5,rss5,Uimm8_0813 EndPacket is iclass=8 & op2127=0x12 & op0507=5 & Rdd5 & rdd5 & rss5 & Uimm8_0813 & $(END_PACKET) { +:lsr|= Rdd5,rss5,Uimm8_0813 EndPacket is iclass=8 & op2227=0x9 & op0507=5 & Rdd5 & rdd5 & rss5 & Uimm8_0813 & $(END_PACKET) { Rdd5 = rdd5 | (rss5 >> Uimm8_0813); build EndPacket; } @@ -7006,11 +7341,12 @@ LoopUimm10: "#"^val is i1620 & i0507 & i0001 [ val = (i1620 << 5) | (i0507 << # (v2,12) lsr -- "Rxx32 |= lsr ( Rss32 , Rt32 )" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 1 1 0 0 1 0 1 1 0 0 0 s s s s s P P + t t t t t 0 1 + x x x x x +# 1 1 0 0 1 0 1 1 0 0 0 s s s s s P P - t t t t t 0 1 - x x x x x -:lsr|= Rdd5,rss5,rt5 EndPacket is iclass=12 & op2127=0x58 & op13=0 & op0507=2 & Rdd5 & rdd5 & rss5 & rt5 & $(END_PACKET) { - left:1 = rt5 s< 0; - result:8 = (zext(!left) * (rss5 >> rt5)) + (zext(left) * (rss5 << -rt5)); +:lsr|= Rdd5,rss5,rt5 EndPacket is iclass=12 & op2127=0x58 & op0607=1 & Rdd5 & rdd5 & rss5 & rt5 & $(END_PACKET) { + shamt:4 = (rt5 << 25) s>> 25; + left:1 = shamt s< 0; + result:8 = (zext(!left) * (rss5 >> shamt)) + (zext(left) * (rss5 << -shamt)); Rdd5 = rdd5 | result; build EndPacket; } @@ -7018,10 +7354,10 @@ LoopUimm10: "#"^val is i1620 & i0507 & i0001 [ val = (i1620 << 5) | (i0507 << # (v2,8) mask -- "Rdd32 = mask ( Pt4 )" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 1 0 0 0 0 1 1 0 + + + + + + + + P P + + + + t t + + + d d d d d +# 1 0 0 0 0 1 1 0 - - - - - - - - P P - - - - t t - - - d d d d d define pcodeop maskGenerate; -:mask Rdd5,pu0809 EndPacket is iclass=8 & op2127=0x30 & op1620=0 & op1013=0 & op0507=0 & Rdd5 & pu0809 & $(END_PACKET) { +:mask Rdd5,pu0809 EndPacket is iclass=8 & op2427=0x6 & Rdd5 & pu0809 & $(END_PACKET) { val:1 = 0xff; Rdd5[0,8] = val * (pu0809) & 1; Rdd5[8,8] = val * (pu0809 >> 1) & 1; @@ -7039,7 +7375,12 @@ define pcodeop maskGenerate; # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| # 1 0 0 0 1 1 0 1 0 I I - - - - - P P 1 i i i i i I I I d d d d d -:mask Rd5,Uimm8_0812,Uimm8_2122_0507 EndPacket is iclass=8 & op2327=0x1a & op13=1 & Rd5 & op1620=0 & Uimm8_0812 & Uimm8_2122_0507 & $(END_PACKET) { +# (v2,8) mask -- "Rd32 = mask ( #u5 , Uimm8 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 0 0 0 0 0 1 - - - - - - - - P P - i i i i i i i i i i i i i + +:mask Rd5,Uimm8_0812,Uimm8_2122_0507 EndPacket is iclass=8 & op2327=0x1a & op13=1 & Rd5 & Uimm8_0812 & Uimm8_2122_0507 & $(END_PACKET) { Rd5 = ((1< rt5; Rd5 = (zext(bool) * rs5) + (zext(!bool) * rt5); build EndPacket; @@ -7058,9 +7399,9 @@ define pcodeop maskGenerate; # (v4,13) max -- "Rdd32 = max ( Rss32 , Rtt32 )" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 1 1 0 1 0 0 1 1 1 1 0 s s s s s P P + t t t t t 1 0 0 d d d d d +# 1 1 0 1 0 0 1 1 1 1 0 s s s s s P P - t t t t t 1 0 0 d d d d d -:max Rdd5,rss5,rtt5 EndPacket is iclass=13 & op2127=0x1e & op13=0 & op0507=4 & Rdd5 & rss5 & rtt5 & $(END_PACKET) { +:max Rdd5,rss5,rtt5 EndPacket is iclass=13 & op2127=0x1e & op0507=4 & Rdd5 & rss5 & rtt5 & $(END_PACKET) { bool:1 = rss5 s> rtt5; Rdd5 = (zext(bool) * rss5) + (zext(!bool) * rtt5); build EndPacket; @@ -7069,9 +7410,9 @@ define pcodeop maskGenerate; # (v2,13) maxu -- "Rd32 = maxu ( Rs32 , Rt32 )" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 1 1 0 1 0 1 0 1 1 1 0 s s s s s P P + t t t t t 1 + + d d d d d +# 1 1 0 1 0 1 0 1 1 1 0 s s s s s P P - t t t t t 1 - - d d d d d -:maxu Rd5,rs5,rt5 EndPacket is iclass=13 & op2127=0x2e & op13=0 & op0507=4 & Rd5 & rs5 & rt5 & $(END_PACKET) { +:maxu Rd5,rs5,rt5 EndPacket is iclass=13 & op2127=0x2e & op7=1 & Rd5 & rs5 & rt5 & $(END_PACKET) { bool:1 = rs5 > rt5; Rd5 = (zext(bool) * rs5) + (zext(!bool) * rt5); build EndPacket; @@ -7080,9 +7421,9 @@ define pcodeop maskGenerate; # (v4,13) maxu -- "Rdd32 = maxu ( Rss32 , Rtt32 )" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 1 1 0 1 0 0 1 1 1 1 0 s s s s s P P + t t t t t 1 0 1 d d d d d +# 1 1 0 1 0 0 1 1 1 1 0 s s s s s P P - t t t t t 1 0 1 d d d d d -:maxu Rdd5,rss5,rtt5 EndPacket is iclass=13 & op2127=0x1e & op13=0 & op0507=5 & Rdd5 & rss5 & rtt5 & $(END_PACKET) { +:maxu Rdd5,rss5,rtt5 EndPacket is iclass=13 & op2127=0x1e & op0507=5 & Rdd5 & rss5 & rtt5 & $(END_PACKET) { bool:1 = rss5 > rtt5; Rdd5 = (zext(bool) * rss5) + (zext(!bool) * rtt5); build EndPacket; @@ -7101,9 +7442,9 @@ define pcodeop maskGenerate; # (v4,3) memb -- "Rd32 = memb ( Rs32 + Rt32 << #n2 )" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 0 0 1 1 1 0 1 0 0 0 0 s s s s s P P n t t t t t n + + d d d d d +# 0 0 1 1 1 0 1 0 0 0 0 s s s s s P P n t t t t t n - - d d d d d -:memb Rd5,MemRsRelShiftC3b EndPacket is iclass=3 & op2127=0x50 & op0506=0 & Rd5 & MemRsRelShiftC3b & $(END_PACKET) { +:memb Rd5,MemRsRelShiftC3b EndPacket is iclass=3 & op2127=0x50 & Rd5 & MemRsRelShiftC3b & $(END_PACKET) { Rd5 = sext(MemRsRelShiftC3b); build EndPacket; } @@ -7121,9 +7462,9 @@ define pcodeop maskGenerate; # (v4,9) memb -- "Rd32 = memb ( Rf32 = #U6x )" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 1 0 0 1 1 0 1 1 0 0 0 f f f f f P P 0 1 I I I I + I I d d d d d +# 1 0 0 1 1 0 1 1 0 0 0 f f f f f P P 0 1 I I I I - I I d d d d d -:memb Rd5,LdMemRsAssignxC9b EndPacket is iclass=9 & op2127=0x58 & op1213=1 & op7=0 & Rd5 & LdMemRsAssignxC9b & $(END_PACKET) { +:memb Rd5,LdMemRsAssignxC9b EndPacket is iclass=9 & op2127=0x58 & op1213=1 & Rd5 & LdMemRsAssignxC9b & $(END_PACKET) { Rd5 = sext(LdMemRsAssignxC9b); build EndPacket; } @@ -7131,9 +7472,9 @@ define pcodeop maskGenerate; # (v2,9) memb -- "Rd32 = memb ( Rz32 ++ #s4:0 )" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 1 0 0 1 1 0 1 1 0 0 0 z z z z z P P 0 0 + + + i i i i d d d d d +# 1 0 0 1 1 0 1 1 0 0 0 z z z z z P P 0 0 - - - i i i i d d d d d -:memb Rd5,LdMemAIS4C9b0 EndPacket is iclass=9 & op2127=0x58 & op0913=0 & Rd5 & LdMemAIS4C9b0 & $(END_PACKET) { +:memb Rd5,LdMemAIS4C9b0 EndPacket is iclass=9 & op2127=0x58 & op1213=0 & Rd5 & LdMemAIS4C9b0 & $(END_PACKET) { Rd5 = sext(LdMemAIS4C9b0); build EndPacket; } @@ -7142,14 +7483,14 @@ define pcodeop maskGenerate; # (v2,9) memb -- "Rd32 = memb ( Rz32 ++ Mu2 )" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 1 0 0 1 1 1 0 1 0 0 0 z z z z z P P u 0 + + + + 0 + + d d d d d +# 1 0 0 1 1 1 0 1 0 0 0 z z z z z P P u 0 - - - - 0 - - d d d d d # # (v2,9) memb -- "Rd32 = memb ( Rz32 ++ Mu2 :brev )" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 1 0 0 1 1 1 1 1 0 0 0 z z z z z P P u 0 + + + + 0 + + d d d d d +# 1 0 0 1 1 1 1 1 0 0 0 z z z z z P P u 0 - - - - 0 - - d d d d d -:memb Rd5,LdMemAIMuC9b EndPacket is iclass=9 & op2627=3 & op2124=8 & op0512=0 & Rd5 & LdMemAIMuC9b & $(END_PACKET) { +:memb Rd5,LdMemAIMuC9b EndPacket is iclass=9 & op2627=3 & op2124=8 & op12=0 & op7=0 & Rd5 & LdMemAIMuC9b & $(END_PACKET) { Rd5 = sext(LdMemAIMuC9b); build EndPacket; } @@ -7157,9 +7498,9 @@ define pcodeop maskGenerate; # (v2,9) memb -- "Rd32 = memb ( Rz32 ++ #s4:0 :circ ( Mu2 ) )" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 1 0 0 1 1 0 0 1 0 0 0 z z z z z P P u 0 + + 0 i i i i d d d d d +# 1 0 0 1 1 0 0 1 0 0 0 z z z z z P P u 0 - - 0 i i i i d d d d d -:memb Rd5,LdMemAIS4CircMuC9b0 EndPacket is iclass=9 & op2127=0x48 & op0912=0 & Rd5 & LdMemAIS4CircMuC9b0 & $(END_PACKET) { +:memb Rd5,LdMemAIS4CircMuC9b0 EndPacket is iclass=9 & op2127=0x48 & op12=0 & i9=0 & Rd5 & LdMemAIS4CircMuC9b0 & $(END_PACKET) { Rd5 = sext(LdMemAIS4CircMuC9b0); build EndPacket; } @@ -7167,9 +7508,9 @@ define pcodeop maskGenerate; # (v2,9) memb -- "Rd32 = memb ( Rz32 ++I :circ ( Mu2 ) )" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 1 0 0 1 1 0 0 1 0 0 0 z z z z z P P u 0 + + 1 + 0 + + d d d d d +# 1 0 0 1 1 0 0 1 0 0 0 z z z z z P P u 0 - - 1 - 0 - - d d d d d -:memb Rd5,LdMemAIICircMuC9b EndPacket is iclass=9 & op2127=0x48 & op0512=0x10 & Rd5 & LdMemAIICircMuC9b & $(END_PACKET) { +:memb Rd5,LdMemAIICircMuC9b EndPacket is iclass=9 & op2127=0x48 & op12=0x0 & i9=0x1 & op7=0x0 & Rd5 & LdMemAIICircMuC9b & $(END_PACKET) { Rd5 = sext(LdMemAIICircMuC9b); build EndPacket; } @@ -7188,9 +7529,9 @@ define pcodeop maskGenerate; # (v4,10) memb -- "memb ( Rf32 = #U6x ) = Nt8 .new" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 1 0 1 0 1 0 1 1 1 0 1 f f f f f P P 0 0 0 t t t 1 + I I I I I I +# 1 0 1 0 1 0 1 1 1 0 1 f f f f f P P 0 0 0 t t t 1 - I I I I I I -:memb StMemRsAssignxC10b,Nreg0810 EndPacket is iclass=10 & op2127=0x5d & op1113=0 & op0607=2 & Nreg0810 & StMemRsAssignxC10b & $(END_PACKET) { +:memb StMemRsAssignxC10b,Nreg0810 EndPacket is iclass=10 & op2127=0x5d & op1113=0 & op7=1 & Nreg0810 & StMemRsAssignxC10b & $(END_PACKET) { build EndPacket; <> StMemRsAssignxC10b = Nreg0810:1; @@ -7199,9 +7540,9 @@ define pcodeop maskGenerate; # (v4,10) memb -- "memb ( Rf32 = #U6x ) = Rt32" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 1 0 1 0 1 0 1 1 0 0 0 f f f f f P P 0 t t t t t 1 + I I I I I I +# 1 0 1 0 1 0 1 1 0 0 0 f f f f f P P 0 t t t t t 1 - I I I I I I -:memb StMemRsAssignxC10b,rt5 EndPacket is iclass=10 & op2127=0x58 & op13=0 & op0607=2 & rt5 & StMemRsAssignxC10b & $(END_PACKET) { +:memb StMemRsAssignxC10b,rt5 EndPacket is iclass=10 & op2127=0x58 & op13=0 & op7=1 & rt5 & StMemRsAssignxC10b & $(END_PACKET) { tmp:1 = rt5:1; build EndPacket; <> @@ -7234,9 +7575,9 @@ define pcodeop maskGenerate; # (v4,3) memb -- "memb ( Rs32 + #u6:0 ) = #S8x" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 0 0 1 1 1 1 0 + + 0 0 s s s s s P P I i i i i i i I I I I I I I +# 0 0 1 1 1 1 0 - - 0 0 s s s s s P P I i i i i i i I I I I I I I -:memb StMemRsRelC3b,Simm8_13_0006x EndPacket is iclass=3 & op2127=0x60 & StMemRsRelC3b & Simm8_13_0006x & $(END_PACKET) { +:memb StMemRsRelC3b,Simm8_13_0006x EndPacket is iclass=3 & op2527=0x6 & op2122=0x0 & StMemRsRelC3b & Simm8_13_0006x & $(END_PACKET) { build EndPacket; <> StMemRsRelC3b = Simm8_13_0006x; @@ -7245,9 +7586,9 @@ define pcodeop maskGenerate; # (v4,3) memb -- "memb ( Rs32 + #u6:0x ) &= Rt32" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 0 0 1 1 1 1 1 0 + 0 0 s s s s s P P 0 i i i i i i 1 0 t t t t t +# 0 0 1 1 1 1 1 0 - 0 0 s s s s s P P 0 i i i i i i 1 0 t t t t t -:memb&= StMemRsRelxC3b,ru5 EndPacket is iclass=3 & op2127=0x70 & op13=0 & op0506=2 & StMemRsRelxC3b & ru5 & $(END_PACKET) { +:memb&= StMemRsRelxC3b,ru5 EndPacket is iclass=3 & op2427=0xe & op2122=0x0 & op13=0 & op0506=2 & StMemRsRelxC3b & ru5 & $(END_PACKET) { tmp:1 = StMemRsRelxC3b & ru5:1; build EndPacket; <> @@ -7257,9 +7598,9 @@ define pcodeop maskGenerate; # (v4,3) memb -- "memb ( Rs32 + #u6:0x ) += #U5" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 0 0 1 1 1 1 1 1 + 0 0 s s s s s P P 0 i i i i i i 0 0 I I I I I +# 0 0 1 1 1 1 1 1 - 0 0 s s s s s P P 0 i i i i i i 0 0 I I I I I -:memb+= StMemRsRelxC3b,Uimm8_0004 EndPacket is iclass=3 & op2127=0x78 & op13=0 & op0506=0 & StMemRsRelxC3b & Uimm8_0004 & $(END_PACKET) { +:memb+= StMemRsRelxC3b,Uimm8_0004 EndPacket is iclass=3 & op2427=0xf & op2122=0x0 & op13=0 & op0506=0 & StMemRsRelxC3b & Uimm8_0004 & $(END_PACKET) { tmp:1 = StMemRsRelxC3b + Uimm8_0004; build EndPacket; <> @@ -7269,9 +7610,9 @@ define pcodeop maskGenerate; # (v4,3) memb -- "memb ( Rs32 + #u6:0x ) += Rt32" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 0 0 1 1 1 1 1 0 + 0 0 s s s s s P P 0 i i i i i i 0 0 t t t t t +# 0 0 1 1 1 1 1 0 - 0 0 s s s s s P P 0 i i i i i i 0 0 t t t t t -:memb+= StMemRsRelxC3b,ru5 EndPacket is iclass=3 & op2127=0x70 & op13=0 & op0506=0 & StMemRsRelxC3b & ru5 & $(END_PACKET) { +:memb+= StMemRsRelxC3b,ru5 EndPacket is iclass=3 & op2427=0xe & op2122=0x0 & op13=0 & op0506=0 & StMemRsRelxC3b & ru5 & $(END_PACKET) { tmp:1 = StMemRsRelxC3b + ru5:1; build EndPacket; <> @@ -7281,9 +7622,9 @@ define pcodeop maskGenerate; # (v4,3) memb -- "memb ( Rs32 + #u6:0x ) -= #U5" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 0 0 1 1 1 1 1 1 + 0 0 s s s s s P P 0 i i i i i i 0 1 I I I I I +# 0 0 1 1 1 1 1 1 - 0 0 s s s s s P P 0 i i i i i i 0 1 I I I I I -:memb-= StMemRsRelxC3b,Uimm8_0004 EndPacket is iclass=3 & op2127=0x78 & op13=0 & op0506=1 & StMemRsRelxC3b & Uimm8_0004 & $(END_PACKET) { +:memb-= StMemRsRelxC3b,Uimm8_0004 EndPacket is iclass=3 & op2427=0xf & op2122=0x0 & op13=0 & op0506=1 & StMemRsRelxC3b & Uimm8_0004 & $(END_PACKET) { tmp:1 = StMemRsRelxC3b - Uimm8_0004; build EndPacket; <> @@ -7293,9 +7634,9 @@ define pcodeop maskGenerate; # (v4,3) memb -- "memb ( Rs32 + #u6:0x ) -= Rt32" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 0 0 1 1 1 1 1 0 + 0 0 s s s s s P P 0 i i i i i i 0 1 t t t t t +# 0 0 1 1 1 1 1 0 - 0 0 s s s s s P P 0 i i i i i i 0 1 t t t t t -:memb-= StMemRsRelxC3b,ru5 EndPacket is iclass=3 & op2127=0x70 & op13=0 & op0506=1 & StMemRsRelxC3b & ru5 & $(END_PACKET) { +:memb-= StMemRsRelxC3b,ru5 EndPacket is iclass=3 & op2427=0xe & op2122=0x0 & op13=0 & op0506=1 & StMemRsRelxC3b & ru5 & $(END_PACKET) { tmp:1 = StMemRsRelxC3b - ru5:1; build EndPacket; <> @@ -7305,9 +7646,9 @@ define pcodeop maskGenerate; # (v4,3) memb -- "memb ( Rs32 + #u6:0x ) = clrbit ( #U5 )" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 0 0 1 1 1 1 1 1 + 0 0 s s s s s P P 0 i i i i i i 1 0 I I I I I +# 0 0 1 1 1 1 1 1 - 0 0 s s s s s P P 0 i i i i i i 1 0 I I I I I -:memb StMemRsRelxC3b,ClrBit_0004b EndPacket is iclass=3 & op2127=0x78 & op13=0 & op0506=2 & StMemRsRelxC3b & ClrBit_0004b & $(END_PACKET) { +:memb StMemRsRelxC3b,ClrBit_0004b EndPacket is iclass=3 & op2427=0xf & op2122=0x0 & op13=0 & op0506=2 & StMemRsRelxC3b & ClrBit_0004b & $(END_PACKET) { tmp:1 = StMemRsRelxC3b & ClrBit_0004b; build EndPacket; <> @@ -7317,9 +7658,9 @@ define pcodeop maskGenerate; # (v4,3) memb -- "memb ( Rs32 + #u6:0x ) = setbit ( #U5 )" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 0 0 1 1 1 1 1 1 + 0 0 s s s s s P P 0 i i i i i i 1 1 I I I I I +# 0 0 1 1 1 1 1 1 - 0 0 s s s s s P P 0 i i i i i i 1 1 I I I I I -:memb StMemRsRelxC3b,SetBit_0004b EndPacket is iclass=3 & op2127=0x78 & op13=0 & op0506=3 & StMemRsRelxC3b & SetBit_0004b & $(END_PACKET) { +:memb StMemRsRelxC3b,SetBit_0004b EndPacket is iclass=3 & op2427=0xf & op2122=0x0 & op13=0 & op0506=3 & StMemRsRelxC3b & SetBit_0004b & $(END_PACKET) { tmp:1 = StMemRsRelxC3b | SetBit_0004b; build EndPacket; <> @@ -7329,9 +7670,9 @@ define pcodeop maskGenerate; # (v4,3) memb -- "memb ( Rs32 + #u6:0x ) |= Rt32" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 0 0 1 1 1 1 1 0 + 0 0 s s s s s P P 0 i i i i i i 1 1 t t t t t +# 0 0 1 1 1 1 1 0 - 0 0 s s s s s P P 0 i i i i i i 1 1 t t t t t -:memb|= StMemRsRelxC3b,ru5 EndPacket is iclass=3 & op2127=0x70 & op13=0 & op0506=3 & StMemRsRelxC3b & ru5 & $(END_PACKET) { +:memb|= StMemRsRelxC3b,ru5 EndPacket is iclass=3 & op2427=0xe & op2122=0x0 & op13=0 & op0506=3 & StMemRsRelxC3b & ru5 & $(END_PACKET) { tmp:1 = StMemRsRelxC3b | ru5:1; build EndPacket; <> @@ -7341,9 +7682,9 @@ define pcodeop maskGenerate; # (v4,3) memb -- "memb ( Rs32 + Ru32 << #n2 ) = Nt8 .new" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 0 0 1 1 1 0 1 1 1 0 1 s s s s s P P n u u u u u n + + 0 0 t t t +# 0 0 1 1 1 0 1 1 1 0 1 s s s s s P P n u u u u u n - - 0 0 t t t -:memb MemRsRelShiftC3b,Nreg0002 EndPacket is iclass=3 & op2127=0x5d & op0306=0 & MemRsRelShiftC3b & Nreg0002 & $(END_PACKET) { +:memb MemRsRelShiftC3b,Nreg0002 EndPacket is iclass=3 & op2127=0x5d & op0304=0 & MemRsRelShiftC3b & Nreg0002 & $(END_PACKET) { build EndPacket; <> MemRsRelShiftC3b = Nreg0002:1; @@ -7352,9 +7693,9 @@ define pcodeop maskGenerate; # (v4,3) memb -- "memb ( Rs32 + Ru32 << #n2 ) = Rt32" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 0 0 1 1 1 0 1 1 0 0 0 s s s s s P P n u u u u u n + + t t t t t +# 0 0 1 1 1 0 1 1 0 0 0 s s s s s P P n u u u u u n - - t t t t t -:memb MemRsRelShiftC3b,ru5 EndPacket is iclass=3 & op2127=0x58 & op0506=0 & MemRsRelShiftC3b & ru5 & $(END_PACKET) { +:memb MemRsRelShiftC3b,ru5 EndPacket is iclass=3 & op2127=0x58 & MemRsRelShiftC3b & ru5 & $(END_PACKET) { tmp:1 = ru5:1; build EndPacket; <> @@ -7387,9 +7728,9 @@ define pcodeop maskGenerate; # (v4,10) memb -- "memb ( Rz32 ++ #s4:0 ) = Nt8 .new" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 1 0 1 0 1 0 1 1 1 0 1 z z z z z P P 0 0 0 t t t 0 i i i i + 0 + +# 1 0 1 0 1 0 1 1 1 0 1 z z z z z P P 0 0 0 t t t 0 i i i i - 0 - -:memb StMemAIS4C10b,Nreg0810 EndPacket is iclass=10 & op2127=0x5d & op1113=0 & op7=0 & op0002=0 & Nreg0810 & StMemAIS4C10b & $(END_PACKET) { +:memb StMemAIS4C10b,Nreg0810 EndPacket is iclass=10 & op2127=0x5d & op1113=0 & op7=0 & op1=0 & Nreg0810 & StMemAIS4C10b & $(END_PACKET) { build EndPacket; <> StMemAIS4C10b = Nreg0810:1; @@ -7398,9 +7739,9 @@ define pcodeop maskGenerate; # (v4,10) memb -- "memb ( Rz32 ++ #s4:0 :circ ( Mu2 ) ) = Nt8 .new" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 1 0 1 0 1 0 0 1 1 0 1 z z z z z P P u 0 0 t t t 0 i i i i + 0 + +# 1 0 1 0 1 0 0 1 1 0 1 z z z z z P P u 0 0 t t t 0 i i i i - 0 - -:memb StMemAIS4CircMuC10b,Nreg0810 EndPacket is iclass=10 & op2127=0x4d & op1112=0 & op7=0 & op0002=0 & Nreg0810 & StMemAIS4CircMuC10b & $(END_PACKET) { +:memb StMemAIS4CircMuC10b,Nreg0810 EndPacket is iclass=10 & op2127=0x4d & op1112=0 & op7=0 & op1=0 & Nreg0810 & StMemAIS4CircMuC10b & $(END_PACKET) { build EndPacket; <> StMemAIS4CircMuC10b = Nreg0810:1; @@ -7409,14 +7750,14 @@ define pcodeop maskGenerate; # (v4,10) memb -- "memb ( Rz32 ++ Mu2 ) = Nt8 .new" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 1 0 1 0 1 1 0 1 1 0 1 z z z z z P P u 0 0 t t t 0 + + + + + + + +# 1 0 1 0 1 1 0 1 1 0 1 z z z z z P P u 0 0 t t t 0 - - - - - - - # # (v4,10) memb -- "memb ( Rz32 ++ Mu2 :brev ) = Nt8 .new" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 1 0 1 0 1 1 1 1 1 0 1 z z z z z P P u 0 0 t t t 0 + + + + + + + +# 1 0 1 0 1 1 1 1 1 0 1 z z z z z P P u 0 0 t t t 0 - - - - - - - -:memb StMemAIMuC10b,Nreg0810 EndPacket is iclass=10 & op2627=3 & op2124=0xd & op1112=0 & op0007=0 & Nreg0810 & StMemAIMuC10b & $(END_PACKET) { +:memb StMemAIMuC10b,Nreg0810 EndPacket is iclass=10 & op2627=3 & op2124=0xd & op1112=0 & op7=0 & Nreg0810 & StMemAIMuC10b & $(END_PACKET) { build EndPacket; <> StMemAIMuC10b = Nreg0810:1; @@ -7425,9 +7766,9 @@ define pcodeop maskGenerate; # (v4,10) memb -- "memb ( Rz32 ++I :circ ( Mu2 ) ) = Nt8 .new" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 1 0 1 0 1 0 0 1 1 0 1 z z z z z P P u 0 0 t t t 0 + + + + + 1 + +# 1 0 1 0 1 0 0 1 1 0 1 z z z z z P P u 0 0 t t t 0 - - - - - 1 - -:memb StMemAIICircMuC10b,Nreg0810 EndPacket is iclass=10 & op2127=0x4d & op1112=0 & op0007=2 & Nreg0810 & StMemAIICircMuC10b & $(END_PACKET) { +:memb StMemAIICircMuC10b,Nreg0810 EndPacket is iclass=10 & op2127=0x4d & op1112=0 & op7=0 & op1=1 & Nreg0810 & StMemAIICircMuC10b & $(END_PACKET) { build EndPacket; <> StMemAIICircMuC10b = Nreg0810:1; @@ -7436,9 +7777,9 @@ define pcodeop maskGenerate; # (v2,10) memb -- "memb ( Rz32 ++ #s4:0 ) = Rt32" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 1 0 1 0 1 0 1 1 0 0 0 z z z z z P P 0 t t t t t 0 i i i i + 0 + +# 1 0 1 0 1 0 1 1 0 0 0 z z z z z P P 0 t t t t t 0 i i i i - 0 - -:memb StMemAIS4C10b,rt5 EndPacket is iclass=10 & op2127=0x58 & op13=0 & op7=0 & op0002=0 & rt5 & StMemAIS4C10b & $(END_PACKET) { +:memb StMemAIS4C10b^StNt24,rt5 EndPacket is iclass=10 & op2527=5 & op2123=0 & op13=0 & op7=0 & op1=0 & StNt24 & rt5 & StMemAIS4C10b & $(END_PACKET) { tmp:1 = rt5:1; build EndPacket; <> @@ -7448,9 +7789,9 @@ define pcodeop maskGenerate; # (v2,10) memb -- "memb ( Rz32 ++ #s4:0 :circ ( Mu2 ) ) = Rt32" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 1 0 1 0 1 0 0 1 0 0 0 z z z z z P P u t t t t t 0 i i i i + 0 + +# 1 0 1 0 1 0 0 1 0 0 0 z z z z z P P u t t t t t 0 i i i i - 0 - -:memb StMemAIS4CircMuC10b,rt5 EndPacket is iclass=10 & op2127=0x48 & op7=0 & op0002=0 & rt5 & StMemAIS4CircMuC10b & $(END_PACKET) { +:memb StMemAIS4CircMuC10b,rt5 EndPacket is iclass=10 & op2127=0x48 & op7=0 & op1=0 & rt5 & StMemAIS4CircMuC10b & $(END_PACKET) { tmp:1 = rt5:1; build EndPacket; <> @@ -7460,14 +7801,14 @@ define pcodeop maskGenerate; # (v2,10) memb -- "memb ( Rz32 ++ Mu2 ) = Rt32" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 1 0 1 0 1 1 0 1 0 0 0 z z z z z P P u t t t t t 0 + + + + + + + +# 1 0 1 0 1 1 0 1 0 0 0 z z z z z P P u t t t t t 0 - - - - - - - # # (v2,10) memb -- "memb ( Rz32 ++ Mu2 :brev ) = Rt32" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 1 0 1 0 1 1 1 1 0 0 0 z z z z z P P u t t t t t 0 + + + + + + + +# 1 0 1 0 1 1 1 1 0 0 0 z z z z z P P u t t t t t 0 - - - - - - - -:memb StMemAIMuC10b,rt5 EndPacket is iclass=10 & op2627=3 & op2124=8 & op0007=0 & rt5 & StMemAIMuC10b & $(END_PACKET) { +:memb StMemAIMuC10b,rt5 EndPacket is iclass=10 & op2627=3 & op2124=8 & op7=0 & rt5 & StMemAIMuC10b & $(END_PACKET) { tmp:1 = rt5:1; build EndPacket; <> @@ -7477,9 +7818,9 @@ define pcodeop maskGenerate; # (v2,10) memb -- "memb ( Rz32 ++I :circ ( Mu2 ) ) = Rt32" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 1 0 1 0 1 0 0 1 0 0 0 z z z z z P P u t t t t t 0 + + + + + 1 + +# 1 0 1 0 1 0 0 1 0 0 0 z z z z z P P u t t t t t 0 - - - - - 1 - -:memb StMemAIICircMuC10b,rt5 EndPacket is iclass=10 & op2127=0x48 & op0007=0x2 & rt5 & StMemAIICircMuC10b & $(END_PACKET) { +:memb StMemAIICircMuC10b,rt5 EndPacket is iclass=10 & op2127=0x48 & op7=0x0 & op1=0x1 & rt5 & StMemAIICircMuC10b & $(END_PACKET) { tmp:1 = rt5:1; build EndPacket; <> @@ -7512,32 +7853,34 @@ define pcodeop maskGenerate; # (v4,9) memb -- "if ( Pt4 ) Rd32 = memb ( #u6x )" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 1 0 0 1 1 1 1 1 0 0 0 i i i i i P P 1 0 0 t t i 1 + + d d d d d +# 1 0 0 1 1 1 1 1 0 0 0 i i i i i P P 1 0 0 t t i 1 - - d d d d d # # (v4,9) memb -- "if ( ! Pt4 ) Rd32 = memb ( #u6x )" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 1 0 0 1 1 1 1 1 0 0 0 i i i i i P P 1 0 1 t t i 1 + + d d d d d +# 1 0 0 1 1 1 1 1 0 0 0 i i i i i P P 1 0 1 t t i 1 - - d d d d d # # (v4,9) memb -- "if ( Pt4 .new ) Rd32 = memb ( #u6x )" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 1 0 0 1 1 1 1 1 0 0 0 i i i i i P P 1 1 0 t t i 1 + + d d d d d +# 1 0 0 1 1 1 1 1 0 0 0 i i i i i P P 1 1 0 t t i 1 - - d d d d d # # (v4,9) memb -- "if ( ! Pt4 .new ) Rd32 = memb ( #u6x )" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 1 0 0 1 1 1 1 1 0 0 0 i i i i i P P 1 1 1 t t i 1 + + d d d d d +# 1 0 0 1 1 1 1 1 0 0 0 i i i i i P P 1 1 1 t t i 1 - - d d d d d -:memb^PuCond0910_N12_S11 rd5,LdMemAbsU6xC9b EndPacket is iclass=9 & op2127=0x78 & op13=1 & op0507=4 & rd5 & LdMemAbsU6xC9b & PuCond0910_N12_S11 & $(END_PACKET) { +:memb^PuCond0910_N12_S11 rd5,LdMemAbsU6xC9b EndPacket is iclass=9 & op2127=0x78 & op13=1 & op7=1 & rd5 & LdMemAbsU6xC9b & PuCond0910_N12_S11 & $(END_PACKET) { tmp:4 = 0; build PuCond0910_N12_S11; build EndPacket; <> + build PuCond0910_N12_S11; if (ConditionReg == 0) goto ; tmp = sext(LdMemAbsU6xC9b); <> + build PuCond0910_N12_S11; if (ConditionReg == 0) goto ; rd5 = tmp; @@ -7568,10 +7911,12 @@ define pcodeop maskGenerate; build PuCond1112_N25_S26; build EndPacket; <> + build PuCond1112_N25_S26; if (ConditionReg == 0) goto ; tmp = sext(LdMemRsRelxC4b); <> + build PuCond1112_N25_S26; if (ConditionReg == 0) goto ; rd5 = tmp; @@ -7602,10 +7947,13 @@ define pcodeop maskGenerate; build PuCond0910_N12_S11; build EndPacket; <> + build PuCond0910_N12_S11; if (ConditionReg == 0) goto ; tmp = sext(LdMemAIS4C9b0); <> + build PuCond0910_N12_S11; + build LdMemAIS4C9b0; if (ConditionReg == 0) goto ; rd5 = tmp; @@ -7636,10 +7984,12 @@ define pcodeop maskGenerate; build PuCond0506_N25_S24; build EndPacket; <> + build PuCond0506_N25_S24; if (ConditionReg == 0) goto ; tmp = sext(MemRsRelShiftC3b); <> + build PuCond0506_N25_S24; if (ConditionReg == 0) goto ; rd5 = tmp; @@ -7648,27 +7998,28 @@ define pcodeop maskGenerate; # (v4,10) memb -- "if ( Pv4 ) memb ( #u6x ) = Nt8 .new" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 1 0 1 0 1 1 1 1 1 0 1 + + + i i P P 0 0 0 t t t 1 i i i i 0 v v +# 1 0 1 0 1 1 1 1 1 0 1 - - - i i P P 0 0 0 t t t 1 i i i i 0 v v # # (v4,10) memb -- "if ( Pv4 .new ) memb ( #u6x ) = Nt8 .new" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 1 0 1 0 1 1 1 1 1 0 1 + + + i i P P 1 0 0 t t t 1 i i i i 0 v v +# 1 0 1 0 1 1 1 1 1 0 1 - - - i i P P 1 0 0 t t t 1 i i i i 0 v v # # (v4,10) memb -- "if ( ! Pv4 ) memb ( #u6x ) = Nt8 .new" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 1 0 1 0 1 1 1 1 1 0 1 + + + i i P P 0 0 0 t t t 1 i i i i 1 v v +# 1 0 1 0 1 1 1 1 1 0 1 - - - i i P P 0 0 0 t t t 1 i i i i 1 v v # # (v4,10) memb -- "if ( ! Pv4 .new ) memb ( #u6x ) = Nt8 .new" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 1 0 1 0 1 1 1 1 1 0 1 + + + i i P P 1 0 0 t t t 1 i i i i 1 v v +# 1 0 1 0 1 1 1 1 1 0 1 - - - i i P P 1 0 0 t t t 1 i i i i 1 v v -:memb^PuCond0001_N13_S02 StMemAbsU6xC10b,Nreg0810 EndPacket is iclass=10 & op2127=0x7d & op1820=0 & op1112=0 & op7=1 & Nreg0810 & StMemAbsU6xC10b & PuCond0001_N13_S02 & $(END_PACKET) { +:memb^PuCond0001_N13_S02 StMemAbsU6xC10b,Nreg0810 EndPacket is iclass=10 & op2127=0x7d & op1112=0 & op7=1 & Nreg0810 & StMemAbsU6xC10b & PuCond0001_N13_S02 & $(END_PACKET) { build PuCond0001_N13_S02; build EndPacket; <> + build PuCond0001_N13_S02; if (ConditionReg == 0) goto ; StMemAbsU6xC10b = Nreg0810:1; @@ -7694,11 +8045,12 @@ define pcodeop maskGenerate; # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| # 1 0 1 0 1 1 1 1 0 0 0 - - - i i P P 1 t t t t t 1 i i i i 1 v v -:memb^PuCond0001_N13_S02 StMemAbsU6xC10b,rt5 EndPacket is iclass=10 & op2127=0x78 & op1820=0 & op7=1 & rt5 & StMemAbsU6xC10b & PuCond0001_N13_S02 & $(END_PACKET) { +:memb^PuCond0001_N13_S02 StMemAbsU6xC10b,rt5 EndPacket is iclass=10 & op2127=0x78 & op7=1 & rt5 & StMemAbsU6xC10b & PuCond0001_N13_S02 & $(END_PACKET) { tmp:1 = rt5:1; build PuCond0001_N13_S02; build EndPacket; <> + build PuCond0001_N13_S02; if (ConditionReg == 0) goto ; StMemAbsU6xC10b = tmp; @@ -7728,6 +8080,7 @@ define pcodeop maskGenerate; build PuCond0506_N24_S23; build EndPacket; <> + build PuCond0506_N24_S23; if (ConditionReg == 0) goto ; StMemRsRelC3b = Simm8_13_0004x; @@ -7757,6 +8110,7 @@ define pcodeop maskGenerate; build PuCond0001_N25_S26; build EndPacket; <> + build PuCond0001_N25_S26; if (ConditionReg == 0) goto ; StMemRsRelxC4b = Nreg0810:1; @@ -7787,6 +8141,7 @@ define pcodeop maskGenerate; build PuCond0001_N25_S26; build EndPacket; <> + build PuCond0001_N25_S26; if (ConditionReg == 0) goto ; StMemRsRelxC4b = tmp; @@ -7816,6 +8171,7 @@ define pcodeop maskGenerate; build PuCond0506_N25_S24; build EndPacket; <> + build PuCond0506_N25_S24; if (ConditionReg == 0) goto ; MemRsRelShiftC3b = Nreg0002:1; @@ -7846,6 +8202,7 @@ define pcodeop maskGenerate; build PuCond0506_N25_S24; build EndPacket; <> + build PuCond0506_N25_S24; if (ConditionReg == 0) goto ; MemRsRelShiftC3b = tmp; @@ -7875,6 +8232,8 @@ define pcodeop maskGenerate; build PuCond0001_N07_S02; build EndPacket; <> + build PuCond0001_N07_S02; + build StMemAIS4C10b; if (ConditionReg == 0) goto ; StMemAIS4C10b = Nreg0810:1; @@ -7900,11 +8259,13 @@ define pcodeop maskGenerate; # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| # 1 0 1 0 1 0 1 1 0 0 0 z z z z z P P 1 t t t t t 0 i i i i 1 v v -:memb^PuCond0001_N07_S02 StMemAIS4C10b,rt5 EndPacket is iclass=10 & op2127=0x58 & op13=1 & rt5 & StMemAIS4C10b & PuCond0001_N07_S02 & $(END_PACKET) [ cond=1; ] { +:memb^PuCond0001_N07_S02 StMemAIS4C10b^StNt24,rt5 EndPacket is iclass=10 & op2527=5 & op2123=0 & op13=1 & StNt24 & rt5 & StMemAIS4C10b & PuCond0001_N07_S02 & $(END_PACKET) [ cond=1; ] { tmp:1 = rt5:1; build PuCond0001_N07_S02; build EndPacket; <> + build PuCond0001_N07_S02; + build StMemAIS4C10b; if (ConditionReg == 0) goto ; StMemAIS4C10b = tmp; @@ -7913,10 +8274,10 @@ define pcodeop maskGenerate; # (v4,9) memb_fifo -- "Ryy32 = memb_fifo ( Rf32 = #U6x )" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 1 0 0 1 1 0 1 0 1 0 0 f f f f f P P 0 1 I I I I + I I y y y y y +# 1 0 0 1 1 0 1 0 1 0 0 f f f f f P P 0 1 I I I I - I I y y y y y -:memb_fifo Rdd5,LdMemRsAssignxC9b EndPacket is iclass=9 & op2127=0x54 & op1213=1 & op7=0 & LdMemRsAssignxC9b & Rdd5 & $(END_PACKET) { +:memb_fifo Rdd5,LdMemRsAssignxC9b EndPacket is iclass=9 & op2127=0x54 & op1213=1 & LdMemRsAssignxC9b & Rdd5 & $(END_PACKET) { local tmp_byte = LdMemRsAssignxC9b; Rdd5 = (Rdd5 >> 8) | (zext(tmp_byte) << 56); build EndPacket; @@ -7947,9 +8308,9 @@ define pcodeop maskGenerate; # (v4,9) memb_fifo -- "Ryy32 = memb_fifo ( Rz32 ++ #s4:0 )" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 1 0 0 1 1 0 1 0 1 0 0 z z z z z P P 0 0 + + + i i i i y y y y y +# 1 0 0 1 1 0 1 0 1 0 0 z z z z z P P 0 0 - - - i i i i y y y y y -:memb_fifo Rdd5,LdMemAIS4C9b0 EndPacket is iclass=9 & op2127=0x54 & op0913=0 & LdMemAIS4C9b0 & Rdd5 & $(END_PACKET) { +:memb_fifo Rdd5,LdMemAIS4C9b0 EndPacket is iclass=9 & op2127=0x54 & op1213=0 & LdMemAIS4C9b0 & Rdd5 & $(END_PACKET) { local tmp_byte = LdMemAIS4C9b0; Rdd5 = (Rdd5 >> 8) | (zext(tmp_byte) << 56); build EndPacket; @@ -7958,9 +8319,9 @@ define pcodeop maskGenerate; # (v4,9) memb_fifo -- "Ryy32 = memb_fifo ( Rz32 ++ #s4:0 :circ ( Mu2 ) )" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 1 0 0 1 1 0 0 0 1 0 0 z z z z z P P u 0 + + 0 i i i i y y y y y +# 1 0 0 1 1 0 0 0 1 0 0 z z z z z P P u 0 - - 0 i i i i y y y y y -:memb_fifo Rdd5,LdMemAIS4CircMuC9b0 EndPacket is iclass=9 & op2127=0x44 & op0912=0 & LdMemAIS4CircMuC9b0 & Rdd5 & $(END_PACKET) { +:memb_fifo Rdd5,LdMemAIS4CircMuC9b0 EndPacket is iclass=9 & op2127=0x44 & op12=0 & i9=0 & LdMemAIS4CircMuC9b0 & Rdd5 & $(END_PACKET) { local tmp_byte = LdMemAIS4CircMuC9b0; Rdd5 = (Rdd5 >> 8) | (zext(tmp_byte) << 56); build EndPacket; @@ -7969,14 +8330,14 @@ define pcodeop maskGenerate; # (v4,9) memb_fifo -- "Ryy32 = memb_fifo ( Rz32 ++ Mu2 )" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 1 0 0 1 1 1 0 0 1 0 0 z z z z z P P u 0 + + + + 0 + + y y y y y +# 1 0 0 1 1 1 0 0 1 0 0 z z z z z P P u 0 - - - - 0 - - y y y y y # # (v4,9) memb_fifo -- "Ryy32 = memb_fifo ( Rz32 ++ Mu2 :brev )" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 1 0 0 1 1 1 1 0 1 0 0 z z z z z P P u 0 + + + + 0 + + y y y y y +# 1 0 0 1 1 1 1 0 1 0 0 z z z z z P P u 0 - - - - 0 - - y y y y y -:memb_fifo Rdd5,LdMemAIMuC9b EndPacket is iclass=9 & op2627=3 & op2124=4 & op0512=0 & LdMemAIMuC9b & Rdd5 & $(END_PACKET) { +:memb_fifo Rdd5,LdMemAIMuC9b EndPacket is iclass=9 & op2627=3 & op2124=4 & op12=0 & op7=0 & LdMemAIMuC9b & Rdd5 & $(END_PACKET) { local tmp_byte = LdMemAIMuC9b; Rdd5 = (Rdd5 >> 8) | (zext(tmp_byte) << 56); build EndPacket; @@ -7985,9 +8346,9 @@ define pcodeop maskGenerate; # (v4,9) memb_fifo -- "Ryy32 = memb_fifo ( Rz32 ++I :circ ( Mu2 ) )" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 1 0 0 1 1 0 0 0 1 0 0 z z z z z P P u 0 + + 1 + 0 + + y y y y y +# 1 0 0 1 1 0 0 0 1 0 0 z z z z z P P u 0 - - 1 - 0 - - y y y y y -:memb_fifo Rdd5,LdMemAIICircMuC9b EndPacket is iclass=9 & op2127=0x44 & op0512=0x10 & LdMemAIICircMuC9b & Rdd5 & $(END_PACKET) { +:memb_fifo Rdd5,LdMemAIICircMuC9b EndPacket is iclass=9 & op2127=0x44 & op12=0x0 & i9=0x1 & op7=0x0 & LdMemAIICircMuC9b & Rdd5 & $(END_PACKET) { local tmp_byte = LdMemAIICircMuC9b; Rdd5 = (Rdd5 >> 8) | (zext(tmp_byte) << 56); build EndPacket; @@ -7996,13 +8357,13 @@ define pcodeop maskGenerate; # (v4,9) membh -- "Rd32 = membh ( Rf32 = #U6x )" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 1 0 0 1 1 0 1 0 0 0 1 f f f f f P P 0 1 I I I I + I I d d d d d +# 1 0 0 1 1 0 1 0 0 0 1 f f f f f P P 0 1 I I I I - I I d d d d d # TODO: Uncertain how dest register is modified - could be very simple define pcodeop membh32; # It is assumed that a byte is loaded from memory at the specified address define pcodeop membh64; # It is assumed that a byte is loaded from memory at the specified address -:membh Rd5,LdMemRsAssignxC9b EndPacket is iclass=9 & op2127=0x51 & op1213=1 & op7=0 & Rd5 & LdMemRsAssignxC9b & $(END_PACKET) { +:membh Rd5,LdMemRsAssignxC9b EndPacket is iclass=9 & op2127=0x51 & op1213=1 & Rd5 & LdMemRsAssignxC9b & $(END_PACKET) { Rd5 = membh32(LdMemRsAssignxC9b); build EndPacket; } @@ -8030,9 +8391,9 @@ define pcodeop membh64; # It is assumed that a byte is loaded from memory at the # (v4,9) membh -- "Rd32 = membh ( Rz32 ++ #s4:1 )" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 1 0 0 1 1 0 1 0 0 0 1 z z z z z P P 0 0 + + + i i i i d d d d d +# 1 0 0 1 1 0 1 0 0 0 1 z z z z z P P 0 0 - - - i i i i d d d d d -:membh Rd5,LdMemAIS4C9b1 EndPacket is iclass=9 & op2127=0x51 & op0913=0 & Rd5 & LdMemAIS4C9b1 & $(END_PACKET) { +:membh Rd5,LdMemAIS4C9b1 EndPacket is iclass=9 & op2127=0x51 & op1213=0 & Rd5 & LdMemAIS4C9b1 & $(END_PACKET) { Rd5 = membh32(LdMemAIS4C9b1); build EndPacket; } @@ -8040,9 +8401,9 @@ define pcodeop membh64; # It is assumed that a byte is loaded from memory at the # (v4,9) membh -- "Rd32 = membh ( Rz32 ++ #s4:1 :circ ( Mu2 ) )" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 1 0 0 1 1 0 0 0 0 0 1 z z z z z P P u 0 + + 0 i i i i d d d d d +# 1 0 0 1 1 0 0 0 0 0 1 z z z z z P P u 0 - - 0 i i i i d d d d d -:membh Rd5,LdMemAIS4CircMuC9b1 EndPacket is iclass=9 & op2127=0x41 & op0912=0 & Rd5 & LdMemAIS4CircMuC9b1 & $(END_PACKET) { +:membh Rd5,LdMemAIS4CircMuC9b1 EndPacket is iclass=9 & op2127=0x41 & op12=0 & i9=0 & Rd5 & LdMemAIS4CircMuC9b1 & $(END_PACKET) { Rd5 = membh32(LdMemAIS4CircMuC9b1); build EndPacket; } @@ -8050,14 +8411,14 @@ define pcodeop membh64; # It is assumed that a byte is loaded from memory at the # (v4,9) membh -- "Rd32 = membh ( Rz32 ++ Mu2 )" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 1 0 0 1 1 1 0 0 0 0 1 z z z z z P P u 0 + + + + 0 + + d d d d d +# 1 0 0 1 1 1 0 0 0 0 1 z z z z z P P u 0 - - - - 0 - - d d d d d # # (v4,9) membh -- "Rd32 = membh ( Rz32 ++ Mu2 :brev )" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 1 0 0 1 1 1 1 0 0 0 1 z z z z z P P u 0 + + + + 0 + + d d d d d +# 1 0 0 1 1 1 1 0 0 0 1 z z z z z P P u 0 - - - - 0 - - d d d d d -:membh Rd5,LdMemAIMuC9b EndPacket is iclass=9 & op2627=3 & op2124=1 & op0512=0 & Rd5 & LdMemAIMuC9b & $(END_PACKET) { +:membh Rd5,LdMemAIMuC9b EndPacket is iclass=9 & op2627=3 & op2124=1 & op12=0 & op7=0 & Rd5 & LdMemAIMuC9b & $(END_PACKET) { Rd5 = membh32(LdMemAIMuC9b); build EndPacket; } @@ -8065,9 +8426,9 @@ define pcodeop membh64; # It is assumed that a byte is loaded from memory at the # (v4,9) membh -- "Rd32 = membh ( Rz32 ++I :circ ( Mu2 ) )" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 1 0 0 1 1 0 0 0 0 0 1 z z z z z P P u 0 + + 1 + 0 + + d d d d d +# 1 0 0 1 1 0 0 0 0 0 1 z z z z z P P u 0 - - 1 - 0 - - d d d d d -:membh Rd5,LdMemAIICircMuC9b EndPacket is iclass=9 & op2127=0x41 & op0512=0x10 & Rd5 & LdMemAIICircMuC9b & $(END_PACKET) { +:membh Rd5,LdMemAIICircMuC9b EndPacket is iclass=9 & op2127=0x41 & op12=0x0 & i9=0x1 & op7=0x0 & Rd5 & LdMemAIICircMuC9b & $(END_PACKET) { Rd5 = membh32(LdMemAIICircMuC9b); build EndPacket; } @@ -8075,9 +8436,9 @@ define pcodeop membh64; # It is assumed that a byte is loaded from memory at the # (v4,9) membh -- "Rdd32 = membh ( Rf32 = #U6x )" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 1 0 0 1 1 0 1 0 1 1 1 f f f f f P P 0 1 I I I I + I I d d d d d +# 1 0 0 1 1 0 1 0 1 1 1 f f f f f P P 0 1 I I I I - I I d d d d d -:membh Rdd5,LdMemRsAssignxC9b EndPacket is iclass=9 & op2127=0x57 & op1213=1 & op7=0 & Rdd5 & LdMemRsAssignxC9b & $(END_PACKET) { +:membh Rdd5,LdMemRsAssignxC9b EndPacket is iclass=9 & op2127=0x57 & op1213=1 & Rdd5 & LdMemRsAssignxC9b & $(END_PACKET) { Rdd5 = membh64(LdMemRsAssignxC9b); build EndPacket; } @@ -8105,9 +8466,9 @@ define pcodeop membh64; # It is assumed that a byte is loaded from memory at the # (v4,9) membh -- "Rdd32 = membh ( Rz32 ++ #s4:2 )" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 1 0 0 1 1 0 1 0 1 1 1 z z z z z P P 0 0 + + + i i i i d d d d d +# 1 0 0 1 1 0 1 0 1 1 1 z z z z z P P 0 0 - - - i i i i d d d d d -:membh Rdd5,LdMemAIS4C9b2 EndPacket is iclass=9 & op2127=0x57 & op0913=0 & Rdd5 & LdMemAIS4C9b2 & $(END_PACKET) { +:membh Rdd5,LdMemAIS4C9b2 EndPacket is iclass=9 & op2127=0x57 & op1213=0 & Rdd5 & LdMemAIS4C9b2 & $(END_PACKET) { Rdd5 = membh64(LdMemAIS4C9b2); build EndPacket; } @@ -8115,9 +8476,9 @@ define pcodeop membh64; # It is assumed that a byte is loaded from memory at the # (v4,9) membh -- "Rdd32 = membh ( Rz32 ++ #s4:2 :circ ( Mu2 ) )" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 1 0 0 1 1 0 0 0 1 1 1 z z z z z P P u 0 + + 0 i i i i d d d d d +# 1 0 0 1 1 0 0 0 1 1 1 z z z z z P P u 0 - - 0 i i i i d d d d d -:membh Rdd5,LdMemAIS4CircMuC9b2 EndPacket is iclass=9 & op2127=0x47 & op0912=0 & Rdd5 & LdMemAIS4CircMuC9b2 & $(END_PACKET) { +:membh Rdd5,LdMemAIS4CircMuC9b2 EndPacket is iclass=9 & op2127=0x47 & op12=0 & i9=0 & Rdd5 & LdMemAIS4CircMuC9b2 & $(END_PACKET) { Rdd5 = membh64(LdMemAIS4CircMuC9b2); build EndPacket; } @@ -8125,14 +8486,14 @@ define pcodeop membh64; # It is assumed that a byte is loaded from memory at the # (v4,9) membh -- "Rdd32 = membh ( Rz32 ++ Mu2 )" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 1 0 0 1 1 1 0 0 1 1 1 z z z z z P P u 0 + + + + 0 + + d d d d d +# 1 0 0 1 1 1 0 0 1 1 1 z z z z z P P u 0 - - - - 0 - - d d d d d # # (v4,9) membh -- "Rdd32 = membh ( Rz32 ++ Mu2 :brev )" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 1 0 0 1 1 1 1 0 1 1 1 z z z z z P P u 0 + + + + 0 + + d d d d d +# 1 0 0 1 1 1 1 0 1 1 1 z z z z z P P u 0 - - - - 0 - - d d d d d -:membh Rdd5,LdMemAIMuC9b EndPacket is iclass=9 & op2627=3 & op2124=7 & op0512=0 & Rdd5 & LdMemAIMuC9b & $(END_PACKET) { +:membh Rdd5,LdMemAIMuC9b EndPacket is iclass=9 & op2627=3 & op2124=7 & op12=0 & op7=0 & Rdd5 & LdMemAIMuC9b & $(END_PACKET) { Rdd5 = membh64(LdMemAIMuC9b); build EndPacket; } @@ -8140,19 +8501,30 @@ define pcodeop membh64; # It is assumed that a byte is loaded from memory at the # (v4,9) membh -- "Rdd32 = membh ( Rz32 ++I :circ ( Mu2 ) )" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 1 0 0 1 1 0 0 0 1 1 1 z z z z z P P u 0 + + 1 + 0 + + d d d d d +# 1 0 0 1 1 0 0 0 1 1 1 z z z z z P P u 0 - - 1 - 0 - - d d d d d -:membh Rdd5,LdMemAIICircMuC9b EndPacket is iclass=9 & op2127=0x47 & op0512=0x10 & Rdd5 & LdMemAIICircMuC9b & $(END_PACKET) { +:membh Rdd5,LdMemAIICircMuC9b EndPacket is iclass=9 & op2127=0x47 & op12=0x0 & i9=0x1 & op7=0x0 & Rdd5 & LdMemAIICircMuC9b & $(END_PACKET) { Rdd5 = membh64(LdMemAIICircMuC9b); build EndPacket; } +# (v66,9) memcpy -- "memcpy ( Rs32 , Rt32 , Mu2 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 0 1 0 0 1 0 0 0 0 s s s s s P P u t t t t t 0 1 0 0 0 0 0 0 + +define pcodeop memBulkCopy; +:memcpy rs5,rt5,mu EndPacket is iclass=9 & op2127=0x10 & op0507=2 & op0004=0 & rs5 & rt5 & mu & $(END_PACKET) { + memBulkCopy(rs5, rt5, mu); + build EndPacket; +} + # (v4,9) memd -- "Rdd32 = memd ( Rf32 = #U6x )" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 1 0 0 1 1 0 1 1 1 1 0 f f f f f P P 0 1 I I I I + I I d d d d d +# 1 0 0 1 1 0 1 1 1 1 0 f f f f f P P 0 1 I I I I - I I d d d d d -:memd Rdd5,LdMemRsAssignxC9d EndPacket is iclass=9 & op2127=0x5e & op7=0 & op1213=1 & Rdd5 & LdMemRsAssignxC9d & $(END_PACKET) { +:memd Rdd5,LdMemRsAssignxC9d EndPacket is iclass=9 & op2127=0x5e & op1213=1 & Rdd5 & LdMemRsAssignxC9d & $(END_PACKET) { Rdd5 = LdMemRsAssignxC9d; build EndPacket; } @@ -8190,9 +8562,9 @@ define pcodeop membh64; # It is assumed that a byte is loaded from memory at the # (v2,9) memd -- "Rdd32 = memd ( Rz32 ++ #s4:3 )" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 1 0 0 1 1 0 1 1 1 1 0 z z z z z P P 0 0 + + + i i i i d d d d d +# 1 0 0 1 1 0 1 1 1 1 0 z z z z z P P 0 0 - - - i i i i d d d d d -:memd Rdd5,LdMemAIS4C9d EndPacket is iclass=9 & op2127=0x5e & op0913=0 & Rdd5 & LdMemAIS4C9d & $(END_PACKET) { +:memd Rdd5,LdMemAIS4C9d EndPacket is iclass=9 & op2127=0x5e & op1213=0 & Rdd5 & LdMemAIS4C9d & $(END_PACKET) { Rdd5 = LdMemAIS4C9d; build EndPacket; } @@ -8200,9 +8572,9 @@ define pcodeop membh64; # It is assumed that a byte is loaded from memory at the # (v2,9) memd -- "Rdd32 = memd ( Rz32 ++ #s4:3 :circ ( Mu2 ) )" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 1 0 0 1 1 0 0 1 1 1 0 z z z z z P P u 0 + + 0 i i i i d d d d d +# 1 0 0 1 1 0 0 1 1 1 0 z z z z z P P u 0 - - 0 i i i i d d d d d -:memd Rdd5,LdMemAIS4CircMuC9d EndPacket is iclass=9 & op2127=0x4e & op0912=0 & Rdd5 & LdMemAIS4CircMuC9d & $(END_PACKET) { +:memd Rdd5,LdMemAIS4CircMuC9d EndPacket is iclass=9 & op2127=0x4e & op12=0 & i9=0 & Rdd5 & LdMemAIS4CircMuC9d & $(END_PACKET) { Rdd5 = LdMemAIS4CircMuC9d; build EndPacket; } @@ -8215,9 +8587,9 @@ define pcodeop membh64; # It is assumed that a byte is loaded from memory at the # (v2,9) memd -- "Rdd32 = memd ( Rz32 ++ Mu2 :brev )" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 1 0 0 1 1 1 1 1 1 1 0 z z z z z P P u 0 + + + + 0 + + d d d d d +# 1 0 0 1 1 1 1 1 1 1 0 z z z z z P P u 0 - - - - 0 - - d d d d d -:memd Rdd5,LdMemAIMuC9d EndPacket is iclass=9 & op2627=3 & op2124=0xe & op0512=0 & Rdd5 & LdMemAIMuC9d & $(END_PACKET) { +:memd Rdd5,LdMemAIMuC9d EndPacket is iclass=9 & op2627=3 & op2124=0xe & op12=0 & op7=0 & Rdd5 & LdMemAIMuC9d & $(END_PACKET) { Rdd5 = LdMemAIMuC9d; build EndPacket; } @@ -8225,9 +8597,9 @@ define pcodeop membh64; # It is assumed that a byte is loaded from memory at the # (v2,9) memd -- "Rdd32 = memd ( Rz32 ++I :circ ( Mu2 ) )" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 1 0 0 1 1 0 0 1 1 1 0 z z z z z P P u 0 + + 1 + 0 + + d d d d d +# 1 0 0 1 1 0 0 1 1 1 0 z z z z z P P u 0 - - 1 - 0 - - d d d d d -:memd Rdd5,LdMemAIICircMuC9d EndPacket is iclass=9 & op2127=0x4e & op0512=0x10 & Rdd5 & LdMemAIICircMuC9d & $(END_PACKET) { +:memd Rdd5,LdMemAIICircMuC9d EndPacket is iclass=9 & op2127=0x4e & op12=0x0 & i9=0x1 & op7=0x0 & Rdd5 & LdMemAIICircMuC9d & $(END_PACKET) { Rdd5 = LdMemAIICircMuC9d; build EndPacket; } @@ -8246,9 +8618,9 @@ define pcodeop membh64; # It is assumed that a byte is loaded from memory at the # (v4,10) memd -- "memd ( Rf32 = #U6x ) = Rtt32" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 1 0 1 0 1 0 1 1 1 1 0 f f f f f P P 0 t t t t t 1 + I I I I I I +# 1 0 1 0 1 0 1 1 1 1 0 f f f f f P P 0 t t t t t 1 - I I I I I I -:memd StMemRsAssignxC10d,rtt5 EndPacket is iclass=10 & op2127=0x5e & op13=0 & op0607=2 & rtt5 & StMemRsAssignxC10d & $(END_PACKET) { +:memd StMemRsAssignxC10d,rtt5 EndPacket is iclass=10 & op2127=0x5e & op13=0 & op7=1 & rtt5 & StMemRsAssignxC10d & $(END_PACKET) { tmp:8 = rtt5; build EndPacket; <> @@ -8294,9 +8666,9 @@ define pcodeop membh64; # It is assumed that a byte is loaded from memory at the # (v2,10) memd -- "memd ( Rz32 ++ #s4:3 ) = Rtt32" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 1 0 1 0 1 0 1 1 1 1 0 z z z z z P P 0 t t t t t 0 i i i i + 0 + +# 1 0 1 0 1 0 1 1 1 1 0 z z z z z P P 0 t t t t t 0 i i i i - 0 - -:memd StMemAIS4C10d,rtt5 EndPacket is iclass=10 & op2127=0x5e & op13=0 & op7=0 & op0002=0 & rtt5 & StMemAIS4C10d & $(END_PACKET) { +:memd StMemAIS4C10d^StNt24,rtt5 EndPacket is iclass=10 & op2527=5 & op2123=6 & op13=0 & op7=0 & op1=0 & StNt24 & rtt5 & StMemAIS4C10d & $(END_PACKET) { tmp:8 = rtt5; build EndPacket; <> @@ -8306,9 +8678,9 @@ define pcodeop membh64; # It is assumed that a byte is loaded from memory at the # (v2,10) memd -- "memd ( Rz32 ++ #s4:3 :circ ( Mu2 ) ) = Rtt32" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 1 0 1 0 1 0 0 1 1 1 0 z z z z z P P u t t t t t 0 i i i i + 0 + +# 1 0 1 0 1 0 0 1 1 1 0 z z z z z P P u t t t t t 0 i i i i - 0 - -:memd StMemAIS4CircMuC10d,rtt5 EndPacket is iclass=10 & op2127=0x4e & op7=0 & op0002=0 & rtt5 & StMemAIS4CircMuC10d & $(END_PACKET) { +:memd StMemAIS4CircMuC10d,rtt5 EndPacket is iclass=10 & op2127=0x4e & op7=0 & op1=0 & rtt5 & StMemAIS4CircMuC10d & $(END_PACKET) { tmp:8 = rtt5; build EndPacket; <> @@ -8318,12 +8690,12 @@ define pcodeop membh64; # It is assumed that a byte is loaded from memory at the # (v2,10) memd -- "memd ( Rz32 ++ Mu2 ) = Rtt32" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 1 0 1 0 1 1 0 1 1 1 0 z z z z z P P u t t t t t 0 + + + + + + + +# 1 0 1 0 1 1 0 1 1 1 0 z z z z z P P u t t t t t 0 - - - - - - - # # (v2,10) memd -- "memd ( Rz32 ++ Mu2 :brev ) = Rtt32" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 1 0 1 0 1 1 1 1 1 1 0 z z z z z P P u t t t t t 0 + + + + + + + +# 1 0 1 0 1 1 1 1 1 1 0 z z z z z P P u t t t t t 0 - - - - - - - :memd StMemAIMuC10d,rtt5 EndPacket is iclass=10 & op2627=3 & op2124=0xe & rtt5 & StMemAIMuC10d & $(END_PACKET) { tmp:8 = rtt5; @@ -8335,9 +8707,9 @@ define pcodeop membh64; # It is assumed that a byte is loaded from memory at the # (v2,10) memd -- "memd ( Rz32 ++I :circ ( Mu2 ) ) = Rtt32" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 1 0 1 0 1 0 0 1 1 1 0 z z z z z P P u t t t t t 0 + + + + + 1 + +# 1 0 1 0 1 0 0 1 1 1 0 z z z z z P P u t t t t t 0 - - - - - 1 - -:memd StMemAIICircMuC10d,rtt5 EndPacket is iclass=10 & op2127=0x4e & op0007=2 & rtt5 & StMemAIICircMuC10d & $(END_PACKET) { +:memd StMemAIICircMuC10d,rtt5 EndPacket is iclass=10 & op2127=0x4e & op7=0 & op1=1 & rtt5 & StMemAIICircMuC10d & $(END_PACKET) { tmp:8 = rtt5; build EndPacket; <> @@ -8359,32 +8731,34 @@ define pcodeop membh64; # It is assumed that a byte is loaded from memory at the # (v4,9) memd -- "if ( Pt4 ) Rdd32 = memd ( #u6x )" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 1 0 0 1 1 1 1 1 1 1 0 i i i i i P P 1 0 0 t t i 1 + + d d d d d +# 1 0 0 1 1 1 1 1 1 1 0 i i i i i P P 1 0 0 t t i 1 - - d d d d d # # (v4,9) memd -- "if ( ! Pt4 ) Rdd32 = memd ( #u6x )" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 1 0 0 1 1 1 1 1 1 1 0 i i i i i P P 1 0 1 t t i 1 + + d d d d d +# 1 0 0 1 1 1 1 1 1 1 0 i i i i i P P 1 0 1 t t i 1 - - d d d d d # # (v4,9) memd -- "if ( Pt4 .new ) Rdd32 = memd ( #u6x )" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 1 0 0 1 1 1 1 1 1 1 0 i i i i i P P 1 1 0 t t i 1 + + d d d d d +# 1 0 0 1 1 1 1 1 1 1 0 i i i i i P P 1 1 0 t t i 1 - - d d d d d # # (v4,9) memd -- "if ( ! Pt4 .new ) Rdd32 = memd ( #u6x )" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 1 0 0 1 1 1 1 1 1 1 0 i i i i i P P 1 1 1 t t i 1 + + d d d d d +# 1 0 0 1 1 1 1 1 1 1 0 i i i i i P P 1 1 1 t t i 1 - - d d d d d -:memd^PuCond0910_N12_S11 rdd5,LdMemAbsU6xC9d EndPacket is iclass=9 & op2127=0x7e & op13=1 & op0507=4 & rdd5 & LdMemAbsU6xC9d & PuCond0910_N12_S11 & $(END_PACKET) { +:memd^PuCond0910_N12_S11 rdd5,LdMemAbsU6xC9d EndPacket is iclass=9 & op2127=0x7e & op13=1 & op7=1 & rdd5 & LdMemAbsU6xC9d & PuCond0910_N12_S11 & $(END_PACKET) { tmp:8 = 0; build PuCond0910_N12_S11; build EndPacket; <> + build PuCond0910_N12_S11; if (ConditionReg == 0) goto ; tmp = LdMemAbsU6xC9d; <> + build PuCond0910_N12_S11; if (ConditionReg == 0) goto ; rdd5 = tmp; @@ -8415,10 +8789,12 @@ define pcodeop membh64; # It is assumed that a byte is loaded from memory at the build PuCond1112_N25_S26; build EndPacket; <> + build PuCond1112_N25_S26; if (ConditionReg == 0) goto ; tmp = LdMemRsRelxC4d; <> + build PuCond1112_N25_S26; if (ConditionReg == 0) goto ; rdd5 = tmp; @@ -8449,10 +8825,13 @@ define pcodeop membh64; # It is assumed that a byte is loaded from memory at the build PuCond0910_N12_S11; build EndPacket; <> + build PuCond0910_N12_S11; if (ConditionReg == 0) goto ; tmp = LdMemAIS4C9d; <> + build PuCond0910_N12_S11; + build LdMemAIS4C9d; if (ConditionReg == 0) goto ; rdd5 = tmp; @@ -8483,10 +8862,12 @@ define pcodeop membh64; # It is assumed that a byte is loaded from memory at the build PuCond0506_N25_S24; build EndPacket; <> + build PuCond0506_N25_S24; if (ConditionReg == 0) goto ; tmp = MemRsRelShiftC3d; <> + build PuCond0506_N25_S24; if (ConditionReg == 0) goto ; rdd5 = tmp; @@ -8495,28 +8876,29 @@ define pcodeop membh64; # It is assumed that a byte is loaded from memory at the # (v4,10) memd -- "if ( Pv4 ) memd ( #u6x ) = Rtt32" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 1 0 1 0 1 1 1 1 1 1 0 + + + i i P P 0 t t t t t 1 i i i i 0 v v +# 1 0 1 0 1 1 1 1 1 1 0 - - - i i P P 0 t t t t t 1 i i i i 0 v v # # (v4,10) memd -- "if ( ! Pv4 ) memd ( #u6x ) = Rtt32" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 1 0 1 0 1 1 1 1 1 1 0 + + + i i P P 0 t t t t t 1 i i i i 1 v v +# 1 0 1 0 1 1 1 1 1 1 0 - - - i i P P 0 t t t t t 1 i i i i 1 v v # # (v4,10) memd -- "if ( Pv4 .new ) memd ( #u6x ) = Rtt32" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 1 0 1 0 1 1 1 1 1 1 0 + + + i i P P 1 t t t t t 1 i i i i 0 v v +# 1 0 1 0 1 1 1 1 1 1 0 - - - i i P P 1 t t t t t 1 i i i i 0 v v # # (v4,10) memd -- "if ( ! Pv4 .new ) memd ( #u6x ) = Rtt32" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 1 0 1 0 1 1 1 1 1 1 0 + + + i i P P 1 t t t t t 1 i i i i 1 v v +# 1 0 1 0 1 1 1 1 1 1 0 - - - i i P P 1 t t t t t 1 i i i i 1 v v -:memd^PuCond0001_N13_S02 StMemAbsU6xC10d,rtt5 EndPacket is iclass=10 & op2127=0x7e & op1820=0 & op7=1 & rtt5 & StMemAbsU6xC10d & PuCond0001_N13_S02 & $(END_PACKET) { +:memd^PuCond0001_N13_S02 StMemAbsU6xC10d,rtt5 EndPacket is iclass=10 & op2127=0x7e & op7=1 & rtt5 & StMemAbsU6xC10d & PuCond0001_N13_S02 & $(END_PACKET) { tmp:8 = rtt5; build PuCond0001_N13_S02; build EndPacket; <> + build PuCond0001_N13_S02; if (ConditionReg == 0) goto ; StMemAbsU6xC10d = tmp; @@ -8547,6 +8929,7 @@ define pcodeop membh64; # It is assumed that a byte is loaded from memory at the build PuCond0001_N25_S26; build EndPacket; <> + build PuCond0001_N25_S26; if (ConditionReg == 0) goto ; StMemRsRelxC4d = tmp; @@ -8577,6 +8960,7 @@ define pcodeop membh64; # It is assumed that a byte is loaded from memory at the build PuCond0506_N25_S24; build EndPacket; <> + build PuCond0506_N25_S24; if (ConditionReg == 0) goto ; MemRsRelShiftC3d = tmp; @@ -8602,22 +8986,24 @@ define pcodeop membh64; # It is assumed that a byte is loaded from memory at the # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| # 1 0 1 0 1 0 1 1 1 1 0 z z z z z P P 1 t t t t t 0 i i i i 1 v v -:memd^PuCond0001_N07_S02 StMemAIS4C10d,rtt5 EndPacket is iclass=10 & op2127=0x5e & op13=1 & rtt5 & StMemAIS4C10d & PuCond0001_N07_S02 & $(END_PACKET) [ cond=1; ] { +:memd^PuCond0001_N07_S02 StMemAIS4C10d^StNt24,rtt5 EndPacket is iclass=10 & op2527=5 & op2123=6 & op13=1 & StNt24 & rtt5 & StMemAIS4C10d & PuCond0001_N07_S02 & $(END_PACKET) [ cond=1; ] { tmp:8 = rtt5; build PuCond0001_N07_S02; build EndPacket; <> + build PuCond0001_N07_S02; + build StMemAIS4C10d; if (ConditionReg == 0) goto ; StMemAIS4C10d = tmp; } -# memd_aq -- "Rdd32 = memd_aq ( Rs32 )" +# (v68,9) memd_aq -- "Rdd32 = memd_aq ( Rs32 )" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 1 0 0 1 0 0 1 0 0 0 0 s s s s s P P 0 1 1 - - - 0 0 0 d d d d d +# 1 0 0 1 0 0 1 0 0 0 0 s s s s s P P 0 1 1 - - - 0 0 0 d d d d d -:memd_aq Rdd5,LdMemRsRelC9d EndPacket is iclass=9 & op2527=1 & op2224=0 & op21=0 & Rdd5 & op1113=3 & op0810=0 & op0507=0 & LdMemRsRelC9d & $(END_PACKET) { +:memd_aq Rdd5,LdMemRsRelC9d EndPacket is iclass=9 & op2527=1 & op2224=0 & op21=0 & op1113=3 & op0507=0 & Rdd5 & LdMemRsRelC9d & $(END_PACKET) { Rdd5 = LdMemRsRelC9d; build EndPacket; } @@ -8627,7 +9013,7 @@ define pcodeop membh64; # It is assumed that a byte is loaded from memory at the # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| # 1 0 1 0 0 0 0 0 1 1 1 s s s s s P P 0 t t t t t - - 0 0 1 0 d d define pcodeop waitAllThreads; -:memd_rl":at" StMemRsRelPdC9d, rtt5 EndPacket is iclass=0xa & op2527=0 & op2224=3 & op21=1 & op13=0 & rtt5 & op0607=0 & op0205=0x2 & StMemRsRelPdC9d & $(END_PACKET) { +:memd_rl":at" StMemRsRelPdC9d, rtt5 EndPacket is iclass=0xa & op2527=0 & op2224=3 & op21=1 & op13=0 & op0205=0x2 & rtt5 & StMemRsRelPdC9d & $(END_PACKET) { tmp:8 = rtt5; build EndPacket; <> @@ -8639,8 +9025,10 @@ define pcodeop waitAllThreads; # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| # 1 0 1 0 0 0 0 0 1 1 1 s s s s s P P 0 t t t t t - - 1 0 1 0 d d + define pcodeop waitSameDomain; -:memd_rl":st" StMemRsRelPdC9d, rtt5 EndPacket is iclass=0xa & op2527=0 & op2224=3 & op21=1 & op13=0 & rtt5 & op0607=0 & op0205=0xa & StMemRsRelPdC9d & $(END_PACKET) { + +:memd_rl":st" StMemRsRelPdC9d, rtt5 EndPacket is iclass=0xa & op2527=0 & op2224=3 & op21=1 & op13=0 & op0205=0xa & rtt5 & StMemRsRelPdC9d & $(END_PACKET) { tmp:8 = rtt5; build EndPacket; <> @@ -8651,9 +9039,9 @@ define pcodeop waitSameDomain; # (v4,9) memd_locked -- "Rdd32 = memd_locked ( Rs32 )" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 1 0 0 1 0 0 1 0 0 0 0 s s s s s P P 0 1 + + + + + + + d d d d d +# 1 0 0 1 0 0 1 0 0 0 0 s s s s s P P 0 1 - - - - 0 0 0 d d d d d -:memd_locked Rdd5,StMemRsRelPdC9d EndPacket is iclass=9 & op2127=0x10 & op0513=0x80 & Rdd5 & StMemRsRelPdC9d & $(END_PACKET) { +:memd_locked Rdd5,StMemRsRelPdC9d EndPacket is iclass=9 & op2127=0x10 & op1213=0x1 & op0507=0 & Rdd5 & StMemRsRelPdC9d & $(END_PACKET) { # NOTE: Manual does not indicate lock use, cannot be group with other instructions Rdd5 = StMemRsRelPdC9d; build EndPacket; @@ -8662,9 +9050,9 @@ define pcodeop waitSameDomain; # (v4,10) memd_locked -- "memd_locked ( Rs32 , Pd4 ) = Rtt32" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 1 0 1 0 0 0 0 0 1 1 1 s s s s s P P + t t t t t + + + + + + d d +# 1 0 1 0 0 0 0 0 1 1 1 s s s s s P P - t t t t t - - - - - - d d -:memd_locked StMemRsRelPdC9d,rtt5 EndPacket is iclass=10 & op2127=0x07 & op13=0 & op0207=0 & StMemRsRelPdC9d & rtt5 & pu0001 & $(END_PACKET) { +:memd_locked StMemRsRelPdC9d,rtt5 EndPacket is iclass=10 & op2127=0x07 & StMemRsRelPdC9d & rtt5 & pu0001 & $(END_PACKET) { # NOTE: cannot be group with other instructions rc:1 = lock(); lockOK:1 = rc != 0; @@ -8682,9 +9070,9 @@ define pcodeop waitSameDomain; # (v4,9) memh -- "Rd32 = memh ( Rf32 = #U6x )" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 1 0 0 1 1 0 1 1 0 1 0 f f f f f P P 0 1 I I I I + I I d d d d d +# 1 0 0 1 1 0 1 1 0 1 0 f f f f f P P 0 1 I I I I - I I d d d d d -:memh Rd5,LdMemRsAssignxC9h EndPacket is iclass=9 & op2127=0x5a & op1213=1 & op7=0 & Rd5 & LdMemRsAssignxC9h & $(END_PACKET) { +:memh Rd5,LdMemRsAssignxC9h EndPacket is iclass=9 & op2127=0x5a & op1213=1 & Rd5 & LdMemRsAssignxC9h & $(END_PACKET) { Rd5 = sext(LdMemRsAssignxC9h); build EndPacket; } @@ -8702,9 +9090,9 @@ define pcodeop waitSameDomain; # (v4,3) memh -- "Rd32 = memh ( Rs32 + Rt32 << #n2 )" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 0 0 1 1 1 0 1 0 0 1 0 s s s s s P P n t t t t t n + + d d d d d +# 0 0 1 1 1 0 1 0 0 1 0 s s s s s P P n t t t t t n - - d d d d d -:memh Rd5,MemRsRelShiftC3h EndPacket is iclass=3 & op2127=0x52 & op0506=0 & Rd5 & MemRsRelShiftC3h & $(END_PACKET) { +:memh Rd5,MemRsRelShiftC3h EndPacket is iclass=3 & op2127=0x52 & Rd5 & MemRsRelShiftC3h & $(END_PACKET) { Rd5 = sext(MemRsRelShiftC3h); build EndPacket; } @@ -8722,9 +9110,9 @@ define pcodeop waitSameDomain; # (v2,9) memh -- "Rd32 = memh ( Rz32 ++ #s4:1 )" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 1 0 0 1 1 0 1 1 0 1 0 z z z z z P P 0 0 + + + i i i i d d d d d +# 1 0 0 1 1 0 1 1 0 1 0 z z z z z P P 0 0 - - - i i i i d d d d d -:memh Rd5,LdMemAIS4C9h EndPacket is iclass=9 & op2127=0x5a & op0913=0 & Rd5 & LdMemAIS4C9h & $(END_PACKET) { +:memh Rd5,LdMemAIS4C9h EndPacket is iclass=9 & op2127=0x5a & op1213=0 & Rd5 & LdMemAIS4C9h & $(END_PACKET) { Rd5 = sext(LdMemAIS4C9h); build EndPacket; } @@ -8732,9 +9120,9 @@ define pcodeop waitSameDomain; # (v2,9) memh -- "Rd32 = memh ( Rz32 ++ #s4:1 :circ ( Mu2 ) )" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 1 0 0 1 1 0 0 1 0 1 0 z z z z z P P u 0 + + 0 i i i i d d d d d +# 1 0 0 1 1 0 0 1 0 1 0 z z z z z P P u 0 - - 0 i i i i d d d d d -:memh Rd5,LdMemAIS4CircMuC9h EndPacket is iclass=9 & op2127=0x4a & op0912=0 & Rd5 & LdMemAIS4CircMuC9h & $(END_PACKET) { +:memh Rd5,LdMemAIS4CircMuC9h EndPacket is iclass=9 & op2127=0x4a & op12=0 & i9=0 & Rd5 & LdMemAIS4CircMuC9h & $(END_PACKET) { Rd5 = sext(LdMemAIS4CircMuC9h); build EndPacket; } @@ -8742,14 +9130,14 @@ define pcodeop waitSameDomain; # (v2,9) memh -- "Rd32 = memh ( Rz32 ++ Mu2 )" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 1 0 0 1 1 1 0 1 0 1 0 z z z z z P P u 0 + + + + 0 + + d d d d d +# 1 0 0 1 1 1 0 1 0 1 0 z z z z z P P u 0 - - - - 0 - - d d d d d # # (v2,9) memh -- "Rd32 = memh ( Rz32 ++ Mu2 :brev )" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 1 0 0 1 1 1 1 1 0 1 0 z z z z z P P u 0 + + + + 0 + + d d d d d +# 1 0 0 1 1 1 1 1 0 1 0 z z z z z P P u 0 - - - - 0 - - d d d d d -:memh Rd5,LdMemAIMuC9h EndPacket is iclass=9 & op2627=3 & op2124=0xa & op0512=0 & Rd5 & LdMemAIMuC9h & $(END_PACKET) { +:memh Rd5,LdMemAIMuC9h EndPacket is iclass=9 & op2627=3 & op2124=0xa & op12=0 & op7=0 & Rd5 & LdMemAIMuC9h & $(END_PACKET) { Rd5 = sext(LdMemAIMuC9h); build EndPacket; } @@ -8757,9 +9145,9 @@ define pcodeop waitSameDomain; # (v2,9) memh -- "Rd32 = memh ( Rz32 ++I :circ ( Mu2 ) )" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 1 0 0 1 1 0 0 1 0 1 0 z z z z z P P u 0 + + 1 + 0 + + d d d d d +# 1 0 0 1 1 0 0 1 0 1 0 z z z z z P P u 0 - - 1 - 0 - - d d d d d -:memh Rd5,LdMemAIICircMuC9h EndPacket is iclass=9 & op2127=0x4a & op0512=0x10 & Rd5 & LdMemAIICircMuC9h & $(END_PACKET) { +:memh Rd5,LdMemAIICircMuC9h EndPacket is iclass=9 & op2127=0x4a & op12=0x0 & i9=0x1 & op7=0x0 & Rd5 & LdMemAIICircMuC9h & $(END_PACKET) { Rd5 = sext(LdMemAIICircMuC9h); build EndPacket; } @@ -8777,9 +9165,9 @@ define pcodeop waitSameDomain; # (v4,10) memh -- "memh ( Rf32 = #U6x ) = Nt8 .new" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 1 0 1 0 1 0 1 1 1 0 1 f f f f f P P 0 0 1 t t t 1 + I I I I I I +# 1 0 1 0 1 0 1 1 1 0 1 f f f f f P P 0 0 1 t t t 1 - I I I I I I -:memh StMemRsAssignxC10h,Nreg0810 EndPacket is iclass=10 & op2127=0x5d & op1113=1 & op0607=2 & Nreg0810 & StMemRsAssignxC10h & $(END_PACKET) { +:memh StMemRsAssignxC10h,Nreg0810 EndPacket is iclass=10 & op2127=0x5d & op1113=1 & op7=1 & Nreg0810 & StMemRsAssignxC10h & $(END_PACKET) { build EndPacket; <> StMemRsAssignxC10h = Nreg0810:2; @@ -8788,14 +9176,14 @@ define pcodeop waitSameDomain; # (v4,10) memh -- "memh ( Rf32 = #U6x ) = Rt32" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 1 0 1 0 1 0 1 1 0 1 0 f f f f f P P 0 t t t t t 1 + I I I I I I +# 1 0 1 0 1 0 1 1 0 1 0 f f f f f P P 0 t t t t t 1 - I I I I I I # # (v4,10) memh -- "memh ( Rf32 = #U6x ) = Rt32.h" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 1 0 1 0 1 0 1 1 0 1 1 f f f f f P P 0 t t t t t 1 + I I I I I I +# 1 0 1 0 1 0 1 1 0 1 1 f f f f f P P 0 t t t t t 1 - I I I I I I -:memh StMemRsAssignxC10h,Rt5HL21 EndPacket is iclass=10 & op2227=0x2d & op13=0 & op0607=2 & Rt5HL21 & StMemRsAssignxC10h & $(END_PACKET) { +:memh StMemRsAssignxC10h,Rt5HL21 EndPacket is iclass=10 & op2227=0x2d & op13=0 & op7=1 & Rt5HL21 & StMemRsAssignxC10h & $(END_PACKET) { tmp:2 = Rt5HL21; build EndPacket; <> @@ -8833,9 +9221,9 @@ define pcodeop waitSameDomain; # (v4,3) memh -- "memh ( Rs32 + #u6:1 ) = #S8x" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 0 0 1 1 1 1 0 + + 0 1 s s s s s P P I i i i i i i I I I I I I I +# 0 0 1 1 1 1 0 - - 0 1 s s s s s P P I i i i i i i I I I I I I I -:memh StMemRsRelC3h,Simm16_13_0006x EndPacket is iclass=3 & op2127=0x61 & StMemRsRelC3h & Simm16_13_0006x & $(END_PACKET) { +:memh StMemRsRelC3h,Simm16_13_0006x EndPacket is iclass=3 & op2527=0x6 & op2122=0x1 & StMemRsRelC3h & Simm16_13_0006x & $(END_PACKET) { build EndPacket; <> StMemRsRelC3h = Simm16_13_0006x; @@ -8844,9 +9232,9 @@ define pcodeop waitSameDomain; # (v4,3) memh -- "memh ( Rs32 + #u6:1x ) &= Rt32" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 0 0 1 1 1 1 1 0 + 0 1 s s s s s P P 0 i i i i i i 1 0 t t t t t +# 0 0 1 1 1 1 1 0 - 0 1 s s s s s P P 0 i i i i i i 1 0 t t t t t -:memh&= StMemRsRelxC3h,ru5 EndPacket is iclass=3 & op2127=0x71 & op13=0 & op0506=2 & StMemRsRelxC3h & ru5 & $(END_PACKET) { +:memh&= StMemRsRelxC3h,ru5 EndPacket is iclass=3 & op2427=0xe & op2122=0x1 & op13=0 & op0506=2 & StMemRsRelxC3h & ru5 & $(END_PACKET) { tmp:2 = StMemRsRelxC3h & ru5:2; build EndPacket; <> @@ -8856,9 +9244,9 @@ define pcodeop waitSameDomain; # (v4,3) memh -- "memh ( Rs32 + #u6:1x ) += #U5" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 0 0 1 1 1 1 1 1 + 0 1 s s s s s P P 0 i i i i i i 0 0 I I I I I +# 0 0 1 1 1 1 1 1 - 0 1 s s s s s P P 0 i i i i i i 0 0 I I I I I -:memh+= StMemRsRelxC3h,Uimm8_0004 EndPacket is iclass=3 & op2127=0x79 & op13=0 & op0506=0 & StMemRsRelxC3h & Uimm8_0004 & $(END_PACKET) { +:memh+= StMemRsRelxC3h,Uimm8_0004 EndPacket is iclass=3 & op2427=0xf & op2122=0x1 & op13=0 & op0506=0 & StMemRsRelxC3h & Uimm8_0004 & $(END_PACKET) { tmp:2 = StMemRsRelxC3h + zext(Uimm8_0004); build EndPacket; <> @@ -8868,9 +9256,9 @@ define pcodeop waitSameDomain; # (v4,3) memh -- "memh ( Rs32 + #u6:1x ) += Rt32" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 0 0 1 1 1 1 1 0 + 0 1 s s s s s P P 0 i i i i i i 0 0 t t t t t +# 0 0 1 1 1 1 1 0 - 0 1 s s s s s P P 0 i i i i i i 0 0 t t t t t -:memh+= StMemRsRelxC3h,ru5 EndPacket is iclass=3 & op2127=0x71 & op13=0 & op0506=0 & StMemRsRelxC3h & ru5 & $(END_PACKET) { +:memh+= StMemRsRelxC3h,ru5 EndPacket is iclass=3 & op2427=0xe & op2122=0x1 & op13=0 & op0506=0 & StMemRsRelxC3h & ru5 & $(END_PACKET) { tmp:2 = StMemRsRelxC3h + ru5:2; build EndPacket; <> @@ -8880,9 +9268,9 @@ define pcodeop waitSameDomain; # (v4,3) memh -- "memh ( Rs32 + #u6:1x ) -= #U5" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 0 0 1 1 1 1 1 1 + 0 1 s s s s s P P 0 i i i i i i 0 1 I I I I I +# 0 0 1 1 1 1 1 1 - 0 1 s s s s s P P 0 i i i i i i 0 1 I I I I I -:memh-= StMemRsRelxC3h,Uimm8_0004 EndPacket is iclass=3 & op2127=0x79 & op13=0 & op0506=1 & StMemRsRelxC3h & Uimm8_0004 & $(END_PACKET) { +:memh-= StMemRsRelxC3h,Uimm8_0004 EndPacket is iclass=3 & op2427=0xf & op2122=0x1 & op13=0 & op0506=1 & StMemRsRelxC3h & Uimm8_0004 & $(END_PACKET) { tmp:2 = StMemRsRelxC3h - zext(Uimm8_0004); build EndPacket; <> @@ -8892,9 +9280,9 @@ define pcodeop waitSameDomain; # (v4,3) memh -- "memh ( Rs32 + #u6:1x ) -= Rt32" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 0 0 1 1 1 1 1 0 + 0 1 s s s s s P P 0 i i i i i i 0 1 t t t t t +# 0 0 1 1 1 1 1 0 - 0 1 s s s s s P P 0 i i i i i i 0 1 t t t t t -:memh-= StMemRsRelxC3h,ru5 EndPacket is iclass=3 & op2127=0x71 & op13=0 & op0506=1 & StMemRsRelxC3h & ru5 & $(END_PACKET) { +:memh-= StMemRsRelxC3h,ru5 EndPacket is iclass=3 & op2427=0xe & op2122=0x1 & op13=0 & op0506=1 & StMemRsRelxC3h & ru5 & $(END_PACKET) { tmp:2 = StMemRsRelxC3h - ru5:2; build EndPacket; <> @@ -8904,9 +9292,9 @@ define pcodeop waitSameDomain; # (v4,3) memh -- "memh ( Rs32 + #u6:1x ) = clrbit ( #U5 )" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 0 0 1 1 1 1 1 1 + 0 1 s s s s s P P 0 i i i i i i 1 0 I I I I I +# 0 0 1 1 1 1 1 1 - 0 1 s s s s s P P 0 i i i i i i 1 0 I I I I I -:memh StMemRsRelxC3h,ClrBit_0004h EndPacket is iclass=3 & op2127=0x79 & op13=0 & op0506=2 & StMemRsRelxC3h & ClrBit_0004h & $(END_PACKET) { +:memh StMemRsRelxC3h,ClrBit_0004h EndPacket is iclass=3 & op2427=0xf & op2122=0x1 & op13=0 & op0506=2 & StMemRsRelxC3h & ClrBit_0004h & $(END_PACKET) { tmp:2 = StMemRsRelxC3h & ClrBit_0004h; build EndPacket; <> @@ -8916,9 +9304,9 @@ define pcodeop waitSameDomain; # (v4,3) memh -- "memh ( Rs32 + #u6:1x ) = setbit ( #U5 )" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 0 0 1 1 1 1 1 1 + 0 1 s s s s s P P 0 i i i i i i 1 1 I I I I I +# 0 0 1 1 1 1 1 1 - 0 1 s s s s s P P 0 i i i i i i 1 1 I I I I I -:memh StMemRsRelxC3h,SetBit_0004h EndPacket is iclass=3 & op2127=0x79 & op13=0 & op0506=3 & StMemRsRelxC3h & SetBit_0004h & $(END_PACKET) { +:memh StMemRsRelxC3h,SetBit_0004h EndPacket is iclass=3 & op2427=0xf & op2122=0x1 & op13=0 & op0506=3 & StMemRsRelxC3h & SetBit_0004h & $(END_PACKET) { tmp:2 = StMemRsRelxC3h | SetBit_0004h; build EndPacket; <> @@ -8928,9 +9316,9 @@ define pcodeop waitSameDomain; # (v4,3) memh -- "memh ( Rs32 + #u6:1x ) |= Rt32" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 0 0 1 1 1 1 1 0 + 0 1 s s s s s P P 0 i i i i i i 1 1 t t t t t +# 0 0 1 1 1 1 1 0 - 0 1 s s s s s P P 0 i i i i i i 1 1 t t t t t -:memh|= StMemRsRelxC3h,ru5 EndPacket is iclass=3 & op2127=0x71 & op13=0 & op0506=3 & StMemRsRelxC3h & ru5 & $(END_PACKET) { +:memh|= StMemRsRelxC3h,ru5 EndPacket is iclass=3 & op2427=0xe & op2122=0x1 & op13=0 & op0506=3 & StMemRsRelxC3h & ru5 & $(END_PACKET) { tmp:2 = StMemRsRelxC3h | ru5:2; build EndPacket; <> @@ -8940,9 +9328,9 @@ define pcodeop waitSameDomain; # (v4,3) memh -- "memh ( Rs32 + Ru32 << #n2 ) = Nt8 .new" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 0 0 1 1 1 0 1 1 1 0 1 s s s s s P P n u u u u u n + + 0 1 t t t +# 0 0 1 1 1 0 1 1 1 0 1 s s s s s P P n u u u u u n - - 0 1 t t t -:memh MemRsRelShiftC3h,Nreg0002 EndPacket is iclass=3 & op2127=0x5d & op0306=1 & MemRsRelShiftC3h & Nreg0002 & $(END_PACKET) { +:memh MemRsRelShiftC3h,Nreg0002 EndPacket is iclass=3 & op2127=0x5d & op0304=1 & MemRsRelShiftC3h & Nreg0002 & $(END_PACKET) { build EndPacket; <> MemRsRelShiftC3h = Nreg0002:2; @@ -8951,14 +9339,14 @@ define pcodeop waitSameDomain; # (v4,3) memh -- "memh ( Rs32 + Ru32 << #n2 ) = Rt32" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 0 0 1 1 1 0 1 1 0 1 0 s s s s s P P n u u u u u n + + t t t t t +# 0 0 1 1 1 0 1 1 0 1 0 s s s s s P P n u u u u u n - - t t t t t # # (v4,3) memh -- "memh ( Rs32 + Ru32 << #n2 ) = Rt32.h" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 0 0 1 1 1 0 1 1 0 1 1 s s s s s P P n u u u u u n + + t t t t t +# 0 0 1 1 1 0 1 1 0 1 1 s s s s s P P n u u u u u n - - t t t t t -:memh MemRsRelShiftC3h,Ru5HL21 EndPacket is iclass=3 & op2227=0x2d & op0506=0 & MemRsRelShiftC3h & Ru5HL21 & $(END_PACKET) { +:memh MemRsRelShiftC3h,Ru5HL21 EndPacket is iclass=3 & op2227=0x2d & MemRsRelShiftC3h & Ru5HL21 & $(END_PACKET) { tmp:2 = Ru5HL21; build EndPacket; <> @@ -8996,9 +9384,9 @@ define pcodeop waitSameDomain; # (v4,10) memh -- "memh ( Rz32 ++ #s4:1 ) = Nt8 .new" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 1 0 1 0 1 0 1 1 1 0 1 z z z z z P P 0 0 1 t t t 0 i i i i + 0 + +# 1 0 1 0 1 0 1 1 1 0 1 z z z z z P P 0 0 1 t t t 0 i i i i - 0 - -:memh StMemAIS4C10h,Nreg0810 EndPacket is iclass=10 & op2127=0x5d & op1113=1 & op7=0 & op0002=0 & Nreg0810 & StMemAIS4C10h & $(END_PACKET) { +:memh StMemAIS4C10h,Nreg0810 EndPacket is iclass=10 & op2127=0x5d & op1113=1 & op7=0 & op1=0 & Nreg0810 & StMemAIS4C10h & $(END_PACKET) { build EndPacket; <> StMemAIS4C10h = Nreg0810:2; @@ -9007,9 +9395,9 @@ define pcodeop waitSameDomain; # (v4,10) memh -- "memh ( Rz32 ++ #s4:1 :circ ( Mu2 ) ) = Nt8 .new" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 1 0 1 0 1 0 0 1 1 0 1 z z z z z P P u 0 1 t t t 0 i i i i + 0 + +# 1 0 1 0 1 0 0 1 1 0 1 z z z z z P P u 0 1 t t t 0 i i i i - 0 - -:memh StMemAIS4CircMuC10h,Nreg0810 EndPacket is iclass=10 & op2127=0x4d & op1112=1 & op7=0 & op0002=0 & Nreg0810 & StMemAIS4CircMuC10h & $(END_PACKET) { +:memh StMemAIS4CircMuC10h,Nreg0810 EndPacket is iclass=10 & op2127=0x4d & op1112=1 & op7=0 & op1=0 & Nreg0810 & StMemAIS4CircMuC10h & $(END_PACKET) { build EndPacket; <> StMemAIS4CircMuC10h = Nreg0810:2; @@ -9018,14 +9406,14 @@ define pcodeop waitSameDomain; # (v4,10) memh -- "memh ( Rz32 ++ Mu2 ) = Nt8 .new" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 1 0 1 0 1 1 0 1 1 0 1 z z z z z P P u 0 1 t t t 0 + + + + + + + +# 1 0 1 0 1 1 0 1 1 0 1 z z z z z P P u 0 1 t t t 0 - - - - - - - # # (v4,10) memh -- "memh ( Rz32 ++ Mu2 :brev ) = Nt8 .new" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 1 0 1 0 1 1 1 1 1 0 1 z z z z z P P u 0 1 t t t 0 + + + + + + + +# 1 0 1 0 1 1 1 1 1 0 1 z z z z z P P u 0 1 t t t 0 - - - - - - - -:memh StMemAIMuC10h,Nreg0810 EndPacket is iclass=10 & op2627=3 & op2124=0xd & op1112=1 & op0007=0 & Nreg0810 & StMemAIMuC10h & $(END_PACKET) { +:memh StMemAIMuC10h,Nreg0810 EndPacket is iclass=10 & op2627=3 & op2124=0xd & op1112=1 & op7=0 & Nreg0810 & StMemAIMuC10h & $(END_PACKET) { build EndPacket; <> StMemAIMuC10h = Nreg0810:2; @@ -9034,9 +9422,9 @@ define pcodeop waitSameDomain; # (v4,10) memh -- "memh ( Rz32 ++I :circ ( Mu2 ) ) = Nt8 .new" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 1 0 1 0 1 0 0 1 1 0 1 z z z z z P P u 0 1 t t t 0 + + + + + 1 + +# 1 0 1 0 1 0 0 1 1 0 1 z z z z z P P u 0 1 t t t 0 - - - - - 1 - -:memh StMemAIICircMuC10h,Nreg0810 EndPacket is iclass=10 & op2127=0x4d & op1112=1 & op0007=2 & Nreg0810 & StMemAIICircMuC10h & $(END_PACKET) { +:memh StMemAIICircMuC10h,Nreg0810 EndPacket is iclass=10 & op2127=0x4d & op1112=1 & op7=0 & op1=1 & Nreg0810 & StMemAIICircMuC10h & $(END_PACKET) { build EndPacket; <> StMemAIICircMuC10h = Nreg0810:2; @@ -9045,14 +9433,14 @@ define pcodeop waitSameDomain; # (v2,10) memh -- "memh ( Rz32 ++ #s4:1 ) = Rt32" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 1 0 1 0 1 0 1 1 0 1 0 z z z z z P P 0 t t t t t 0 i i i i + 0 + +# 1 0 1 0 1 0 1 1 0 1 0 z z z z z P P 0 t t t t t 0 i i i i - 0 - # # (v2,10) memh -- "memh ( Rz32 ++ #s4:1 ) = Rt32.h" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 1 0 1 0 1 0 1 1 0 1 1 z z z z z P P 0 t t t t t 0 i i i i + 0 + +# 1 0 1 0 1 0 1 1 0 1 1 z z z z z P P 0 t t t t t 0 i i i i - 0 - -:memh StMemAIS4C10h,Rt5HL21 EndPacket is iclass=10 & op2227=0x2d & op13=0 & op7=0 & op0002=0 & Rt5HL21 & StMemAIS4C10h & $(END_PACKET) { +:memh StMemAIS4C10h^StNt24,Rt5HL21 EndPacket is iclass=10 & op2527=5 & op2223=1 & op13=0 & op7=0 & op1=0 & StNt24 & Rt5HL21 & StMemAIS4C10h & $(END_PACKET) { tmp:2 = Rt5HL21; build EndPacket; <> @@ -9062,14 +9450,14 @@ define pcodeop waitSameDomain; # (v2,10) memh -- "memh ( Rz32 ++ #s4:1 :circ ( Mu2 ) ) = Rt32" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 1 0 1 0 1 0 0 1 0 1 0 z z z z z P P u t t t t t 0 i i i i + 0 + +# 1 0 1 0 1 0 0 1 0 1 0 z z z z z P P u t t t t t 0 i i i i - 0 - # # (v2,10) memh -- "memh ( Rz32 ++ #s4:1 :circ ( Mu2 ) ) = Rt32.h" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 1 0 1 0 1 0 0 1 0 1 1 z z z z z P P u t t t t t 0 i i i i + 0 + +# 1 0 1 0 1 0 0 1 0 1 1 z z z z z P P u t t t t t 0 i i i i - 0 - -:memh StMemAIS4CircMuC10h,Rt5HL21 EndPacket is iclass=10 & op2227=0x25 & op7=0 & op0002=0 & Rt5HL21 & StMemAIS4CircMuC10h & $(END_PACKET) { +:memh StMemAIS4CircMuC10h,Rt5HL21 EndPacket is iclass=10 & op2227=0x25 & op7=0 & op1=0 & Rt5HL21 & StMemAIS4CircMuC10h & $(END_PACKET) { tmp:2 = Rt5HL21; build EndPacket; <> @@ -9089,14 +9477,14 @@ define pcodeop waitSameDomain; # (v2,10) memh -- "memh ( Rz32 ++ Mu2 :brev ) = Rt32" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 1 0 1 0 1 1 1 1 0 1 0 z z z z z P P u t t t t t 0 + + + + + + + +# 1 0 1 0 1 1 1 1 0 1 0 z z z z z P P u t t t t t 0 - - - - - - - # # (v2,10) memh -- "memh ( Rz32 ++ Mu2 :brev ) = Rt32.h" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 1 0 1 0 1 1 1 1 0 1 1 z z z z z P P u t t t t t 0 + + + + + + + +# 1 0 1 0 1 1 1 1 0 1 1 z z z z z P P u t t t t t 0 - - - - - - - -:memh StMemAIMuC10h,Rt5HL21 EndPacket is iclass=10 & op2627=3 & op2224=5 & op0007=0 & Rt5HL21 & StMemAIMuC10h & $(END_PACKET) { +:memh StMemAIMuC10h,Rt5HL21 EndPacket is iclass=10 & op2627=3 & op2224=5 & op7=0 & Rt5HL21 & StMemAIMuC10h & $(END_PACKET) { tmp:2 = Rt5HL21; build EndPacket; <> @@ -9106,14 +9494,14 @@ define pcodeop waitSameDomain; # (v2,10) memh -- "memh ( Rz32 ++I :circ ( Mu2 ) ) = Rt32" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 1 0 1 0 1 0 0 1 0 1 0 z z z z z P P u t t t t t 0 + + + + + 1 + +# 1 0 1 0 1 0 0 1 0 1 0 z z z z z P P u t t t t t 0 - - - - - 1 - # # (v2,10) memh -- "memh ( Rz32 ++I :circ ( Mu2 ) ) = Rt32.h" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 1 0 1 0 1 0 0 1 0 1 1 z z z z z P P u t t t t t 0 + + + + + 1 + +# 1 0 1 0 1 0 0 1 0 1 1 z z z z z P P u t t t t t 0 - - - - - 1 - -:memh StMemAIICircMuC10h,Rt5HL21 EndPacket is iclass=10 & op2227=0x25 & op0007=2 & Rt5HL21 & StMemAIICircMuC10h & $(END_PACKET) { +:memh StMemAIICircMuC10h,Rt5HL21 EndPacket is iclass=10 & op2227=0x25 & op7=0 & op1=1 & Rt5HL21 & StMemAIICircMuC10h & $(END_PACKET) { tmp:2 = Rt5HL21; build EndPacket; <> @@ -9151,32 +9539,34 @@ define pcodeop waitSameDomain; # (v4,9) memh -- "if ( Pt4 ) Rd32 = memh ( #u6x )" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 1 0 0 1 1 1 1 1 0 1 0 i i i i i P P 1 0 0 t t i 1 + + d d d d d +# 1 0 0 1 1 1 1 1 0 1 0 i i i i i P P 1 0 0 t t i 1 - - d d d d d # # (v4,9) memh -- "if ( ! Pt4 ) Rd32 = memh ( #u6x )" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 1 0 0 1 1 1 1 1 0 1 0 i i i i i P P 1 0 1 t t i 1 + + d d d d d +# 1 0 0 1 1 1 1 1 0 1 0 i i i i i P P 1 0 1 t t i 1 - - d d d d d # # (v4,9) memh -- "if ( Pt4 .new ) Rd32 = memh ( #u6x )" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 1 0 0 1 1 1 1 1 0 1 0 i i i i i P P 1 1 0 t t i 1 + + d d d d d +# 1 0 0 1 1 1 1 1 0 1 0 i i i i i P P 1 1 0 t t i 1 - - d d d d d # # (v4,9) memh -- "if ( ! Pt4 .new ) Rd32 = memh ( #u6x )" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 1 0 0 1 1 1 1 1 0 1 0 i i i i i P P 1 1 1 t t i 1 + + d d d d d +# 1 0 0 1 1 1 1 1 0 1 0 i i i i i P P 1 1 1 t t i 1 - - d d d d d -:memh^PuCond0910_N12_S11 rd5,LdMemAbsU6xC9h EndPacket is iclass=9 & op2127=0x7a & op13=1 & op0507=4 & rd5 & LdMemAbsU6xC9h & PuCond0910_N12_S11 & $(END_PACKET) { +:memh^PuCond0910_N12_S11 rd5,LdMemAbsU6xC9h EndPacket is iclass=9 & op2127=0x7a & op13=1 & op7=1 & rd5 & LdMemAbsU6xC9h & PuCond0910_N12_S11 & $(END_PACKET) { tmp:4 = 0; build PuCond0910_N12_S11; build EndPacket; <> + build PuCond0910_N12_S11; if (ConditionReg == 0) goto ; tmp = sext(LdMemAbsU6xC9h); <> + build PuCond0910_N12_S11; if (ConditionReg == 0) goto ; rd5 = tmp; @@ -9207,10 +9597,12 @@ define pcodeop waitSameDomain; build PuCond1112_N25_S26; build EndPacket; <> + build PuCond1112_N25_S26; if (ConditionReg == 0) goto ; tmp = sext(LdMemRsRelxC4h); <> + build PuCond1112_N25_S26; if (ConditionReg == 0) goto ; rd5 = tmp; @@ -9241,10 +9633,13 @@ define pcodeop waitSameDomain; build PuCond0910_N12_S11; build EndPacket; <> + build PuCond0910_N12_S11; if (ConditionReg == 0) goto ; tmp = sext(LdMemAIS4C9h); <> + build PuCond0910_N12_S11; + build LdMemAIS4C9h; if (ConditionReg == 0) goto ; rd5 = tmp; @@ -9275,10 +9670,12 @@ define pcodeop waitSameDomain; build PuCond0506_N25_S24; build EndPacket; <> + build PuCond0506_N25_S24; if (ConditionReg == 0) goto ; tmp = sext(MemRsRelShiftC3h); <> + build PuCond0506_N25_S24; if (ConditionReg == 0) goto ; rd5 = tmp; @@ -9287,27 +9684,28 @@ define pcodeop waitSameDomain; # (v4,10) memh -- "if ( Pv4 ) memh ( #u6x ) = Nt8 .new" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 1 0 1 0 1 1 1 1 1 0 1 + + + i i P P 0 0 1 t t t 1 i i i i 0 v v +# 1 0 1 0 1 1 1 1 1 0 1 - - - i i P P 0 0 1 t t t 1 i i i i 0 v v # # (v4,10) memh -- "if ( Pv4 .new ) memh ( #u6x ) = Nt8 .new" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 1 0 1 0 1 1 1 1 1 0 1 + + + i i P P 1 0 1 t t t 1 i i i i 0 v v +# 1 0 1 0 1 1 1 1 1 0 1 - - - i i P P 1 0 1 t t t 1 i i i i 0 v v # # (v4,10) memh -- "if ( ! Pv4 ) memh ( #u6x ) = Nt8 .new" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 1 0 1 0 1 1 1 1 1 0 1 + + + i i P P 0 0 1 t t t 1 i i i i 1 v v +# 1 0 1 0 1 1 1 1 1 0 1 - - - i i P P 0 0 1 t t t 1 i i i i 1 v v # # (v4,10) memh -- "if ( ! Pv4 .new ) memh ( #u6x ) = Nt8 .new" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 1 0 1 0 1 1 1 1 1 0 1 + + + i i P P 1 0 1 t t t 1 i i i i 1 v v +# 1 0 1 0 1 1 1 1 1 0 1 - - - i i P P 1 0 1 t t t 1 i i i i 1 v v -:memh^PuCond0001_N13_S02 StMemAbsU6xC10h,Nreg0810 EndPacket is iclass=10 & op2127=0x7d & op1820=0 & op1112=1 & op7=1 & Nreg0810 & StMemAbsU6xC10h & PuCond0001_N13_S02 & $(END_PACKET) { +:memh^PuCond0001_N13_S02 StMemAbsU6xC10h,Nreg0810 EndPacket is iclass=10 & op2127=0x7d & op1112=1 & op7=1 & Nreg0810 & StMemAbsU6xC10h & PuCond0001_N13_S02 & $(END_PACKET) { build PuCond0001_N13_S02; build EndPacket; <> + build PuCond0001_N13_S02; if (ConditionReg == 0) goto ; StMemAbsU6xC10h = Nreg0810:2; @@ -9353,11 +9751,12 @@ define pcodeop waitSameDomain; # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| # 1 0 1 0 1 1 1 1 0 1 1 - - - i i P P 1 t t t t t 1 i i i i 1 v v -:memh^PuCond0001_N13_S02 StMemAbsU6xC10h,Rt5HL21 EndPacket is iclass=10 & op2227=0x3d & op1820=0 & op7=1 & Rt5HL21 & StMemAbsU6xC10h & PuCond0001_N13_S02 & $(END_PACKET) { +:memh^PuCond0001_N13_S02 StMemAbsU6xC10h,Rt5HL21 EndPacket is iclass=10 & op2227=0x3d & op7=1 & Rt5HL21 & StMemAbsU6xC10h & PuCond0001_N13_S02 & $(END_PACKET) { tmp:2 = Rt5HL21; build PuCond0001_N13_S02; build EndPacket; <> + build PuCond0001_N13_S02; if (ConditionReg == 0) goto ; StMemAbsU6xC10h = tmp; @@ -9387,6 +9786,7 @@ define pcodeop waitSameDomain; build PuCond0506_N24_S23; build EndPacket; <> + build PuCond0506_N24_S23; if (ConditionReg == 0) goto ; StMemRsRelC3h = Simm16_13_0004x; @@ -9416,6 +9816,7 @@ define pcodeop waitSameDomain; build PuCond0001_N25_S26; build EndPacket; <> + build PuCond0001_N25_S26; if (ConditionReg == 0) goto ; StMemRsRelxC4h = Nreg0810:2; @@ -9466,6 +9867,7 @@ define pcodeop waitSameDomain; build PuCond0001_N25_S26; build EndPacket; <> + build PuCond0001_N25_S26; if (ConditionReg == 0) goto ; StMemRsRelxC4h = tmp; @@ -9495,6 +9897,7 @@ define pcodeop waitSameDomain; build PuCond0506_N25_S24; build EndPacket; <> + build PuCond0506_N25_S24; if (ConditionReg == 0) goto ; MemRsRelShiftC3h = Nreg0002:2; @@ -9545,6 +9948,7 @@ define pcodeop waitSameDomain; build PuCond0506_N25_S24; build EndPacket; <> + build PuCond0506_N25_S24; if (ConditionReg == 0) goto ; MemRsRelShiftC3h = tmp; @@ -9574,6 +9978,8 @@ define pcodeop waitSameDomain; build PuCond0001_N07_S02; build EndPacket; <> + build PuCond0001_N07_S02; + build StMemAIS4C10h; if (ConditionReg == 0) goto ; StMemAIS4C10h = Nreg0810:2; @@ -9620,11 +10026,13 @@ define pcodeop waitSameDomain; # 1 0 1 0 1 0 1 1 0 1 1 z z z z z P P 1 t t t t t 0 i i i i 1 v v # -:memh^PuCond0001_N07_S02 StMemAIS4C10h,Rt5HL21 EndPacket is iclass=10 & op2227=0x2d & op13=1 & Rt5HL21 & StMemAIS4C10h & PuCond0001_N07_S02 & $(END_PACKET) [ cond=1; ] { +:memh^PuCond0001_N07_S02 StMemAIS4C10h^StNt24,Rt5HL21 EndPacket is iclass=10 & op2527=5 & op2223=1 & op13=1 & StNt24 & Rt5HL21 & StMemAIS4C10h & PuCond0001_N07_S02 & $(END_PACKET) [ cond=1; ] { tmp:2 = Rt5HL21; build PuCond0001_N07_S02; build EndPacket; <> + build PuCond0001_N07_S02; + build StMemAIS4C10h; if (ConditionReg == 0) goto ; StMemAIS4C10h = tmp; @@ -9633,9 +10041,9 @@ define pcodeop waitSameDomain; # (v4,9) memh_fifo -- "Ryy32 = memh_fifo ( Rf32 = #U6x )" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 1 0 0 1 1 0 1 0 0 1 0 f f f f f P P 0 1 I I I I + I I y y y y y +# 1 0 0 1 1 0 1 0 0 1 0 f f f f f P P 0 1 I I I I - I I y y y y y -:memh_fifo Rdd5,LdMemRsAssignxC9h EndPacket is iclass=9 & op2127=0x52 & op1213=1 & op7=0 & LdMemRsAssignxC9h & Rdd5 & $(END_PACKET) { +:memh_fifo Rdd5,LdMemRsAssignxC9h EndPacket is iclass=9 & op2127=0x52 & op1213=1 & LdMemRsAssignxC9h & Rdd5 & $(END_PACKET) { local tmp_hword = LdMemRsAssignxC9h; Rdd5 = (Rdd5 >> 16) | (zext(tmp_hword) << 48); build EndPacket; @@ -9666,9 +10074,9 @@ define pcodeop waitSameDomain; # (v4,9) memh_fifo -- "Ryy32 = memh_fifo ( Rz32 ++ #s4:1 )" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 1 0 0 1 1 0 1 0 0 1 0 z z z z z P P 0 0 + + + i i i i y y y y y +# 1 0 0 1 1 0 1 0 0 1 0 z z z z z P P 0 0 - - - i i i i y y y y y -:memh_fifo Rdd5,LdMemAIS4C9h EndPacket is iclass=9 & op2127=0x52 & op0913=0 & LdMemAIS4C9h & Rdd5 & $(END_PACKET) { +:memh_fifo Rdd5,LdMemAIS4C9h EndPacket is iclass=9 & op2127=0x52 & op1213=0 & LdMemAIS4C9h & Rdd5 & $(END_PACKET) { local tmp_hword = LdMemAIS4C9h; Rdd5 = (Rdd5 >> 16) | (zext(tmp_hword) << 48); build EndPacket; @@ -9677,9 +10085,9 @@ define pcodeop waitSameDomain; # (v4,9) memh_fifo -- "Ryy32 = memh_fifo ( Rz32 ++ #s4:1 :circ ( Mu2 ) )" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 1 0 0 1 1 0 0 0 0 1 0 z z z z z P P u 0 + + 0 i i i i y y y y y +# 1 0 0 1 1 0 0 0 0 1 0 z z z z z P P u 0 - - 0 i i i i y y y y y -:memh_fifo Rdd5,LdMemAIS4CircMuC9h EndPacket is iclass=9 & op2127=0x42 & op0912=0 & LdMemAIS4CircMuC9h & Rdd5 & $(END_PACKET) { +:memh_fifo Rdd5,LdMemAIS4CircMuC9h EndPacket is iclass=9 & op2127=0x42 & op12=0 & i9=0 & LdMemAIS4CircMuC9h & Rdd5 & $(END_PACKET) { local tmp_hword = LdMemAIS4CircMuC9h; Rdd5 = (Rdd5 >> 16) | (zext(tmp_hword) << 48); build EndPacket; @@ -9688,14 +10096,14 @@ define pcodeop waitSameDomain; # (v4,9) memh_fifo -- "Ryy32 = memh_fifo ( Rz32 ++ Mu2 )" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 1 0 0 1 1 1 0 0 0 1 0 z z z z z P P u 0 + + + + 0 + + y y y y y +# 1 0 0 1 1 1 0 0 0 1 0 z z z z z P P u 0 - - - - 0 - - y y y y y # # (v4,9) memh_fifo -- "Ryy32 = memh_fifo ( Rz32 ++ Mu2 :brev )" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 1 0 0 1 1 1 1 0 0 1 0 z z z z z P P u 0 + + + + 0 + + y y y y y +# 1 0 0 1 1 1 1 0 0 1 0 z z z z z P P u 0 - - - - 0 - - y y y y y -:memh_fifo Rdd5,LdMemAIMuC9h EndPacket is iclass=9 & op2627=3 & op2124=2 & op0512=0 & LdMemAIMuC9h & Rdd5 & $(END_PACKET) { +:memh_fifo Rdd5,LdMemAIMuC9h EndPacket is iclass=9 & op2627=3 & op2124=2 & op12=0 & op7=0 & LdMemAIMuC9h & Rdd5 & $(END_PACKET) { local tmp_hword = LdMemAIMuC9h; Rdd5 = (Rdd5 >> 16) | (zext(tmp_hword) << 48); build EndPacket; @@ -9704,9 +10112,9 @@ define pcodeop waitSameDomain; # (v4,9) memh_fifo -- "Ryy32 = memh_fifo ( Rz32 ++I :circ ( Mu2 ) )" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 1 0 0 1 1 0 0 0 0 1 0 z z z z z P P u 0 + + 1 + 0 + + y y y y y +# 1 0 0 1 1 0 0 0 0 1 0 z z z z z P P u 0 - - 1 - 0 - - y y y y y -:memh_fifo Rdd5,LdMemAIICircMuC9h EndPacket is iclass=9 & op2127=0x42 & op0512=0x10 & LdMemAIICircMuC9h & Rdd5 & $(END_PACKET) { +:memh_fifo Rdd5,LdMemAIICircMuC9h EndPacket is iclass=9 & op2127=0x42 & op12=0x0 & i9=0x1 & op7=0x0 & LdMemAIICircMuC9h & Rdd5 & $(END_PACKET) { local tmp_hword = LdMemAIICircMuC9h; Rdd5 = (Rdd5 >> 16) | (zext(tmp_hword) << 48); build EndPacket; @@ -9715,9 +10123,9 @@ define pcodeop waitSameDomain; # (v4,9) memub -- "Rd32 = memub ( Rf32 = #U6x )" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 1 0 0 1 1 0 1 1 0 0 1 f f f f f P P 0 1 I I I I + I I d d d d d +# 1 0 0 1 1 0 1 1 0 0 1 f f f f f P P 0 1 I I I I - I I d d d d d -:memub Rd5,LdMemRsAssignxC9b EndPacket is iclass=9 & op2127=0x59 & op1213=1 & op7=0 & Rd5 & LdMemRsAssignxC9b & $(END_PACKET) { +:memub Rd5,LdMemRsAssignxC9b EndPacket is iclass=9 & op2127=0x59 & op1213=1 & Rd5 & LdMemRsAssignxC9b & $(END_PACKET) { Rd5 = zext(LdMemRsAssignxC9b); build EndPacket; } @@ -9735,9 +10143,9 @@ define pcodeop waitSameDomain; # (v4,3) memub -- "Rd32 = memub ( Rs32 + Rt32 << #n2 )" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 0 0 1 1 1 0 1 0 0 0 1 s s s s s P P n t t t t t n + + d d d d d +# 0 0 1 1 1 0 1 0 0 0 1 s s s s s P P n t t t t t n - - d d d d d -:memub Rd5,MemRsRelShiftC3b EndPacket is iclass=3 & op2127=0x51 & op0506=0 & Rd5 & MemRsRelShiftC3b & $(END_PACKET) { +:memub Rd5,MemRsRelShiftC3b EndPacket is iclass=3 & op2127=0x51 & Rd5 & MemRsRelShiftC3b & $(END_PACKET) { Rd5 = zext(MemRsRelShiftC3b); build EndPacket; } @@ -9755,9 +10163,9 @@ define pcodeop waitSameDomain; # (v2,9) memub -- "Rd32 = memub ( Rz32 ++ #s4:0 )" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 1 0 0 1 1 0 1 1 0 0 1 z z z z z P P 0 0 + + + i i i i d d d d d +# 1 0 0 1 1 0 1 1 0 0 1 z z z z z P P 0 0 - - - i i i i d d d d d -:memub Rd5,LdMemAIS4C9b0 EndPacket is iclass=9 & op2127=0x59 & op0913=0 & Rd5 & LdMemAIS4C9b0 & $(END_PACKET) { +:memub Rd5,LdMemAIS4C9b0 EndPacket is iclass=9 & op2127=0x59 & op1213=0 & Rd5 & LdMemAIS4C9b0 & $(END_PACKET) { Rd5 = zext(LdMemAIS4C9b0); build EndPacket; } @@ -9765,9 +10173,9 @@ define pcodeop waitSameDomain; # (v2,9) memub -- "Rd32 = memub ( Rz32 ++ #s4:0 :circ ( Mu2 ) )" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 1 0 0 1 1 0 0 1 0 0 1 z z z z z P P u 0 + + 0 i i i i d d d d d +# 1 0 0 1 1 0 0 1 0 0 1 z z z z z P P u 0 - - 0 i i i i d d d d d -:memub Rd5,LdMemAIS4CircMuC9b0 EndPacket is iclass=9 & op2127=0x49 & op0912=0 & Rd5 & LdMemAIS4CircMuC9b0 & $(END_PACKET) { +:memub Rd5,LdMemAIS4CircMuC9b0 EndPacket is iclass=9 & op2127=0x49 & op12=0 & i9=0 & Rd5 & LdMemAIS4CircMuC9b0 & $(END_PACKET) { Rd5 = zext(LdMemAIS4CircMuC9b0); build EndPacket; } @@ -9775,14 +10183,14 @@ define pcodeop waitSameDomain; # (v2,9) memub -- "Rd32 = memub ( Rz32 ++ Mu2 )" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 1 0 0 1 1 1 0 1 0 0 1 z z z z z P P u 0 + + + + 0 + + d d d d d +# 1 0 0 1 1 1 0 1 0 0 1 z z z z z P P u 0 - - - - 0 - - d d d d d # # (v2,9) memub -- "Rd32 = memub ( Rz32 ++ Mu2 :brev )" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 1 0 0 1 1 1 1 1 0 0 1 z z z z z P P u 0 + + + + 0 + + d d d d d +# 1 0 0 1 1 1 1 1 0 0 1 z z z z z P P u 0 - - - - 0 - - d d d d d -:memub Rd5,LdMemAIMuC9b EndPacket is iclass=9 & op2627=3 & op2124=9 & op0512=0 & Rd5 & LdMemAIMuC9b & $(END_PACKET) { +:memub Rd5,LdMemAIMuC9b EndPacket is iclass=9 & op2627=3 & op2124=9 & op12=0 & op7=0 & Rd5 & LdMemAIMuC9b & $(END_PACKET) { Rd5 = zext(LdMemAIMuC9b); build EndPacket; } @@ -9790,9 +10198,9 @@ define pcodeop waitSameDomain; # (v2,9) memub -- "Rd32 = memub ( Rz32 ++I :circ ( Mu2 ) )" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 1 0 0 1 1 0 0 1 0 0 1 z z z z z P P u 0 + + 1 + 0 + + d d d d d +# 1 0 0 1 1 0 0 1 0 0 1 z z z z z P P u 0 - - 1 - 0 - - d d d d d -:memub Rd5,LdMemAIICircMuC9b EndPacket is iclass=9 & op2127=0x49 & op0512=0x10 & Rd5 & LdMemAIICircMuC9b & $(END_PACKET) { +:memub Rd5,LdMemAIICircMuC9b EndPacket is iclass=9 & op2127=0x49 & op12=0x0 & i9=0x1 & op7=0x0 & Rd5 & LdMemAIICircMuC9b & $(END_PACKET) { Rd5 = zext(LdMemAIICircMuC9b); build EndPacket; } @@ -9810,32 +10218,34 @@ define pcodeop waitSameDomain; # (v4,9) memub -- "if ( Pt4 ) Rd32 = memub ( #u6x )" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 1 0 0 1 1 1 1 1 0 0 1 i i i i i P P 1 0 0 t t i 1 + + d d d d d +# 1 0 0 1 1 1 1 1 0 0 1 i i i i i P P 1 0 0 t t i 1 - - d d d d d # # (v4,9) memub -- "if ( ! Pt4 ) Rd32 = memub ( #u6x )" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 1 0 0 1 1 1 1 1 0 0 1 i i i i i P P 1 0 1 t t i 1 + + d d d d d +# 1 0 0 1 1 1 1 1 0 0 1 i i i i i P P 1 0 1 t t i 1 - - d d d d d # # (v4,9) memub -- "if ( Pt4 .new ) Rd32 = memub ( #u6x )" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 1 0 0 1 1 1 1 1 0 0 1 i i i i i P P 1 1 0 t t i 1 + + d d d d d +# 1 0 0 1 1 1 1 1 0 0 1 i i i i i P P 1 1 0 t t i 1 - - d d d d d # # (v4,9) memub -- "if ( ! Pt4 .new ) Rd32 = memub ( #u6x )" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 1 0 0 1 1 1 1 1 0 0 1 i i i i i P P 1 1 1 t t i 1 + + d d d d d +# 1 0 0 1 1 1 1 1 0 0 1 i i i i i P P 1 1 1 t t i 1 - - d d d d d -:memub^PuCond0910_N12_S11 rd5,LdMemAbsU6xC9b EndPacket is iclass=9 & op2127=0x79 & op13=1 & op0507=4 & rd5 & LdMemAbsU6xC9b & PuCond0910_N12_S11 & $(END_PACKET) { +:memub^PuCond0910_N12_S11 rd5,LdMemAbsU6xC9b EndPacket is iclass=9 & op2127=0x79 & op13=1 & op7=1 & rd5 & LdMemAbsU6xC9b & PuCond0910_N12_S11 & $(END_PACKET) { tmp:4 = 0; build PuCond0910_N12_S11; build EndPacket; <> + build PuCond0910_N12_S11; if (ConditionReg == 0) goto ; tmp = zext(LdMemAbsU6xC9b); <> + build PuCond0910_N12_S11; if (ConditionReg == 0) goto ; rd5 = tmp; @@ -9866,10 +10276,12 @@ define pcodeop waitSameDomain; build PuCond1112_N25_S26; build EndPacket; <> + build PuCond1112_N25_S26; if (ConditionReg == 0) goto ; tmp = zext(LdMemRsRelxC4b); <> + build PuCond1112_N25_S26; if (ConditionReg == 0) goto ; rd5 = tmp; @@ -9900,10 +10312,13 @@ define pcodeop waitSameDomain; build PuCond0910_N12_S11; build EndPacket; <> + build PuCond0910_N12_S11; if (ConditionReg == 0) goto ; tmp = zext(LdMemAIS4C9b0); <> + build PuCond0910_N12_S11; + build LdMemAIS4C9b0; if (ConditionReg == 0) goto ; rd5 = tmp; @@ -9934,10 +10349,12 @@ define pcodeop waitSameDomain; build PuCond0506_N25_S24; build EndPacket; <> + build PuCond0506_N25_S24; if (ConditionReg == 0) goto ; tmp = zext(MemRsRelShiftC3b); <> + build PuCond0506_N25_S24; if (ConditionReg == 0) goto ; rd5 = tmp; @@ -9946,7 +10363,7 @@ define pcodeop waitSameDomain; # (v4,9) memubh -- "Rd32 = memubh ( Rf32 = #U6x )" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 1 0 0 1 1 0 1 0 0 1 1 f f f f f P P 0 1 I I I I + I I d d d d d +# 1 0 0 1 1 0 1 0 0 1 1 f f f f f P P 0 1 I I I I - I I d d d d d macro unpack16to32(src2, dest4) { hi:2 = src2 & 0xff00; @@ -9954,7 +10371,7 @@ macro unpack16to32(src2, dest4) { dest4 = (zext(hi) << 8) + zext(lo); } -:memubh Rd5,LdMemRsAssignxC9h EndPacket is iclass=9 & op2127=0x53 & op1213=1 & op7=0 & Rd5 & LdMemRsAssignxC9h & $(END_PACKET) { +:memubh Rd5,LdMemRsAssignxC9h EndPacket is iclass=9 & op2127=0x53 & op1213=1 & Rd5 & LdMemRsAssignxC9h & $(END_PACKET) { unpack16to32(LdMemRsAssignxC9h, Rd5); build EndPacket; } @@ -9982,9 +10399,9 @@ macro unpack16to32(src2, dest4) { # (v2,9) memubh -- "Rd32 = memubh ( Rz32 ++ #s4:1 )" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 1 0 0 1 1 0 1 0 0 1 1 z z z z z P P 0 0 + + + i i i i d d d d d +# 1 0 0 1 1 0 1 0 0 1 1 z z z z z P P 0 0 - - - i i i i d d d d d -:memubh Rd5,LdMemAIS4C9h EndPacket is iclass=9 & op2127=0x53 & op0913=0 & Rd5 & LdMemAIS4C9h & $(END_PACKET) { +:memubh Rd5,LdMemAIS4C9h EndPacket is iclass=9 & op2127=0x53 & op1213=0 & Rd5 & LdMemAIS4C9h & $(END_PACKET) { unpack16to32(LdMemAIS4C9h, Rd5); build EndPacket; } @@ -9992,9 +10409,9 @@ macro unpack16to32(src2, dest4) { # (v2,9) memubh -- "Rd32 = memubh ( Rz32 ++ #s4:1 :circ ( Mu2 ) )" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 1 0 0 1 1 0 0 0 0 1 1 z z z z z P P u 0 + + 0 i i i i d d d d d +# 1 0 0 1 1 0 0 0 0 1 1 z z z z z P P u 0 - - 0 i i i i d d d d d -:memubh Rd5,LdMemAIS4CircMuC9h EndPacket is iclass=9 & op2127=0x43 & op0912=0 & Rd5 & LdMemAIS4CircMuC9h & $(END_PACKET) { +:memubh Rd5,LdMemAIS4CircMuC9h EndPacket is iclass=9 & op2127=0x43 & op12=0 & i9=0 & Rd5 & LdMemAIS4CircMuC9h & $(END_PACKET) { unpack16to32(LdMemAIS4CircMuC9h, Rd5); build EndPacket; } @@ -10002,14 +10419,14 @@ macro unpack16to32(src2, dest4) { # (v2,9) memubh -- "Rd32 = memubh ( Rz32 ++ Mu2 )" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 1 0 0 1 1 1 0 0 0 1 1 z z z z z P P u 0 + + + + 0 + + d d d d d +# 1 0 0 1 1 1 0 0 0 1 1 z z z z z P P u 0 - - - - 0 - - d d d d d # # (v2,9) memubh -- "Rd32 = memubh ( Rz32 ++ Mu2 :brev )" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 1 0 0 1 1 1 1 0 0 1 1 z z z z z P P u 0 + + + + 0 + + d d d d d +# 1 0 0 1 1 1 1 0 0 1 1 z z z z z P P u 0 - - - - 0 - - d d d d d -:memubh Rd5,LdMemAIMuC9h EndPacket is iclass=9 & op2627=3 & op2124=0x3 & op0512=0 & Rd5 & LdMemAIMuC9h & $(END_PACKET) { +:memubh Rd5,LdMemAIMuC9h EndPacket is iclass=9 & op2627=3 & op2124=0x3 & op12=0 & op7=0 & Rd5 & LdMemAIMuC9h & $(END_PACKET) { unpack16to32(LdMemAIMuC9h, Rd5); build EndPacket; } @@ -10017,9 +10434,9 @@ macro unpack16to32(src2, dest4) { # (v2,9) memubh -- "Rd32 = memubh ( Rz32 ++I :circ ( Mu2 ) )" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 1 0 0 1 1 0 0 0 0 1 1 z z z z z P P u 0 + + 1 + 0 + + d d d d d +# 1 0 0 1 1 0 0 0 0 1 1 z z z z z P P u 0 - - 1 - 0 - - d d d d d -:memubh Rd5,LdMemAIICircMuC9h EndPacket is iclass=9 & op2127=0x43 & op0512=0x10 & Rd5 & LdMemAIICircMuC9h & $(END_PACKET) { +:memubh Rd5,LdMemAIICircMuC9h EndPacket is iclass=9 & op2127=0x43 & op12=0x0 & i9=0x1 & op7=0x0 & Rd5 & LdMemAIICircMuC9h & $(END_PACKET) { unpack16to32(LdMemAIICircMuC9h, Rd5); build EndPacket; } @@ -10027,17 +10444,17 @@ macro unpack16to32(src2, dest4) { # (v4,9) memubh -- "Rdd32 = memubh ( Rf32 = #U6x )" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 1 0 0 1 1 0 1 0 1 0 1 f f f f f P P 0 1 I I I I + I I d d d d d +# 1 0 0 1 1 0 1 0 1 0 1 f f f f f P P 0 1 I I I I - I I d d d d d macro unpack32to64(src4, dest8) { hi0:4 = src4 & 0x0000ff00; lo0:4 = src4 & 0x000000ff; hi1:4 = src4 & 0xff000000; lo1:4 = src4 & 0x00ff0000; - dest8 = (zext(hi1) << 32) + (zext(lo1) << 16) + (zext(hi0) << 8) + zext(lo0); + dest8 = (zext(hi1) << 48) + (zext(lo1) << 32) + (zext(hi0) << 16) + zext(lo0); } -:memubh Rdd5,LdMemRsAssignxC9w EndPacket is iclass=9 & op2127=0x55 & op1213=1 & op7=0 & Rdd5 & LdMemRsAssignxC9w & $(END_PACKET) { +:memubh Rdd5,LdMemRsAssignxC9w EndPacket is iclass=9 & op2127=0x55 & op1213=1 & Rdd5 & LdMemRsAssignxC9w & $(END_PACKET) { unpack32to64(LdMemRsAssignxC9w, Rdd5); build EndPacket; } @@ -10065,9 +10482,9 @@ macro unpack32to64(src4, dest8) { # (v2,9) memubh -- "Rdd32 = memubh ( Rz32 ++ #s4:2 )" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 1 0 0 1 1 0 1 0 1 0 1 z z z z z P P 0 0 + + + i i i i d d d d d +# 1 0 0 1 1 0 1 0 1 0 1 z z z z z P P 0 0 - - - i i i i d d d d d -:memubh Rdd5,LdMemAIS4C9w EndPacket is iclass=9 & op2127=0x55 & op0913=0 & Rdd5 & LdMemAIS4C9w & $(END_PACKET) { +:memubh Rdd5,LdMemAIS4C9w EndPacket is iclass=9 & op2127=0x55 & op1213=0 & Rdd5 & LdMemAIS4C9w & $(END_PACKET) { unpack32to64(LdMemAIS4C9w, Rdd5); build EndPacket; } @@ -10075,9 +10492,9 @@ macro unpack32to64(src4, dest8) { # (v2,9) memubh -- "Rdd32 = memubh ( Rz32 ++ #s4:2 :circ ( Mu2 ) )" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 1 0 0 1 1 0 0 0 1 0 1 z z z z z P P u 0 + + 0 i i i i d d d d d +# 1 0 0 1 1 0 0 0 1 0 1 z z z z z P P u 0 - - 0 i i i i d d d d d -:memubh Rdd5,LdMemAIS4CircMuC9w EndPacket is iclass=9 & op2127=0x45 & op0912=0 & Rdd5 & LdMemAIS4CircMuC9w & $(END_PACKET) { +:memubh Rdd5,LdMemAIS4CircMuC9w EndPacket is iclass=9 & op2127=0x45 & op12=0 & i9=0 & Rdd5 & LdMemAIS4CircMuC9w & $(END_PACKET) { unpack32to64(LdMemAIS4CircMuC9w, Rdd5); build EndPacket; } @@ -10085,14 +10502,14 @@ macro unpack32to64(src4, dest8) { # (v2,9) memubh -- "Rdd32 = memubh ( Rz32 ++ Mu2 )" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 1 0 0 1 1 1 0 0 1 0 1 z z z z z P P u 0 + + + + 0 + + d d d d d +# 1 0 0 1 1 1 0 0 1 0 1 z z z z z P P u 0 - - - - 0 - - d d d d d # # (v2,9) memubh -- "Rdd32 = memubh ( Rz32 ++ Mu2 :brev )" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 1 0 0 1 1 1 1 0 1 0 1 z z z z z P P u 0 + + + + 0 + + d d d d d +# 1 0 0 1 1 1 1 0 1 0 1 z z z z z P P u 0 - - - - 0 - - d d d d d -:memubh Rdd5,LdMemAIMuC9w EndPacket is iclass=9 & op2627=3 & op2124=0x5 & op0512=0 & Rdd5 & LdMemAIMuC9w & $(END_PACKET) { +:memubh Rdd5,LdMemAIMuC9w EndPacket is iclass=9 & op2627=3 & op2124=0x5 & op12=0 & op7=0 & Rdd5 & LdMemAIMuC9w & $(END_PACKET) { unpack32to64(LdMemAIMuC9w, Rdd5); build EndPacket; } @@ -10100,9 +10517,9 @@ macro unpack32to64(src4, dest8) { # (v2,9) memubh -- "Rdd32 = memubh ( Rz32 ++I :circ ( Mu2 ) )" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 1 0 0 1 1 0 0 0 1 0 1 z z z z z P P u 0 + + 1 + 0 + + d d d d d +# 1 0 0 1 1 0 0 0 1 0 1 z z z z z P P u 0 - - 1 - 0 - - d d d d d -:memubh Rdd5,LdMemAIICircMuC9w EndPacket is iclass=9 & op2127=0x45 & op0512=0x10 & Rdd5 & LdMemAIICircMuC9w & $(END_PACKET) { +:memubh Rdd5,LdMemAIICircMuC9w EndPacket is iclass=9 & op2127=0x45 & op12=0x0 & i9=0x1 & op7=0x0 & Rdd5 & LdMemAIICircMuC9w & $(END_PACKET) { unpack32to64(LdMemAIICircMuC9w, Rdd5); build EndPacket; } @@ -10110,9 +10527,9 @@ macro unpack32to64(src4, dest8) { # (v4,9) memuh -- "Rd32 = memuh ( Rf32 = #U6x )" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 1 0 0 1 1 0 1 1 0 1 1 f f f f f P P 0 1 I I I I + I I d d d d d +# 1 0 0 1 1 0 1 1 0 1 1 f f f f f P P 0 1 I I I I - I I d d d d d -:memuh Rd5,LdMemRsAssignxC9h EndPacket is iclass=9 & op2127=0x5b & op1213=1 & op7=0 & Rd5 & LdMemRsAssignxC9h & $(END_PACKET) { +:memuh Rd5,LdMemRsAssignxC9h EndPacket is iclass=9 & op2127=0x5b & op1213=1 & Rd5 & LdMemRsAssignxC9h & $(END_PACKET) { Rd5 = zext(LdMemRsAssignxC9h); build EndPacket; } @@ -10130,9 +10547,9 @@ macro unpack32to64(src4, dest8) { # (v4,3) memuh -- "Rd32 = memuh ( Rs32 + Rt32 << #n2 )" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 0 0 1 1 1 0 1 0 0 1 1 s s s s s P P n t t t t t n + + d d d d d +# 0 0 1 1 1 0 1 0 0 1 1 s s s s s P P n t t t t t n - - d d d d d -:memuh Rd5,MemRsRelShiftC3h EndPacket is iclass=3 & op2127=0x53 & op0506=0 & Rd5 & MemRsRelShiftC3h & $(END_PACKET) { +:memuh Rd5,MemRsRelShiftC3h EndPacket is iclass=3 & op2127=0x53 & Rd5 & MemRsRelShiftC3h & $(END_PACKET) { Rd5 = zext(MemRsRelShiftC3h); build EndPacket; } @@ -10150,9 +10567,9 @@ macro unpack32to64(src4, dest8) { # (v2,9) memuh -- "Rd32 = memuh ( Rz32 ++ #s4:1 )" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 1 0 0 1 1 0 1 1 0 1 1 z z z z z P P 0 0 + + + i i i i d d d d d +# 1 0 0 1 1 0 1 1 0 1 1 z z z z z P P 0 0 - - - i i i i d d d d d -:memuh Rd5,LdMemAIS4C9h EndPacket is iclass=9 & op2127=0x5b & op0913=0 & Rd5 & LdMemAIS4C9h & $(END_PACKET) { +:memuh Rd5,LdMemAIS4C9h EndPacket is iclass=9 & op2127=0x5b & op1213=0 & Rd5 & LdMemAIS4C9h & $(END_PACKET) { Rd5 = zext(LdMemAIS4C9h); build EndPacket; } @@ -10160,9 +10577,9 @@ macro unpack32to64(src4, dest8) { # (v2,9) memuh -- "Rd32 = memuh ( Rz32 ++ #s4:1 :circ ( Mu2 ) )" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 1 0 0 1 1 0 0 1 0 1 1 z z z z z P P u 0 + + 0 i i i i d d d d d +# 1 0 0 1 1 0 0 1 0 1 1 z z z z z P P u 0 - - 0 i i i i d d d d d -:memuh Rd5,LdMemAIS4CircMuC9h EndPacket is iclass=9 & op2127=0x4b & op0912=0 & Rd5 & LdMemAIS4CircMuC9h & $(END_PACKET) { +:memuh Rd5,LdMemAIS4CircMuC9h EndPacket is iclass=9 & op2127=0x4b & op12=0 & i9=0 & Rd5 & LdMemAIS4CircMuC9h & $(END_PACKET) { Rd5 = zext(LdMemAIS4CircMuC9h); build EndPacket; } @@ -10170,14 +10587,14 @@ macro unpack32to64(src4, dest8) { # (v2,9) memuh -- "Rd32 = memuh ( Rz32 ++ Mu2 )" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 1 0 0 1 1 1 0 1 0 1 1 z z z z z P P u 0 + + + + 0 + + d d d d d +# 1 0 0 1 1 1 0 1 0 1 1 z z z z z P P u 0 - - - - 0 - - d d d d d # # (v2,9) memuh -- "Rd32 = memuh ( Rz32 ++ Mu2 :brev )" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 1 0 0 1 1 1 1 1 0 1 1 z z z z z P P u 0 + + + + 0 + + d d d d d +# 1 0 0 1 1 1 1 1 0 1 1 z z z z z P P u 0 - - - - 0 - - d d d d d -:memuh Rd5,LdMemAIMuC9h EndPacket is iclass=9 & op2627=3 & op2124=0xb & op0512=0 & Rd5 & LdMemAIMuC9h & $(END_PACKET) { +:memuh Rd5,LdMemAIMuC9h EndPacket is iclass=9 & op2627=3 & op2124=0xb & op12=0 & op7=0 & Rd5 & LdMemAIMuC9h & $(END_PACKET) { Rd5 = zext(LdMemAIMuC9h); build EndPacket; } @@ -10185,9 +10602,9 @@ macro unpack32to64(src4, dest8) { # (v2,9) memuh -- "Rd32 = memuh ( Rz32 ++I :circ ( Mu2 ) )" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 1 0 0 1 1 0 0 1 0 1 1 z z z z z P P u 0 + + 1 + 0 + + d d d d d +# 1 0 0 1 1 0 0 1 0 1 1 z z z z z P P u 0 - - 1 - 0 - - d d d d d -:memuh Rd5,LdMemAIICircMuC9h EndPacket is iclass=9 & op2127=0x4b & op0512=0x10 & Rd5 & LdMemAIICircMuC9h & $(END_PACKET) { +:memuh Rd5,LdMemAIICircMuC9h EndPacket is iclass=9 & op2127=0x4b & op12=0x0 & i9=0x1 & op7=0x0 & Rd5 & LdMemAIICircMuC9h & $(END_PACKET) { Rd5 = zext(LdMemAIICircMuC9h); build EndPacket; } @@ -10205,32 +10622,34 @@ macro unpack32to64(src4, dest8) { # (v4,9) memuh -- "if ( Pt4 ) Rd32 = memuh ( #u6x )" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 1 0 0 1 1 1 1 1 0 1 1 i i i i i P P 1 0 0 t t i 1 + + d d d d d +# 1 0 0 1 1 1 1 1 0 1 1 i i i i i P P 1 0 0 t t i 1 - - d d d d d # # (v4,9) memuh -- "if ( ! Pt4 ) Rd32 = memuh ( #u6x )" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 1 0 0 1 1 1 1 1 0 1 1 i i i i i P P 1 0 1 t t i 1 + + d d d d d +# 1 0 0 1 1 1 1 1 0 1 1 i i i i i P P 1 0 1 t t i 1 - - d d d d d # # (v4,9) memuh -- "if ( Pt4 .new ) Rd32 = memuh ( #u6x )" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 1 0 0 1 1 1 1 1 0 1 1 i i i i i P P 1 1 0 t t i 1 + + d d d d d +# 1 0 0 1 1 1 1 1 0 1 1 i i i i i P P 1 1 0 t t i 1 - - d d d d d # # (v4,9) memuh -- "if ( ! Pt4 .new ) Rd32 = memuh ( #u6x )" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 1 0 0 1 1 1 1 1 0 1 1 i i i i i P P 1 1 1 t t i 1 + + d d d d d +# 1 0 0 1 1 1 1 1 0 1 1 i i i i i P P 1 1 1 t t i 1 - - d d d d d -:memuh^PuCond0910_N12_S11 rd5,LdMemU6xC9h EndPacket is iclass=9 & op2127=0x7b & op13=1 & op0507=4 & rd5 & LdMemU6xC9h & PuCond0910_N12_S11 & $(END_PACKET) { +:memuh^PuCond0910_N12_S11 rd5,LdMemU6xC9h EndPacket is iclass=9 & op2127=0x7b & op13=1 & op7=1 & rd5 & LdMemU6xC9h & PuCond0910_N12_S11 & $(END_PACKET) { tmp:4 = 0; build PuCond0910_N12_S11; build EndPacket; <> + build PuCond0910_N12_S11; if (ConditionReg == 0) goto ; tmp = zext(LdMemU6xC9h); <> + build PuCond0910_N12_S11; if (ConditionReg == 0) goto ; rd5 = tmp; @@ -10261,10 +10680,12 @@ macro unpack32to64(src4, dest8) { build PuCond1112_N25_S26; build EndPacket; <> + build PuCond1112_N25_S26; if (ConditionReg == 0) goto ; tmp = zext(LdMemRsRelxC4h); <> + build PuCond1112_N25_S26; if (ConditionReg == 0) goto ; rd5 = tmp; @@ -10295,10 +10716,13 @@ macro unpack32to64(src4, dest8) { build PuCond0910_N12_S11; build EndPacket; <> + build PuCond0910_N12_S11; if (ConditionReg == 0) goto ; tmp = zext(LdMemAIS4C9h); <> + build PuCond0910_N12_S11; + build LdMemAIS4C9h; if (ConditionReg == 0) goto ; rd5 = tmp; @@ -10329,10 +10753,12 @@ macro unpack32to64(src4, dest8) { build PuCond0506_N25_S24; build EndPacket; <> + build PuCond0506_N25_S24; if (ConditionReg == 0) goto ; tmp = zext(MemRsRelShiftC3h); <> + build PuCond0506_N25_S24; if (ConditionReg == 0) goto ; rd5 = tmp; @@ -10341,9 +10767,9 @@ macro unpack32to64(src4, dest8) { # (v4,9) memw -- "Rd32 = memw ( Rf32 = #U6x )" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 1 0 0 1 1 0 1 1 1 0 0 f f f f f P P 0 1 I I I I + I I d d d d d +# 1 0 0 1 1 0 1 1 1 0 0 f f f f f P P 0 1 I I I I - I I d d d d d -:memw Rd5,LdMemRsAssignxC9w EndPacket is iclass=9 & op2127=0x5c & op1213=1 & op7=0 & Rd5 & LdMemRsAssignxC9w & $(END_PACKET) { +:memw Rd5,LdMemRsAssignxC9w EndPacket is iclass=9 & op2127=0x5c & op1213=1 & Rd5 & LdMemRsAssignxC9w & $(END_PACKET) { Rd5 = LdMemRsAssignxC9w; build EndPacket; } @@ -10361,9 +10787,9 @@ macro unpack32to64(src4, dest8) { # (v4,3) memw -- "Rd32 = memw ( Rs32 + Rt32 << #n2 )" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 0 0 1 1 1 0 1 0 1 0 0 s s s s s P P n t t t t t n + + d d d d d +# 0 0 1 1 1 0 1 0 1 0 0 s s s s s P P n t t t t t n - - d d d d d -:memw Rd5,MemRsRelShiftC3w EndPacket is iclass=3 & op2127=0x54 & op0506=0 & Rd5 & MemRsRelShiftC3w & $(END_PACKET) { +:memw Rd5,MemRsRelShiftC3w EndPacket is iclass=3 & op2127=0x54 & Rd5 & MemRsRelShiftC3w & $(END_PACKET) { Rd5 = MemRsRelShiftC3w; build EndPacket; } @@ -10381,9 +10807,9 @@ macro unpack32to64(src4, dest8) { # (v2,9) memw -- "Rd32 = memw ( Rz32 ++ #s4:2 )" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 1 0 0 1 1 0 1 1 1 0 0 z z z z z P P 0 0 + + + i i i i d d d d d +# 1 0 0 1 1 0 1 1 1 0 0 z z z z z P P 0 0 - - - i i i i d d d d d -:memw Rd5,LdMemAIS4C9w EndPacket is iclass=9 & op2127=0x5c & op0913=0 & Rd5 & LdMemAIS4C9w & $(END_PACKET) { +:memw Rd5,LdMemAIS4C9w EndPacket is iclass=9 & op2127=0x5c & op1213=0 & Rd5 & LdMemAIS4C9w & $(END_PACKET) { Rd5 = LdMemAIS4C9w; build EndPacket; } @@ -10391,9 +10817,9 @@ macro unpack32to64(src4, dest8) { # (v2,9) memw -- "Rd32 = memw ( Rz32 ++ #s4:2 :circ ( Mu2 ) )" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 1 0 0 1 1 0 0 1 1 0 0 z z z z z P P u 0 + + 0 i i i i d d d d d +# 1 0 0 1 1 0 0 1 1 0 0 z z z z z P P u 0 - - 0 i i i i d d d d d -:memw Rd5,LdMemAIS4CircMuC9w EndPacket is iclass=9 & op2127=0x4c & op0912=0 & Rd5 & LdMemAIS4CircMuC9w & $(END_PACKET) { +:memw Rd5,LdMemAIS4CircMuC9w EndPacket is iclass=9 & op2127=0x4c & op12=0 & i9=0 & Rd5 & LdMemAIS4CircMuC9w & $(END_PACKET) { Rd5 = LdMemAIS4CircMuC9w; build EndPacket; } @@ -10401,14 +10827,14 @@ macro unpack32to64(src4, dest8) { # (v2,9) memw -- "Rd32 = memw ( Rz32 ++ Mu2 )" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 1 0 0 1 1 1 0 1 1 0 0 z z z z z P P u 0 + + + + 0 + + d d d d d +# 1 0 0 1 1 1 0 1 1 0 0 z z z z z P P u 0 - - - - 0 - - d d d d d # # (v2,9) memw -- "Rd32 = memw ( Rz32 ++ Mu2 :brev )" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 1 0 0 1 1 1 1 1 1 0 0 z z z z z P P u 0 + + + + 0 + + d d d d d +# 1 0 0 1 1 1 1 1 1 0 0 z z z z z P P u 0 - - - - 0 - - d d d d d -:memw Rd5,LdMemAIMuC9w EndPacket is iclass=9 & op2627=3 & op2124=0xc & op0512=0 & Rd5 & LdMemAIMuC9w & $(END_PACKET) { +:memw Rd5,LdMemAIMuC9w EndPacket is iclass=9 & op2627=3 & op2124=0xc & op12=0 & op7=0 & Rd5 & LdMemAIMuC9w & $(END_PACKET) { Rd5 = LdMemAIMuC9w; build EndPacket; } @@ -10416,9 +10842,9 @@ macro unpack32to64(src4, dest8) { # (v2,9) memw -- "Rd32 = memw ( Rz32 ++I :circ ( Mu2 ) )" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 1 0 0 1 1 0 0 1 1 0 0 z z z z z P P u 0 + + 1 + 0 + + d d d d d +# 1 0 0 1 1 0 0 1 1 0 0 z z z z z P P u 0 - - 1 - 0 - - d d d d d -:memw Rd5,LdMemAIICircMuC9w EndPacket is iclass=9 & op2127=0x4c & op0512=0x10 & Rd5 & LdMemAIICircMuC9w & $(END_PACKET) { +:memw Rd5,LdMemAIICircMuC9w EndPacket is iclass=9 & op2127=0x4c & op12=0x0 & i9=0x1 & op7=0x0 & Rd5 & LdMemAIICircMuC9w & $(END_PACKET) { Rd5 = LdMemAIICircMuC9w; build EndPacket; } @@ -10436,9 +10862,9 @@ macro unpack32to64(src4, dest8) { # (v4,10) memw -- "memw ( Rf32 = #U6x ) = Nt8 .new" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 1 0 1 0 1 0 1 1 1 0 1 f f f f f P P 0 1 0 t t t 1 + I I I I I I +# 1 0 1 0 1 0 1 1 1 0 1 f f f f f P P 0 1 0 t t t 1 - I I I I I I -:memw StMemRsAssignxC10w,Nreg0810 EndPacket is iclass=10 & op2127=0x5d & op1113=2 & op0607=2 & Nreg0810 & StMemRsAssignxC10w & $(END_PACKET) { +:memw StMemRsAssignxC10w,Nreg0810 EndPacket is iclass=10 & op2127=0x5d & op1113=2 & op7=1 & Nreg0810 & StMemRsAssignxC10w & $(END_PACKET) { build EndPacket; <> StMemRsAssignxC10w = Nreg0810; @@ -10449,7 +10875,7 @@ macro unpack32to64(src4, dest8) { # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| # 1 0 1 0 1 0 1 1 1 0 0 f f f f f P P 0 t t t t t 1 - I I I I I I -:memw StMemRsAssignxC10w,rt5 EndPacket is iclass=10 & op2127=0x5c & op13=0 & op0607=2 & rt5 & StMemRsAssignxC10w & $(END_PACKET) { +:memw StMemRsAssignxC10w,rt5 EndPacket is iclass=10 & op2127=0x5c & op13=0 & op7=1 & rt5 & StMemRsAssignxC10w & $(END_PACKET) { tmp:4 = rt5; build EndPacket; <> @@ -10482,9 +10908,9 @@ macro unpack32to64(src4, dest8) { # (v4,3) memw -- "memw ( Rs32 + #u6:2 ) = #S8x" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 0 0 1 1 1 1 0 + + 1 0 s s s s s P P I i i i i i i I I I I I I I +# 0 0 1 1 1 1 0 - - 1 0 s s s s s P P I i i i i i i I I I I I I I -:memw StMemRsRelC3w,Simm32_13_0006x EndPacket is iclass=3 & op2127=0x62 & StMemRsRelC3w & Simm32_13_0006x & $(END_PACKET) { +:memw StMemRsRelC3w,Simm32_13_0006x EndPacket is iclass=3 & op2527=0x6 & op2122=0x2 & StMemRsRelC3w & Simm32_13_0006x & $(END_PACKET) { build EndPacket; <> StMemRsRelC3w = Simm32_13_0006x; @@ -10493,9 +10919,9 @@ macro unpack32to64(src4, dest8) { # (v4,3) memw -- "memw ( Rs32 + #u6:2x ) &= Rt32" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 0 0 1 1 1 1 1 0 + 1 0 s s s s s P P 0 i i i i i i 1 0 t t t t t +# 0 0 1 1 1 1 1 0 - 1 0 s s s s s P P 0 i i i i i i 1 0 t t t t t -:memw&= StMemRsRelxC3w,ru5 EndPacket is iclass=3 & op2127=0x72 & op13=0 & op0506=2 & StMemRsRelxC3w & ru5 & $(END_PACKET) { +:memw&= StMemRsRelxC3w,ru5 EndPacket is iclass=3 & op2427=0xe & op2122=0x2 & op13=0 & op0506=2 & StMemRsRelxC3w & ru5 & $(END_PACKET) { tmp:4 = StMemRsRelxC3w & ru5; build EndPacket; <> @@ -10505,9 +10931,9 @@ macro unpack32to64(src4, dest8) { # (v4,3) memw -- "memw ( Rs32 + #u6:2x ) += #U5" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 0 0 1 1 1 1 1 1 + 1 0 s s s s s P P 0 i i i i i i 0 0 I I I I I +# 0 0 1 1 1 1 1 1 - 1 0 s s s s s P P 0 i i i i i i 0 0 I I I I I -:memw+= StMemRsRelxC3w,Uimm8_0004 EndPacket is iclass=3 & op2127=0x7a & op13=0 & op0506=0 & StMemRsRelxC3w & Uimm8_0004 & $(END_PACKET) { +:memw+= StMemRsRelxC3w,Uimm8_0004 EndPacket is iclass=3 & op2427=0xf & op2122=0x2 & op13=0 & op0506=0 & StMemRsRelxC3w & Uimm8_0004 & $(END_PACKET) { tmp:4 = StMemRsRelxC3w + zext(Uimm8_0004); build EndPacket; <> @@ -10517,9 +10943,9 @@ macro unpack32to64(src4, dest8) { # (v4,3) memw -- "memw ( Rs32 + #u6:2x ) += Rt32" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 0 0 1 1 1 1 1 0 + 1 0 s s s s s P P 0 i i i i i i 0 0 t t t t t +# 0 0 1 1 1 1 1 0 - 1 0 s s s s s P P 0 i i i i i i 0 0 t t t t t -:memw+= StMemRsRelxC3w,ru5 EndPacket is iclass=3 & op2127=0x72 & op13=0 & op0506=0 & StMemRsRelxC3w & ru5 & $(END_PACKET) { +:memw+= StMemRsRelxC3w,ru5 EndPacket is iclass=3 & op2427=0xe & op2122=0x2 & op13=0 & op0506=0 & StMemRsRelxC3w & ru5 & $(END_PACKET) { tmp:4 = StMemRsRelxC3w + ru5; build EndPacket; <> @@ -10529,9 +10955,9 @@ macro unpack32to64(src4, dest8) { # (v4,3) memw -- "memw ( Rs32 + #u6:2x ) -= #U5" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 0 0 1 1 1 1 1 1 + 1 0 s s s s s P P 0 i i i i i i 0 1 I I I I I +# 0 0 1 1 1 1 1 1 - 1 0 s s s s s P P 0 i i i i i i 0 1 I I I I I -:memw-= StMemRsRelxC3w,Uimm8_0004 EndPacket is iclass=3 & op2127=0x7a & op13=0 & op0506=1 & StMemRsRelxC3w & Uimm8_0004 & $(END_PACKET) { +:memw-= StMemRsRelxC3w,Uimm8_0004 EndPacket is iclass=3 & op2427=0xf & op2122=0x2 & op13=0 & op0506=1 & StMemRsRelxC3w & Uimm8_0004 & $(END_PACKET) { tmp:4 = StMemRsRelxC3w - zext(Uimm8_0004); build EndPacket; <> @@ -10541,9 +10967,9 @@ macro unpack32to64(src4, dest8) { # (v4,3) memw -- "memw ( Rs32 + #u6:2x ) -= Rt32" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 0 0 1 1 1 1 1 0 + 1 0 s s s s s P P 0 i i i i i i 0 1 t t t t t +# 0 0 1 1 1 1 1 0 - 1 0 s s s s s P P 0 i i i i i i 0 1 t t t t t -:memw-= StMemRsRelxC3w,ru5 EndPacket is iclass=3 & op2127=0x72 & op13=0 & op0506=1 & StMemRsRelxC3w & ru5 & $(END_PACKET) { +:memw-= StMemRsRelxC3w,ru5 EndPacket is iclass=3 & op2427=0xe & op2122=0x2 & op13=0 & op0506=1 & StMemRsRelxC3w & ru5 & $(END_PACKET) { tmp:4 = StMemRsRelxC3w - ru5; build EndPacket; <> @@ -10553,9 +10979,9 @@ macro unpack32to64(src4, dest8) { # (v4,3) memw -- "memw ( Rs32 + #u6:2x ) = clrbit ( #U5 )" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 0 0 1 1 1 1 1 1 + 1 0 s s s s s P P 0 i i i i i i 1 0 I I I I I +# 0 0 1 1 1 1 1 1 - 1 0 s s s s s P P 0 i i i i i i 1 0 I I I I I -:memw StMemRsRelxC3w,ClrBit_0004w EndPacket is iclass=3 & op2127=0x7a & op13=0 & op0506=2 & StMemRsRelxC3w & ClrBit_0004w & $(END_PACKET) { +:memw StMemRsRelxC3w,ClrBit_0004w EndPacket is iclass=3 & op2427=0xf & op2122=0x2 & op13=0 & op0506=2 & StMemRsRelxC3w & ClrBit_0004w & $(END_PACKET) { tmp:4 = StMemRsRelxC3w & ClrBit_0004w; build EndPacket; <> @@ -10565,9 +10991,9 @@ macro unpack32to64(src4, dest8) { # (v4,3) memw -- "memw ( Rs32 + #u6:2x ) = setbit ( #U5 )" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 0 0 1 1 1 1 1 1 + 1 0 s s s s s P P 0 i i i i i i 1 1 I I I I I +# 0 0 1 1 1 1 1 1 - 1 0 s s s s s P P 0 i i i i i i 1 1 I I I I I -:memw StMemRsRelxC3w,SetBit_0004w EndPacket is iclass=3 & op2127=0x7a & op13=0 & op0506=3 & StMemRsRelxC3w & SetBit_0004w & $(END_PACKET) { +:memw StMemRsRelxC3w,SetBit_0004w EndPacket is iclass=3 & op2427=0xf & op2122=0x2 & op13=0 & op0506=3 & StMemRsRelxC3w & SetBit_0004w & $(END_PACKET) { tmp:4 = StMemRsRelxC3w | SetBit_0004w; build EndPacket; <> @@ -10577,9 +11003,9 @@ macro unpack32to64(src4, dest8) { # (v4,3) memw -- "memw ( Rs32 + #u6:2x ) |= Rt32" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 0 0 1 1 1 1 1 0 + 1 0 s s s s s P P 0 i i i i i i 1 1 t t t t t +# 0 0 1 1 1 1 1 0 - 1 0 s s s s s P P 0 i i i i i i 1 1 t t t t t -:memw|= StMemRsRelxC3w,ru5 EndPacket is iclass=3 & op2127=0x72 & op13=0 & op0506=3 & StMemRsRelxC3w & ru5 & $(END_PACKET) { +:memw|= StMemRsRelxC3w,ru5 EndPacket is iclass=3 & op2427=0xe & op2122=0x2 & op13=0 & op0506=3 & StMemRsRelxC3w & ru5 & $(END_PACKET) { tmp:4 = StMemRsRelxC3w | ru5; build EndPacket; <> @@ -10589,9 +11015,9 @@ macro unpack32to64(src4, dest8) { # (v4,3) memw -- "memw ( Rs32 + Ru32 << #n2 ) = Nt8 .new" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 0 0 1 1 1 0 1 1 1 0 1 s s s s s P P n u u u u u n + + 1 0 t t t +# 0 0 1 1 1 0 1 1 1 0 1 s s s s s P P n u u u u u n - - 1 0 t t t -:memw MemRsRelShiftC3w,Nreg0002 EndPacket is iclass=3 & op2127=0x5d & op0306=2 & MemRsRelShiftC3w & Nreg0002 & $(END_PACKET) { +:memw MemRsRelShiftC3w,Nreg0002 EndPacket is iclass=3 & op2127=0x5d & op0304=2 & MemRsRelShiftC3w & Nreg0002 & $(END_PACKET) { build EndPacket; <> MemRsRelShiftC3w = Nreg0002; @@ -10600,9 +11026,9 @@ macro unpack32to64(src4, dest8) { # (v4,3) memw -- "memw ( Rs32 + Ru32 << #n2 ) = Rt32" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 0 0 1 1 1 0 1 1 1 0 0 s s s s s P P n u u u u u n + + t t t t t +# 0 0 1 1 1 0 1 1 1 0 0 s s s s s P P n u u u u u n - - t t t t t -:memw MemRsRelShiftC3w,ru5 EndPacket is iclass=3 & op2127=0x5c & op0506=0 & MemRsRelShiftC3w & ru5 & $(END_PACKET) { +:memw MemRsRelShiftC3w,ru5 EndPacket is iclass=3 & op2127=0x5c & MemRsRelShiftC3w & ru5 & $(END_PACKET) { tmp:4 = ru5; build EndPacket; <> @@ -10635,9 +11061,9 @@ macro unpack32to64(src4, dest8) { # (v4,10) memw -- "memw ( Rz32 ++ #s4:2 ) = Nt8 .new" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 1 0 1 0 1 0 1 1 1 0 1 z z z z z P P 0 1 0 t t t 0 i i i i + 0 + +# 1 0 1 0 1 0 1 1 1 0 1 z z z z z P P 0 1 0 t t t 0 i i i i - 0 - -:memw StMemAIS4C10w,Nreg0810 EndPacket is iclass=10 & op2127=0x5d & op1113=2 & op7=0 & op0002=0 & Nreg0810 & StMemAIS4C10w & $(END_PACKET) { +:memw StMemAIS4C10w,Nreg0810 EndPacket is iclass=10 & op2127=0x5d & op1113=2 & op7=0 & op1=0 & Nreg0810 & StMemAIS4C10w & $(END_PACKET) { build EndPacket; <> StMemAIS4C10w = Nreg0810; @@ -10646,9 +11072,9 @@ macro unpack32to64(src4, dest8) { # (v4,10) memw -- "memw ( Rz32 ++ #s4:2 :circ ( Mu2 ) ) = Nt8 .new" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 1 0 1 0 1 0 0 1 1 0 1 z z z z z P P u 1 0 t t t 0 i i i i + 0 + +# 1 0 1 0 1 0 0 1 1 0 1 z z z z z P P u 1 0 t t t 0 i i i i - 0 - -:memw StMemAIS4CircMuC10w,Nreg0810 EndPacket is iclass=10 & op2127=0x4d & op1112=2 & op7=0 & op0002=0 & Nreg0810 & StMemAIS4CircMuC10w & $(END_PACKET) { +:memw StMemAIS4CircMuC10w,Nreg0810 EndPacket is iclass=10 & op2127=0x4d & op1112=2 & op7=0 & op1=0 & Nreg0810 & StMemAIS4CircMuC10w & $(END_PACKET) { build EndPacket; <> StMemAIS4CircMuC10w = Nreg0810; @@ -10657,14 +11083,14 @@ macro unpack32to64(src4, dest8) { # (v4,10) memw -- "memw ( Rz32 ++ Mu2 ) = Nt8 .new" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 1 0 1 0 1 1 0 1 1 0 1 z z z z z P P u 1 0 t t t 0 + + + + + + + +# 1 0 1 0 1 1 0 1 1 0 1 z z z z z P P u 1 0 t t t 0 - - - - - - - # # (v4,10) memw -- "memw ( Rz32 ++ Mu2 :brev ) = Nt8 .new" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 1 0 1 0 1 1 1 1 1 0 1 z z z z z P P u 1 0 t t t 0 + + + + + + + +# 1 0 1 0 1 1 1 1 1 0 1 z z z z z P P u 1 0 t t t 0 - - - - - - - -:memw StMemAIMuC10w,Nreg0810 EndPacket is iclass=10 & op2627=3 & op2124=0xd & op1112=2 & op0007=0 & Nreg0810 & StMemAIMuC10w & $(END_PACKET) { +:memw StMemAIMuC10w,Nreg0810 EndPacket is iclass=10 & op2627=3 & op2124=0xd & op1112=2 & op7=0 & Nreg0810 & StMemAIMuC10w & $(END_PACKET) { build EndPacket; <> StMemAIMuC10w = Nreg0810; @@ -10673,9 +11099,9 @@ macro unpack32to64(src4, dest8) { # (v4,10) memw -- "memw ( Rz32 ++I :circ ( Mu2 ) ) = Nt8 .new" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 1 0 1 0 1 0 0 1 1 0 1 z z z z z P P u 1 0 t t t 0 + + + + + 1 + +# 1 0 1 0 1 0 0 1 1 0 1 z z z z z P P u 1 0 t t t 0 - - - - - 1 - -:memw StMemAIICircMuC10w,Nreg0810 EndPacket is iclass=10 & op2127=0x4d & op1112=2 & op0007=2 & Nreg0810 & StMemAIICircMuC10w & $(END_PACKET) { +:memw StMemAIICircMuC10w,Nreg0810 EndPacket is iclass=10 & op2127=0x4d & op1112=2 & op7=0 & op1=1 & Nreg0810 & StMemAIICircMuC10w & $(END_PACKET) { build EndPacket; <> StMemAIICircMuC10w = Nreg0810; @@ -10686,7 +11112,7 @@ macro unpack32to64(src4, dest8) { # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| # 1 0 1 0 1 0 1 1 1 0 0 z z z z z P P 0 t t t t t 0 i i i i - 0 - -:memw StMemAIS4C10w,rt5 EndPacket is iclass=10 & op2127=0x5c & op13=0 & op7=0 & op0002=0 & rt5 & StMemAIS4C10w & $(END_PACKET) { +:memw StMemAIS4C10w^StNt24,rt5 EndPacket is iclass=10 & op2527=5 & op2123=4 & op13=0 & op7=0 & op1=0 & StNt24 & rt5 & StMemAIS4C10w & $(END_PACKET) { tmp:4 = rt5; build EndPacket; <> @@ -10696,9 +11122,9 @@ macro unpack32to64(src4, dest8) { # (v2,10) memw -- "memw ( Rz32 ++ #s4:2 :circ ( Mu2 ) ) = Rt32" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 1 0 1 0 1 0 0 1 1 0 0 z z z z z P P u t t t t t 0 i i i i + 0 + +# 1 0 1 0 1 0 0 1 1 0 0 z z z z z P P u t t t t t 0 i i i i - 0 - -:memw StMemAIS4CircMuC10w,rt5 EndPacket is iclass=10 & op2127=0x4c & op7=0 & op0002=0 & rt5 & StMemAIS4CircMuC10w & $(END_PACKET) { +:memw StMemAIS4CircMuC10w,rt5 EndPacket is iclass=10 & op2127=0x4c & op7=0 & op1=0 & rt5 & StMemAIS4CircMuC10w & $(END_PACKET) { tmp:4 = rt5; build EndPacket; <> @@ -10708,14 +11134,14 @@ macro unpack32to64(src4, dest8) { # (v2,10) memw -- "memw ( Rz32 ++ Mu2 ) = Rt32" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 1 0 1 0 1 1 0 1 1 0 0 z z z z z P P u t t t t t 0 + + + + + + + +# 1 0 1 0 1 1 0 1 1 0 0 z z z z z P P u t t t t t 0 - - - - - - - # # (v2,10) memw -- "memw ( Rz32 ++ Mu2 :brev ) = Rt32" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 1 0 1 0 1 1 1 1 1 0 0 z z z z z P P u t t t t t 0 + + + + + + + +# 1 0 1 0 1 1 1 1 1 0 0 z z z z z P P u t t t t t 0 - - - - - - - -:memw StMemAIMuC10w,rt5 EndPacket is iclass=10 & op2627=3 & op2124=0xc & op0007=0 & rt5 & StMemAIMuC10w & $(END_PACKET) { +:memw StMemAIMuC10w,rt5 EndPacket is iclass=10 & op2627=3 & op2124=0xc & op7=0 & rt5 & StMemAIMuC10w & $(END_PACKET) { tmp:4 = rt5; build EndPacket; <> @@ -10725,9 +11151,9 @@ macro unpack32to64(src4, dest8) { # (v2,10) memw -- "memw ( Rz32 ++I :circ ( Mu2 ) ) = Rt32" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 1 0 1 0 1 0 0 1 1 0 0 z z z z z P P u t t t t t 0 + + + + + 1 + +# 1 0 1 0 1 0 0 1 1 0 0 z z z z z P P u t t t t t 0 - - - - - 1 - -:memw StMemAIICircMuC10w,rt5 EndPacket is iclass=10 & op2127=0x4c & op0007=2 & rt5 & StMemAIICircMuC10w & $(END_PACKET) { +:memw StMemAIICircMuC10w,rt5 EndPacket is iclass=10 & op2127=0x4c & op7=0 & op1=1 & rt5 & StMemAIICircMuC10w & $(END_PACKET) { tmp:4 = rt5; build EndPacket; <> @@ -10760,32 +11186,34 @@ macro unpack32to64(src4, dest8) { # (v4,9) memw -- "if ( Pt4 ) Rd32 = memw ( #u6x )" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 1 0 0 1 1 1 1 1 1 0 0 i i i i i P P 1 0 0 t t i 1 + + d d d d d +# 1 0 0 1 1 1 1 1 1 0 0 i i i i i P P 1 0 0 t t i 1 - - d d d d d # # (v4,9) memw -- "if ( ! Pt4 ) Rd32 = memw ( #u6x )" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 1 0 0 1 1 1 1 1 1 0 0 i i i i i P P 1 0 1 t t i 1 + + d d d d d +# 1 0 0 1 1 1 1 1 1 0 0 i i i i i P P 1 0 1 t t i 1 - - d d d d d # # (v4,9) memw -- "if ( Pt4 .new ) Rd32 = memw ( #u6x )" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 1 0 0 1 1 1 1 1 1 0 0 i i i i i P P 1 1 0 t t i 1 + + d d d d d +# 1 0 0 1 1 1 1 1 1 0 0 i i i i i P P 1 1 0 t t i 1 - - d d d d d # # (v4,9) memw -- "if ( ! Pt4 .new ) Rd32 = memw ( #u6x )" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 1 0 0 1 1 1 1 1 1 0 0 i i i i i P P 1 1 1 t t i 1 + + d d d d d +# 1 0 0 1 1 1 1 1 1 0 0 i i i i i P P 1 1 1 t t i 1 - - d d d d d -:memw^PuCond0910_N12_S11 rd5,LdMemAbsU6xC9w EndPacket is iclass=9 & op2127=0x7c & op13=1 & op0507=4 & rd5 & LdMemAbsU6xC9w & PuCond0910_N12_S11 & $(END_PACKET) { +:memw^PuCond0910_N12_S11 rd5,LdMemAbsU6xC9w EndPacket is iclass=9 & op2127=0x7c & op13=1 & op7=1 & rd5 & LdMemAbsU6xC9w & PuCond0910_N12_S11 & $(END_PACKET) { tmp:4 = 0; build PuCond0910_N12_S11; build EndPacket; <> + build PuCond0910_N12_S11; if (ConditionReg == 0) goto ; tmp = LdMemAbsU6xC9w; <> + build PuCond0910_N12_S11; if (ConditionReg == 0) goto ; rd5 = tmp; @@ -10816,10 +11244,12 @@ macro unpack32to64(src4, dest8) { build PuCond1112_N25_S26; build EndPacket; <> + build PuCond1112_N25_S26; if (ConditionReg == 0) goto ; tmp = LdMemRsRelxC4w; <> + build PuCond1112_N25_S26; if (ConditionReg == 0) goto ; rd5 = tmp; @@ -10850,10 +11280,13 @@ macro unpack32to64(src4, dest8) { build PuCond0910_N12_S11; build EndPacket; <> + build PuCond0910_N12_S11; if (ConditionReg == 0) goto ; tmp = LdMemAIS4C9w; <> + build PuCond0910_N12_S11; + build LdMemAIS4C9w; if (ConditionReg == 0) goto ; rd5 = tmp; @@ -10884,10 +11317,12 @@ macro unpack32to64(src4, dest8) { build PuCond0506_N25_S24; build EndPacket; <> + build PuCond0506_N25_S24; if (ConditionReg == 0) goto ; tmp = MemRsRelShiftC3w; <> + build PuCond0506_N25_S24; if (ConditionReg == 0) goto ; rd5 = tmp; @@ -10896,27 +11331,28 @@ macro unpack32to64(src4, dest8) { # (v4,10) memw -- "if ( Pv4 ) memw ( #u6x ) = Nt8 .new" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 1 0 1 0 1 1 1 1 1 0 1 + + + i i P P 0 1 0 t t t 1 i i i i 0 v v +# 1 0 1 0 1 1 1 1 1 0 1 - - - i i P P 0 1 0 t t t 1 i i i i 0 v v # # (v4,10) memw -- "if ( Pv4 .new ) memw ( #u6x ) = Nt8 .new" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 1 0 1 0 1 1 1 1 1 0 1 + + + i i P P 1 1 0 t t t 1 i i i i 0 v v +# 1 0 1 0 1 1 1 1 1 0 1 - - - i i P P 1 1 0 t t t 1 i i i i 0 v v # # (v4,10) memw -- "if ( ! Pv4 ) memw ( #u6x ) = Nt8 .new" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 1 0 1 0 1 1 1 1 1 0 1 + + + i i P P 0 1 0 t t t 1 i i i i 1 v v +# 1 0 1 0 1 1 1 1 1 0 1 - - - i i P P 0 1 0 t t t 1 i i i i 1 v v # # (v4,10) memw -- "if ( ! Pv4 .new ) memw ( #u6x ) = Nt8 .new" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 1 0 1 0 1 1 1 1 1 0 1 + + + i i P P 1 1 0 t t t 1 i i i i 1 v v +# 1 0 1 0 1 1 1 1 1 0 1 - - - i i P P 1 1 0 t t t 1 i i i i 1 v v -:memw^PuCond0001_N13_S02 StMemAbsU6xC10w,Nreg0810 EndPacket is iclass=10 & op2127=0x7d & op1820=0 & op1112=2 & op7=1 & Nreg0810 & StMemAbsU6xC10w & PuCond0001_N13_S02 & $(END_PACKET) { +:memw^PuCond0001_N13_S02 StMemAbsU6xC10w,Nreg0810 EndPacket is iclass=10 & op2127=0x7d & op1112=2 & op7=1 & Nreg0810 & StMemAbsU6xC10w & PuCond0001_N13_S02 & $(END_PACKET) { build PuCond0001_N13_S02; build EndPacket; <> + build PuCond0001_N13_S02; if (ConditionReg == 0) goto ; StMemAbsU6xC10w = Nreg0810; @@ -10940,13 +11376,14 @@ macro unpack32to64(src4, dest8) { # (v4,10) memw -- "if ( ! Pv4 .new ) memw ( #u6x ) = Rt32" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 1 0 1 0 1 1 1 1 1 0 0 + + + i i P P 1 t t t t t 1 i i i i 1 v v +# 1 0 1 0 1 1 1 1 1 0 0 - - - i i P P 1 t t t t t 1 i i i i 1 v v -:memw^PuCond0001_N13_S02 StMemAbsU6xC10w,rt5 EndPacket is iclass=10 & op2127=0x7c & op1820=0 & op7=1 & rt5 & StMemAbsU6xC10w & PuCond0001_N13_S02 & $(END_PACKET) { +:memw^PuCond0001_N13_S02 StMemAbsU6xC10w,rt5 EndPacket is iclass=10 & op2127=0x7c & op7=1 & rt5 & StMemAbsU6xC10w & PuCond0001_N13_S02 & $(END_PACKET) { tmp:4 = rt5; build PuCond0001_N13_S02; build EndPacket; <> + build PuCond0001_N13_S02; if (ConditionReg == 0) goto ; StMemAbsU6xC10w = tmp; @@ -10976,6 +11413,7 @@ macro unpack32to64(src4, dest8) { build PuCond0506_N24_S23; build EndPacket; <> + build PuCond0506_N24_S23; if (ConditionReg == 0) goto ; StMemRsRelC3w = Simm32_13_0004x; @@ -11005,6 +11443,7 @@ macro unpack32to64(src4, dest8) { build PuCond0001_N25_S26; build EndPacket; <> + build PuCond0001_N25_S26; if (ConditionReg == 0) goto ; StMemRsRelxC4w = Nreg0810; @@ -11035,6 +11474,7 @@ macro unpack32to64(src4, dest8) { build PuCond0001_N25_S26; build EndPacket; <> + build PuCond0001_N25_S26; if (ConditionReg == 0) goto ; StMemRsRelxC4w = tmp; @@ -11064,6 +11504,7 @@ macro unpack32to64(src4, dest8) { build PuCond0506_N25_S24; build EndPacket; <> + build PuCond0506_N25_S24; if (ConditionReg == 0) goto ; MemRsRelShiftC3w = Nreg0002; @@ -11094,6 +11535,7 @@ macro unpack32to64(src4, dest8) { build PuCond0506_N25_S24; build EndPacket; <> + build PuCond0506_N25_S24; if (ConditionReg == 0) goto ; MemRsRelShiftC3w = tmp; @@ -11123,6 +11565,8 @@ macro unpack32to64(src4, dest8) { build PuCond0001_N07_S02; build EndPacket; <> + build PuCond0001_N07_S02; + build StMemAIS4C10w; if (ConditionReg == 0) goto ; StMemAIS4C10w = Nreg0810; @@ -11148,11 +11592,13 @@ macro unpack32to64(src4, dest8) { # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| # 1 0 1 0 1 0 1 1 1 0 0 z z z z z P P 1 t t t t t 0 i i i i 1 v v -:memw^PuCond0001_N07_S02 StMemAIS4C10w,rt5 EndPacket is iclass=10 & op2127=0x5c & op13=1 & rt5 & StMemAIS4C10w & PuCond0001_N07_S02 & $(END_PACKET) [ cond=1; ] { +:memw^PuCond0001_N07_S02 StMemAIS4C10w^StNt24,rt5 EndPacket is iclass=10 & op2527=5 & op2123=4 & op13=1 & StNt24 & rt5 & StMemAIS4C10w & PuCond0001_N07_S02 & $(END_PACKET) [ cond=1; ] { tmp:4 = rt5; build PuCond0001_N07_S02; build EndPacket; <> + build PuCond0001_N07_S02; + build StMemAIS4C10w; if (ConditionReg == 0) goto ; StMemAIS4C10w = tmp; @@ -11163,7 +11609,12 @@ macro unpack32to64(src4, dest8) { # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| # 1 0 1 0 0 0 0 0 1 0 1 s s s s s P P - t t t t t - - 0 0 1 0 d d -:memw_rl":at" StMemRsRelPdC9w, rt5 EndPacket is iclass=0xa & op2127=0x05 & op13=0 & rt5 & op0607=0 & op0205=0x2 & StMemRsRelPdC9w & $(END_PACKET) { +# (v68,10) memw_rl":at" -- "if (Pv4) memw_rl ( Rs32 ):at = Rt32" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 1 0 0 0 0 0 0 0 1 s s s s s P P - - - - - - - - - t t t t t + +:memw_rl":at" StMemRsRelPdC9w, rt5 EndPacket is iclass=0xa & op2127=0x05 & op0205=0x2 & rt5 & StMemRsRelPdC9w & $(END_PACKET) { tmp:4 = rt5; build EndPacket; <> @@ -11171,12 +11622,12 @@ macro unpack32to64(src4, dest8) { StMemRsRelPdC9w = tmp; } -# memw_rl -- "memw_rl ( Rs32 ):st = Rt32" +# (v68,10) memw_rl -- "memw_rl ( Rs32 ):st = Rt32" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| # 1 0 1 0 0 0 0 0 1 0 1 s s s s s P P - t t t t t - - 1 0 1 0 d d -:memw_rl":st" StMemRsRelPdC9w, rt5 EndPacket is iclass=0xa & op2127=0x05 & op13=0 & rt5 & op0607=0 & op0205=0xa & StMemRsRelPdC9w & $(END_PACKET) { +:memw_rl":st" StMemRsRelPdC9w, rt5 EndPacket is iclass=0xa & op2127=0x05 & op0205=0xa & rt5 & StMemRsRelPdC9w & $(END_PACKET) { tmp:4 = rt5; build EndPacket; <> @@ -11188,20 +11639,30 @@ macro unpack32to64(src4, dest8) { # (v2,9) memw_locked -- "Rd32 = memw_locked ( Rs32 )" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 1 0 0 1 0 0 1 0 0 0 0 s s s s s P P 0 0 + + + + + + + d d d d d +# 1 0 0 1 0 0 1 0 0 0 0 s s s s s P P 0 0 - - - - 0 0 0 d d d d d -:memw_locked Rd5,LdMemRsRelC9w EndPacket is iclass=9 & op2127=0x10 & op0513=0 & Rd5 & LdMemRsRelC9w & $(END_PACKET) { +:memw_locked Rd5,LdMemRsRelC9w EndPacket is iclass=9 & op2127=0x10 & op1213=0 & op0507=0 & Rd5 & LdMemRsRelC9w & $(END_PACKET) { # NOTE: Manual does not indicate lock use, cannot be group with other instructions Rd5 = LdMemRsRelC9w; build EndPacket; } +# (v68,9) memw_aq -- "Rd32 = memw_aq ( Rs32 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 0 1 0 0 1 0 0 0 0 s s s s s P P 0 0 1 - - - 0 0 0 d d d d d + +:memw_aq Rd5,LdMemRsRelC9w EndPacket is iclass=9 & op2527=1 & op2224=0 & op21=0 & op1113=1 & op0507=0 & Rd5 & LdMemRsRelC9w & $(END_PACKET) { + Rd5 = LdMemRsRelC9w; + build EndPacket; +} + # (v2,10) memw_locked -- "memw_locked ( Rs32 , Pd4 ) = Rt32" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 1 0 1 0 0 0 0 0 1 0 1 s s s s s P P + t t t t t + + + + + + d d +# 1 0 1 0 0 0 0 0 1 0 1 s s s s s P P - t t t t t - - - - - - d d -:memw_locked StMemRsRelPdC9w,rt5 EndPacket is iclass=10 & op2127=0x05 & op13=0 & op0207=0 & StMemRsRelPdC9w & rt5 & pu0001 & $(END_PACKET) { +:memw_locked StMemRsRelPdC9w,rt5 EndPacket is iclass=10 & op2127=0x05 & StMemRsRelPdC9w & rt5 & pu0001 & $(END_PACKET) { # NOTE: cannot be group with other instructions rc:1 = lock(); lockOK:1 = rc != 0; @@ -11219,7 +11680,7 @@ macro unpack32to64(src4, dest8) { # (v4,9) memw_phys -- "Rd32 = memw_phys ( Rs32 , Rt32 )" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 1 0 0 1 0 0 1 0 0 0 0 s s s s s P P 1 t t t t t + + + d d d d d +# 1 0 0 1 0 0 1 0 0 0 0 s s s s s P P 1 t t t t t 0 0 0 d d d d d define pcodeop memw_phys; @@ -11228,14 +11689,25 @@ define pcodeop memw_phys; build EndPacket; } +# (v68,9) memw_aq -- "Rd32 = memw_aq ( Rs32 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 0 1 0 0 1 0 0 0 0 s s s s s P P 0 0 1 0 0 0 0 0 0 d d d d d + +define pcodeop memw_aq; + +:memw_aq Rd5,rs5 EndPacket is iclass=9 & op2127=0x10 & op0513=0x40 & Rd5 & rs5 & $(END_PACKET) { + Rd5 = memw_aq(rs5); +} + # (v2,13) min -- "Rd32 = min ( Rt32 , Rs32 )" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 1 1 0 1 0 1 0 1 1 0 1 s s s s s P P + t t t t t 0 + + d d d d d +# 1 1 0 1 0 1 0 1 1 0 1 s s s s s P P - t t t t t 0 - - d d d d d define pcodeop min; -:min Rd5,rs5,rt5 EndPacket is iclass=13 & op2127=0x2d & op13=0 & op0507=0 & rs5 & rt5 & Rd5 & $(END_PACKET) { +:min Rd5,rt5,rs5 EndPacket is iclass=13 & op2127=0x2d & op7=0 & rs5 & rt5 & Rd5 & $(END_PACKET) { Rd5 = min(rt5,rs5); build EndPacket; } @@ -11243,9 +11715,9 @@ define pcodeop min; # (v4,13) min -- "Rdd32 = min ( Rtt32 , Rss32 )" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 1 1 0 1 0 0 1 1 1 0 1 s s s s s P P + t t t t t 1 1 0 d d d d d +# 1 1 0 1 0 0 1 1 1 0 1 s s s s s P P - t t t t t 1 1 0 d d d d d -:min Rdd5,rss5,rtt5 EndPacket is iclass=13 & op2127=0x1d & op13=0 & op0507=6 & rss5 & rtt5 & Rdd5 & $(END_PACKET) { +:min Rdd5,rtt5,rss5 EndPacket is iclass=13 & op2127=0x1d & op0507=6 & rss5 & rtt5 & Rdd5 & $(END_PACKET) { Rdd5 = min(rtt5,rss5); build EndPacket; } @@ -11253,11 +11725,11 @@ define pcodeop min; # (v2,13) minu -- "Rd32 = minu ( Rt32 , Rs32 )" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 1 1 0 1 0 1 0 1 1 0 1 s s s s s P P + t t t t t 1 + + d d d d d +# 1 1 0 1 0 1 0 1 1 0 1 s s s s s P P - t t t t t 1 - - d d d d d define pcodeop minu; -:minu Rd5,rs5,rt5 EndPacket is iclass=13 & op2127=0x2d & op13=0 & op0507=4 & rs5 & rt5 & Rd5 & $(END_PACKET) { +:minu Rd5,rt5,rs5 EndPacket is iclass=13 & op2127=0x2d & op7=1 & rs5 & rt5 & Rd5 & $(END_PACKET) { Rd5 = minu(rt5,rs5); build EndPacket; } @@ -11265,9 +11737,9 @@ define pcodeop minu; # (v4,13) minu -- "Rdd32 = minu ( Rtt32 , Rss32 )" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 1 1 0 1 0 0 1 1 1 0 1 s s s s s P P + t t t t t 1 1 1 d d d d d +# 1 1 0 1 0 0 1 1 1 0 1 s s s s s P P - t t t t t 1 1 1 d d d d d -:minu Rdd5,rss5,rtt5 EndPacket is iclass=13 & op2127=0x1d & op13=0 & op0507=7 & rss5 & rtt5 & Rdd5 & $(END_PACKET) { +:minu Rdd5,rtt5,rss5 EndPacket is iclass=13 & op2127=0x1d & op0507=7 & rss5 & rtt5 & Rdd5 & $(END_PACKET) { Rdd5 = minu(rtt5,rss5); build EndPacket; } @@ -11275,9 +11747,9 @@ define pcodeop minu; # (v4,13) modwrap -- "Rd32 = modwrap ( Rs32 , Rt32 )" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 1 1 0 1 0 0 1 1 1 1 1 s s s s s P P + t t t t t 1 1 1 d d d d d +# 1 1 0 1 0 0 1 1 1 1 1 s s s s s P P - t t t t t 1 1 1 d d d d d define pcodeop modwrap; -:modwrap Rd5,rs5,rt5 EndPacket is iclass=13 & op2127=0x1f & op13=0 & op0507=7 & rs5 & rt5 & Rd5 & $(END_PACKET) { +:modwrap Rd5,rs5,rt5 EndPacket is iclass=13 & op2127=0x1f & op0507=7 & rs5 & rt5 & Rd5 & $(END_PACKET) { Rd5 = modwrap(rs5,rt5); build EndPacket; } @@ -11287,6 +11759,7 @@ define pcodeop modwrap; # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| # 0 1 1 0 1 1 1 1 1 1 1 t t t t t P P 0 s s s s s 0 1 0 d d d d d # (Rs and Rt are swapped in this instruction) + define pcodeop movlen; :movlen Rd5,rt5,rs5 EndPacket is iclass=6 & op2127=0x7f & op13=0 & op0507=2 & rs5 & rt5 & Rd5 & $(END_PACKET) { @@ -11297,7 +11770,7 @@ define pcodeop movlen; # (v2,14) mpy -- "Rd32 = mpy ( Rs32 , Rt32 )" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 1 1 1 0 1 1 0 1 0 0 0 s s s s s P P + t t t t t 0 0 1 d d d d d +# 1 1 1 0 1 1 0 1 0 0 0 s s s s s P P 0 t t t t t 0 0 1 d d d d d :mpy Rd5,rs5,rt5 EndPacket is iclass=14 & op2127=0x68 & op13=0 & op0507=1 & rs5 & rt5 & Rd5 & $(END_PACKET) { tmp:8 = sext(rs5) * sext(rt5); @@ -11308,7 +11781,7 @@ define pcodeop movlen; # (v4,14) mpy -- "Rd32 = mpy ( Rs32 , Rt32 ) :<<1" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 1 1 1 0 1 1 0 1 1 0 1 s s s s s P P + t t t t t 0 1 0 d d d d d +# 1 1 1 0 1 1 0 1 1 0 1 s s s s s P P 0 t t t t t 0 1 0 d d d d d :mpy^":<<1" Rd5,rs5,rt5 EndPacket is iclass=14 & op2127=0x6d & op13=0 & op0507=2 & rs5 & rt5 & Rd5 & $(END_PACKET) { tmp:8 = (sext(rs5) * sext(rt5)) << 1; @@ -11319,9 +11792,9 @@ define pcodeop movlen; # (v2,14) mpy -- "Rd32 = mpy ( Rs32 , Rt32 ) :rnd" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 1 1 1 0 1 1 0 1 0 0 1 s s s s s P P + t t t t t 0 0 1 d d d d d +# 1 1 1 0 1 1 0 1 0 0 1 s s s s s P P 0 t t t t t 0 0 1 d d d d d -:mpy^":rnd" Rd5,rs5,rt5 EndPacket is iclass=14 & op2127=0x69 & op13=0 & op0507=1 & rs5 & rt5 & Rd5 & $(END_PACKET){ +:mpy^":rnd" Rd5,rs5,rt5 EndPacket is iclass=14 & op2127=0x69 & op13=0 & op0507=1 & rs5 & rt5 & Rd5 & $(END_PACKET) { tmp:8 = (sext(rs5) * sext(rt5)) + 0x80000000; Rd5 = tmp(4); # Use upper 32-bits of result build EndPacket; @@ -11330,7 +11803,7 @@ define pcodeop movlen; # (v4,14) mpy -- "Rd32 = mpy ( Rs32 , Rt32 ) :<<1 :sat" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 1 1 1 0 1 1 0 1 1 1 1 s s s s s P P + t t t t t 0 0 0 d d d d d +# 1 1 1 0 1 1 0 1 1 1 1 s s s s s P P 0 t t t t t 0 0 0 d d d d d # mpyX2SatUpper(a,b,shift) sat_32( ((a * b) << 1) >> shift ) # Multiply (a * b) with additional x2 multiplier and use shifted result before saturation for a 32-bit result @@ -11344,7 +11817,7 @@ define pcodeop mpyX2SatUpper; # (v4,14) mpy -- "Rd32 = mpy ( Rs32 , Rt32.h ) :<<1 :sat" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 1 1 1 0 1 1 0 1 1 0 1 s s s s s P P + t t t t t 0 0 0 d d d d d +# 1 1 1 0 1 1 0 1 1 0 1 s s s s s P P 0 t t t t t 0 0 0 d d d d d :mpy^":<<1:sat" Rd5,rs5,rt5H EndPacket is iclass=14 & op2127=0x6d & op13=0 & op0507=0 & rs5 & rt5H & Rd5 & $(END_PACKET) { Rd5 = mpyX2SatUpper(rs5, rt5H, 16:1); @@ -11354,7 +11827,7 @@ define pcodeop mpyX2SatUpper; # (v4,14) mpy -- "Rd32 = mpy ( Rs32 , Rt32.l ) :<<1 :sat" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 1 1 1 0 1 1 0 1 1 0 1 s s s s s P P + t t t t t 0 0 1 d d d d d +# 1 1 1 0 1 1 0 1 1 0 1 s s s s s P P 0 t t t t t 0 0 1 d d d d d :mpy^":<<1:sat" Rd5,rs5,rt5L EndPacket is iclass=14 & op2127=0x6d & op13=0 & op0507=1 & rs5 & rt5L & Rd5 & $(END_PACKET) { Rd5 = mpyX2SatUpper(rs5, rt5L, 16:1); @@ -11364,7 +11837,7 @@ define pcodeop mpyX2SatUpper; # (v2,14) mpy -- "Rd32 = mpy ( Rs32 , Rt32.h ) :<<1 :rnd :sat" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 1 1 1 0 1 1 0 1 1 0 1 s s s s s P P + t t t t t 1 0 0 d d d d d +# 1 1 1 0 1 1 0 1 1 0 1 s s s s s P P 0 t t t t t 1 0 0 d d d d d # mpyX2RndSatUpper(a,b,shift) sat_32( ( ((a * b) << 1 + (1<<(shift-1)) ) >> shift ) # Multiply (a * b) with additional x2 multiplier and use shifted and rounded result before saturation for a 32-bit result @@ -11378,7 +11851,7 @@ define pcodeop mpyX2RndSatUpper; # (v2,14) mpy -- "Rd32 = mpy ( Rs32 , Rt32.l ) :<<1 :rnd :sat" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 1 1 1 0 1 1 0 1 1 1 1 s s s s s P P + t t t t t 1 0 0 d d d d d +# 1 1 1 0 1 1 0 1 1 1 1 s s s s s P P 0 t t t t t 1 0 0 d d d d d :mpy^":<<1:rnd:sat" Rd5,rs5,rt5L EndPacket is iclass=14 & op2127=0x6f & op13=0 & op0507=4 & rs5 & rt5L & Rd5 & $(END_PACKET) { Rd5 = mpyX2RndSatUpper(rs5, rt5L, 16:1); @@ -11388,24 +11861,24 @@ define pcodeop mpyX2RndSatUpper; # (v2,14) mpy -- "Rd32 = mpy ( Rs32.h , Rt32.h )" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 1 1 1 0 1 1 0 0 0 0 0 s s s s s P P + t t t t t 0 1 1 d d d d d +# 1 1 1 0 1 1 0 0 0 0 0 s s s s s P P - t t t t t 0 1 1 d d d d d # # (v2,14) mpy -- "Rd32 = mpy ( Rs32.h , Rt32.l )" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 1 1 1 0 1 1 0 0 0 0 0 s s s s s P P + t t t t t 0 1 0 d d d d d +# 1 1 1 0 1 1 0 0 0 0 0 s s s s s P P - t t t t t 0 1 0 d d d d d # # (v2,14) mpy -- "Rd32 = mpy ( Rs32.l , Rt32.h )" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 1 1 1 0 1 1 0 0 0 0 0 s s s s s P P + t t t t t 0 0 1 d d d d d +# 1 1 1 0 1 1 0 0 0 0 0 s s s s s P P - t t t t t 0 0 1 d d d d d # # (v2,14) mpy -- "Rd32 = mpy ( Rs32.l , Rt32.l )" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 1 1 1 0 1 1 0 0 0 0 0 s s s s s P P + t t t t t 0 0 0 d d d d d +# 1 1 1 0 1 1 0 0 0 0 0 s s s s s P P - t t t t t 0 0 0 d d d d d -:mpy Rd5,Rs5HL06,Rt5HL05 EndPacket is iclass=14 & op2127=0x60 & op13=0 & op7=0 & Rs5HL06 & Rt5HL05 & Rd5 & $(END_PACKET) { +:mpy Rd5,Rs5HL06,Rt5HL05 EndPacket is iclass=14 & op2127=0x60 & op7=0 & Rs5HL06 & Rt5HL05 & Rd5 & $(END_PACKET) { Rd5 = sext(Rs5HL06) * sext(Rt5HL05); build EndPacket; } @@ -11413,24 +11886,24 @@ define pcodeop mpyX2RndSatUpper; # (v2,14) mpy -- "Rd32 = mpy ( Rs32.h , Rt32.h ) :<<1" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 1 1 1 0 1 1 0 0 1 0 0 s s s s s P P + t t t t t 0 1 1 d d d d d +# 1 1 1 0 1 1 0 0 1 0 0 s s s s s P P - t t t t t 0 1 1 d d d d d # # (v2,14) mpy -- "Rd32 = mpy ( Rs32.h , Rt32.l ) :<<1" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 1 1 1 0 1 1 0 0 1 0 0 s s s s s P P + t t t t t 0 1 0 d d d d d +# 1 1 1 0 1 1 0 0 1 0 0 s s s s s P P - t t t t t 0 1 0 d d d d d # # (v2,14) mpy -- "Rd32 = mpy ( Rs32.l , Rt32.h ) :<<1" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 1 1 1 0 1 1 0 0 1 0 0 s s s s s P P + t t t t t 0 0 1 d d d d d +# 1 1 1 0 1 1 0 0 1 0 0 s s s s s P P - t t t t t 0 0 1 d d d d d # # (v2,14) mpy -- "Rd32 = mpy ( Rs32.l , Rt32.l ) :<<1" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 1 1 1 0 1 1 0 0 1 0 0 s s s s s P P + t t t t t 0 0 0 d d d d d +# 1 1 1 0 1 1 0 0 1 0 0 s s s s s P P - t t t t t 0 0 0 d d d d d -:mpy^":<<1" Rd5,Rs5HL06,Rt5HL05 EndPacket is iclass=14 & op2127=0x64 & op13=0 & op7=0 & Rs5HL06 & Rt5HL05 & Rd5 & $(END_PACKET) { +:mpy^":<<1" Rd5,Rs5HL06,Rt5HL05 EndPacket is iclass=14 & op2127=0x64 & op7=0 & Rs5HL06 & Rt5HL05 & Rd5 & $(END_PACKET) { Rd5 = (sext(Rs5HL06) * sext(Rt5HL05)) << 1; build EndPacket; } @@ -11438,24 +11911,24 @@ define pcodeop mpyX2RndSatUpper; # (v2,14) mpy -- "Rd32 = mpy ( Rs32.h , Rt32.h ) :<<1 :rnd" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 1 1 1 0 1 1 0 0 1 0 1 s s s s s P P + t t t t t 0 1 1 d d d d d +# 1 1 1 0 1 1 0 0 1 0 1 s s s s s P P - t t t t t 0 1 1 d d d d d # # (v2,14) mpy -- "Rd32 = mpy ( Rs32.h , Rt32.l ) :<<1 :rnd" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 1 1 1 0 1 1 0 0 1 0 1 s s s s s P P + t t t t t 0 1 0 d d d d d +# 1 1 1 0 1 1 0 0 1 0 1 s s s s s P P - t t t t t 0 1 0 d d d d d # # (v2,14) mpy -- "Rd32 = mpy ( Rs32.l , Rt32.h ) :<<1 :rnd" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 1 1 1 0 1 1 0 0 1 0 1 s s s s s P P + t t t t t 0 0 1 d d d d d +# 1 1 1 0 1 1 0 0 1 0 1 s s s s s P P - t t t t t 0 0 1 d d d d d # # (v2,14) mpy -- "Rd32 = mpy ( Rs32.l , Rt32.l ) :<<1 :rnd" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 1 1 1 0 1 1 0 0 1 0 1 s s s s s P P + t t t t t 0 0 0 d d d d d +# 1 1 1 0 1 1 0 0 1 0 1 s s s s s P P - t t t t t 0 0 0 d d d d d -:mpy^":<<1:rnd" Rd5,Rs5HL06,Rt5HL05 EndPacket is iclass=14 & op2127=0x65 & op13=0 & op7=0 & Rs5HL06 & Rt5HL05 & Rd5 & $(END_PACKET) { +:mpy^":<<1:rnd" Rd5,Rs5HL06,Rt5HL05 EndPacket is iclass=14 & op2127=0x65 & op7=0 & Rs5HL06 & Rt5HL05 & Rd5 & $(END_PACKET) { tmp:4 = ((sext(Rs5HL06) * sext(Rt5HL05)) << 1) + 0x8000; Rd5 = tmp >> 16; # Use upper 16-bits of result build EndPacket; @@ -11464,28 +11937,28 @@ define pcodeop mpyX2RndSatUpper; # (v2,14) mpy -- "Rd32 = mpy ( Rs32.h , Rt32.h ) :<<1 :rnd :sat" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 1 1 1 0 1 1 0 0 1 0 1 s s s s s P P + t t t t t 1 1 1 d d d d d +# 1 1 1 0 1 1 0 0 1 0 1 s s s s s P P - t t t t t 1 1 1 d d d d d # # (v2,14) mpy -- "Rd32 = mpy ( Rs32.h , Rt32.l ) :<<1 :rnd :sat" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 1 1 1 0 1 1 0 0 1 0 1 s s s s s P P + t t t t t 1 1 0 d d d d d +# 1 1 1 0 1 1 0 0 1 0 1 s s s s s P P - t t t t t 1 1 0 d d d d d # # (v2,14) mpy -- "Rd32 = mpy ( Rs32.l , Rt32.h ) :<<1 :rnd :sat" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 1 1 1 0 1 1 0 0 1 0 1 s s s s s P P + t t t t t 1 0 1 d d d d d +# 1 1 1 0 1 1 0 0 1 0 1 s s s s s P P - t t t t t 1 0 1 d d d d d # # (v2,14) mpy -- "Rd32 = mpy ( Rs32.l , Rt32.l ) :<<1 :rnd :sat" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 1 1 1 0 1 1 0 0 1 0 1 s s s s s P P + t t t t t 1 0 0 d d d d d +# 1 1 1 0 1 1 0 0 1 0 1 s s s s s P P - t t t t t 1 0 0 d d d d d # mpyX2RndSat(a,b) sat_32( ( ((a * b) << 1 + (1<<(shift-1)) ) ) # Multiply (a * b) with additional x2 multiplier and use rounded result before saturation for a 32-bit result define pcodeop mpyX2RndSat; -:mpy^":<<1:rnd:sat" Rd5,Rs5HL06,Rt5HL05 EndPacket is iclass=14 & op2127=0x65 & op13=0 & op7=1 & Rs5HL06 & Rt5HL05 & Rd5 & $(END_PACKET) { +:mpy^":<<1:rnd:sat" Rd5,Rs5HL06,Rt5HL05 EndPacket is iclass=14 & op2127=0x65 & op7=1 & Rs5HL06 & Rt5HL05 & Rd5 & $(END_PACKET) { Rd5 = mpyX2RndSat(Rs5HL06, Rt5HL05); build EndPacket; } @@ -11493,28 +11966,28 @@ define pcodeop mpyX2RndSat; # (v2,14) mpy -- "Rd32 = mpy ( Rs32.h , Rt32.h ) :<<1 :sat" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 1 1 1 0 1 1 0 0 1 0 0 s s s s s P P + t t t t t 1 1 1 d d d d d +# 1 1 1 0 1 1 0 0 1 0 0 s s s s s P P - t t t t t 1 1 1 d d d d d # # (v2,14) mpy -- "Rd32 = mpy ( Rs32.h , Rt32.l ) :<<1 :sat" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 1 1 1 0 1 1 0 0 1 0 0 s s s s s P P + t t t t t 1 1 0 d d d d d +# 1 1 1 0 1 1 0 0 1 0 0 s s s s s P P - t t t t t 1 1 0 d d d d d # # (v2,14) mpy -- "Rd32 = mpy ( Rs32.l , Rt32.h ) :<<1 :sat" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 1 1 1 0 1 1 0 0 1 0 0 s s s s s P P + t t t t t 1 0 1 d d d d d +# 1 1 1 0 1 1 0 0 1 0 0 s s s s s P P - t t t t t 1 0 1 d d d d d # # (v2,14) mpy -- "Rd32 = mpy ( Rs32.l , Rt32.l ) :<<1 :sat" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 1 1 1 0 1 1 0 0 1 0 0 s s s s s P P + t t t t t 1 0 0 d d d d d +# 1 1 1 0 1 1 0 0 1 0 0 s s s s s P P - t t t t t 1 0 0 d d d d d # mpyX2Sat(a,b) sat_32( ((a * b) << 1 ) # Multiply (a * b) with additional x2 multiplier before saturation for a 32-bit result define pcodeop mpyX2Sat; -:mpy^":<<1:sat" Rd5,Rs5HL06,Rt5HL05 EndPacket is iclass=14 & op2127=0x64 & op13=0 & op7=1 & Rs5HL06 & Rt5HL05 & Rd5 & $(END_PACKET) { +:mpy^":<<1:sat" Rd5,Rs5HL06,Rt5HL05 EndPacket is iclass=14 & op2127=0x64 & op7=1 & Rs5HL06 & Rt5HL05 & Rd5 & $(END_PACKET) { Rd5 = mpyX2Sat(Rs5HL06, Rt5HL05); build EndPacket; } @@ -11522,24 +11995,24 @@ define pcodeop mpyX2Sat; # (v2,14) mpy -- "Rd32 = mpy ( Rs32.h , Rt32.h ) :rnd" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 1 1 1 0 1 1 0 0 0 0 1 s s s s s P P + t t t t t 0 1 1 d d d d d +# 1 1 1 0 1 1 0 0 0 0 1 s s s s s P P - t t t t t 0 1 1 d d d d d # # (v2,14) mpy -- "Rd32 = mpy ( Rs32.h , Rt32.l ) :rnd" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 1 1 1 0 1 1 0 0 0 0 1 s s s s s P P + t t t t t 0 1 0 d d d d d +# 1 1 1 0 1 1 0 0 0 0 1 s s s s s P P - t t t t t 0 1 0 d d d d d # # (v2,14) mpy -- "Rd32 = mpy ( Rs32.l , Rt32.h ) :rnd" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 1 1 1 0 1 1 0 0 0 0 1 s s s s s P P + t t t t t 0 0 1 d d d d d +# 1 1 1 0 1 1 0 0 0 0 1 s s s s s P P - t t t t t 0 0 1 d d d d d # # (v2,14) mpy -- "Rd32 = mpy ( Rs32.l , Rt32.l ) :rnd" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 1 1 1 0 1 1 0 0 0 0 1 s s s s s P P + t t t t t 0 0 0 d d d d d +# 1 1 1 0 1 1 0 0 0 0 1 s s s s s P P - t t t t t 0 0 0 d d d d d -:mpy^":rnd" Rd5,Rs5HL06,Rt5HL05 EndPacket is iclass=14 & op2127=0x61 & op13=0 & op7=0 & Rs5HL06 & Rt5HL05 & Rd5 & $(END_PACKET) { +:mpy^":rnd" Rd5,Rs5HL06,Rt5HL05 EndPacket is iclass=14 & op2127=0x61 & op7=0 & Rs5HL06 & Rt5HL05 & Rd5 & $(END_PACKET) { tmp:4 = (sext(Rs5HL06) * sext(Rt5HL05)) + 0x8000; Rd5 = tmp >> 16; # Use upper 16-bits of result build EndPacket; @@ -11548,28 +12021,28 @@ define pcodeop mpyX2Sat; # (v2,14) mpy -- "Rd32 = mpy ( Rs32.h , Rt32.h ) :rnd :sat" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 1 1 1 0 1 1 0 0 0 0 1 s s s s s P P + t t t t t 1 1 1 d d d d d +# 1 1 1 0 1 1 0 0 0 0 1 s s s s s P P - t t t t t 1 1 1 d d d d d # # (v2,14) mpy -- "Rd32 = mpy ( Rs32.h , Rt32.l ) :rnd :sat" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 1 1 1 0 1 1 0 0 0 0 1 s s s s s P P + t t t t t 1 1 0 d d d d d +# 1 1 1 0 1 1 0 0 0 0 1 s s s s s P P - t t t t t 1 1 0 d d d d d # # (v2,14) mpy -- "Rd32 = mpy ( Rs32.l , Rt32.h ) :rnd :sat" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 1 1 1 0 1 1 0 0 0 0 1 s s s s s P P + t t t t t 1 0 1 d d d d d +# 1 1 1 0 1 1 0 0 0 0 1 s s s s s P P - t t t t t 1 0 1 d d d d d # # (v2,14) mpy -- "Rd32 = mpy ( Rs32.l , Rt32.l ) :rnd :sat" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 1 1 1 0 1 1 0 0 0 0 1 s s s s s P P + t t t t t 1 0 0 d d d d d +# 1 1 1 0 1 1 0 0 0 0 1 s s s s s P P - t t t t t 1 0 0 d d d d d # mpyRndSat(a,b) sat_32( ( ((a * b) + (1<<(shift-1)) ) ) # Multiply (a * b) and use rounded result before saturation for a 32-bit result define pcodeop mpyRndSat; -:mpy^":rnd:sat" Rd5,Rs5HL06,Rt5HL05 EndPacket is iclass=14 & op2127=0x61 & op13=0 & op7=1 & Rs5HL06 & Rt5HL05 & Rd5 & $(END_PACKET) { +:mpy^":rnd:sat" Rd5,Rs5HL06,Rt5HL05 EndPacket is iclass=14 & op2127=0x61 & op7=1 & Rs5HL06 & Rt5HL05 & Rd5 & $(END_PACKET) { Rd5 = mpyRndSat(Rs5HL06, Rt5HL05); build EndPacket; } @@ -11577,28 +12050,28 @@ define pcodeop mpyRndSat; # (v2,14) mpy -- "Rd32 = mpy ( Rs32.h , Rt32.h ) :sat" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 1 1 1 0 1 1 0 0 0 0 0 s s s s s P P + t t t t t 1 1 1 d d d d d +# 1 1 1 0 1 1 0 0 0 0 0 s s s s s P P - t t t t t 1 1 1 d d d d d # # (v2,14) mpy -- "Rd32 = mpy ( Rs32.h , Rt32.l ) :sat" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 1 1 1 0 1 1 0 0 0 0 0 s s s s s P P + t t t t t 1 1 0 d d d d d +# 1 1 1 0 1 1 0 0 0 0 0 s s s s s P P - t t t t t 1 1 0 d d d d d # # (v2,14) mpy -- "Rd32 = mpy ( Rs32.l , Rt32.h ) :sat" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 1 1 1 0 1 1 0 0 0 0 0 s s s s s P P + t t t t t 1 0 1 d d d d d +# 1 1 1 0 1 1 0 0 0 0 0 s s s s s P P - t t t t t 1 0 1 d d d d d # # (v2,14) mpy -- "Rd32 = mpy ( Rs32.l , Rt32.l ) :sat" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 1 1 1 0 1 1 0 0 0 0 0 s s s s s P P + t t t t t 1 0 0 d d d d d +# 1 1 1 0 1 1 0 0 0 0 0 s s s s s P P - t t t t t 1 0 0 d d d d d # mpySat(a,b) sat_32( a * b ) # Multiply (a * b) with saturation for a 32-bit result define pcodeop mpySat; -:mpy^":sat" Rd5,Rs5HL06,Rt5HL05 EndPacket is iclass=14 & op2127=0x60 & op13=0 & op7=1 & Rs5HL06 & Rt5HL05 & Rd5 & $(END_PACKET) { +:mpy^":sat" Rd5,Rs5HL06,Rt5HL05 EndPacket is iclass=14 & op2127=0x60 & op7=1 & Rs5HL06 & Rt5HL05 & Rd5 & $(END_PACKET) { Rd5 = mpySat(Rs5HL06, Rt5HL05); build EndPacket; } @@ -11606,7 +12079,7 @@ define pcodeop mpySat; # (v2,14) mpy -- "Rdd32 = mpy ( Rs32 , Rt32 )" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 1 1 1 0 0 1 0 1 0 0 0 s s s s s P P + t t t t t 0 0 0 d d d d d +# 1 1 1 0 0 1 0 1 0 0 0 s s s s s P P 0 t t t t t 0 0 0 d d d d d :mpy Rdd5,rs5,rt5 EndPacket is iclass=14 & op2127=0x28 & op13=0 & op0507=0 & rs5 & rt5 & Rdd5 & $(END_PACKET) { Rdd5 = sext(rs5) * sext(rt5); @@ -11616,24 +12089,24 @@ define pcodeop mpySat; # (v2,14) mpy -- "Rdd32 = mpy ( Rs32.h , Rt32.h )" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 1 1 1 0 0 1 0 0 0 0 0 s s s s s P P + t t t t t + 1 1 d d d d d +# 1 1 1 0 0 1 0 0 0 0 0 s s s s s P P - t t t t t - 1 1 d d d d d # # (v2,14) mpy -- "Rdd32 = mpy ( Rs32.h , Rt32.l )" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 1 1 1 0 0 1 0 0 0 0 0 s s s s s P P + t t t t t + 1 0 d d d d d +# 1 1 1 0 0 1 0 0 0 0 0 s s s s s P P - t t t t t - 1 0 d d d d d # # (v2,14) mpy -- "Rdd32 = mpy ( Rs32.l , Rt32.h )" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 1 1 1 0 0 1 0 0 0 0 0 s s s s s P P + t t t t t + 0 1 d d d d d +# 1 1 1 0 0 1 0 0 0 0 0 s s s s s P P - t t t t t - 0 1 d d d d d # # (v2,14) mpy -- "Rdd32 = mpy ( Rs32.l , Rt32.l )" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 1 1 1 0 0 1 0 0 0 0 0 s s s s s P P + t t t t t + 0 0 d d d d d +# 1 1 1 0 0 1 0 0 0 0 0 s s s s s P P - t t t t t - 0 0 d d d d d -:mpy Rdd5,Rs5HL06,Rt5HL05 EndPacket is iclass=14 & op2127=0x20 & op13=0 & op7=0 & Rs5HL06 & Rt5HL05 & Rdd5 & $(END_PACKET) { +:mpy Rdd5,Rs5HL06,Rt5HL05 EndPacket is iclass=14 & op2127=0x20 & Rs5HL06 & Rt5HL05 & Rdd5 & $(END_PACKET) { Rdd5 = sext(Rs5HL06) * sext(Rt5HL05); build EndPacket; } @@ -11641,24 +12114,24 @@ define pcodeop mpySat; # (v2,14) mpy -- "Rdd32 = mpy ( Rs32.h , Rt32.h ) :<<1" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 1 1 1 0 0 1 0 0 1 0 0 s s s s s P P + t t t t t + 1 1 d d d d d +# 1 1 1 0 0 1 0 0 1 0 0 s s s s s P P - t t t t t - 1 1 d d d d d # # (v2,14) mpy -- "Rdd32 = mpy ( Rs32.h , Rt32.l ) :<<1" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 1 1 1 0 0 1 0 0 1 0 0 s s s s s P P + t t t t t + 1 0 d d d d d +# 1 1 1 0 0 1 0 0 1 0 0 s s s s s P P - t t t t t - 1 0 d d d d d # # (v2,14) mpy -- "Rdd32 = mpy ( Rs32.l , Rt32.h ) :<<1" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 1 1 1 0 0 1 0 0 1 0 0 s s s s s P P + t t t t t + 0 1 d d d d d +# 1 1 1 0 0 1 0 0 1 0 0 s s s s s P P - t t t t t - 0 1 d d d d d # # (v2,14) mpy -- "Rdd32 = mpy ( Rs32.l , Rt32.l ) :<<1" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 1 1 1 0 0 1 0 0 1 0 0 s s s s s P P + t t t t t + 0 0 d d d d d +# 1 1 1 0 0 1 0 0 1 0 0 s s s s s P P - t t t t t - 0 0 d d d d d -:mpy^":<<1" Rdd5,Rs5HL06,Rt5HL05 EndPacket is iclass=14 & op2127=0x24 & op13=0 & op7=0 & Rs5HL06 & Rt5HL05 & Rdd5 & $(END_PACKET) { +:mpy^":<<1" Rdd5,Rs5HL06,Rt5HL05 EndPacket is iclass=14 & op2127=0x24 & Rs5HL06 & Rt5HL05 & Rdd5 & $(END_PACKET) { Rdd5 = (sext(Rs5HL06) * sext(Rt5HL05)) << 1; build EndPacket; } @@ -11666,24 +12139,24 @@ define pcodeop mpySat; # (v2,14) mpy -- "Rdd32 = mpy ( Rs32.h , Rt32.h ) :<<1 :rnd" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 1 1 1 0 0 1 0 0 1 0 1 s s s s s P P + t t t t t + 1 1 d d d d d +# 1 1 1 0 0 1 0 0 1 0 1 s s s s s P P - t t t t t - 1 1 d d d d d # # (v2,14) mpy -- "Rdd32 = mpy ( Rs32.h , Rt32.l ) :<<1 :rnd" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 1 1 1 0 0 1 0 0 1 0 1 s s s s s P P + t t t t t + 1 0 d d d d d +# 1 1 1 0 0 1 0 0 1 0 1 s s s s s P P - t t t t t - 1 0 d d d d d # # (v2,14) mpy -- "Rdd32 = mpy ( Rs32.l , Rt32.h ) :<<1 :rnd" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 1 1 1 0 0 1 0 0 1 0 1 s s s s s P P + t t t t t + 0 1 d d d d d +# 1 1 1 0 0 1 0 0 1 0 1 s s s s s P P - t t t t t - 0 1 d d d d d # # (v2,14) mpy -- "Rdd32 = mpy ( Rs32.l , Rt32.l ) :<<1 :rnd" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 1 1 1 0 0 1 0 0 1 0 1 s s s s s P P + t t t t t + 0 0 d d d d d +# 1 1 1 0 0 1 0 0 1 0 1 s s s s s P P - t t t t t - 0 0 d d d d d -:mpy^":<<1:rnd" Rdd5,Rs5HL06,Rt5HL05 EndPacket is iclass=14 & op2127=0x25 & op13=0 & op7=0 & Rs5HL06 & Rt5HL05 & Rdd5 & $(END_PACKET) { +:mpy^":<<1:rnd" Rdd5,Rs5HL06,Rt5HL05 EndPacket is iclass=14 & op2127=0x25 & Rs5HL06 & Rt5HL05 & Rdd5 & $(END_PACKET) { tmp:8 = ((sext(Rs5HL06) * sext(Rt5HL05)) << 1) + 0x80000000; Rdd5 = tmp >> 32; build EndPacket; @@ -11692,24 +12165,24 @@ define pcodeop mpySat; # (v2,14) mpy -- "Rdd32 = mpy ( Rs32.h , Rt32.h ) :rnd" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 1 1 1 0 0 1 0 0 0 0 1 s s s s s P P + t t t t t + 1 1 d d d d d +# 1 1 1 0 0 1 0 0 0 0 1 s s s s s P P - t t t t t - 1 1 d d d d d # # (v2,14) mpy -- "Rdd32 = mpy ( Rs32.h , Rt32.l ) :rnd" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 1 1 1 0 0 1 0 0 0 0 1 s s s s s P P + t t t t t + 1 0 d d d d d +# 1 1 1 0 0 1 0 0 0 0 1 s s s s s P P - t t t t t - 1 0 d d d d d # # (v2,14) mpy -- "Rdd32 = mpy ( Rs32.l , Rt32.h ) :rnd" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 1 1 1 0 0 1 0 0 0 0 1 s s s s s P P + t t t t t + 0 1 d d d d d +# 1 1 1 0 0 1 0 0 0 0 1 s s s s s P P - t t t t t - 0 1 d d d d d # # (v2,14) mpy -- "Rdd32 = mpy ( Rs32.l , Rt32.l ) :rnd" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 1 1 1 0 0 1 0 0 0 0 1 s s s s s P P + t t t t t + 0 0 d d d d d +# 1 1 1 0 0 1 0 0 0 0 1 s s s s s P P - t t t t t - 0 0 d d d d d -:mpy^":rnd" Rdd5,Rs5HL06,Rt5HL05 EndPacket is iclass=14 & op2127=0x21 & op13=0 & op7=0 & Rs5HL06 & Rt5HL05 & Rdd5 & $(END_PACKET) { +:mpy^":rnd" Rdd5,Rs5HL06,Rt5HL05 EndPacket is iclass=14 & op2127=0x21 & Rs5HL06 & Rt5HL05 & Rdd5 & $(END_PACKET) { tmp:8 = (sext(Rs5HL06) * sext(Rt5HL05)) + 0x80000000; Rdd5 = tmp >> 32; build EndPacket; @@ -11718,7 +12191,7 @@ define pcodeop mpySat; # (v4,14) mpy -- "Rx32 += mpy ( Rs32 , Rt32 ) :<<1 :sat" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 1 1 1 0 1 1 1 1 0 1 1 s s s s s P P + t t t t t + 0 0 x x x x x +# 1 1 1 0 1 1 1 1 0 1 1 s s s s s P P 0 t t t t t 0 0 0 x x x x x # mpyX2SatAddUpper(a,b,shift,accumulator) sat_32( ((a * b) << 1) >> shift + accumulator ) # Multiply (a * b) with additional x2 multiplier and shifted result added to accumulator before saturation for a 32-bit result @@ -11732,28 +12205,28 @@ define pcodeop mpyX2SatAddUpper; # (v2,14) mpy -- "Rx32 += mpy ( Rs32.h , Rt32.h ) :<<1 :sat" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 1 1 1 0 1 1 1 0 1 0 0 s s s s s P P + t t t t t 1 1 1 x x x x x +# 1 1 1 0 1 1 1 0 1 0 0 s s s s s P P - t t t t t 1 1 1 x x x x x # # (v2,14) mpy -- "Rx32 += mpy ( Rs32.h , Rt32.l ) :<<1 :sat" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 1 1 1 0 1 1 1 0 1 0 0 s s s s s P P + t t t t t 1 1 0 x x x x x +# 1 1 1 0 1 1 1 0 1 0 0 s s s s s P P - t t t t t 1 1 0 x x x x x # # (v2,14) mpy -- "Rx32 += mpy ( Rs32.l , Rt32.h ) :<<1 :sat" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 1 1 1 0 1 1 1 0 1 0 0 s s s s s P P + t t t t t 1 0 1 x x x x x +# 1 1 1 0 1 1 1 0 1 0 0 s s s s s P P - t t t t t 1 0 1 x x x x x # # (v2,14) mpy -- "Rx32 += mpy ( Rs32.l , Rt32.l ) :<<1 :sat" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 1 1 1 0 1 1 1 0 1 0 0 s s s s s P P + t t t t t 1 0 0 x x x x x +# 1 1 1 0 1 1 1 0 1 0 0 s s s s s P P - t t t t t 1 0 0 x x x x x # mpyX2SatAdd(a,b,accumulator) sat_32( ((a * b) << 1) + accumulator ) # Multiply (a * b) with additional x2 multiplier and add to accumulator before saturation for a 32-bit result define pcodeop mpyX2SatAdd; -:mpy+=^":<<1:sat" Rd5,Rs5HL06,Rt5HL05 EndPacket is iclass=14 & op2127=0x74 & op13=0 & op7=1 & Rs5HL06 & Rt5HL05 & rd5 & Rd5 & $(END_PACKET) { +:mpy+=^":<<1:sat" Rd5,Rs5HL06,Rt5HL05 EndPacket is iclass=14 & op2127=0x74 & op7=1 & Rs5HL06 & Rt5HL05 & rd5 & Rd5 & $(END_PACKET) { Rd5 = mpyX2SatAdd(Rs5HL06, Rt5HL05, rd5); build EndPacket; } @@ -11761,24 +12234,24 @@ define pcodeop mpyX2SatAdd; # (v2,14) mpy -- "Rx32 += mpy ( Rs32.h , Rt32.h )" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 1 1 1 0 1 1 1 0 0 0 0 s s s s s P P + t t t t t 0 1 1 x x x x x +# 1 1 1 0 1 1 1 0 0 0 0 s s s s s P P - t t t t t 0 1 1 x x x x x # # (v2,14) mpy -- "Rx32 += mpy ( Rs32.h , Rt32.l )" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 1 1 1 0 1 1 1 0 0 0 0 s s s s s P P + t t t t t 0 1 0 x x x x x +# 1 1 1 0 1 1 1 0 0 0 0 s s s s s P P - t t t t t 0 1 0 x x x x x # # (v2,14) mpy -- "Rx32 += mpy ( Rs32.l , Rt32.h )" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 1 1 1 0 1 1 1 0 0 0 0 s s s s s P P + t t t t t 0 0 1 x x x x x +# 1 1 1 0 1 1 1 0 0 0 0 s s s s s P P - t t t t t 0 0 1 x x x x x # # (v2,14) mpy -- "Rx32 += mpy ( Rs32.l , Rt32.l )" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 1 1 1 0 1 1 1 0 0 0 0 s s s s s P P + t t t t t 0 0 0 x x x x x +# 1 1 1 0 1 1 1 0 0 0 0 s s s s s P P - t t t t t 0 0 0 x x x x x -:mpy+= Rd5,Rs5HL06,Rt5HL05 EndPacket is iclass=14 & op2127=0x70 & op13=0 & op7=0 & Rs5HL06 & Rt5HL05 & Rd5 & rd5 & $(END_PACKET) { +:mpy+= Rd5,Rs5HL06,Rt5HL05 EndPacket is iclass=14 & op2127=0x70 & op7=0 & Rs5HL06 & Rt5HL05 & Rd5 & rd5 & $(END_PACKET) { Rd5 = rd5 + (sext(Rs5HL06) * sext(Rt5HL05)); build EndPacket; } @@ -11786,24 +12259,24 @@ define pcodeop mpyX2SatAdd; # (v2,14) mpy -- "Rx32 += mpy ( Rs32.h , Rt32.h ) :<<1" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 1 1 1 0 1 1 1 0 1 0 0 s s s s s P P + t t t t t 0 1 1 x x x x x +# 1 1 1 0 1 1 1 0 1 0 0 s s s s s P P - t t t t t 0 1 1 x x x x x # # (v2,14) mpy -- "Rx32 += mpy ( Rs32.h , Rt32.l ) :<<1" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 1 1 1 0 1 1 1 0 1 0 0 s s s s s P P + t t t t t 0 1 0 x x x x x +# 1 1 1 0 1 1 1 0 1 0 0 s s s s s P P - t t t t t 0 1 0 x x x x x # # (v2,14) mpy -- "Rx32 += mpy ( Rs32.l , Rt32.h ) :<<1" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 1 1 1 0 1 1 1 0 1 0 0 s s s s s P P + t t t t t 0 0 1 x x x x x +# 1 1 1 0 1 1 1 0 1 0 0 s s s s s P P - t t t t t 0 0 1 x x x x x # # (v2,14) mpy -- "Rx32 += mpy ( Rs32.l , Rt32.l ) :<<1" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 1 1 1 0 1 1 1 0 1 0 0 s s s s s P P + t t t t t 0 0 0 x x x x x +# 1 1 1 0 1 1 1 0 1 0 0 s s s s s P P - t t t t t 0 0 0 x x x x x -:mpy+=^":<<1" Rd5,Rs5HL06,Rt5HL05 EndPacket is iclass=14 & op2127=0x74 & op13=0 & op7=0 & Rs5HL06 & Rt5HL05 & Rd5 & rd5 & $(END_PACKET) { +:mpy+=^":<<1" Rd5,Rs5HL06,Rt5HL05 EndPacket is iclass=14 & op2127=0x74 & op7=0 & Rs5HL06 & Rt5HL05 & Rd5 & rd5 & $(END_PACKET) { tmp:4 = sext(Rs5HL06) * sext(Rt5HL05); Rd5 = rd5 + (tmp << 1); build EndPacket; @@ -11812,28 +12285,28 @@ define pcodeop mpyX2SatAdd; # (v2,14) mpy -- "Rx32 += mpy ( Rs32.h , Rt32.h ) :sat" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 1 1 1 0 1 1 1 0 0 0 0 s s s s s P P + t t t t t 1 1 1 x x x x x +# 1 1 1 0 1 1 1 0 0 0 0 s s s s s P P - t t t t t 1 1 1 x x x x x # # (v2,14) mpy -- "Rx32 += mpy ( Rs32.h , Rt32.l ) :sat" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 1 1 1 0 1 1 1 0 0 0 0 s s s s s P P + t t t t t 1 1 0 x x x x x +# 1 1 1 0 1 1 1 0 0 0 0 s s s s s P P - t t t t t 1 1 0 x x x x x # # (v2,14) mpy -- "Rx32 += mpy ( Rs32.l , Rt32.h ) :sat" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 1 1 1 0 1 1 1 0 0 0 0 s s s s s P P + t t t t t 1 0 1 x x x x x +# 1 1 1 0 1 1 1 0 0 0 0 s s s s s P P - t t t t t 1 0 1 x x x x x # # (v2,14) mpy -- "Rx32 += mpy ( Rs32.l , Rt32.l ) :sat" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 1 1 1 0 1 1 1 0 0 0 0 s s s s s P P + t t t t t 1 0 0 x x x x x +# 1 1 1 0 1 1 1 0 0 0 0 s s s s s P P - t t t t t 1 0 0 x x x x x # mpySatAdd(a,b,accumulator) sat_32( (a * b) + accumulator ) # Multiply (a * b) with additional x2 multiplier and add to accumulator before saturation for a 32-bit result define pcodeop mpySatAdd; -:mpy+=^":sat" Rd5,Rs5HL06,Rt5HL05 EndPacket is iclass=14 & op2127=0x70 & op13=0 & op7=1 & Rs5HL06 & Rt5HL05 & rd5 & Rd5 & $(END_PACKET) { +:mpy+=^":sat" Rd5,Rs5HL06,Rt5HL05 EndPacket is iclass=14 & op2127=0x70 & op7=1 & Rs5HL06 & Rt5HL05 & rd5 & Rd5 & $(END_PACKET) { Rd5 = mpySatAdd(Rs5HL06, Rt5HL05, rd5); build EndPacket; } @@ -11841,7 +12314,7 @@ define pcodeop mpySatAdd; # (v4,14) mpy -- "Rx32 -= mpy ( Rs32 , Rt32 ) :<<1 :sat" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 1 1 1 0 1 1 1 1 0 1 1 s s s s s P P + t t t t t + 0 1 x x x x x +# 1 1 1 0 1 1 1 1 0 1 1 s s s s s P P 0 t t t t t 0 0 1 x x x x x # mpyX2SatSubUpper(a,b,shift,accumulator) sat_32( accumulator - ((a * b) << 1) >> shift ) # Multiply (a * b) with additional x2 multiplier and shifted result subtracted from accumulator before saturation for a 32-bit result @@ -11855,12 +12328,12 @@ define pcodeop mpyX2SatSubUpper; # (v2,14) mpy -- "Rx32 -= mpy ( Rs32.h , Rt32.h ) :<<1 :sat" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 1 1 1 0 1 1 1 0 1 0 1 s s s s s P P + t t t t t 1 1 1 x x x x x +# 1 1 1 0 1 1 1 0 1 0 1 s s s s s P P - t t t t t 1 1 1 x x x x x # # (v2,14) mpy -- "Rx32 -= mpy ( Rs32.h , Rt32.l ) :<<1 :sat" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 1 1 1 0 1 1 1 0 1 0 1 s s s s s P P + t t t t t 1 1 0 x x x x x +# 1 1 1 0 1 1 1 0 1 0 1 s s s s s P P - t t t t t 1 1 0 x x x x x # # (v2,14) mpy -- "Rx32 -= mpy ( Rs32.l , Rt32.h ) :<<1 :sat" # _________________________________________________________________________________________________ @@ -11870,13 +12343,13 @@ define pcodeop mpyX2SatSubUpper; # (v2,14) mpy -- "Rx32 -= mpy ( Rs32.l , Rt32.l ) :<<1 :sat" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 1 1 1 0 1 1 1 0 1 0 1 s s s s s P P + t t t t t 1 0 0 x x x x x +# 1 1 1 0 1 1 1 0 1 0 1 s s s s s P P - t t t t t 1 0 0 x x x x x # mpyX2SatSub(a,b,accumulator) sat_32( accumulator - ((a * b) << 1) ) # Multiply (a * b) with additional x2 multiplier and subtract from accumulator before saturation for a 32-bit result define pcodeop mpyX2SatSub; -:mpy-=^":<<1:sat" Rd5,Rs5HL06,Rt5HL05 EndPacket is iclass=14 & op2127=0x75 & op13=0 & op7=1 & Rs5HL06 & Rt5HL05 & rd5 & Rd5 & $(END_PACKET) { +:mpy-=^":<<1:sat" Rd5,Rs5HL06,Rt5HL05 EndPacket is iclass=14 & op2127=0x75 & op7=1 & Rs5HL06 & Rt5HL05 & rd5 & Rd5 & $(END_PACKET) { Rd5 = mpyX2SatSub(Rs5HL06, Rt5HL05, rd5); build EndPacket; } @@ -11884,24 +12357,24 @@ define pcodeop mpyX2SatSub; # (v2,14) mpy -- "Rx32 -= mpy ( Rs32.h , Rt32.h )" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 1 1 1 0 1 1 1 0 0 0 1 s s s s s P P + t t t t t 0 1 1 x x x x x +# 1 1 1 0 1 1 1 0 0 0 1 s s s s s P P - t t t t t 0 1 1 x x x x x # # (v2,14) mpy -- "Rx32 -= mpy ( Rs32.h , Rt32.l )" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 1 1 1 0 1 1 1 0 0 0 1 s s s s s P P + t t t t t 0 1 0 x x x x x +# 1 1 1 0 1 1 1 0 0 0 1 s s s s s P P - t t t t t 0 1 0 x x x x x # # (v2,14) mpy -- "Rx32 -= mpy ( Rs32.l , Rt32.h )" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 1 1 1 0 1 1 1 0 0 0 1 s s s s s P P + t t t t t 0 0 1 x x x x x +# 1 1 1 0 1 1 1 0 0 0 1 s s s s s P P - t t t t t 0 0 1 x x x x x # # (v2,14) mpy -- "Rx32 -= mpy ( Rs32.l , Rt32.l )" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 1 1 1 0 1 1 1 0 0 0 1 s s s s s P P + t t t t t 0 0 0 x x x x x +# 1 1 1 0 1 1 1 0 0 0 1 s s s s s P P - t t t t t 0 0 0 x x x x x -:mpy-= Rd5,Rs5HL06,Rt5HL05 EndPacket is iclass=14 & op2127=0x71 & op13=0 & op7=0 & Rs5HL06 & Rt5HL05 & Rd5 & rd5 & $(END_PACKET) { +:mpy-= Rd5,Rs5HL06,Rt5HL05 EndPacket is iclass=14 & op2127=0x71 & op7=0 & Rs5HL06 & Rt5HL05 & Rd5 & rd5 & $(END_PACKET) { Rd5 = rd5 - (sext(Rs5HL06) * sext(Rt5HL05)); build EndPacket; } @@ -11909,25 +12382,24 @@ define pcodeop mpyX2SatSub; # (v2,14) mpy -- "Rx32 -= mpy ( Rs32.h , Rt32.h ) :<<1" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 1 1 1 0 1 1 1 0 1 0 1 s s s s s P P + t t t t t 0 1 1 x x x x x +# 1 1 1 0 1 1 1 0 1 0 1 s s s s s P P - t t t t t 0 1 1 x x x x x # # (v2,14) mpy -- "Rx32 -= mpy ( Rs32.h , Rt32.l ) :<<1" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 1 1 1 0 1 1 1 0 1 0 1 s s s s s P P + t t t t t 0 1 0 x x x x x +# 1 1 1 0 1 1 1 0 1 0 1 s s s s s P P - t t t t t 0 1 0 x x x x x # # (v2,14) mpy -- "Rx32 -= mpy ( Rs32.l , Rt32.h ) :<<1" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 1 1 1 0 1 1 1 0 1 0 1 s s s s s P P + t t t t t 0 0 1 x x x x x +# 1 1 1 0 1 1 1 0 1 0 1 s s s s s P P - t t t t t 0 0 1 x x x x x # # (v2,14) mpy -- "Rx32 -= mpy ( Rs32.l , Rt32.l ) :<<1" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 1 1 1 0 1 1 1 0 1 0 1 s s s s s P P + t t t t t 0 0 0 x x x x x +# 1 1 1 0 1 1 1 0 1 0 1 s s s s s P P - t t t t t 0 0 0 x x x x x -:mpy-=^":<<1" Rd5,Rs5HL06,Rt5HL05 EndPacket is iclass=14 & op2127=0x75 & op13=0 & op7=0 & Rs5HL06 & Rt5HL05 & Rd5 & rd5 & $(END_PACKET) { - # TODO: is only upper 16-bits of mpy result used? +:mpy-=^":<<1" Rd5,Rs5HL06,Rt5HL05 EndPacket is iclass=14 & op2127=0x75 & op7=0 & Rs5HL06 & Rt5HL05 & Rd5 & rd5 & $(END_PACKET) { tmp:4 = sext(Rs5HL06) * sext(Rt5HL05); Rd5 = rd5 - (tmp << 1); build EndPacket; @@ -11936,28 +12408,28 @@ define pcodeop mpyX2SatSub; # (v2,14) mpy -- "Rx32 -= mpy ( Rs32.h , Rt32.h ) :sat" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 1 1 1 0 1 1 1 0 0 0 1 s s s s s P P + t t t t t 1 1 1 x x x x x +# 1 1 1 0 1 1 1 0 0 0 1 s s s s s P P - t t t t t 1 1 1 x x x x x # # (v2,14) mpy -- "Rx32 -= mpy ( Rs32.h , Rt32.l ) :sat" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 1 1 1 0 1 1 1 0 0 0 1 s s s s s P P + t t t t t 1 1 0 x x x x x +# 1 1 1 0 1 1 1 0 0 0 1 s s s s s P P - t t t t t 1 1 0 x x x x x # # (v2,14) mpy -- "Rx32 -= mpy ( Rs32.l , Rt32.h ) :sat" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 1 1 1 0 1 1 1 0 0 0 1 s s s s s P P + t t t t t 1 0 1 x x x x x +# 1 1 1 0 1 1 1 0 0 0 1 s s s s s P P - t t t t t 1 0 1 x x x x x # # (v2,14) mpy -- "Rx32 -= mpy ( Rs32.l , Rt32.l ) :sat" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 1 1 1 0 1 1 1 0 0 0 1 s s s s s P P + t t t t t 1 0 0 x x x x x +# 1 1 1 0 1 1 1 0 0 0 1 s s s s s P P - t t t t t 1 0 0 x x x x x # mpySatSub(a,b,accumulator) sat_32( accumulator - (a * b) ) # Multiply (a * b) and subtract from accumulator before saturation for a 32-bit result define pcodeop mpySatSub; -:mpy-=^":sat" Rd5,Rs5HL06,Rt5HL05 EndPacket is iclass=14 & op2127=0x71 & op13=0 & op7=1 & Rs5HL06 & Rt5HL05 & rd5 & Rd5 & $(END_PACKET) { +:mpy-=^":sat" Rd5,Rs5HL06,Rt5HL05 EndPacket is iclass=14 & op2127=0x71 & op7=1 & Rs5HL06 & Rt5HL05 & rd5 & Rd5 & $(END_PACKET) { Rd5 = mpySatSub(Rs5HL06, Rt5HL05, rd5); build EndPacket; } @@ -11965,7 +12437,7 @@ define pcodeop mpySatSub; # (v2,14) mpy -- "Rxx32 += mpy ( Rs32 , Rt32 )" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 1 1 1 0 0 1 1 1 0 0 0 s s s s s P P + t t t t t 0 0 0 x x x x x +# 1 1 1 0 0 1 1 1 0 0 0 s s s s s P P 0 t t t t t 0 0 0 x x x x x :mpy+= Rdd5,rs5,rt5 EndPacket is iclass=14 & op2127=0x38 & op13=0 & op0507=0 & rs5 & rt5 & Rdd5 & rdd5 & $(END_PACKET) { tmp:8 = sext(rs5) * sext(rt5); @@ -11976,24 +12448,24 @@ define pcodeop mpySatSub; # (v2,14) mpy -- "Rxx32 += mpy ( Rs32.h , Rt32.h )" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 1 1 1 0 0 1 1 0 0 0 0 s s s s s P P + t t t t t 0 1 1 x x x x x +# 1 1 1 0 0 1 1 0 0 0 0 s s s s s P P - t t t t t 0 1 1 x x x x x # # (v2,14) mpy -- "Rxx32 += mpy ( Rs32.h , Rt32.l )" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 1 1 1 0 0 1 1 0 0 0 0 s s s s s P P + t t t t t 0 1 0 x x x x x +# 1 1 1 0 0 1 1 0 0 0 0 s s s s s P P - t t t t t 0 1 0 x x x x x # # (v2,14) mpy -- "Rxx32 += mpy ( Rs32.l , Rt32.h )" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 1 1 1 0 0 1 1 0 0 0 0 s s s s s P P + t t t t t 0 0 1 x x x x x +# 1 1 1 0 0 1 1 0 0 0 0 s s s s s P P - t t t t t 0 0 1 x x x x x # # (v2,14) mpy -- "Rxx32 += mpy ( Rs32.l , Rt32.l )" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 1 1 1 0 0 1 1 0 0 0 0 s s s s s P P + t t t t t 0 0 0 x x x x x +# 1 1 1 0 0 1 1 0 0 0 0 s s s s s P P - t t t t t 0 0 0 x x x x x -:mpy+= Rdd5,Rs5HL06,Rt5HL05 EndPacket is iclass=14 & op2127=0x30 & op13=0 & op7=0 & Rs5HL06 & Rt5HL05 & Rdd5 & rdd5 & $(END_PACKET) { +:mpy+= Rdd5,Rs5HL06,Rt5HL05 EndPacket is iclass=14 & op2127=0x30 & op7=0 & Rs5HL06 & Rt5HL05 & Rdd5 & rdd5 & $(END_PACKET) { tmp:8 = sext(Rs5HL06) * sext(Rt5HL05); Rdd5 = rdd5 + tmp; build EndPacket; @@ -12002,24 +12474,24 @@ define pcodeop mpySatSub; # (v2,14) mpy -- "Rxx32 += mpy ( Rs32.h , Rt32.h ) :<<1" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 1 1 1 0 0 1 1 0 1 0 0 s s s s s P P + t t t t t 0 1 1 x x x x x +# 1 1 1 0 0 1 1 0 1 0 0 s s s s s P P - t t t t t 0 1 1 x x x x x # # (v2,14) mpy -- "Rxx32 += mpy ( Rs32.h , Rt32.l ) :<<1" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 1 1 1 0 0 1 1 0 1 0 0 s s s s s P P + t t t t t 0 1 0 x x x x x +# 1 1 1 0 0 1 1 0 1 0 0 s s s s s P P - t t t t t 0 1 0 x x x x x # # (v2,14) mpy -- "Rxx32 += mpy ( Rs32.l , Rt32.h ) :<<1" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 1 1 1 0 0 1 1 0 1 0 0 s s s s s P P + t t t t t 0 0 1 x x x x x +# 1 1 1 0 0 1 1 0 1 0 0 s s s s s P P - t t t t t 0 0 1 x x x x x # # (v2,14) mpy -- "Rxx32 += mpy ( Rs32.l , Rt32.l ) :<<1" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 1 1 1 0 0 1 1 0 1 0 0 s s s s s P P + t t t t t 0 0 0 x x x x x +# 1 1 1 0 0 1 1 0 1 0 0 s s s s s P P - t t t t t 0 0 0 x x x x x -:mpy+=^":<<1" Rdd5,Rs5HL06,Rt5HL05 EndPacket is iclass=14 & op2127=0x34 & op13=0 & op7=0 & Rs5HL06 & Rt5HL05 & Rdd5 & rdd5 & $(END_PACKET) { +:mpy+=^":<<1" Rdd5,Rs5HL06,Rt5HL05 EndPacket is iclass=14 & op2127=0x34 & op7=0 & Rs5HL06 & Rt5HL05 & Rdd5 & rdd5 & $(END_PACKET) { tmp:8 = sext(Rs5HL06) * sext(Rt5HL05); Rdd5 = rdd5 + (tmp << 1); build EndPacket; @@ -12028,7 +12500,7 @@ define pcodeop mpySatSub; # (v2,14) mpy -- "Rxx32 -= mpy ( Rs32 , Rt32 )" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 1 1 1 0 0 1 1 1 0 0 1 s s s s s P P + t t t t t 0 0 0 x x x x x +# 1 1 1 0 0 1 1 1 0 0 1 s s s s s P P 0 t t t t t 0 0 0 x x x x x :mpy-= Rdd5,rs5,rt5 EndPacket is iclass=14 & op2127=0x39 & op13=0 & op0507=0 & rs5 & rt5 & Rdd5 & rdd5 & $(END_PACKET) { Rdd5 = rdd5 - (sext(rs5) * sext(rt5)); @@ -12038,24 +12510,24 @@ define pcodeop mpySatSub; # (v2,14) mpy -- "Rxx32 -= mpy ( Rs32.h , Rt32.h )" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 1 1 1 0 0 1 1 0 0 0 1 s s s s s P P + t t t t t 0 1 1 x x x x x +# 1 1 1 0 0 1 1 0 0 0 1 s s s s s P P - t t t t t 0 1 1 x x x x x # # (v2,14) mpy -- "Rxx32 -= mpy ( Rs32.h , Rt32.l )" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 1 1 1 0 0 1 1 0 0 0 1 s s s s s P P + t t t t t 0 1 0 x x x x x +# 1 1 1 0 0 1 1 0 0 0 1 s s s s s P P - t t t t t 0 1 0 x x x x x # # (v2,14) mpy -- "Rxx32 -= mpy ( Rs32.l , Rt32.h )" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 1 1 1 0 0 1 1 0 0 0 1 s s s s s P P + t t t t t 0 0 1 x x x x x +# 1 1 1 0 0 1 1 0 0 0 1 s s s s s P P - t t t t t 0 0 1 x x x x x # # (v2,14) mpy -- "Rxx32 -= mpy ( Rs32.l , Rt32.l )" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 1 1 1 0 0 1 1 0 0 0 1 s s s s s P P + t t t t t 0 0 0 x x x x x +# 1 1 1 0 0 1 1 0 0 0 1 s s s s s P P - t t t t t 0 0 0 x x x x x -:mpy-= Rdd5,Rs5HL06,Rt5HL05 EndPacket is iclass=14 & op2127=0x31 & op13=0 & op7=0 & Rs5HL06 & Rt5HL05 & Rdd5 & rdd5 & $(END_PACKET) { +:mpy-= Rdd5,Rs5HL06,Rt5HL05 EndPacket is iclass=14 & op2127=0x31 & op7=0 & Rs5HL06 & Rt5HL05 & Rdd5 & rdd5 & $(END_PACKET) { tmp:8 = sext(Rs5HL06) * sext(Rt5HL05); Rdd5 = rdd5 - tmp; build EndPacket; @@ -12064,24 +12536,24 @@ define pcodeop mpySatSub; # (v2,14) mpy -- "Rxx32 -= mpy ( Rs32.h , Rt32.h ) :<<1" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 1 1 1 0 0 1 1 0 1 0 1 s s s s s P P + t t t t t 0 1 1 x x x x x +# 1 1 1 0 0 1 1 0 1 0 1 s s s s s P P - t t t t t 0 1 1 x x x x x # # (v2,14) mpy -- "Rxx32 -= mpy ( Rs32.h , Rt32.l ) :<<1" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 1 1 1 0 0 1 1 0 1 0 1 s s s s s P P + t t t t t 0 1 0 x x x x x +# 1 1 1 0 0 1 1 0 1 0 1 s s s s s P P - t t t t t 0 1 0 x x x x x # # (v2,14) mpy -- "Rxx32 -= mpy ( Rs32.l , Rt32.h ) :<<1" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 1 1 1 0 0 1 1 0 1 0 1 s s s s s P P + t t t t t 0 0 1 x x x x x +# 1 1 1 0 0 1 1 0 1 0 1 s s s s s P P - t t t t t 0 0 1 x x x x x # # (v2,14) mpy -- "Rxx32 -= mpy ( Rs32.l , Rt32.l ) :<<1" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 1 1 1 0 0 1 1 0 1 0 1 s s s s s P P + t t t t t 0 0 0 x x x x x +# 1 1 1 0 0 1 1 0 1 0 1 s s s s s P P - t t t t t 0 0 0 x x x x x -:mpy-=^":<<1" Rdd5,Rs5HL06,Rt5HL05 EndPacket is iclass=14 & op2127=0x35 & op13=0 & op7=0 & Rs5HL06 & Rt5HL05 & Rdd5 & rdd5 & $(END_PACKET) { +:mpy-=^":<<1" Rdd5,Rs5HL06,Rt5HL05 EndPacket is iclass=14 & op2127=0x35 & op7=0 & Rs5HL06 & Rt5HL05 & Rdd5 & rdd5 & $(END_PACKET) { tmp:8 = sext(Rs5HL06) * sext(Rt5HL05); Rdd5 = rdd5 - (tmp << 1); build EndPacket; @@ -12090,9 +12562,9 @@ define pcodeop mpySatSub; # (v2,14) mpyi -- "Rd32 = + mpyi ( Rs32 , #u8x )" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 1 1 1 0 0 0 0 0 0 + + s s s s s P P + i i i i i i i i d d d d d +# 1 1 1 0 0 0 0 0 0 - - s s s s s P P 0 i i i i i i i i d d d d d -:"+mpyi" Rd5,rs5,Uimm32_0512x EndPacket is iclass=14 &op2127=0x00 & op13=0 & rs5 & Rd5 & Uimm32_0512x & $(END_PACKET) { +:"+mpyi" Rd5,rs5,Uimm32_0512x EndPacket is iclass=14 & op2327=0x0 & op13=0 & rs5 & Rd5 & Uimm32_0512x & $(END_PACKET) { Rd5 = rs5 * Uimm32_0512x; build EndPacket; } @@ -12100,9 +12572,9 @@ define pcodeop mpySatSub; # (v2,14) mpyi -- "Rd32 = - mpyi ( Rs32 , #u8 )" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 1 1 1 0 0 0 0 0 1 + + s s s s s P P + i i i i i i i i d d d d d +# 1 1 1 0 0 0 0 0 1 - - s s s s s P P 0 i i i i i i i i d d d d d -:"-mpyi" Rd5,rs5,Uimm8_0512 EndPacket is iclass=14 &op2127=0x04 & op13=0 & rs5 & Rd5 & Uimm8_0512 & $(END_PACKET) { +:"-mpyi" Rd5,rs5,Uimm8_0512 EndPacket is iclass=14 & op2327=0x1 & op13=0 & rs5 & Rd5 & Uimm8_0512 & $(END_PACKET) { Rd5 = rs5 * sext(-Uimm8_0512); build EndPacket; } @@ -12110,9 +12582,9 @@ define pcodeop mpySatSub; # (v2,14) mpyi -- "Rd32 = mpyi ( Rs32 , Rt32 )" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 1 1 1 0 1 1 0 1 0 0 0 s s s s s P P - t t t t t 0 0 0 d d d d d +# 1 1 1 0 1 1 0 1 0 0 0 s s s s s P P 0 t t t t t 0 0 0 d d d d d -:mpyi Rd5,rs5,rt5 EndPacket is iclass=14 &op2127=0x68 & op13=0 & rs5 & rt5 & op0507=0 & Rd5 & $(END_PACKET) { +:mpyi Rd5,rs5,rt5 EndPacket is iclass=14 & op2127=0x68 & op13=0 & op0507=0 & rs5 & rt5 & Rd5 & $(END_PACKET) { Rd5 = rs5 * rt5; build EndPacket; } @@ -12120,9 +12592,9 @@ define pcodeop mpySatSub; # (v2,14) mpyi -- "Rx32 += mpyi ( Rs32 , #u8x )" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 1 1 1 0 0 0 0 1 0 + + s s s s s P P + i i i i i i i i x x x x x +# 1 1 1 0 0 0 0 1 0 - - s s s s s P P 0 i i i i i i i i x x x x x -:mpyi+= Rd5,rs5,Uimm32_0512x EndPacket is iclass=14 &op2127=0x08 & op13=0 & rs5 & Rd5 & rd5 & Uimm32_0512x & $(END_PACKET) { +:mpyi+= Rd5,rs5,Uimm32_0512x EndPacket is iclass=14 & op2327=0x2 & op13=0 & rs5 & Rd5 & rd5 & Uimm32_0512x & $(END_PACKET) { Rd5 = rd5 + (rs5 * Uimm32_0512x); build EndPacket; } @@ -12130,9 +12602,9 @@ define pcodeop mpySatSub; # (v2,14) mpyi -- "Rx32 += mpyi ( Rs32 , Rt32 )" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 1 1 1 0 1 1 1 1 0 0 0 s s s s s P P + t t t t t + 0 0 x x x x x +# 1 1 1 0 1 1 1 1 0 0 0 s s s s s P P - t t t t t - 0 0 x x x x x -:mpyi+= Rd5,rs5,rt5 EndPacket is iclass=14 &op2127=0x78 & op13=0 & op0507=0 & rs5 & Rd5 & rd5 & rt5 & $(END_PACKET) { +:mpyi+= Rd5,rs5,rt5 EndPacket is iclass=14 &op2127=0x78 & op0506=0 & rs5 & Rd5 & rd5 & rt5 & $(END_PACKET) { Rd5 = rd5 + (rs5 * rt5); build EndPacket; } @@ -12140,9 +12612,9 @@ define pcodeop mpySatSub; # (v2,14) mpyi -- "Rx32 -= mpyi ( Rs32 , #u8x )" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 1 1 1 0 0 0 0 1 1 + + s s s s s P P + i i i i i i i i x x x x x +# 1 1 1 0 0 0 0 1 1 - - s s s s s P P 0 i i i i i i i i x x x x x -:mpyi-= Rd5,rs5,Uimm32_0512x EndPacket is iclass=14 &op2127=0x0c & op13=0 & rs5 & Rd5 & rd5 & Uimm32_0512x & $(END_PACKET) { +:mpyi-= Rd5,rs5,Uimm32_0512x EndPacket is iclass=14 & op2327=0x3 & op13=0 & rs5 & Rd5 & rd5 & Uimm32_0512x & $(END_PACKET) { Rd5 = rd5 - (rs5 * Uimm32_0512x); build EndPacket; } @@ -12150,9 +12622,9 @@ define pcodeop mpySatSub; # (v2,14) mpyi -- "Rx32 -= mpyi ( Rs32 , Rt32 )" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 1 1 1 0 1 1 1 1 0 0 0 s s s s s P P + t t t t t + 0 0 x x x x x +# 1 1 1 0 1 1 1 1 1 0 0 s s s s s P P 0 t t t t t 0 0 0 x x x x x -:mpyi-= Rd5,rs5,rt5 EndPacket is iclass=14 &op2127=0x7c & op13=0 & op0507=0 & rs5 & Rd5 & rd5 & rt5 & $(END_PACKET) { +:mpyi-= Rd5,rs5,rt5 EndPacket is iclass=14 & op2127=0x7c & op13=0 & op7=0 & op0506=0 & rs5 & Rd5 & rd5 & rt5 & $(END_PACKET) { Rd5 = rd5 - (rs5 * rt5); build EndPacket; } @@ -12160,7 +12632,7 @@ define pcodeop mpySatSub; # (v4,14) mpysu -- "Rd32 = mpysu ( Rs32 , Rt32 )" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 1 1 1 0 1 1 0 1 0 1 1 s s s s s P P + t t t t t 0 0 1 d d d d d +# 1 1 1 0 1 1 0 1 0 1 1 s s s s s P P 0 t t t t t 0 0 1 d d d d d :mpysu Rd5,rs5,rt5 EndPacket is iclass=14 & op2127=0x6b & op13=0 & op0507=1 & rs5 & rt5 & Rd5 & $(END_PACKET) { tmp:8 = sext(rs5) * zext(rt5); @@ -12171,7 +12643,7 @@ define pcodeop mpySatSub; # (v2,14) mpyu -- "Rd32 = mpyu ( Rs32 , Rt32 )" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 1 1 1 0 1 1 0 1 0 1 0 s s s s s P P + t t t t t 0 0 1 d d d d d +# 1 1 1 0 1 1 0 1 0 1 0 s s s s s P P 0 t t t t t 0 0 1 d d d d d :mpyu Rd5,rs5,rt5 EndPacket is iclass=14 & op2127=0x6a & op13=0 & op0507=1 & rs5 & rt5 & Rd5 & $(END_PACKET) { tmp:8 = zext(rs5) * zext(rt5); @@ -12182,24 +12654,24 @@ define pcodeop mpySatSub; # (v2,14) mpyu -- "Rd32 = mpyu ( Rs32.h , Rt32.l )" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 1 1 1 0 1 1 0 0 0 1 0 s s s s s P P + t t t t t 0 1 0 d d d d d +# 1 1 1 0 1 1 0 0 0 1 0 s s s s s P P - t t t t t 0 1 0 d d d d d # # (v2,14) mpyu -- "Rd32 = mpyu ( Rs32.l , Rt32.h )" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 1 1 1 0 1 1 0 0 0 1 0 s s s s s P P + t t t t t 0 0 1 d d d d d +# 1 1 1 0 1 1 0 0 0 1 0 s s s s s P P - t t t t t 0 0 1 d d d d d # # (v2,14) mpyu -- "Rd32 = mpyu ( Rs32.h , Rt32.h )" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 1 1 1 0 1 1 0 0 0 1 0 s s s s s P P + t t t t t 0 1 1 d d d d d +# 1 1 1 0 1 1 0 0 0 1 0 s s s s s P P - t t t t t 0 1 1 d d d d d # # (v2,14) mpyu -- "Rd32 = mpyu ( Rs32.l , Rt32.l )" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 1 1 1 0 1 1 0 0 0 1 0 s s s s s P P + t t t t t 0 0 0 d d d d d +# 1 1 1 0 1 1 0 0 0 1 0 s s s s s P P - t t t t t 0 0 0 d d d d d -:mpyu Rd5,Rs5HL06,Rt5HL05 EndPacket is iclass=14 & op2127=0x62 & op13=0 & op7=0 & Rs5HL06 & Rt5HL05 & Rd5 & $(END_PACKET) { +:mpyu Rd5,Rs5HL06,Rt5HL05 EndPacket is iclass=14 & op2127=0x62 & op7=0 & Rs5HL06 & Rt5HL05 & Rd5 & $(END_PACKET) { Rd5 = zext(Rs5HL06) * zext(Rt5HL05); build EndPacket; } @@ -12207,25 +12679,25 @@ define pcodeop mpySatSub; # (v2,14) mpyu -- "Rd32 = mpyu ( Rs32.h , Rt32.h ) :<<1" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 1 1 1 0 1 1 0 0 1 1 0 s s s s s P P + t t t t t 0 1 1 d d d d d +# 1 1 1 0 1 1 0 0 1 1 0 s s s s s P P - t t t t t 0 1 1 d d d d d # # (v2,14) mpyu -- "Rd32 = mpyu ( Rs32.h , Rt32.l ) :<<1" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 1 1 1 0 1 1 0 0 1 1 0 s s s s s P P + t t t t t 0 1 0 d d d d d +# 1 1 1 0 1 1 0 0 1 1 0 s s s s s P P - t t t t t 0 1 0 d d d d d # # (v2,14) mpyu -- "Rd32 = mpyu ( Rs32.l , Rt32.h ) :<<1" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 1 1 1 0 1 1 0 0 1 1 0 s s s s s P P + t t t t t 0 0 1 d d d d d +# 1 1 1 0 1 1 0 0 1 1 0 s s s s s P P - t t t t t 0 0 1 d d d d d # # (v2,14) mpyu -- "Rd32 = mpyu ( Rs32.l , Rt32.l ) :<<1" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 1 1 1 0 1 1 0 0 1 1 0 s s s s s P P + t t t t t 0 0 0 d d d d d +# 1 1 1 0 1 1 0 0 1 1 0 s s s s s P P - t t t t t 0 0 0 d d d d d -:mpyu^":<<1" Rd5,Rs5HL06,Rt5HL05 EndPacket is iclass=14 & op2127=0x66 & op13=0 & op7=0 & Rs5HL06 & Rt5HL05 & Rd5 & $(END_PACKET) { - Rd5 = zext(Rs5HL06) * zext(Rs5HL06); +:mpyu^":<<1" Rd5,Rs5HL06,Rt5HL05 EndPacket is iclass=14 & op2127=0x66 & op7=0 & Rs5HL06 & Rt5HL05 & Rd5 & $(END_PACKET) { + Rd5 = zext(Rs5HL06) * zext(Rt5HL05); Rd5 = Rd5 << 1; build EndPacket; } @@ -12233,7 +12705,7 @@ define pcodeop mpySatSub; # (v2,14) mpyu -- "Rdd32 = mpyu ( Rs32 , Rt32 )" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 1 1 1 0 0 1 0 1 0 1 0 s s s s s P P + t t t t t 0 0 0 d d d d d +# 1 1 1 0 0 1 0 1 0 1 0 s s s s s P P 0 t t t t t 0 0 0 d d d d d :mpyu Rdd5,rs5,rt5 EndPacket is iclass=14 & op2127=0x2a & op13=0 & op0507=0 & rs5 & rt5 & Rdd5 & $(END_PACKET) { Rdd5 = zext(rs5) * zext(rt5); @@ -12243,24 +12715,24 @@ define pcodeop mpySatSub; # (v2,14) mpyu -- "Rdd32 = mpyu ( Rs32.h , Rt32.h )" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 1 1 1 0 0 1 0 0 0 1 0 s s s s s P P + t t t t t + 1 1 d d d d d +# 1 1 1 0 0 1 0 0 0 1 0 s s s s s P P - t t t t t - 1 1 d d d d d # # (v2,14) mpyu -- "Rdd32 = mpyu ( Rs32.h , Rt32.l )" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 1 1 1 0 0 1 0 0 0 1 0 s s s s s P P + t t t t t + 1 0 d d d d d +# 1 1 1 0 0 1 0 0 0 1 0 s s s s s P P - t t t t t - 1 0 d d d d d # # (v2,14) mpyu -- "Rdd32 = mpyu ( Rs32.l , Rt32.h )" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 1 1 1 0 0 1 0 0 0 1 0 s s s s s P P + t t t t t + 0 1 d d d d d +# 1 1 1 0 0 1 0 0 0 1 0 s s s s s P P - t t t t t - 0 1 d d d d d # # (v2,14) mpyu -- "Rdd32 = mpyu ( Rs32.l , Rt32.l )" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 1 1 1 0 0 1 0 0 0 1 0 s s s s s P P + t t t t t + 0 0 d d d d d +# 1 1 1 0 0 1 0 0 0 1 0 s s s s s P P - t t t t t - 0 0 d d d d d -:mpyu Rdd5,Rs5HL06,Rt5HL05 EndPacket is iclass=14 & op2127=0x22 & op13=0 & op7=0 & Rs5HL06 & Rt5HL05 & Rdd5 & $(END_PACKET) { +:mpyu Rdd5,Rs5HL06,Rt5HL05 EndPacket is iclass=14 & op2127=0x22 & Rs5HL06 & Rt5HL05 & Rdd5 & $(END_PACKET) { Rdd5 = zext(Rs5HL06) * zext(Rt5HL05); build EndPacket; } @@ -12268,24 +12740,24 @@ define pcodeop mpySatSub; # (v2,14) mpyu -- "Rdd32 = mpyu ( Rs32.h , Rt32.h ) :<<1" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 1 1 1 0 0 1 0 0 1 1 0 s s s s s P P + t t t t t + 1 1 d d d d d +# 1 1 1 0 0 1 0 0 1 1 0 s s s s s P P - t t t t t - 1 1 d d d d d # # (v2,14) mpyu -- "Rdd32 = mpyu ( Rs32.h , Rt32.l ) :<<1" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 1 1 1 0 0 1 0 0 1 1 0 s s s s s P P + t t t t t + 1 0 d d d d d +# 1 1 1 0 0 1 0 0 1 1 0 s s s s s P P - t t t t t - 1 0 d d d d d # # (v2,14) mpyu -- "Rdd32 = mpyu ( Rs32.l , Rt32.h ) :<<1" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 1 1 1 0 0 1 0 0 1 1 0 s s s s s P P + t t t t t + 0 1 d d d d d +# 1 1 1 0 0 1 0 0 1 1 0 s s s s s P P - t t t t t - 0 1 d d d d d # # (v2,14) mpyu -- "Rdd32 = mpyu ( Rs32.l , Rt32.l ) :<<1" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 1 1 1 0 0 1 0 0 1 1 0 s s s s s P P + t t t t t + 0 0 d d d d d +# 1 1 1 0 0 1 0 0 1 1 0 s s s s s P P - t t t t t - 0 0 d d d d d -:mpyu^":<<1" Rdd5,Rs5HL06,Rt5HL05 EndPacket is iclass=14 & op2127=0x26 & op13=0 & op7=0 & Rs5HL06 & Rt5HL05 & Rdd5 & $(END_PACKET) { +:mpyu^":<<1" Rdd5,Rs5HL06,Rt5HL05 EndPacket is iclass=14 & op2127=0x26 & Rs5HL06 & Rt5HL05 & Rdd5 & $(END_PACKET) { Rdd5 = zext(Rs5HL06) * zext(Rt5HL05); Rdd5 = Rdd5 << 1; build EndPacket; @@ -12294,24 +12766,24 @@ define pcodeop mpySatSub; # (v2,14) mpyu -- "Rx32 += mpyu ( Rs32.h , Rt32.h )" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 1 1 1 0 1 1 1 0 0 1 0 s s s s s P P + t t t t t 0 1 1 x x x x x +# 1 1 1 0 1 1 1 0 0 1 0 s s s s s P P - t t t t t 0 1 1 x x x x x # # (v2,14) mpyu -- "Rx32 += mpyu ( Rs32.h , Rt32.l )" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 1 1 1 0 1 1 1 0 0 1 0 s s s s s P P + t t t t t 0 1 0 x x x x x +# 1 1 1 0 1 1 1 0 0 1 0 s s s s s P P - t t t t t 0 1 0 x x x x x # # (v2,14) mpyu -- "Rx32 += mpyu ( Rs32.l , Rt32.h )" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 1 1 1 0 1 1 1 0 0 1 0 s s s s s P P + t t t t t 0 0 1 x x x x x +# 1 1 1 0 1 1 1 0 0 1 0 s s s s s P P - t t t t t 0 0 1 x x x x x # # (v2,14) mpyu -- "Rx32 += mpyu ( Rs32.l , Rt32.l )" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 1 1 1 0 1 1 1 0 0 1 0 s s s s s P P + t t t t t 0 0 0 x x x x x +# 1 1 1 0 1 1 1 0 0 1 0 s s s s s P P - t t t t t 0 0 0 x x x x x -:mpyu+= Rd5,Rs5HL06,Rt5HL05 EndPacket is iclass=14 & op2127=0x72 & op13=0 & op7=0 & Rs5HL06 & Rt5HL05 & Rd5 & rd5 & $(END_PACKET) { +:mpyu+= Rd5,Rs5HL06,Rt5HL05 EndPacket is iclass=14 & op2127=0x72 & op7=0 & Rs5HL06 & Rt5HL05 & Rd5 & rd5 & $(END_PACKET) { Rd5 = rd5 + (zext(Rs5HL06) * zext(Rt5HL05)); build EndPacket; } @@ -12319,24 +12791,24 @@ define pcodeop mpySatSub; # (v2,14) mpyu -- "Rx32 += mpyu ( Rs32.h , Rt32.h ) :<<1" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 1 1 1 0 1 1 1 0 1 1 0 s s s s s P P + t t t t t 0 1 1 x x x x x +# 1 1 1 0 1 1 1 0 1 1 0 s s s s s P P - t t t t t 0 1 1 x x x x x # # (v2,14) mpyu -- "Rx32 += mpyu ( Rs32.h , Rt32.l ) :<<1" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 1 1 1 0 1 1 1 0 1 1 0 s s s s s P P + t t t t t 0 1 0 x x x x x +# 1 1 1 0 1 1 1 0 1 1 0 s s s s s P P - t t t t t 0 1 0 x x x x x # # (v2,14) mpyu -- "Rx32 += mpyu ( Rs32.l , Rt32.h ) :<<1" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 1 1 1 0 1 1 1 0 1 1 0 s s s s s P P + t t t t t 0 0 1 x x x x x +# 1 1 1 0 1 1 1 0 1 1 0 s s s s s P P - t t t t t 0 0 1 x x x x x # # (v2,14) mpyu -- "Rx32 += mpyu ( Rs32.l , Rt32.l ) :<<1" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 1 1 1 0 1 1 1 0 1 1 0 s s s s s P P + t t t t t 0 0 0 x x x x x +# 1 1 1 0 1 1 1 0 1 1 0 s s s s s P P - t t t t t 0 0 0 x x x x x -:mpyu+=^":<<1" Rd5,Rs5HL06,Rt5HL05 EndPacket is iclass=14 & op2127=0x76 & op13=0 & op7=0 & Rs5HL06 & Rt5HL05 & Rd5 & rd5 & $(END_PACKET) { +:mpyu+=^":<<1" Rd5,Rs5HL06,Rt5HL05 EndPacket is iclass=14 & op2127=0x76 & op7=0 & Rs5HL06 & Rt5HL05 & Rd5 & rd5 & $(END_PACKET) { tmp:4 = zext(Rs5HL06) * zext(Rt5HL05); Rd5 = rd5 + (tmp << 1); build EndPacket; @@ -12345,24 +12817,24 @@ define pcodeop mpySatSub; # (v2,14) mpyu -- "Rx32 -= mpyu ( Rs32.h , Rt32.h )" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 1 1 1 0 1 1 1 0 0 1 1 s s s s s P P + t t t t t 0 1 1 x x x x x +# 1 1 1 0 1 1 1 0 0 1 1 s s s s s P P - t t t t t 0 1 1 x x x x x # # (v2,14) mpyu -- "Rx32 -= mpyu ( Rs32.h , Rt32.l )" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 1 1 1 0 1 1 1 0 0 1 1 s s s s s P P + t t t t t 0 1 0 x x x x x +# 1 1 1 0 1 1 1 0 0 1 1 s s s s s P P - t t t t t 0 1 0 x x x x x # # (v2,14) mpyu -- "Rx32 -= mpyu ( Rs32.l , Rt32.h )" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 1 1 1 0 1 1 1 0 0 1 1 s s s s s P P + t t t t t 0 0 1 x x x x x +# 1 1 1 0 1 1 1 0 0 1 1 s s s s s P P - t t t t t 0 0 1 x x x x x # # (v2,14) mpyu -- "Rx32 -= mpyu ( Rs32.l , Rt32.l )" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 1 1 1 0 1 1 1 0 0 1 1 s s s s s P P + t t t t t 0 0 0 x x x x x +# 1 1 1 0 1 1 1 0 0 1 1 s s s s s P P - t t t t t 0 0 0 x x x x x -:mpyu-= Rd5,Rs5HL06,Rt5HL05 EndPacket is iclass=14 & op2127=0x73 & op13=0 & op7=0 & Rs5HL06 & Rt5HL05 & Rd5 & rd5 & $(END_PACKET) { +:mpyu-= Rd5,Rs5HL06,Rt5HL05 EndPacket is iclass=14 & op2127=0x73 & op7=0 & Rs5HL06 & Rt5HL05 & Rd5 & rd5 & $(END_PACKET) { Rd5 = rd5 - (zext(Rs5HL06) * zext(Rt5HL05)); build EndPacket; } @@ -12370,24 +12842,24 @@ define pcodeop mpySatSub; # (v2,14) mpyu -- "Rx32 -= mpyu ( Rs32.h , Rt32.h ) :<<1" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 1 1 1 0 1 1 1 0 1 1 1 s s s s s P P + t t t t t 0 1 1 x x x x x +# 1 1 1 0 1 1 1 0 1 1 1 s s s s s P P - t t t t t 0 1 1 x x x x x # # (v2,14) mpyu -- "Rx32 -= mpyu ( Rs32.h , Rt32.l ) :<<1" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 1 1 1 0 1 1 1 0 1 1 1 s s s s s P P + t t t t t 0 1 0 x x x x x +# 1 1 1 0 1 1 1 0 1 1 1 s s s s s P P - t t t t t 0 1 0 x x x x x # # (v2,14) mpyu -- "Rx32 -= mpyu ( Rs32.l , Rt32.h ) :<<1" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 1 1 1 0 1 1 1 0 1 1 1 s s s s s P P + t t t t t 0 0 1 x x x x x +# 1 1 1 0 1 1 1 0 1 1 1 s s s s s P P - t t t t t 0 0 1 x x x x x # # (v2,14) mpyu -- "Rx32 -= mpyu ( Rs32.l , Rt32.l ) :<<1" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 1 1 1 0 1 1 1 0 1 1 1 s s s s s P P + t t t t t 0 0 0 x x x x x +# 1 1 1 0 1 1 1 0 1 1 1 s s s s s P P - t t t t t 0 0 0 x x x x x -:mpyu-=^":<<1" Rd5,Rs5HL06,Rt5HL05 EndPacket is iclass=14 & op2127=0x77 & op13=0 & op7=0 & Rs5HL06 & Rt5HL05 & Rd5 & rd5 & $(END_PACKET) { +:mpyu-=^":<<1" Rd5,Rs5HL06,Rt5HL05 EndPacket is iclass=14 & op2127=0x77 & op7=0 & Rs5HL06 & Rt5HL05 & Rd5 & rd5 & $(END_PACKET) { tmp:4 = zext(Rs5HL06) * zext(Rt5HL05); Rd5 = rd5 - (tmp << 1); build EndPacket; @@ -12396,7 +12868,7 @@ define pcodeop mpySatSub; # (v2,14) mpyu -- "Rxx32 += mpyu ( Rs32 , Rt32 )" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 1 1 1 0 0 1 1 1 0 1 0 s s s s s P P + t t t t t 0 0 0 x x x x x +# 1 1 1 0 0 1 1 1 0 1 0 s s s s s P P 0 t t t t t 0 0 0 x x x x x :mpyu+= Rdd5,rs5,rt5 EndPacket is iclass=14 & op2127=0x3a & op13=0 & op0507=0 & rs5 & rt5 & Rdd5 & rdd5 & $(END_PACKET) { tmp:8 = zext(rs5) * zext(rt5); @@ -12407,24 +12879,24 @@ define pcodeop mpySatSub; # (v2,14) mpyu -- "Rxx32 += mpyu ( Rs32.h , Rt32.h )" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 1 1 1 0 0 1 1 0 0 1 0 s s s s s P P + t t t t t 0 1 1 x x x x x +# 1 1 1 0 0 1 1 0 0 1 0 s s s s s P P - t t t t t 0 1 1 x x x x x # # (v2,14) mpyu -- "Rxx32 += mpyu ( Rs32.h , Rt32.l )" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 1 1 1 0 0 1 1 0 0 1 0 s s s s s P P + t t t t t 0 1 0 x x x x x +# 1 1 1 0 0 1 1 0 0 1 0 s s s s s P P - t t t t t 0 1 0 x x x x x # # (v2,14) mpyu -- "Rxx32 += mpyu ( Rs32.l , Rt32.h )" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 1 1 1 0 0 1 1 0 0 1 0 s s s s s P P + t t t t t 0 0 1 x x x x x +# 1 1 1 0 0 1 1 0 0 1 0 s s s s s P P - t t t t t 0 0 1 x x x x x # # (v2,14) mpyu -- "Rxx32 += mpyu ( Rs32.l , Rt32.l )" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 1 1 1 0 0 1 1 0 0 1 0 s s s s s P P + t t t t t 0 0 0 x x x x x +# 1 1 1 0 0 1 1 0 0 1 0 s s s s s P P - t t t t t 0 0 0 x x x x x -:mpyu+= Rdd5,Rs5HL06,Rt5HL05 EndPacket is iclass=14 & op2127=0x32 & op13=0 & op7=0 & Rs5HL06 & Rt5HL05 & Rdd5 & rdd5 & $(END_PACKET) { +:mpyu+= Rdd5,Rs5HL06,Rt5HL05 EndPacket is iclass=14 & op2127=0x32 & op7=0 & Rs5HL06 & Rt5HL05 & Rdd5 & rdd5 & $(END_PACKET) { tmp:8 = zext(Rs5HL06) * zext(Rt5HL05); Rdd5 = rdd5 + tmp; build EndPacket; @@ -12433,25 +12905,25 @@ define pcodeop mpySatSub; # (v2,14) mpyu -- "Rxx32 += mpyu ( Rs32.h , Rt32.h ) :<<1" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 1 1 1 0 0 1 1 0 1 1 0 s s s s s P P + t t t t t 0 1 1 x x x x x +# 1 1 1 0 0 1 1 0 1 1 0 s s s s s P P - t t t t t 0 1 1 x x x x x # # (v2,14) mpyu -- "Rxx32 += mpyu ( Rs32.h , Rt32.l ) :<<1" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 1 1 1 0 0 1 1 0 1 1 0 s s s s s P P + t t t t t 0 1 0 x x x x x +# 1 1 1 0 0 1 1 0 1 1 0 s s s s s P P - t t t t t 0 1 0 x x x x x # # (v2,14) mpyu -- "Rxx32 += mpyu ( Rs32.l , Rt32.h ) :<<1" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 1 1 1 0 0 1 1 0 1 1 0 s s s s s P P + t t t t t 0 0 1 x x x x x +# 1 1 1 0 0 1 1 0 1 1 0 s s s s s P P - t t t t t 0 0 1 x x x x x # # (v2,14) mpyu -- "Rxx32 += mpyu ( Rs32.l , Rt32.l ) :<<1" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 1 1 1 0 0 1 1 0 1 1 0 s s s s s P P + t t t t t 0 0 0 x x x x x +# 1 1 1 0 0 1 1 0 1 1 0 s s s s s P P - t t t t t 0 0 0 x x x x x -:mpyu+=^":<<1" Rdd5,Rs5HL06,Rt5HL05 EndPacket is iclass=14 & op2127=0x36 & op13=0 & op7=0 & Rs5HL06 & Rt5HL05 & Rdd5 & rdd5 & $(END_PACKET) { - tmp:8 = zext(Rs5HL06) * zext(Rs5HL06); +:mpyu+=^":<<1" Rdd5,Rs5HL06,Rt5HL05 EndPacket is iclass=14 & op2127=0x36 & op7=0 & Rs5HL06 & Rt5HL05 & Rdd5 & rdd5 & $(END_PACKET) { + tmp:8 = zext(Rs5HL06) * zext(Rt5HL05); Rdd5 = rdd5 + (tmp << 1); build EndPacket; } @@ -12459,7 +12931,7 @@ define pcodeop mpySatSub; # (v2,14) mpyu -- "Rxx32 -= mpyu ( Rs32 , Rt32 )" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 1 1 1 0 0 1 1 1 0 1 1 s s s s s P P + t t t t t 0 0 0 x x x x x +# 1 1 1 0 0 1 1 1 0 1 1 s s s s s P P 0 t t t t t 0 0 0 x x x x x :mpyu-= Rdd5,rs5,rt5 EndPacket is iclass=14 & op2127=0x3b & op13=0 & op0507=0 & rs5 & rt5 & Rdd5 & rdd5 & $(END_PACKET) { tmp:8 = zext(rs5) * zext(rt5); @@ -12470,24 +12942,24 @@ define pcodeop mpySatSub; # (v2,14) mpyu -- "Rxx32 -= mpyu ( Rs32.h , Rt32.h )" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 1 1 1 0 0 1 1 0 0 1 1 s s s s s P P + t t t t t 0 1 1 x x x x x +# 1 1 1 0 0 1 1 0 0 1 1 s s s s s P P - t t t t t 0 1 1 x x x x x # # (v2,14) mpyu -- "Rxx32 -= mpyu ( Rs32.h , Rt32.l )" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 1 1 1 0 0 1 1 0 0 1 1 s s s s s P P + t t t t t 0 1 0 x x x x x +# 1 1 1 0 0 1 1 0 0 1 1 s s s s s P P - t t t t t 0 1 0 x x x x x # # (v2,14) mpyu -- "Rxx32 -= mpyu ( Rs32.l , Rt32.h )" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 1 1 1 0 0 1 1 0 0 1 1 s s s s s P P + t t t t t 0 0 1 x x x x x +# 1 1 1 0 0 1 1 0 0 1 1 s s s s s P P - t t t t t 0 0 1 x x x x x # # (v2,14) mpyu -- "Rxx32 -= mpyu ( Rs32.l , Rt32.l )" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 1 1 1 0 0 1 1 0 0 1 1 s s s s s P P + t t t t t 0 0 0 x x x x x +# 1 1 1 0 0 1 1 0 0 1 1 s s s s s P P - t t t t t 0 0 0 x x x x x -:mpyu-= Rdd5,Rs5HL06,Rt5HL05 EndPacket is iclass=14 & op2127=0x33 & op13=0 & op7=0 & Rs5HL06 & Rt5HL05 & Rdd5 & rdd5 & $(END_PACKET) { +:mpyu-= Rdd5,Rs5HL06,Rt5HL05 EndPacket is iclass=14 & op2127=0x33 & op7=0 & Rs5HL06 & Rt5HL05 & Rdd5 & rdd5 & $(END_PACKET) { tmp:8 = zext(Rs5HL06) * zext(Rt5HL05); Rdd5 = rdd5 - tmp; build EndPacket; @@ -12496,24 +12968,24 @@ define pcodeop mpySatSub; # (v2,14) mpyu -- "Rxx32 -= mpyu ( Rs32.h , Rt32.h ) :<<1" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 1 1 1 0 0 1 1 0 1 1 1 s s s s s P P + t t t t t 0 1 1 x x x x x +# 1 1 1 0 0 1 1 0 1 1 1 s s s s s P P - t t t t t 0 1 1 x x x x x # # (v2,14) mpyu -- "Rxx32 -= mpyu ( Rs32.h , Rt32.l ) :<<1" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 1 1 1 0 0 1 1 0 1 1 1 s s s s s P P + t t t t t 0 1 0 x x x x x +# 1 1 1 0 0 1 1 0 1 1 1 s s s s s P P - t t t t t 0 1 0 x x x x x # # (v2,14) mpyu -- "Rxx32 -= mpyu ( Rs32.l , Rt32.h ) :<<1" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 1 1 1 0 0 1 1 0 1 1 1 s s s s s P P + t t t t t 0 0 1 x x x x x +# 1 1 1 0 0 1 1 0 1 1 1 s s s s s P P - t t t t t 0 0 1 x x x x x # # (v2,14) mpyu -- "Rxx32 -= mpyu ( Rs32.l , Rt32.l ) :<<1" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 1 1 1 0 0 1 1 0 1 1 1 s s s s s P P + t t t t t 0 0 0 x x x x x +# 1 1 1 0 0 1 1 0 1 1 1 s s s s s P P - t t t t t 0 0 0 x x x x x -:mpyu-=^":<<1" Rdd5,Rs5HL06,Rt5HL05 EndPacket is iclass=14 & op2127=0x37 & op13=0 & op7=0 & Rs5HL06 & Rt5HL05 & Rdd5 & rdd5 & $(END_PACKET) { +:mpyu-=^":<<1" Rdd5,Rs5HL06,Rt5HL05 EndPacket is iclass=14 & op2127=0x37 & op7=0 & Rs5HL06 & Rt5HL05 & Rdd5 & rdd5 & $(END_PACKET) { tmp:8 = zext(Rs5HL06) * zext(Rt5HL05); Rdd5 = rdd5 - (tmp << 1); build EndPacket; @@ -12564,11 +13036,6 @@ define pcodeop mpySatSub; build EndPacket; } -# (v2,15) mux -- "Rd32 = mux ( Pu4 , Rs32 , Rt32 )" -# _________________________________________________________________________________________________ -# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 1 1 1 1 0 1 0 0 + + + s s s s s P P + t t t t t + u u d d d d d - # Sleigh can't distinguish the two simplification cases when -l option is used with compiler #:mux Rd5,pu0506,rs5,rt5 EndPacket is iclass=15 & op2127=0x20 & op13=0 & op7=0 & Rd5 & rd5=op1620 & rs5 & rt5 & pu0506 & $(END_PACKET) { # if ((pu0506 & 1) == 0) goto ; @@ -12585,7 +13052,12 @@ define pcodeop mpySatSub; # build EndPacket; #} -:mux Rd5,pu0506,rs5,rt5 EndPacket is iclass=15 & op2127=0x20 & op13=0 & op7=0 & Rd5 & rs5 & rt5 & pu0506 & $(END_PACKET) { +# (v2,15) mux -- "Rd32 = mux ( Pu4 , Rs32 , Rt32 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 1 1 0 1 0 0 - - - s s s s s P P - t t t t t - u u d d d d d + +:mux Rd5,pu0506,rs5,rt5 EndPacket is iclass=15 & op2427=0x4 & Rd5 & rs5 & rt5 & pu0506 & $(END_PACKET) { if ((pu0506 & 1) != 0) goto ; Rd5 = rt5; goto ; @@ -12598,9 +13070,9 @@ define pcodeop mpySatSub; # (v2,8) neg -- "Rd32 = neg ( Rs32 ) :sat" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 1 0 0 0 1 1 0 0 1 0 0 s s s s s P P + + + + + + 1 1 0 d d d d d +# 1 0 0 0 1 1 0 0 1 0 0 s s s s s P P - - - - - - 1 1 0 d d d d d -:neg":sat" Rd5,rs5 EndPacket is iclass=0x8 & op2127=0x64 & op0513=0x06 & Rd5 & rs5 & $(END_PACKET) +:neg":sat" Rd5,rs5 EndPacket is iclass=0x8 & op2127=0x64 & op0507=0x6 & Rd5 & rs5 & $(END_PACKET) { tmp:8 = -sext(rs5); Rd5 = saturate32(tmp); @@ -12613,9 +13085,9 @@ define pcodeop mpySatSub; # (v2,8) neg -- "Rdd32 = neg ( Rss32 )" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 1 0 0 0 0 0 0 0 1 0 + s s s s s P P + + + + + + 1 0 1 d d d d d +# 1 0 0 0 0 0 0 0 1 0 0 s s s s s P P - - - - - - 1 0 1 d d d d d -:neg Rdd5,rss5 EndPacket is iclass=0x8 & op2127=0x04 & op0513=0x05 & Rdd5 & rss5 & $(END_PACKET) +:neg Rdd5,rss5 EndPacket is iclass=0x8 & op2227=0x2 & op21=0 & op0507=0x5 & Rdd5 & rss5 & $(END_PACKET) { Rdd5 = -rss5; build EndPacket; @@ -12624,11 +13096,11 @@ define pcodeop mpySatSub; # (v4,6) nmi -- "nmi ( Rs32 )" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 0 1 1 0 0 1 0 0 0 1 1 s s s s s P P + + + + + + 0 1 0 + + + + + +# 0 1 1 0 0 1 0 0 0 1 1 s s s s s P P - - - - - - 0 1 0 - - - - - define pcodeop nmi; # TODO: Need to determine what is affected -:nmi rs5 EndPacket is iclass=0x6 & op2127=0x23 & op0013=0x40 & rs5 & $(END_PACKET) +:nmi rs5 EndPacket is iclass=0x6 & op2127=0x23 & op0507=0x2 & rs5 & $(END_PACKET) { nmi(rs5); build EndPacket; @@ -12646,9 +13118,9 @@ define pcodeop nmi; # TODO: Need to determine what is affected # (v2,8) normamt -- "Rd32 = normamt ( Rs32 )" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 1 0 0 0 1 1 0 0 0 0 0 s s s s s P P + + + + + + 1 1 1 d d d d d +# 1 0 0 0 1 1 0 0 0 0 0 s s s s s P P - - - - - - 1 1 1 d d d d d -:normamt Rd5,rs5 EndPacket is iclass=0x8 & op2127=0x60 & op0513=0x07 & Rd5 & rs5 & $(END_PACKET) +:normamt Rd5,rs5 EndPacket is iclass=0x8 & op2127=0x60 & op0507=0x7 & Rd5 & rs5 & $(END_PACKET) { if (rs5 != 0) goto ; Rd5 = 0; @@ -12662,9 +13134,9 @@ define pcodeop nmi; # TODO: Need to determine what is affected # (v4,8) normamt -- "Rd32 = normamt ( Rss32 )" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 1 0 0 0 1 0 0 0 0 1 1 s s s s s P P + + + + + + 0 0 + d d d d d +# 1 0 0 0 1 0 0 0 0 1 1 s s s s s P P - - - - - - 0 0 - d d d d d -:normamt Rd5,rss5 EndPacket is iclass=0x8 & op2127=0x43 & op0513=0x0 & Rd5 & rss5 & $(END_PACKET) +:normamt Rd5,rss5 EndPacket is iclass=0x8 & op2127=0x43 & op0607=0x0 & Rd5 & rss5 & $(END_PACKET) { if (rss5 != 0) goto ; Rd5 = 0; @@ -12680,7 +13152,7 @@ define pcodeop nmi; # TODO: Need to determine what is affected # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| # 0 1 1 0 1 0 1 1 1 1 0 0 - - s s P P 0 - - - - - - - - - - - d d -:not Pd2,pu1617 EndPacket is iclass=6 & op2127=0x5e & op1820=0 & op0213=0 & pu1617 & Pd2 & $(END_PACKET) { +:not Pd2,pu1617 EndPacket is iclass=6 & op2127=0x5e & op20=0 & op13=0 & pu1617 & Pd2 & $(END_PACKET) { Pd2 = Pd2 & ~pu1617; # NOTE: Implemented as full byte logic instead of single-bit boolean logic build EndPacket; } @@ -12688,9 +13160,9 @@ define pcodeop nmi; # TODO: Need to determine what is affected # (v2,8) not -- "Rdd32 = not ( Rss32 )" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 1 0 0 0 0 0 0 0 1 0 + s s s s s P P - - - - - - 1 0 0 d d d d d +# 1 0 0 0 0 0 0 0 1 0 0 s s s s s P P - - - - - - 1 0 0 d d d d d -:not Rdd5,rss5 EndPacket is iclass=8 & op2127=0x04 & op0507=4 & Rdd5 & rss5 & $(END_PACKET) { +:not Rdd5,rss5 EndPacket is iclass=8 & op2227=0x2 & op21=0 & op0507=4 & Rdd5 & rss5 & $(END_PACKET) { Rdd5 = ~rss5; build EndPacket; } @@ -12698,24 +13170,24 @@ define pcodeop nmi; # TODO: Need to determine what is affected # (v4,6) or -- "Pd4 = or ( Ps4 , and ( Pt4 , Pu4 ) )" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 0 1 1 0 1 0 1 1 0 1 0 1 + + s s P P 0 - - - t t u u - - - - d d +# 0 1 1 0 1 0 1 1 0 1 0 1 - - s s P P 0 - - - t t u u - - - - d d # # (v4,6) or -- "Pd4 = or ( Ps4 , and ( Pt4 , ! Pu4 ) )" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 0 1 1 0 1 0 1 1 1 1 0 1 + + s s P P 0 - - - t t u u - - - - d d +# 0 1 1 0 1 0 1 1 1 1 0 1 - - s s P P 0 - - - t t u u - - - - d d # # (v4,6) or -- "Pd4 = or ( Ps4 , or ( Pt4 , Pu4 ) )" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 0 1 1 0 1 0 1 1 0 1 1 1 + + s s P P 0 - - - t t u u - - - - d d +# 0 1 1 0 1 0 1 1 0 1 1 1 - - s s P P 0 - - - t t u u - - - - d d # # (v4,6) or -- "Pd4 = or ( Ps4 , or ( Pt4 , ! Pu4 ) )" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 0 1 1 0 1 0 1 1 1 1 1 1 + + s s P P 0 - - - t t u u - - - - d d +# 0 1 1 0 1 0 1 1 1 1 1 1 - - s s P P 0 - - - t t u u - - - - d d -:or Pd2,pu1617,PredLogic_L21_S23_P0809_P0607 EndPacket is iclass=6 & op2427=0xb & op22=1 & op1820=4 & pu1617 & Pd2 & PredLogic_L21_S23_P0809_P0607 & $(END_PACKET) { +:or Pd2,pu1617,PredLogic_L21_S23_P0809_P0607 EndPacket is iclass=6 & op2427=0xb & op22=1 & op20=1 & pu1617 & Pd2 & PredLogic_L21_S23_P0809_P0607 & $(END_PACKET) { Pd2 = Pd2 & (pu1617 | PredLogic_L21_S23_P0809_P0607); build EndPacket; } @@ -12725,7 +13197,7 @@ define pcodeop nmi; # TODO: Need to determine what is affected # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| # 0 1 1 0 1 0 1 1 0 0 1 0 - - s s P P 0 - - - t t - - - - - - d d -:or Pd2,pu0809,pu1617 EndPacket is iclass=6 & op2127=0x59 & op1820=0 & op1013=0 & op0207=0 & pu0809 & pu1617 & Pd2 & $(END_PACKET) { +:or Pd2,pu0809,pu1617 EndPacket is iclass=6 & op2127=0x59 & op20=0 & op13=0 & pu0809 & pu1617 & Pd2 & $(END_PACKET) { Pd2 = Pd2 & (pu1617 | pu0809); build EndPacket; } @@ -12741,7 +13213,7 @@ define pcodeop nmi; # TODO: Need to determine what is affected # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| # 0 1 1 0 1 0 1 1 1 1 1 0 - - s s P P 0 - - - t t - - - - - - d d -:or Pd2,pu0809,NotPs2 EndPacket is iclass=6 & op2127=0x5f & op1820=0 & op1013=0 & op0207=0 & pu0809 & NotPs2 & Pd2 & $(END_PACKET) { +:or Pd2,pu0809,NotPs2 EndPacket is iclass=6 & op2127=0x5f & op20=0 & op13=0 & pu0809 & NotPs2 & Pd2 & $(END_PACKET) { Pd2 = Pd2 & (NotPs2 | pu0809); build EndPacket; } @@ -12799,9 +13271,9 @@ define pcodeop nmi; # TODO: Need to determine what is affected # (v4,14) or -- "Rx32 &= or ( Rs32 , Rt32 )" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 1 1 1 0 1 1 1 1 0 1 0 s s s s s P P + t t t t t + 0 1 x x x x x +# 1 1 1 0 1 1 1 1 0 1 0 s s s s s P P 0 t t t t t 0 0 1 x x x x x -:or&= Rd5,rs5,rt5 EndPacket is iclass=0xe & op2127=0x7a & op13=0 & op0507=1 & rs5 & rt5 & rd5 & Rd5 & $(END_PACKET) +:or&= Rd5,rs5,rt5 EndPacket is iclass=0xe & op2127=0x7a & op13=0 & op7=0 & op0506=1 & rs5 & rt5 & rd5 & Rd5 & $(END_PACKET) { Rd5 = rd5 & (rs5 | rt5); build EndPacket; @@ -12810,14 +13282,14 @@ define pcodeop nmi; # TODO: Need to determine what is affected # (v4,13) or -- "Rx32 = or ( #u8x , asl ( Rx32 , #U5 ) )" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 1 1 0 1 1 1 1 0 i i i x x x x x P P i I I I I I i i i 0 i 0 1 + +# 1 1 0 1 1 1 1 0 i i i x x x x x P P i I I I I I i i i 0 i 0 1 - # # (v4,13) or -- "Rx32 = or ( #u8x , lsr ( Rx32 , #U5 ) )" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 1 1 0 1 1 1 1 0 i i i x x x x x P P i I I I I I i i i 1 i 0 1 + +# 1 1 0 1 1 1 1 0 i i i x x x x x P P i I I I I I i i i 1 i 0 1 - -:or Rx5,Uimm32_2123_13_0507_03x,ShiftRx_D04_I0812 EndPacket is iclass=13 & op2427=14 & op0002=2 & Uimm32_2123_13_0507_03x & ShiftRx_D04_I0812 & Rx5 & $(END_PACKET) +:or Rx5,Uimm32_2123_13_0507_03x,ShiftRx_D04_I0812 EndPacket is iclass=13 & op2427=14 & op0102=1 & Uimm32_2123_13_0507_03x & ShiftRx_D04_I0812 & Rx5 & $(END_PACKET) { Rx5 = Uimm32_2123_13_0507_03x & ShiftRx_D04_I0812; build EndPacket; @@ -12842,9 +13314,9 @@ AndRx_21_0513: "and("^rx5,Simm32_21_0513x^")" is rx5 & Simm32_21_0513x { # (v4,14) or -- "Rx32 ^= or ( Rs32 , Rt32 )" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 1 1 1 0 1 1 1 1 1 1 0 s s s s s P P + t t t t t + 1 1 x x x x x +# 1 1 1 0 1 1 1 1 1 1 0 s s s s s P P 0 t t t t t 0 1 1 x x x x x -:or"^=" Rd5,rs5,rt5 EndPacket is iclass=0xe & op2127=0x7e & op13=0 & op0507=3 & rs5 & rt5 & rd5 & Rd5 & $(END_PACKET) +:or"^=" Rd5,rs5,rt5 EndPacket is iclass=0xe & op2127=0x7e & op13=0 & op7=0 & op0506=3 & rs5 & rt5 & rd5 & Rd5 & $(END_PACKET) { Rd5 = rd5 ^ (rs5 | rt5); build EndPacket; @@ -12863,9 +13335,9 @@ AndRx_21_0513: "and("^rx5,Simm32_21_0513x^")" is rx5 & Simm32_21_0513x { # (v4,14) or -- "Rx32 |= or ( Rs32 , Rt32 )" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 1 1 1 0 1 1 1 1 1 1 0 s s s s s P P + t t t t t + 0 0 x x x x x +# 1 1 1 0 1 1 1 1 1 1 0 s s s s s P P 0 t t t t t 0 0 0 x x x x x -:or|= Rd5,rs5,rt5 EndPacket is iclass=0xe & op2127=0x7e & op13=0 & op0507=0 & rs5 & rt5 & rd5 & Rd5 & $(END_PACKET) +:or|= Rd5,rs5,rt5 EndPacket is iclass=0xe & op2127=0x7e & op13=0 & op7=0 & op0506=0 & rs5 & rt5 & rd5 & Rd5 & $(END_PACKET) { Rd5 = rd5 | rs5 | rt5; build EndPacket; @@ -12874,31 +13346,33 @@ AndRx_21_0513: "and("^rx5,Simm32_21_0513x^")" is rx5 & Simm32_21_0513x { # (v2,15) or -- "if ( Pu4 ) Rd32 = or ( Rs32 , Rt32 )" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 1 1 1 1 1 0 0 1 + 0 1 s s s s s P P 0 t t t t t 0 u u d d d d d +# 1 1 1 1 1 0 0 1 - 0 1 s s s s s P P 0 t t t t t 0 u u d d d d d # # (v2,15) or -- "if ( ! Pu4 ) Rd32 = or ( Rs32 , Rt32 )" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 1 1 1 1 1 0 0 1 + 0 1 s s s s s P P 0 t t t t t 1 u u d d d d d +# 1 1 1 1 1 0 0 1 - 0 1 s s s s s P P 0 t t t t t 1 u u d d d d d # # (v2,15) or -- "if ( Pu4 .new ) Rd32 = or ( Rs32 , Rt32 )" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 1 1 1 1 1 0 0 1 + 0 1 s s s s s P P 1 t t t t t 0 u u d d d d d +# 1 1 1 1 1 0 0 1 - 0 1 s s s s s P P 1 t t t t t 0 u u d d d d d # # (v2,15) or -- "if ( ! Pu4 .new ) Rd32 = or ( Rs32 , Rt32 )" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 1 1 1 1 1 0 0 1 + 0 1 s s s s s P P 1 t t t t t 1 u u d d d d d +# 1 1 1 1 1 0 0 1 - 0 1 s s s s s P P 1 t t t t t 1 u u d d d d d -:or^PuCond0506_N13_S07 rd5,rs5,rt5 EndPacket is iclass=15 & op2327=0x12 & op22=0 & op21=1 & PuCond0506_N13_S07 & rs5 & rt5 & rd5 & rd5_ & SetNRegRd5 & $(END_PACKET) { +:or^PuCond0506_N13_S07 rd5,rs5,rt5 EndPacket is iclass=15 & op2427=0x9 & op22=0 & op21=1 & PuCond0506_N13_S07 & rs5 & rt5 & rd5 & rd5_ & SetNRegRd5 & $(END_PACKET) { build PuCond0506_N13_S07; build EndPacket; <> + build PuCond0506_N13_S07; if (ConditionReg == 0) goto ; rd5_ = rs5 | rt5; <> + build PuCond0506_N13_S07; if (ConditionReg == 0) goto ; rd5 = rd5_; @@ -12907,9 +13381,9 @@ AndRx_21_0513: "and("^rx5,Simm32_21_0513x^")" is rx5 & Simm32_21_0513x { # (v4,15) packhl -- "Rdd32 = packhl ( Rs32 , Rt32 )" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 1 1 1 1 0 1 0 1 1 + + s s s s s P P + t t t t t + + + d d d d d +# 1 1 1 1 0 1 0 1 1 - - s s s s s P P - t t t t t - - - d d d d d -:packhl Rdd5,rs5,rt5 EndPacket is iclass=0xf & op2127=0x2c & op13=0 & op0507=0 & rs5 & rt5 & Rdd5 & $(END_PACKET) +:packhl Rdd5,rs5,rt5 EndPacket is iclass=0xf & op2327=0xb & rs5 & rt5 & Rdd5 & $(END_PACKET) { Rdd5 = (zext(rs5 & 0xff00) << 32) + (zext(rt5 & 0xff00) << 16) + (zext(rs5 & 0xff) << 8) + zext(rt5 & 0xff); build EndPacket; @@ -12918,9 +13392,9 @@ AndRx_21_0513: "and("^rx5,Simm32_21_0513x^")" is rx5 & Simm32_21_0513x { # (v2,13) packhl -- "Rdd32 = packhl ( Rs32 , Rt32 ) :deprecated" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 1 1 0 1 0 1 0 0 + + 0 s s s s s P P + t t t t t + + + d d d d d +# 1 1 0 1 0 1 0 0 - - 0 s s s s s P P - t t t t t - - - d d d d d -:packhl^":deprecated" Rdd5,rs5,rt5 EndPacket is iclass=0xd & op2127=0x20 & op13=0 & op0507=0 & rs5 & rt5 & Rdd5 & $(END_PACKET) +:packhl^":deprecated" Rdd5,rs5,rt5 EndPacket is iclass=0xd & op2427=0x4 & op21=0x0 & rs5 & rt5 & Rdd5 & $(END_PACKET) { Rdd5 = (zext(rs5 & 0xff00) << 32) + (zext(rt5 & 0xff00) << 16) + (zext(rs5 & 0xff) << 8) + zext(rt5 & 0xff); build EndPacket; @@ -12929,11 +13403,11 @@ AndRx_21_0513: "and("^rx5,Simm32_21_0513x^")" is rx5 & Simm32_21_0513x { # (v4,13) parity -- "Rd32 = parity ( Rs32 , Rt32 )" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 1 1 0 1 0 1 0 1 1 1 1 s s s s s P P + t t t t t + + + d d d d d +# 1 1 0 1 0 1 0 1 1 1 1 s s s s s P P - t t t t t - - - d d d d d define pcodeop parity; -:parity Rd5,rs5,rt5 EndPacket is iclass=0xd & op2127=0x2f & op13=0 & op0507=0 & rs5 & rt5 & Rd5 & $(END_PACKET) +:parity Rd5,rs5,rt5 EndPacket is iclass=0xd & op2127=0x2f & rs5 & rt5 & Rd5 & $(END_PACKET) { Rd5 = parity(rs5,rt5); build EndPacket; @@ -12942,9 +13416,9 @@ define pcodeop parity; # (v2,13) parity -- "Rd32 = parity ( Rss32 , Rtt32 )" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 1 1 0 1 0 0 0 0 + + + s s s s s P P + t t t t t + + + d d d d d +# 1 1 0 1 0 0 0 0 - - - s s s s s P P - t t t t t - - - d d d d d -:parity Rd5,rss5,rtt5 EndPacket is iclass=0xd & op2127=0x0 & op13=0 & op0507=0 & rss5 & rtt5 & Rd5 & $(END_PACKET) +:parity Rd5,rss5,rtt5 EndPacket is iclass=0xd & op2427=0x0 & rss5 & rtt5 & Rd5 & $(END_PACKET) { Rd5 = parity(rss5,rtt5); build EndPacket; @@ -12957,20 +13431,20 @@ define pcodeop parity; define pcodeop pause; -:pause Uimm10_1617_0812_0204 EndPacket is iclass=0x5 & op2127=0x22 & op1820=0 & op13=0 & op0507=0 & op0001=0 & Uimm10_1617_0812_0204 & $(END_PACKET) +:pause Uimm10_1617_0812_0204 EndPacket is iclass=0x5 & op2227=0x11 & Uimm10_1617_0812_0204 & $(END_PACKET) { pause(Uimm10_1617_0812_0204); build EndPacket; } -# unpause -- "unpause" +# (v2,5) unpause -- "unpause" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 0 1 0 1 0 1 1 1 1 1 1 - - - - - P P 0 1 - - - - 0 0 0 - - - - - +# 0 1 0 1 0 1 1 1 1 1 1 - - - - - P P 0 1 - - - - 0 0 0 - - - - - define pcodeop unpause; -:unpause EndPacket is iclass=0x5 & op2127=0x3f & op1620=0 & op0213=0x400 & op0001=0 & $(END_PACKET) +:unpause EndPacket is iclass=0x5 & op2127=0x3f & op1213=0x1 & op0507=0x0 & $(END_PACKET) { unpause(); build EndPacket; @@ -12992,7 +13466,7 @@ define pcodeop pmemcpy; # (v4,14) pmpyw -- "Rdd32 = pmpyw ( Rs32 , Rt32 )" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 1 1 1 0 0 1 0 1 0 1 0 s s s s s P P + t t t t t 1 1 1 d d d d d +# 1 1 1 0 0 1 0 1 0 1 0 s s s s s P P 0 t t t t t 1 1 1 d d d d d define pcodeop pmpyw; @@ -13005,7 +13479,7 @@ define pcodeop pmpyw; # (v4,14) pmpyw -- "Rxx32 ^= pmpyw ( Rs32 , Rt32 )" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 1 1 1 0 0 1 1 1 0 0 1 s s s s s P P + t t t t t 1 1 1 x x x x x +# 1 1 1 0 0 1 1 1 0 0 1 s s s s s P P 0 t t t t t 1 1 1 x x x x x :pmpyw"^=" Rdd5,rs5,rt5 EndPacket is iclass=0xe & op2127=0x39 & op13=0 & op0507=7 & rs5 & rt5 & rdd5 & Rdd5 & $(END_PACKET) { @@ -13013,17 +13487,12 @@ define pcodeop pmpyw; build EndPacket; } -# (v2,6) resume -- "resume ( Rs32 )" -# _________________________________________________________________________________________________ -# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 0 1 1 0 0 1 0 0 0 1 0 s s s s s P P + + + + + + 0 0 1 + + + + + - # (v5,8) popcount -- "Rd32 = popcount ( Rss32 )" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 1 0 0 0 1 0 0 0 0 1 1 s s s s s P P + + + + + + 0 1 1 d d d d d +# 1 0 0 0 1 0 0 0 0 1 1 s s s s s P P - - - - - - 0 1 1 d d d d d -:popcount Rd5,rss5 EndPacket is iclass=8 & op2127=0x43 & op0513=0x03 & rss5 & Rd5 & $(END_PACKET) { +:"popcount" Rd5,rss5 EndPacket is iclass=8 & op2127=0x43 & op0507=0x3 & rss5 & Rd5 & $(END_PACKET) { Rd5 = popcount(rss5); build EndPacket; } @@ -13051,7 +13520,7 @@ define pcodeop releaseSameDomain; # (v4,6) resume -- "resume ( Rs32 )" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 0 1 1 0 0 1 0 0 0 1 0 s s s s s P P + + + + + + 0 0 1 + + + + + +# 0 1 1 0 0 1 0 0 0 1 0 s s s s s P P - - - - - - 0 0 1 - - - - - define pcodeop resume; :resume rs5 EndPacket is iclass=0x6 & op2127=0x22 & op0507=1 & rs5 & $(END_PACKET) @@ -13063,9 +13532,9 @@ define pcodeop resume; # (v4,8) round -- "Rd32 = round ( Rs32 , #u5 )" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 1 0 0 0 1 1 0 0 1 1 1 s s s s s P P 0 i i i i i 1 0 + d d d d d +# 1 0 0 0 1 1 0 0 1 1 1 s s s s s P P 0 i i i i i 1 0 - d d d d d -:round Rd5,rs5,Uimm8_0812 EndPacket is iclass=8 & op2127=0x67 & op13=0 & op0507=4 & Rd5 & rs5 & Uimm8_0812 & $(END_PACKET) { +:round Rd5,rs5,Uimm8_0812 EndPacket is iclass=8 & op2127=0x67 & op13=0 & op0607=2 & Rd5 & rs5 & Uimm8_0812 & $(END_PACKET) { Rd5 = roundArithmetic(rs5, Uimm8_0812); build EndPacket; } @@ -13073,9 +13542,9 @@ define pcodeop resume; # (v4,8) round -- "Rd32 = round ( Rs32 , #u5 ) :sat" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 1 0 0 0 1 1 0 0 1 1 1 s s s s s P P 0 i i i i i 1 1 + d d d d d +# 1 0 0 0 1 1 0 0 1 1 1 s s s s s P P 0 i i i i i 1 1 - d d d d d -:round":sat" Rd5,rs5,Uimm8_0812 EndPacket is iclass=0x8 & op2127=0x67 & op13=0 & op0507=6 & Uimm8_0812 & Rd5 & rs5 & $(END_PACKET) { +:round":sat" Rd5,rs5,Uimm8_0812 EndPacket is iclass=0x8 & op2127=0x67 & op13=0 & op0607=3 & Uimm8_0812 & Rd5 & rs5 & $(END_PACKET) { Rd5 = roundArithmeticSaturate(rs5, Uimm8_0812); build EndPacket; } @@ -13083,9 +13552,9 @@ define pcodeop resume; # (v4,12) round -- "Rd32 = round ( Rs32 , Rt32 )" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 1 1 0 0 0 1 1 0 1 1 + s s s s s P P + t t t t t 1 0 + d d d d d +# 1 1 0 0 0 1 1 0 1 1 - s s s s s P P - t t t t t 1 0 - d d d d d -:round Rd5,rs5,rt5 EndPacket is iclass=12 & op2127=0x36 & op13=0 & op0507=4 & Rd5 & rs5 & rt5 & $(END_PACKET) { +:round Rd5,rs5,rt5 EndPacket is iclass=12 & op2227=0x1b & op0607=2 & Rd5 & rs5 & rt5 & $(END_PACKET) { Rd5 = roundArithmetic(rs5, rt5); build EndPacket; } @@ -13093,9 +13562,9 @@ define pcodeop resume; # (v4,12) round -- "Rd32 = round ( Rs32 , Rt32 ) :sat" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 1 1 0 0 0 1 1 0 1 1 + s s s s s P P + t t t t t 1 1 + d d d d d +# 1 1 0 0 0 1 1 0 1 1 - s s s s s P P - t t t t t 1 1 - d d d d d -:round":sat" Rd5,rs5,rt5 EndPacket is iclass=12 & op2127=0x36 & op13=0 & op0507=6 & rt5 & Rd5 & rs5 & $(END_PACKET) { +:round":sat" Rd5,rs5,rt5 EndPacket is iclass=12 & op2227=0x1b & op0607=3 & rt5 & Rd5 & rs5 & $(END_PACKET) { Rd5 = roundArithmeticSaturate(rs5, rt5); build EndPacket; } @@ -13103,10 +13572,10 @@ define pcodeop resume; # (v5,8) round -- "Rd32 = round ( Rss32 ) :sat" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 1 0 0 0 1 0 0 0 1 1 0 s s s s s P P + + + + + + 0 0 1 d d d d d +# 1 0 0 0 1 0 0 0 1 1 0 s s s s s P P - - - - - - 0 0 1 d d d d d define pcodeop roundArithmeticPSat; -:round":sat" Rd5,rss5 EndPacket is iclass=8 & op2127=0x46 & op0513=1 & Rd5 & rss5 & $(END_PACKET) { +:round":sat" Rd5,rss5 EndPacket is iclass=8 & op2127=0x46 & op0507=1 & Rd5 & rss5 & $(END_PACKET) { Rd5 = roundArithmeticPSat(rss5); build EndPacket; } @@ -13114,9 +13583,9 @@ define pcodeop roundArithmeticPSat; # (v2,5) rte -- "rte" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 0 1 0 1 0 1 1 1 1 1 1 + + + + + P P 0 0 + + + + 0 0 0 + + + + + +# 0 1 0 1 0 1 1 1 1 1 1 - - - - - P P 0 0 - - - - 0 0 0 - - - - - -:rte EndPacket is iclass=5 & op2127=0x3f & op1620=0 & op0013=0 & $(END_PACKET) { +:rte EndPacket is iclass=5 & op2127=0x3f & op1213=0 & op0507=0 & $(END_PACKET) { # Treat as return dest:4 = $(ELR); build EndPacket; @@ -13128,9 +13597,9 @@ define pcodeop roundArithmeticPSat; # (v2,8) sat -- "Rd32 = sat ( Rss32 )" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 1 0 0 0 1 0 0 0 1 1 0 s s s s s P P + + + + + + 0 0 + d d d d d +# 1 0 0 0 1 0 0 0 1 1 0 s s s s s P P - - - - - - 0 0 - d d d d d -:sat Rd5,rss5 EndPacket is iclass=8 & op2127=0x46 & op0513=0 & Rd5 & rss5 & $(END_PACKET) { +:sat Rd5,rss5 EndPacket is iclass=8 & op2127=0x46 & op0607=0 & Rd5 & rss5 & $(END_PACKET) { Rd5 = saturate32(rss5); sat:1 = (rss5 s< 0xffffffff80000000) || (rss5 s> 0x7fffffff); build EndPacket; @@ -13141,9 +13610,9 @@ define pcodeop roundArithmeticPSat; # (v2,8) satb -- "Rd32 = satb ( Rs32 )" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 1 0 0 0 1 1 0 0 1 1 0 s s s s s P P + + + + + + 1 1 1 d d d d d +# 1 0 0 0 1 1 0 0 1 1 0 s s s s s P P - - - - - - 1 1 1 d d d d d -:satb Rd5,rs5 EndPacket is iclass=8 & op2127=0x66 & op0513=7 & Rd5 & rs5 & $(END_PACKET) { +:satb Rd5,rs5 EndPacket is iclass=8 & op2127=0x66 & op0507=7 & Rd5 & rs5 & $(END_PACKET) { byte:1 = saturate8(rs5); Rd5 = sext(byte); sat:1 = (rs5 s< 0xffffff80) || (rs5 s> 0x7f); @@ -13155,9 +13624,9 @@ define pcodeop roundArithmeticPSat; # (v2,8) sath -- "Rd32 = sath ( Rs32 )" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 1 0 0 0 1 1 0 0 1 1 0 s s s s s P P + + + + + + 1 0 0 d d d d d +# 1 0 0 0 1 1 0 0 1 1 0 s s s s s P P - - - - - - 1 0 0 d d d d d -:sath Rd5,rs5 EndPacket is iclass=8 & op2127=0x66 & op0513=4 & Rd5 & rs5 & $(END_PACKET) { +:sath Rd5,rs5 EndPacket is iclass=8 & op2127=0x66 & op0507=4 & Rd5 & rs5 & $(END_PACKET) { half:2 = saturate16(rs5); Rd5 = sext(half); sat:1 = (rs5 s< 0xffff8000) || (rs5 s> 0x7fff); @@ -13169,9 +13638,9 @@ define pcodeop roundArithmeticPSat; # (v2,8) satub -- "Rd32 = satub ( Rs32 )" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 1 0 0 0 1 1 0 0 1 1 0 s s s s s P P + + + + + + 1 1 0 d d d d d +# 1 0 0 0 1 1 0 0 1 1 0 s s s s s P P - - - - - - 1 1 0 d d d d d -:satub Rd5,rs5 EndPacket is iclass=8 & op2127=0x66 & op0513=6 & Rd5 & rs5 & $(END_PACKET) { +:satub Rd5,rs5 EndPacket is iclass=8 & op2127=0x66 & op0507=6 & Rd5 & rs5 & $(END_PACKET) { byte:1 = usaturate8(rs5); Rd5 = zext(byte); sat:1 = (rs5 > 0x7f); @@ -13183,9 +13652,9 @@ define pcodeop roundArithmeticPSat; # (v2,8) satuh -- "Rd32 = satuh ( Rs32 )" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 1 0 0 0 1 1 0 0 1 1 0 s s s s s P P + + + + + + 1 0 1 d d d d d +# 1 0 0 0 1 1 0 0 1 1 0 s s s s s P P - - - - - - 1 0 1 d d d d d -:satuh Rd5,rs5 EndPacket is iclass=8 & op2127=0x66 & op0513=5 & Rd5 & rs5 & $(END_PACKET) { +:satuh Rd5,rs5 EndPacket is iclass=8 & op2127=0x66 & op0507=5 & Rd5 & rs5 & $(END_PACKET) { half:2 = usaturate16(rs5); Rd5 = zext(half); sat:1 = (rs5 > 0x7fff); @@ -13208,10 +13677,11 @@ define pcodeop roundArithmeticPSat; # (v2,12) setbit -- "Rd32 = setbit ( Rs32 , Rt32 )" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 1 1 0 0 0 1 1 0 1 0 + s s s s s P P + t t t t t 0 0 + d d d d d +# 1 1 0 0 0 1 1 0 1 0 - s s s s s P P - t t t t t 0 0 - d d d d d -:setbit Rd5,rs5,rt5 EndPacket is iclass=12 & op2127=0x34 & op13=0 & op0507=0 & Rd5 & rs5 & rt5 & $(END_PACKET) { - mask:4 = 1 << rt5; +:setbit Rd5,rs5,rt5 EndPacket is iclass=12 & op2227=0x1a & op0607=0 & Rd5 & rs5 & rt5 & $(END_PACKET) { + shamt:4 = (rt5 << 25) s>> 25; + mask:4 = zext(shamt s>= 0) * (1 << shamt); Rd5 = rs5 | mask; build EndPacket; } @@ -13219,11 +13689,11 @@ define pcodeop roundArithmeticPSat; # (v4,6) setimask -- "setimask ( Pt4 , Rs32 )" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 0 1 1 0 0 1 0 0 1 0 0 s s s s s P P + + + + t t 0 0 0 + + + + + +# 0 1 1 0 0 1 0 0 1 0 0 s s s s s P P - - - - t t 0 0 0 - - - - - define pcodeop setimask; # TODO: Determine what is affected by this instruction -:setimask pu0809,rs5 EndPacket is iclass=6 & op2127=0x24 & op1013=0 & op0007=0 & pu0809 & rs5 & $(END_PACKET) { +:setimask pu0809,rs5 EndPacket is iclass=6 & op2127=0x24 & op0507=0 & pu0809 & rs5 & $(END_PACKET) { setimask(pu0809,rs5); build EndPacket; } @@ -13242,11 +13712,11 @@ define pcodeop setprio; # (v2,12) shuffeb -- "Rdd32 = shuffeb ( Rss32 , Rtt32 )" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 1 1 0 0 0 0 0 1 0 0 + s s s s s P P + t t t t t 0 1 + d d d d d +# 1 1 0 0 0 0 0 1 0 0 - s s s s s P P - t t t t t 0 1 - d d d d d define pcodeop shuffeb; -:shuffeb Rdd5,rss5,rtt5 EndPacket is iclass=12 & op2127=0x08 & op13=0 & op0507=2 & Rdd5 & rss5 & rtt5 & $(END_PACKET) { +:shuffeb Rdd5,rss5,rtt5 EndPacket is iclass=12 & op2227=0x4 & op0607=1 & Rdd5 & rss5 & rtt5 & $(END_PACKET) { Rdd5 = shuffeb(rss5,rtt5); build EndPacket; } @@ -13254,11 +13724,11 @@ define pcodeop shuffeb; # (v2,12) shuffeh -- "Rdd32 = shuffeh ( Rss32 , Rtt32 )" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 1 1 0 0 0 0 0 1 0 0 + s s s s s P P + t t t t t 1 1 + d d d d d +# 1 1 0 0 0 0 0 1 0 0 - s s s s s P P - t t t t t 1 1 - d d d d d define pcodeop shuffeh; -:shuffeh Rdd5,rss5,rtt5 EndPacket is iclass=12 & op2127=0x08 & op13=0 & op0507=6 & Rdd5 & rss5 & rtt5 & $(END_PACKET) { +:shuffeh Rdd5,rss5,rtt5 EndPacket is iclass=12 & op2227=0x4 & op0607=3 & Rdd5 & rss5 & rtt5 & $(END_PACKET) { Rdd5 = shuffeh(rss5,rtt5); build EndPacket; } @@ -13266,33 +13736,33 @@ define pcodeop shuffeh; # (v2,12) shuffob -- "Rdd32 = shuffob ( Rtt32 , Rss32 )" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 1 1 0 0 0 0 0 1 0 0 + s s s s s P P + t t t t t 1 0 + d d d d d +# 1 1 0 0 0 0 0 1 0 0 - s s s s s P P - t t t t t 1 0 - d d d d d define pcodeop shuffob; -:shuffob Rdd5,rss5,rtt5 EndPacket is iclass=12 & op2127=0x08 & op13=0 & op0507=4 & Rdd5 & rss5 & rtt5 & $(END_PACKET) { - Rdd5 = shuffob(rss5,rtt5); +:shuffob Rdd5,rtt5,rss5 EndPacket is iclass=12 & op2227=0x4 & op0607=2 & Rdd5 & rss5 & rtt5 & $(END_PACKET) { + Rdd5 = shuffob(rtt5,rss5); build EndPacket; } # (v2,12) shuffoh -- "Rdd32 = shuffoh ( Rtt32 , Rss32 )" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 1 1 0 0 0 0 0 1 1 0 + s s s s s P P + t t t t t 0 0 + d d d d d +# 1 1 0 0 0 0 0 1 1 0 - s s s s s P P - t t t t t 0 0 0 d d d d d define pcodeop shuffoh; -:shuffoh Rdd5,rss5,rtt5 EndPacket is iclass=12 & op2127=0x0c & op13=0 & op0507=0 & Rdd5 & rss5 & rtt5 & $(END_PACKET) { - Rdd5 = shuffoh(rss5,rtt5); +:shuffoh Rdd5,rtt5,rss5 EndPacket is iclass=12 & op2227=0x6 & op0607=0 & op5=0 & Rdd5 & rss5 & rtt5 & $(END_PACKET) { + Rdd5 = shuffoh(rtt5,rss5); build EndPacket; } # (v4,6) siad -- "siad ( Rs32 )" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 0 1 1 0 0 1 0 0 1 0 0 s s s s s P P + + + + + + 0 1 1 + + + + + +# 0 1 1 0 0 1 0 0 1 0 0 s s s s s P P - - - - - - 0 1 1 - - - - - -:siad rs5 EndPacket is iclass=6 & op2127=0x24 & op0013=0x60 & rs5 & $(END_PACKET) { +:siad rs5 EndPacket is iclass=6 & op2127=0x24 & op0507=0x3 & rs5 & $(END_PACKET) { S22 = S22 | rs5; build EndPacket; } @@ -13302,7 +13772,7 @@ define pcodeop shuffoh; # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| # 0 1 1 0 1 0 0 1 1 0 1 I I I I I P P - i i i i i I I I i i - I I -:sp1loop0 P3,LoopRelMem7x,LoopUimm10 EndPacket is iclass=6 & op2127=0x4d & op13=0 & op2=0 & P3 & LoopRelMem7x & LoopRelAddr7x & LoopUimm10 & $(END_PACKET) [ useLoopCfg=1; ] { +:sp1loop0 P3,LoopRelMem7x,LoopUimm10 EndPacket is iclass=6 & op2127=0x4d & P3 & LoopRelMem7x & LoopRelAddr7x & LoopUimm10 & $(END_PACKET) [ useLoopCfg=1; ] { SA0_ = LoopRelAddr7x; LC0_ = LoopUimm10; build EndPacket; @@ -13318,7 +13788,7 @@ define pcodeop shuffoh; # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| # 0 1 1 0 0 0 0 0 1 0 1 s s s s s P P - i i i i i - - - i i - - - -:sp1loop0 P3,LoopRelMem7x,rs5 EndPacket is iclass=6 & op2127=5 & op13=0 & op0507=0 & op0002=0 & P3 & LoopRelMem7x & LoopRelAddr7x & rs5 & $(END_PACKET) [ useLoopCfg=1; ] { +:sp1loop0 P3,LoopRelMem7x,rs5 EndPacket is iclass=6 & op2127=5 & P3 & LoopRelMem7x & LoopRelAddr7x & rs5 & $(END_PACKET) [ useLoopCfg=1; ] { SA0_ = LoopRelAddr7x; LC0_ = rs5; build EndPacket; @@ -13334,7 +13804,7 @@ define pcodeop shuffoh; # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| # 0 1 1 0 1 0 0 1 1 1 0 I I I I I P P - i i i i i I I I i i - I I -:sp2loop0 P3,LoopRelMem7x,LoopUimm10 EndPacket is iclass=6 & op2127=0x4e & op13=0 & op2=0 & P3 & LoopRelMem7x & LoopRelAddr7x & LoopUimm10 & $(END_PACKET) [ useLoopCfg=1; ] { +:sp2loop0 P3,LoopRelMem7x,LoopUimm10 EndPacket is iclass=6 & op2127=0x4e & P3 & LoopRelMem7x & LoopRelAddr7x & LoopUimm10 & $(END_PACKET) [ useLoopCfg=1; ] { SA0_ = LoopRelAddr7x; LC0_ = LoopUimm10; build EndPacket; @@ -13350,7 +13820,7 @@ define pcodeop shuffoh; # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| # 0 1 1 0 0 0 0 0 1 1 0 s s s s s P P - i i i i i - - - i i - - - -:sp2loop0 P3,LoopRelMem7x,rs5 EndPacket is iclass=6 & op2127=6 & op13=0 & op0507=0 & op0002=0 & P3 & LoopRelMem7x & LoopRelAddr7x & rs5 & $(END_PACKET) [ useLoopCfg=1; ] { +:sp2loop0 P3,LoopRelMem7x,rs5 EndPacket is iclass=6 & op2127=6 & P3 & LoopRelMem7x & LoopRelAddr7x & rs5 & $(END_PACKET) [ useLoopCfg=1; ] { SA0_ = LoopRelAddr7x; LC0_ = rs5; build EndPacket; @@ -13366,7 +13836,7 @@ define pcodeop shuffoh; # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| # 0 1 1 0 1 0 0 1 1 1 1 I I I I I P P - i i i i i I I I i i - I I -:sp3loop0 P3,LoopRelMem7x,LoopUimm10 EndPacket is iclass=6 & op2127=0x4f & op13=0 & op2=0 & P3 & LoopRelMem7x & LoopRelAddr7x & LoopUimm10 & $(END_PACKET) [ useLoopCfg=1; ] { +:sp3loop0 P3,LoopRelMem7x,LoopUimm10 EndPacket is iclass=6 & op2127=0x4f & P3 & LoopRelMem7x & LoopRelAddr7x & LoopUimm10 & $(END_PACKET) [ useLoopCfg=1; ] { SA0_ = LoopRelAddr7x; LC0_ = LoopUimm10; build EndPacket; @@ -13382,7 +13852,7 @@ define pcodeop shuffoh; # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| # 0 1 1 0 0 0 0 0 1 1 1 s s s s s P P - i i i i i - - - i i - - - -:sp3loop0 P3,LoopRelMem7x,rs5 EndPacket is iclass=6 & op2127=7 & op13=0 & op0507=0 & op0002=0 & P3 & LoopRelMem7x & LoopRelAddr7x & rs5 & $(END_PACKET) [ useLoopCfg=1; ] { +:sp3loop0 P3,LoopRelMem7x,rs5 EndPacket is iclass=6 & op2127=7 & P3 & LoopRelMem7x & LoopRelAddr7x & rs5 & $(END_PACKET) [ useLoopCfg=1; ] { SA0_ = LoopRelAddr7x; LC0_ = rs5; build EndPacket; @@ -13422,37 +13892,41 @@ define pcodeop stop; # (v2,13) sub -- "Rd32 = sub ( Rt32.h , Rs32.h ) :sat :<<16" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 1 1 0 1 0 1 0 1 0 1 1 s s s s s P P + t t t t t 1 1 1 d d d d d +# 1 1 0 1 0 1 0 1 0 1 1 s s s s s P P - t t t t t 1 1 1 d d d d d # # (v2,13) sub -- "Rd32 = sub ( Rt32.l , Rs32.h ) :sat :<<16" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 1 1 0 1 0 1 0 1 0 1 1 s s s s s P P + t t t t t 1 0 1 d d d d d +# 1 1 0 1 0 1 0 1 0 1 1 s s s s s P P - t t t t t 1 0 1 d d d d d # # (v2,13) sub -- "Rd32 = sub ( Rt32.h , Rs32.l ) :sat :<<16" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 1 1 0 1 0 1 0 1 0 1 1 s s s s s P P + t t t t t 1 1 0 d d d d d +# 1 1 0 1 0 1 0 1 0 1 1 s s s s s P P - t t t t t 1 1 0 d d d d d # # (v2,13) sub -- "Rd32 = sub ( Rt32.l , Rs32.l ) :sat :<<16" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 1 1 0 1 0 1 0 1 0 1 1 s s s s s P P + t t t t t 1 0 0 d d d d d +# 1 1 0 1 0 1 0 1 0 1 1 s s s s s P P - t t t t t 1 0 0 d d d d d -:sub^":sat:<<16" Rd5,Rt5HL06,Rs5HL05 EndPacket is iclass=0xd & op2127=0x2b & op13=0 & op7=1 & Rs5HL05 & Rt5HL06 & Rd5 & $(END_PACKET) -unimpl +define pcodeop subSatX16; + +:sub^":sat:<<16" Rd5,Rt5HL06,Rs5HL05 EndPacket is iclass=0xd & op2127=0x2b & op7=1 & Rs5HL05 & Rt5HL06 & Rd5 & $(END_PACKET) { + Rd5 = subSatX16(Rt5HL06, Rs5HL05); + build EndPacket; +} # (v2,13) sub -- "Rd32 = sub ( Rt32.l , Rs32.h )" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 1 1 0 1 0 1 0 1 0 0 1 s s s s s P P + t t t t t 0 1 + d d d d d +# 1 1 0 1 0 1 0 1 0 0 1 s s s s s P P - t t t t t 0 1 - d d d d d # # (v2,13) sub -- "Rd32 = sub ( Rt32.l , Rs32.l )" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 1 1 0 1 0 1 0 1 0 0 1 s s s s s P P + t t t t t 0 0 + d d d d d +# 1 1 0 1 0 1 0 1 0 0 1 s s s s s P P - t t t t t 0 0 - d d d d d -:sub Rd5,rt5L,Rs5HL06 EndPacket is iclass=0xd & op2127=0x29 & op13=0 & op7=0 & op5=0 & rt5L & Rs5HL06 & Rd5 & $(END_PACKET) +:sub Rd5,rt5L,Rs5HL06 EndPacket is iclass=0xd & op2127=0x29 & op7=0 & rt5L & Rs5HL06 & Rd5 & $(END_PACKET) { Rd5 = sext(rt5L - Rs5HL06); build EndPacket; @@ -13461,24 +13935,24 @@ unimpl # (v2,13) sub -- "Rd32 = sub ( Rt32.h , Rs32.h ) :<<16" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 1 1 0 1 0 1 0 1 0 1 1 s s s s s P P + t t t t t 0 1 1 d d d d d +# 1 1 0 1 0 1 0 1 0 1 1 s s s s s P P - t t t t t 0 1 1 d d d d d # # (v2,13) sub -- "Rd32 = sub ( Rt32.h , Rs32.l ) :<<16" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 1 1 0 1 0 1 0 1 0 1 1 s s s s s P P + t t t t t 0 1 0 d d d d d +# 1 1 0 1 0 1 0 1 0 1 1 s s s s s P P - t t t t t 0 1 0 d d d d d # # (v2,13) sub -- "Rd32 = sub ( Rt32.l , Rs32.h ) :<<16" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 1 1 0 1 0 1 0 1 0 1 1 s s s s s P P + t t t t t 0 0 1 d d d d d +# 1 1 0 1 0 1 0 1 0 1 1 s s s s s P P - t t t t t 0 0 1 d d d d d # # (v2,13) sub -- "Rd32 = sub ( Rt32.l , Rs32.l ) :<<16" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 1 1 0 1 0 1 0 1 0 1 1 s s s s s P P + t t t t t 0 0 0 d d d d d +# 1 1 0 1 0 1 0 1 0 1 1 s s s s s P P - t t t t t 0 0 0 d d d d d -:sub^":<<16" Rd5,Rt5HL06,Rs5HL05 EndPacket is iclass=0xd & op2127=0x2b & op13=0 & op7=0 & Rs5HL05 & Rt5HL06 & Rd5 & $(END_PACKET) +:sub^":<<16" Rd5,Rt5HL06,Rs5HL05 EndPacket is iclass=0xd & op2127=0x2b & op7=0 & Rs5HL05 & Rt5HL06 & Rd5 & $(END_PACKET) { Rd5 = zext(Rt5HL06 - Rs5HL05) << 16; build EndPacket; @@ -13487,14 +13961,14 @@ unimpl # (v2,13) sub -- "Rd32 = sub ( Rt32.l , Rs32.h ) :sat" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 1 1 0 1 0 1 0 1 0 0 1 s s s s s P P + t t t t t 1 1 + d d d d d +# 1 1 0 1 0 1 0 1 0 0 1 s s s s s P P - t t t t t 1 1 - d d d d d # # (v2,13) sub -- "Rd32 = sub ( Rt32.l , Rs32.l ) :sat" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 1 1 0 1 0 1 0 1 0 0 1 s s s s s P P + t t t t t 1 0 + d d d d d +# 1 1 0 1 0 1 0 1 0 0 1 s s s s s P P - t t t t t 1 0 - d d d d d -:sub^":sat" Rd5,rt5L,Rs5HL06 EndPacket is iclass=0xd & op2127=0x29 & rs5 & op13=0 & op7=1 & op5=0 & rt5L & Rs5HL06 & Rd5 & $(END_PACKET) +:sub^":sat" Rd5,rt5L,Rs5HL06 EndPacket is iclass=0xd & op2127=0x29 & op7=1 & rs5 & rt5L & Rs5HL06 & Rd5 & $(END_PACKET) { subSat16(Rd5, rt5L, Rs5HL06); sat:1 = sborrow(rt5L, Rs5HL06); @@ -13524,9 +13998,9 @@ unimpl # (v2,15) sub -- "Rd32 = sub ( Rt32 , Rs32 )" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 1 1 1 1 0 0 1 1 0 0 1 s s s s s P P + t t t t t + + + d d d d d +# 1 1 1 1 0 0 1 1 0 0 1 s s s s s P P - t t t t t - - - d d d d d -:sub Rd5,rt5,rs5 EndPacket is iclass=15 & op2127=0x19 & op13=0 & op0507=0 & rs5 & rt5 & Rd5 & $(END_PACKET) +:sub Rd5,rt5,rs5 EndPacket is iclass=15 & op2127=0x19 & rs5 & rt5 & Rd5 & $(END_PACKET) { Rd5 = rt5 - rs5; build EndPacket; @@ -13535,9 +14009,9 @@ unimpl # (v4,15) sub -- "Rd32 = sub ( Rt32 , Rs32 ) :sat" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 1 1 1 1 0 1 1 0 1 1 0 s s s s s P P + t t t t t + + + d d d d d +# 1 1 1 1 0 1 1 0 1 1 0 s s s s s P P - t t t t t - - - d d d d d -:sub":sat" Rd5,rt5,rs5 EndPacket is iclass=15 & op2127=0x36 & op13=0 & op0507=0 & rs5 & rt5 & Rd5 & $(END_PACKET) { +:sub":sat" Rd5,rt5,rs5 EndPacket is iclass=15 & op2127=0x36 & rs5 & rt5 & Rd5 & $(END_PACKET) { subSat32(Rd5, rt5, rs5); sat:1 = sborrow(rt5, rs5); build EndPacket; @@ -13548,9 +14022,9 @@ unimpl # (v2,13) sub -- "Rd32 = sub ( Rt32 , Rs32 ) :sat :deprecated" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 1 1 0 1 0 1 0 1 1 0 0 s s s s s P P + t t t t t 1 + + d d d d d +# 1 1 0 1 0 1 0 1 1 0 0 s s s s s P P - t t t t t 1 - - d d d d d -:sub":sat:deprecated" Rd5,rt5,rs5 EndPacket is iclass=13 & op2127=0x2c & op13=0 & op0507=4 & rs5 & rt5 & Rd5 & $(END_PACKET) { +:sub":sat:deprecated" Rd5,rt5,rs5 EndPacket is iclass=13 & op2127=0x2c & op7=1 & rs5 & rt5 & Rd5 & $(END_PACKET) { subSat32(Rd5, rt5, rs5); sat:1 = sborrow(rt5, rs5); build EndPacket; @@ -13561,23 +14035,26 @@ unimpl # (v4,12) sub -- "Rdd32 = sub ( Rss32 , Rtt32 , Px4 ) :carry" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 1 1 0 0 0 0 1 0 1 1 1 s s s s s P P + t t t t t + x x d d d d d +# 1 1 0 0 0 0 1 0 1 1 1 s s s s s P P - t t t t t - x x d d d d d -:sub":carry" Rdd5,rss5,rtt5,pu0506 EndPacket is iclass=12 & op2127=0x17 & op13=0 & op7=0 & Rdd5 & rss5 & rtt5 & pu0506 & pu0506_ & $(END_PACKET) { - prevCarry:8 = zext(pu0506); - pu0506_ = (rss5 < rtt5) | carry(rtt5,prevCarry); # compute new carry - Rdd5 = rss5 - rtt5 - prevCarry; +:sub":carry" Rdd5,rss5,rtt5,pu0506 EndPacket is iclass=12 & op2127=0x17 & Rdd5 & rss5 & rtt5 & pu0506 & pu0506_ & $(END_PACKET) { + cin:8 = zext(pu0506 & 1); # carry-in (not-borrow): bit 0 of predicate + partial:8 = rss5 + ~rtt5; # Rss + ~Rtt = Rss - Rtt - 1 (mod 2^64) + c1:1 = carry(rss5, ~rtt5); # carry from Rss + ~Rtt (i.e. Rss > Rtt) + c2:1 = carry(partial, cin); # carry if partial + cin also overflows + Rdd5 = partial + cin; # = Rss - Rtt - 1 + cin = Rss - Rtt + (cin-1) + pu0506_ = (c1 | c2) * 0xff; build EndPacket; <> - pu0506 = pu0506_; + pu0506 = pu0506_; } # (v2,13) sub -- "Rdd32 = sub ( Rtt32 , Rss32 )" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 1 1 0 1 0 0 1 1 0 0 1 s s s s s P P + t t t t t 1 1 1 d d d d d +# 1 1 0 1 0 0 1 1 0 0 1 s s s s s P P - t t t t t 1 1 1 d d d d d -:sub Rdd5,rtt5,rss5 EndPacket is iclass=0xd & op2127=0x19 & rss5 & op13=0 & rtt5 & op0507=0x7 & Rdd5 & $(END_PACKET) +:sub Rdd5,rtt5,rss5 EndPacket is iclass=0xd & op2127=0x19 & op0507=0x7 & rss5 & rtt5 & Rdd5 & $(END_PACKET) { Rdd5 = rtt5 - rss5; build EndPacket; @@ -13586,9 +14063,9 @@ unimpl # (v2,14) sub -- "Rx32 += sub ( Rt32 , Rs32 )" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 1 1 1 0 1 1 1 1 0 0 0 s s s s s P P + t t t t t + 1 1 x x x x x +# 1 1 1 0 1 1 1 1 0 0 0 s s s s s P P - t t t t t - 1 1 x x x x x -:sub+= Rd5,rt5,rs5 EndPacket is iclass=0xe & op2127=0x78 & rs5 & op13=0 & op0507=0x3 & rt5 & rd5 & Rd5 & $(END_PACKET) +:sub+= Rd5,rt5,rs5 EndPacket is iclass=0xe & op2127=0x78 & op0506=0x3 & rs5 & rt5 & rd5 & Rd5 & $(END_PACKET) { Rd5 = rd5 + (rt5 - rs5); build EndPacket; @@ -13597,14 +14074,14 @@ unimpl # (v4,13) sub -- "Rx32 = sub ( #u8x , asl ( Rx32 , #U5 ) )" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 1 1 0 1 1 1 1 0 i i i x x x x x P P i I I I I I i i i 0 i 1 1 + +# 1 1 0 1 1 1 1 0 i i i x x x x x P P i I I I I I i i i 0 i 1 1 - # # (v4,13) sub -- "Rx32 = sub ( #u8x , lsr ( Rx32 , #U5 ) )" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 1 1 0 1 1 1 1 0 i i i x x x x x P P i I I I I I i i i 1 i 1 1 + +# 1 1 0 1 1 1 1 0 i i i x x x x x P P i I I I I I i i i 1 i 1 1 - -:sub Rx5,Uimm32_2123_13_0507_03x,ShiftRx_D04_I0812 EndPacket is iclass=13 & op2427=14 & op0002=6 & Uimm32_2123_13_0507_03x & ShiftRx_D04_I0812 & Rx5 & $(END_PACKET) +:sub Rx5,Uimm32_2123_13_0507_03x,ShiftRx_D04_I0812 EndPacket is iclass=13 & op2427=14 & op0102=3 & Uimm32_2123_13_0507_03x & ShiftRx_D04_I0812 & Rx5 & $(END_PACKET) { Rx5 = Uimm32_2123_13_0507_03x - ShiftRx_D04_I0812; build EndPacket; @@ -13613,31 +14090,33 @@ unimpl # (v2,15) sub -- "if ( Pu4 ) Rd32 = sub ( Rt32 , Rs32 )" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 1 1 1 1 1 0 1 1 0 + 1 s s s s s P P 0 t t t t t 0 u u d d d d d +# 1 1 1 1 1 0 1 1 0 - 1 s s s s s P P 0 t t t t t 0 u u d d d d d # # (v2,15) sub -- "if ( ! Pu4 ) Rd32 = sub ( Rt32 , Rs32 )" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 1 1 1 1 1 0 1 1 0 + 1 s s s s s P P 0 t t t t t 1 u u d d d d d +# 1 1 1 1 1 0 1 1 0 - 1 s s s s s P P 0 t t t t t 1 u u d d d d d # # (v2,15) sub -- "if ( Pu4 .new ) Rd32 = sub ( Rt32 , Rs32 )" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 1 1 1 1 1 0 1 1 0 + 1 s s s s s P P 1 t t t t t 0 u u d d d d d +# 1 1 1 1 1 0 1 1 0 - 1 s s s s s P P 1 t t t t t 0 u u d d d d d # # (v2,15) sub -- "if ( ! Pu4 .new ) Rd32 = sub ( Rt32 , Rs32 )" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 1 1 1 1 1 0 1 1 0 + 1 s s s s s P P 1 t t t t t 1 u u d d d d d +# 1 1 1 1 1 0 1 1 0 - 1 s s s s s P P 1 t t t t t 1 u u d d d d d -:sub^PuCond0506_N13_S07 rd5,rt5,rs5 EndPacket is iclass=15 & op2327=0x16 & op22=0 & op21=1 & PuCond0506_N13_S07 & rs5 & rt5 & rd5 & rd5_ & SetNRegRd5 & $(END_PACKET) { +:sub^PuCond0506_N13_S07 rd5,rt5,rs5 EndPacket is iclass=15 & op2327=0x16 & op21=1 & PuCond0506_N13_S07 & rs5 & rt5 & rd5 & rd5_ & SetNRegRd5 & $(END_PACKET) { build PuCond0506_N13_S07; build EndPacket; <> + build PuCond0506_N13_S07; if (ConditionReg == 0) goto ; rd5_ = rt5 - rs5; <> + build PuCond0506_N13_S07; if (ConditionReg == 0) goto ; rd5 = rd5_; @@ -13646,11 +14125,11 @@ unimpl # (v2,6) swi -- "swi ( Rs32 )" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 0 1 1 0 0 1 0 0 0 0 0 s s s s s P P + + + + + + 0 0 0 + + + + + +# 0 1 1 0 0 1 0 0 0 0 0 s s s s s P P - - - - - - 0 0 0 - - - - - define pcodeop swi; -:swi rs5 EndPacket is iclass=6 & op2127=0x20 & op0013=0x00 & rs5 & $(END_PACKET) { +:swi rs5 EndPacket is iclass=6 & op2127=0x20 & op0507=0x0 & rs5 & $(END_PACKET) { swi(rs5); build EndPacket; } @@ -13658,11 +14137,11 @@ define pcodeop swi; # (v2,8) swiz -- "Rd32 = swiz ( Rs32 )" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 1 0 0 0 1 1 0 0 1 0 0 s s s s s P P + + + + + + 1 1 1 d d d d d +# 1 0 0 0 1 1 0 0 1 0 0 s s s s s P P - - - - - - 1 1 1 d d d d d define pcodeop swizzle; -:swiz Rd5,rs5 EndPacket is iclass=8 & op2127=0x64 & op0513=0x07 & rs5 & Rd5 & $(END_PACKET) { +:swiz Rd5,rs5 EndPacket is iclass=8 & op2127=0x64 & op0507=0x7 & rs5 & Rd5 & $(END_PACKET) { Rd5 = swizzle(rs5); build EndPacket; } @@ -13670,9 +14149,9 @@ define pcodeop swizzle; # (v2,7) sxtb -- "Rd32 = sxtb ( Rs32 )" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 0 1 1 1 0 0 0 0 1 0 1 s s s s s P P 0 + + + + + + + + d d d d d +# 0 1 1 1 0 0 0 0 1 0 1 s s s s s P P 0 - - - - - - - - d d d d d -:sxtb Rd5,rs5 EndPacket is iclass=7 & op2127=0x05 & op0513=0 & rs5 & Rd5 & $(END_PACKET) +:sxtb Rd5,rs5 EndPacket is iclass=7 & op2127=0x05 & op13=0 & rs5 & Rd5 & $(END_PACKET) { Rd5 = sext(rs5:1); build EndPacket; @@ -13681,32 +14160,34 @@ define pcodeop swizzle; # (v4,7) sxtb -- "if ( Pu4 ) Rd32 = sxtb ( Rs32 )" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 0 1 1 1 0 0 0 0 1 0 1 s s s s s P P 1 + 0 0 u u + + + d d d d d +# 0 1 1 1 0 0 0 0 1 0 1 s s s s s P P 1 - 0 0 u u - - - d d d d d # # (v4,7) sxtb -- "if ( ! Pu4 ) Rd32 = sxtb ( Rs32 )" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 0 1 1 1 0 0 0 0 1 0 1 s s s s s P P 1 + 1 0 u u + + + d d d d d +# 0 1 1 1 0 0 0 0 1 0 1 s s s s s P P 1 - 1 0 u u - - - d d d d d # # (v4,7) sxtb -- "if ( Pu4 .new ) Rd32 = sxtb ( Rs32 )" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 0 1 1 1 0 0 0 0 1 0 1 s s s s s P P 1 + 0 1 u u + + + d d d d d +# 0 1 1 1 0 0 0 0 1 0 1 s s s s s P P 1 - 0 1 u u - - - d d d d d # # (v4,7) sxtb -- "if ( ! Pu4 .new ) Rd32 = sxtb ( Rs32 )" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 0 1 1 1 0 0 0 0 1 0 1 s s s s s P P 1 + 1 1 u u + + + d d d d d +# 0 1 1 1 0 0 0 0 1 0 1 s s s s s P P 1 - 1 1 u u - - - d d d d d -:sxtb^PuCond0809_N10_S11 rd5,rs5 EndPacket is iclass=7 & op2127=0x05 & op1213=2 & op0507=0 & rs5 & rd5 & rd5_ & SetNRegRd5 & PuCond0809_N10_S11 & $(END_PACKET) +:sxtb^PuCond0809_N10_S11 rd5,rs5 EndPacket is iclass=7 & op2127=0x05 & op13=1 & rs5 & rd5 & rd5_ & SetNRegRd5 & PuCond0809_N10_S11 & $(END_PACKET) { build PuCond0809_N10_S11; build EndPacket; <> + build PuCond0809_N10_S11; if (ConditionReg == 0) goto ; rd5_ = sext(rs5:1); <> + build PuCond0809_N10_S11; if (ConditionReg == 0) goto ; rd5 = rd5_; @@ -13715,9 +14196,9 @@ define pcodeop swizzle; # (v2,7) sxth -- "Rd32 = sxth ( Rs32 )" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 0 1 1 1 0 0 0 0 1 1 1 s s s s s P P 0 + + + + + + + + d d d d d +# 0 1 1 1 0 0 0 0 1 1 1 s s s s s P P 0 - - - - - - - - d d d d d -:sxth Rd5,rs5 EndPacket is iclass=7 & op2127=0x07 & op0513=0 & rs5 & Rd5 & $(END_PACKET) +:sxth Rd5,rs5 EndPacket is iclass=7 & op2127=0x07 & op13=0 & rs5 & Rd5 & $(END_PACKET) { Rd5 = sext(rs5:2); build EndPacket; @@ -13726,32 +14207,34 @@ define pcodeop swizzle; # (v4,7) sxth -- "if ( Pu4 ) Rd32 = sxth ( Rs32 )" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 0 1 1 1 0 0 0 0 1 1 1 s s s s s P P 1 + 0 0 u u + + + d d d d d +# 0 1 1 1 0 0 0 0 1 1 1 s s s s s P P 1 - 0 0 u u - - - d d d d d # # (v4,7) sxth -- "if ( ! Pu4 ) Rd32 = sxth ( Rs32 )" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 0 1 1 1 0 0 0 0 1 1 1 s s s s s P P 1 + 1 0 u u + + + d d d d d +# 0 1 1 1 0 0 0 0 1 1 1 s s s s s P P 1 - 1 0 u u - - - d d d d d # # (v4,7) sxth -- "if ( Pu4 .new ) Rd32 = sxth ( Rs32 )" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 0 1 1 1 0 0 0 0 1 1 1 s s s s s P P 1 + 0 1 u u + + + d d d d d +# 0 1 1 1 0 0 0 0 1 1 1 s s s s s P P 1 - 0 1 u u - - - d d d d d # # (v4,7) sxth -- "if ( ! Pu4 .new ) Rd32 = sxth ( Rs32 )" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 0 1 1 1 0 0 0 0 1 1 1 s s s s s P P 1 + 1 1 u u + + + d d d d d +# 0 1 1 1 0 0 0 0 1 1 1 s s s s s P P 1 - 1 1 u u - - - d d d d d -:sxth^PuCond0809_N10_S11 rd5,rs5 EndPacket is iclass=7 & op2127=0x07 & op1213=2 & op0507=0 & rs5 & rd5 & rd5_ & SetNRegRd5 & PuCond0809_N10_S11 & $(END_PACKET) +:sxth^PuCond0809_N10_S11 rd5,rs5 EndPacket is iclass=7 & op2127=0x07 & op13=1 & rs5 & rd5 & rd5_ & SetNRegRd5 & PuCond0809_N10_S11 & $(END_PACKET) { build PuCond0809_N10_S11; build EndPacket; <> + build PuCond0809_N10_S11; if (ConditionReg == 0) goto ; rd5_ = sext(rs5:2); <> + build PuCond0809_N10_S11; if (ConditionReg == 0) goto ; rd5 = rd5_; @@ -13760,9 +14243,9 @@ define pcodeop swizzle; # (v2,8) sxtw -- "Rdd32 = sxtw ( Rs32 )" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 1 0 0 0 0 1 0 0 0 1 + s s s s s P P + + + + + + 0 0 + d d d d d +# 1 0 0 0 0 1 0 0 0 1 - s s s s s P P - - - - - - 0 0 - d d d d d -:sxtw Rdd5,rs5 EndPacket is iclass=8 & op2127=0x22 & op0513=0 & rs5 & Rdd5 & $(END_PACKET) +:sxtw Rdd5,rs5 EndPacket is iclass=8 & op2227=0x11 & op0607=0 & rs5 & Rdd5 & $(END_PACKET) { Rdd5 = sext(rs5); build EndPacket; @@ -13843,7 +14326,7 @@ define pcodeop syncht; # (v65,6) tlbinvasid -- "tlbinvasid( Rs32 )" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 0 1 1 0 1 1 0 0 1 0 1 s s s s s P P + + + + + + + + + + + + + + +# 0 1 1 0 1 1 0 0 1 0 1 s s s s s P P - - - - - - - - - - - - - - define pcodeop tlbinvasid; @@ -13855,11 +14338,11 @@ define pcodeop tlbinvasid; # (v4,6) tlblock -- "tlblock" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 0 1 1 0 1 1 0 0 0 0 1 + + + + + P P + + + + + + 0 0 1 + + + + + +# 0 1 1 0 1 1 0 0 0 0 1 - - - - - P P - - - - - - 0 0 1 - - - - - define pcodeop tlblock; -:tlblock EndPacket is iclass=6 & op2127=0x61 & op1620=0 & op0013=0x20 & $(END_PACKET) { +:tlblock EndPacket is iclass=6 & op2127=0x61 & op0507=0x1 & $(END_PACKET) { tlblock(); build EndPacket; } @@ -13867,11 +14350,11 @@ define pcodeop tlblock; # (v4,13) tlbmatch -- "Pd4 = tlbmatch ( Rss32 , Rt32 )" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 1 1 0 1 0 0 1 0 0 + + s s s s s P P 1 t t t t t 0 1 1 + + + d d +# 1 1 0 1 0 0 1 0 0 - - s s s s s P P 1 t t t t t 0 1 1 - - - d d define pcodeop tlbmatch; -:tlbmatch Pd2,rss5,rt5 EndPacket is iclass=13 & op2127=0x10 & op13=1 & op0207=0x18 & Pd2 & rss5 & rt5 & $(END_PACKET) { +:tlbmatch Pd2,rss5,rt5 EndPacket is iclass=13 & op2327=0x4 & op13=1 & op0507=0x3 & Pd2 & rss5 & rt5 & $(END_PACKET) { Pd2 = tlbmatch(rss5,rt5); build EndPacket; } @@ -13879,7 +14362,7 @@ define pcodeop tlbmatch; # (v65,6) tlboc -- "Rd32 = tlboc( Rss32 )" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 0 1 1 0 1 1 0 0 1 1 1 s s s s s P P + + + + + + + + + d d d d d +# 0 1 1 0 1 1 0 0 1 1 1 s s s s s P P - - - - - - - - - d d d d d define pcodeop tlboc; @@ -13891,23 +14374,33 @@ define pcodeop tlboc; # (v2,6) tlbp -- "Rd32 = tlbp ( Rs32 )" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 0 1 1 0 1 1 0 0 1 0 0 s s s s s P P + + + + + + + + + d d d d d +# 0 1 1 0 1 1 0 0 1 0 0 s s s s s P P - - - - - - - - - d d d d d define pcodeop tlbp; -:tlbp Rd5,rs5 EndPacket is iclass=6 & op2127=0x64 & op0513=0 & Rd5 & rs5 & $(END_PACKET) { +:tlbp Rd5,rs5 EndPacket is iclass=6 & op2127=0x64 & Rd5 & rs5 & $(END_PACKET) { Rd5 = tlbp(rs5); build EndPacket; } +# (v65,6) tlbp -- "Rd32 = tlbp ( Rss32 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 1 1 0 1 1 0 0 0 1 1 s s s s s P P 0 0 0 0 0 0 0 0 0 d d d d d + +:tlbp Rd5,rss5 EndPacket is iclass=6 & op2127=0x63 & op0513=0 & Rd5 & rss5 & $(END_PACKET) { + Rd5 = tlbp(rss5); + build EndPacket; +} + # (v2,6) tlbr -- "Rdd32 = tlbr ( Rs32 )" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 0 1 1 0 1 1 0 0 0 1 0 s s s s s P P + + + + + + + + + d d d d d +# 0 1 1 0 1 1 0 0 0 1 0 s s s s s P P - - - - - - - - - d d d d d define pcodeop tlbr; -:tlbr Rdd5,rs5 EndPacket is iclass=6 & op2127=0x62 & op0513=0 & Rdd5 & rs5 & $(END_PACKET) { +:tlbr Rdd5,rs5 EndPacket is iclass=6 & op2127=0x62 & Rdd5 & rs5 & $(END_PACKET) { Rdd5 = tlbr(rs5); build EndPacket; } @@ -13915,11 +14408,11 @@ define pcodeop tlbr; # (v4,6) tlbunlock -- "tlbunlock" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 0 1 1 0 1 1 0 0 0 0 1 + + + + + P P + + + + + + 0 1 0 + + + + + +# 0 1 1 0 1 1 0 0 0 0 1 - - - - - P P - - - - - - 0 1 0 - - - - - define pcodeop tlbunlock; -:tlbunlock EndPacket is iclass=6 & op2127=0x61 & op1620=0 & op0013=0x40 & $(END_PACKET) { +:tlbunlock EndPacket is iclass=6 & op2127=0x61 & op0507=0x2 & $(END_PACKET) { tlbunlock(); build EndPacket; } @@ -13927,11 +14420,11 @@ define pcodeop tlbunlock; # (v2,6) tlbw -- "tlbw ( Rss32 , Rt32 )" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 0 1 1 0 1 1 0 0 0 0 0 s s s s s P P 0 t t t t t + + + + + + + + +# 0 1 1 0 1 1 0 0 0 0 0 s s s s s P P 0 t t t t t - - - - - - - - define pcodeop tlbw; -:tlbw rss5,rt5 EndPacket is iclass=6 & op2127=0x60 & op13=0 & op0007=0 & rss5 & rt5 & $(END_PACKET) { +:tlbw rss5,rt5 EndPacket is iclass=6 & op2127=0x60 & op13=0 & rss5 & rt5 & $(END_PACKET) { tlbw(rss5, rt5); build EndPacket; } @@ -13950,24 +14443,23 @@ define pcodeop tlbw; # (v2,12) togglebit -- "Rd32 = togglebit ( Rs32 , Rt32 )" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 1 1 0 0 0 1 1 0 1 0 + s s s s s P P + t t t t t 1 0 + d d d d d +# 1 1 0 0 0 1 1 0 1 0 - s s s s s P P - t t t t t 1 0 - d d d d d -:togglebit Rd5,rs5,rt5 EndPacket is iclass=12 & op2127=0x34 & op13=0 & op0507=4 & Rd5 & rs5 & rt5 & $(END_PACKET) { - if (rt5 > 31) goto ; - mask:4 = 1 << rt5; +:togglebit Rd5,rs5,rt5 EndPacket is iclass=12 & op2227=0x1a & op0607=2 & Rd5 & rs5 & rt5 & $(END_PACKET) { + shamt:4 = (rt5 << 25) s>> 25; + mask:4 = zext(shamt s>= 0) * (1 << shamt); Rd5 = rs5 ^ mask; - build EndPacket; } # (v4,6) trace -- "trace ( Rs32 )" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 0 1 1 0 0 0 1 0 0 1 0 s s s s s P P + + + + + + + + + + + + + + +# 0 1 1 0 0 0 1 0 0 1 0 s s s s s P P - - - - - - - - - - - - - - define pcodeop trace; -:trace rs5 EndPacket is iclass=6 & op2127=0x12 & op0013=0 & rs5 & $(END_PACKET) { +:trace rs5 EndPacket is iclass=6 & op2127=0x12 & rs5 & $(END_PACKET) { trace(rs5); build EndPacket; } @@ -13975,11 +14467,11 @@ define pcodeop trace; # (v2,5) trap0 -- "trap0 ( #u8 )" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 0 1 0 1 0 1 0 0 0 0 + + + + + + P P - i i i i i - - - i i i - - +# 0 1 0 1 0 1 0 0 0 0 - - - - - - P P - i i i i i - - - i i i - - define pcodeop getTrap0Vector; -:trap0 Uimm8_0812_0204 EndPacket is iclass=5 & op2127=0x20 & op1620=0 & op13=0 & op0507=0 & op0001=0 & Uimm8_0812_0204 & $(END_PACKET) { +:trap0 Uimm8_0812_0204 EndPacket is iclass=5 & op2227=0x10 & Uimm8_0812_0204 & $(END_PACKET) { dest:4 = getTrap0Vector(); build EndPacket; <> @@ -13996,8 +14488,11 @@ define pcodeop getTrap0Vector; define pcodeop getTrap1Vector; -:trap1 rx5, Uimm8_0812_0204 EndPacket is iclass=5 & op2127=0x24 & rx5 & op13=0 & op0507=0 & op0001=0 & Uimm8_0812_0204 & $(END_PACKET) { - # TODO: Instruction manual does not specify the behavior of the Rx register in this instruction +:trap1 rx5, Uimm8_0812_0204 EndPacket is iclass=5 & op2227=0x12 & rx5 & Uimm8_0812_0204 & $(END_PACKET) { + # Per PRM 80-N2040-60 sec.12.9 SYSTEM, trap1(Rx32,#u8): Rx is used as an input/output + # parameter for guest-mode operations when #u8 == 1, 3, 4, or 6 (CCR.GRE set). + # In the general case (not in guest mode) Rx is passed to the OS and may be modified. + # The OS-specific side-effect on Rx cannot be modelled; only the trap vector call is emitted. dest:4 = getTrap1Vector(); build EndPacket; <> @@ -14006,6 +14501,11 @@ define pcodeop getTrap1Vector; call [dest]; } +# (v4,5) trap1 -- "trap1 ( #u8 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 1 0 1 0 0 1 0 0 1 0 0 0 0 0 0 P P - i i i i i - - - i i - - - + :trap1 Uimm8_0812_0204 EndPacket is iclass=5 & op2127=0x24 & op1620=0 & op13=0 & op0507=0 & op0001=0 & Uimm8_0812_0204 & $(END_PACKET) { dest:4 = getTrap1Vector(); build EndPacket; @@ -14042,10 +14542,11 @@ define pcodeop getTrap1Vector; # (v2,12) tstbit -- "Pd4 = tstbit ( Rs32 , Rt32 )" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 1 1 0 0 0 1 1 1 0 0 0 s s s s s P P + t t t t t + + + + + + d d +# 1 1 0 0 0 1 1 1 0 0 0 s s s s s P P - t t t t t - - - - - - d d -:tstbit Pd2,rs5,rt5 EndPacket is iclass=12 & op2127=0x38 & op13=0 & op0207=0 & rs5 & rt5 & Pd2 & $(END_PACKET) { - mask:4 = 1 << rt5; +:tstbit Pd2,rs5,rt5 EndPacket is iclass=12 & op2127=0x38 & rs5 & rt5 & Pd2 & $(END_PACKET) { + shamt:4 = (rt5 << 25) s>> 25; + mask:4 = zext(shamt s>= 0) * (1 << shamt); bool:1 = (rs5 & mask) != 0; Pd2 = Pd2 & (bool * 0xff); build EndPacket; @@ -14054,10 +14555,11 @@ define pcodeop getTrap1Vector; # (v4,12) tstbit -- "Pd4 = ! tstbit ( Rs32 , Rt32 )" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 1 1 0 0 0 1 1 1 0 0 1 s s s s s P P + t t t t t + + + + + + d d +# 1 1 0 0 0 1 1 1 0 0 1 s s s s s P P - t t t t t - - - - - - d d -:"!tstbit" Pd2,rs5,rt5 EndPacket is iclass=12 & op2127=0x39 & op13=0 & op0207=0 & rs5 & rt5 & Pd2 & $(END_PACKET) { - mask:4 = 1 << rt5; +:"!tstbit" Pd2,rs5,rt5 EndPacket is iclass=12 & op2127=0x39 & rs5 & rt5 & Pd2 & $(END_PACKET) { + shamt:4 = (rt5 << 25) s>> 25; + mask:4 = zext(shamt s>= 0) * (1 << shamt); bool:1 = (rs5 & mask) == 0; Pd2 = Pd2 & (bool * 0xff); build EndPacket; @@ -14090,7 +14592,7 @@ define pcodeop vabsdiffub; # (v2,14) vabsdiffh -- "Rdd32 = vabsdiffh ( Rtt32 , Rss32 )" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 1 1 1 0 1 0 0 0 0 1 1 s s s s s P P + t t t t t 0 0 0 d d d d d +# 1 1 1 0 1 0 0 0 0 1 1 s s s s s P P 0 t t t t t 0 0 0 d d d d d define pcodeop vabsdiffh; @@ -14102,7 +14604,7 @@ define pcodeop vabsdiffh; # (v2,14) vabsdiffw -- "Rdd32 = vabsdiffw ( Rtt32 , Rss32 )" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 1 1 1 0 1 0 0 0 0 0 1 s s s s s P P + t t t t t 0 0 0 d d d d d +# 1 1 1 0 1 0 0 0 0 0 1 s s s s s P P 0 t t t t t 0 0 0 d d d d d define pcodeop vabsdiffw; @@ -14114,11 +14616,11 @@ define pcodeop vabsdiffw; # (v2,8) vabsh -- "Rdd32 = vabsh ( Rss32 )" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 1 0 0 0 0 0 0 0 0 1 + s s s s s P P + + + + + + 1 0 0 d d d d d +# 1 0 0 0 0 0 0 0 0 1 0 s s s s s P P - - - - - - 1 0 0 d d d d d define pcodeop vabsh; -:vabsh Rdd5,rss5 EndPacket is iclass=8 & op2127=0x02 & op0513=4 & rss5 & Rdd5 & $(END_PACKET) { +:vabsh Rdd5,rss5 EndPacket is iclass=8 & op2227=0x1 & op21=0 & op0507=4 & rss5 & Rdd5 & $(END_PACKET) { Rdd5 = vabsh(rss5); build EndPacket; } @@ -14126,11 +14628,11 @@ define pcodeop vabsh; # (v2,8) vabsh -- "Rdd32 = vabsh ( Rss32 ) :sat" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 1 0 0 0 0 0 0 0 0 1 + s s s s s P P + + + + + + 1 0 1 d d d d d +# 1 0 0 0 0 0 0 0 0 1 0 s s s s s P P - - - - - - 1 0 1 d d d d d define pcodeop vabshSat; -:vabsh":sat" Rdd5,rss5 EndPacket is iclass=8 & op2127=0x02 & op0513=5 & rss5 & Rdd5 & $(END_PACKET) { +:vabsh":sat" Rdd5,rss5 EndPacket is iclass=8 & op2227=0x1 & op21=0 & op0507=5 & rss5 & Rdd5 & $(END_PACKET) { Rdd5 = vabshSat(rss5); build EndPacket; } @@ -14138,11 +14640,11 @@ define pcodeop vabshSat; # (v2,8) vabsw -- "Rdd32 = vabsw ( Rss32 )" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 1 0 0 0 0 0 0 0 0 1 + s s s s s P P + + + + + + 1 1 0 d d d d d +# 1 0 0 0 0 0 0 0 0 1 0 s s s s s P P - - - - - - 1 1 0 d d d d d define pcodeop vabsw; -:vabsw Rdd5,rss5 EndPacket is iclass=8 & op2127=0x02 & op0513=6 & rss5 & Rdd5 & $(END_PACKET) { +:vabsw Rdd5,rss5 EndPacket is iclass=8 & op2227=0x1 & op21=0 & op0507=6 & rss5 & Rdd5 & $(END_PACKET) { Rdd5 = vabsw(rss5); build EndPacket; } @@ -14150,11 +14652,11 @@ define pcodeop vabsw; # (v2,8) vabsw -- "Rdd32 = vabsw ( Rss32 ) :sat" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 1 0 0 0 0 0 0 0 0 1 + s s s s s P P + + + + + + 1 1 1 d d d d d +# 1 0 0 0 0 0 0 0 0 1 0 s s s s s P P - - - - - - 1 1 1 d d d d d define pcodeop vabswSat; -:vabsw":sat" Rdd5,rss5 EndPacket is iclass=8 & op2127=0x02 & op0513=7 & rss5 & Rdd5 & $(END_PACKET) { +:vabsw":sat" Rdd5,rss5 EndPacket is iclass=8 & op2227=0x1 & op21=0 & op0507=7 & rss5 & Rdd5 & $(END_PACKET) { Rdd5 = vabswSat(rss5); build EndPacket; } @@ -14164,15 +14666,23 @@ define pcodeop vabswSat; # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| # 1 1 1 0 1 0 1 0 1 0 1 s s s s s P P 0 t t t t t 0 e e x x x x x -:vacsh Rdd5,pu0506,rss5,rtt5 EndPacket is iclass=14 & op2127=0x55 & op13=0 & op7=0 & rss5 & rtt5 & pu0506 & Rdd5 & $(END_PACKET) -unimpl +define pcodeop vacshSum; # Rxx = vector add/select max halfwords result +define pcodeop vacshPred; # Pe = per-halfword compare bits (2 bits per lane) + +:vacsh Rdd5,pu0506,rss5,rtt5 EndPacket is iclass=14 & op2127=0x55 & op13=0 & op7=0 & rss5 & rtt5 & pu0506 & pu0506_ & Rdd5 & $(END_PACKET) { + Rdd5 = vacshSum(rss5, rtt5, Rdd5); + pu0506_ = vacshPred(rss5, rtt5); + build EndPacket; + <> + pu0506 = pu0506_; +} # (v2,15) vaddh -- "Rd32 = vaddh ( Rs32 , Rt32 )" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 1 1 1 1 0 1 1 0 0 0 0 s s s s s P P + t t t t t + + + d d d d d +# 1 1 1 1 0 1 1 0 0 0 0 s s s s s P P - t t t t t - - - d d d d d -:vaddh Rd5,rs5,rt5 EndPacket is iclass=15 & op2127=0x30 & op13=0 & op0507=0 & rs5 & rt5 & Rd5 & $(END_PACKET) { +:vaddh Rd5,rs5,rt5 EndPacket is iclass=15 & op2127=0x30 & rs5 & rt5 & Rd5 & $(END_PACKET) { Rd5[0,16] = rs5[0,16] + rt5[0,16]; Rd5[16,16] = rs5[16,16] + rt5[16,16]; build EndPacket; @@ -14181,9 +14691,9 @@ unimpl # (v2,15) vaddh -- "Rd32 = vaddh ( Rs32 , Rt32 ) :sat" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 1 1 1 1 0 1 1 0 0 0 1 s s s s s P P + t t t t t + + + d d d d d +# 1 1 1 1 0 1 1 0 0 0 1 s s s s s P P - t t t t t - - - d d d d d -:vaddh":sat" Rd5,rs5,rt5 EndPacket is iclass=15 & op2127=0x31 & op13=0 & op0507=0 & rs5 & rt5 & Rd5 & $(END_PACKET) { +:vaddh":sat" Rd5,rs5,rt5 EndPacket is iclass=15 & op2127=0x31 & rs5 & rt5 & Rd5 & $(END_PACKET) { h:2 = 0; addSat16(h, rt5[0,16], rs5[0,16]); Rd5[0,16] = h; @@ -14195,9 +14705,9 @@ unimpl # (v2,13) vaddh -- "Rdd32 = vaddh ( Rss32 , Rtt32 )" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 1 1 0 1 0 0 1 1 0 0 0 s s s s s P P + t t t t t 0 1 0 d d d d d +# 1 1 0 1 0 0 1 1 0 0 0 s s s s s P P - t t t t t 0 1 0 d d d d d -:vaddh Rdd5,rss5,rtt5 EndPacket is iclass=13 & op2127=0x18 & op13=0 & op0507=2 & rss5 & rtt5 & Rdd5 & $(END_PACKET) { +:vaddh Rdd5,rss5,rtt5 EndPacket is iclass=13 & op2127=0x18 & op0507=2 & rss5 & rtt5 & Rdd5 & $(END_PACKET) { Rdd5[0,16] = rss5[0,16] + rtt5[0,16]; Rdd5[16,16] = rss5[16,16] + rtt5[16,16]; Rdd5[32,16] = rss5[32,16] + rtt5[32,16]; @@ -14208,9 +14718,9 @@ unimpl # (v2,13) vaddh -- "Rdd32 = vaddh ( Rss32 , Rtt32 ) :sat" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 1 1 0 1 0 0 1 1 0 0 0 s s s s s P P + t t t t t 0 1 1 d d d d d +# 1 1 0 1 0 0 1 1 0 0 0 s s s s s P P - t t t t t 0 1 1 d d d d d -:vaddh":sat" Rdd5,rss5,rtt5 EndPacket is iclass=13 & op2127=0x18 & op13=0 & op0507=3 & rss5 & rtt5 & Rdd5 & $(END_PACKET) { +:vaddh":sat" Rdd5,rss5,rtt5 EndPacket is iclass=13 & op2127=0x18 & op0507=3 & rss5 & rtt5 & Rdd5 & $(END_PACKET) { h:2 = 0; addSat16(h, rtt5[0,16], rss5[0,16]); Rdd5[0,16] = h; @@ -14223,14 +14733,14 @@ unimpl build EndPacket; } -# (v?,12) vaddhub -- "Rd32 = vaddhub ( Rss32 , Rtt32 ) :sat" +# (v5,12) vaddhub -- "Rd32 = vaddhub ( Rss32 , Rtt32 ) :sat" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 1 1 0 0 0 0 0 1 0 1 0 s s s s s P P + t t t t t 0 0 1 d d d d d +# 1 1 0 0 0 0 0 1 0 1 - s s s s s P P - t t t t t 0 0 1 d d d d d define pcodeop vaddhub_sat; -:vaddhub":sat" Rd5,rss5,rtt5 EndPacket is iclass=12 & op2127=0x0a & op13=0 & op0507=1 & rss5 & rtt5 & Rd5 & $(END_PACKET) { +:vaddhub":sat" Rd5,rss5,rtt5 EndPacket is iclass=12 & op2227=0x05 & op0507=1 & rss5 & rtt5 & Rd5 & $(END_PACKET) { Rd5 = vaddhub_sat(rss5, rtt5); build EndPacket; } @@ -14238,11 +14748,11 @@ define pcodeop vaddhub_sat; # (v2,13) vaddub -- "Rdd32 = vaddub ( Rss32 , Rtt32 )" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 1 1 0 1 0 0 1 1 0 0 0 s s s s s P P + t t t t t 0 0 0 d d d d d +# 1 1 0 1 0 0 1 1 0 0 0 s s s s s P P - t t t t t 0 0 0 d d d d d define pcodeop vaddub; -:vaddub Rdd5,rss5,rtt5 EndPacket is iclass=13 & op2127=0x18 & op13=0 & op0507=0 & rss5 & rtt5 & Rdd5 & $(END_PACKET) { +:vaddub Rdd5,rss5,rtt5 EndPacket is iclass=13 & op2127=0x18 & op0507=0 & rss5 & rtt5 & Rdd5 & $(END_PACKET) { Rdd5 = vaddub(rss5,rtt5); build EndPacket; } @@ -14250,11 +14760,11 @@ define pcodeop vaddub; # (v2,13) vaddub -- "Rdd32 = vaddub ( Rss32 , Rtt32 ) :sat" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 1 1 0 1 0 0 1 1 0 0 0 s s s s s P P + t t t t t 0 0 1 d d d d d +# 1 1 0 1 0 0 1 1 0 0 0 s s s s s P P - t t t t t 0 0 1 d d d d d define pcodeop vaddubSat; -:vaddub":sat" Rdd5,rss5,rtt5 EndPacket is iclass=13 & op2127=0x18 & op13=0 & op0507=1 & rss5 & rtt5 & Rdd5 & $(END_PACKET) +:vaddub":sat" Rdd5,rss5,rtt5 EndPacket is iclass=13 & op2127=0x18 & op0507=1 & rss5 & rtt5 & Rdd5 & $(END_PACKET) { Rdd5 = vaddubSat(rss5,rtt5); build EndPacket; @@ -14263,9 +14773,9 @@ define pcodeop vaddubSat; # (v2,15) vadduh -- "Rd32 = vadduh ( Rs32 , Rt32 ) :sat" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 1 1 1 1 0 1 1 0 0 1 1 s s s s s P P + t t t t t + + + d d d d d +# 1 1 1 1 0 1 1 0 0 1 1 s s s s s P P - t t t t t - - - d d d d d -:vadduh":sat" Rd5,rs5,rt5 EndPacket is iclass=15 & op2127=0x33 & op13=0 & op0507=0 & rs5 & rt5 & Rd5 & $(END_PACKET) +:vadduh":sat" Rd5,rs5,rt5 EndPacket is iclass=15 & op2127=0x33 & rs5 & rt5 & Rd5 & $(END_PACKET) { h:2 = 0; adduSat16(h, rt5[0,16], rs5[0,16]); @@ -14278,9 +14788,9 @@ define pcodeop vaddubSat; # (v2,13) vadduh -- "Rdd32 = vadduh ( Rss32 , Rtt32 ) :sat" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 1 1 0 1 0 0 1 1 0 0 0 s s s s s P P + t t t t t 1 0 0 d d d d d +# 1 1 0 1 0 0 1 1 0 0 0 s s s s s P P - t t t t t 1 0 0 d d d d d -:vadduh":sat" Rdd5,rss5,rtt5 EndPacket is iclass=0xd & op2127=0x18 & op13=0 & op0507=4 & rss5 & rtt5 & Rdd5 & $(END_PACKET) +:vadduh":sat" Rdd5,rss5,rtt5 EndPacket is iclass=0xd & op2127=0x18 & op0507=4 & rss5 & rtt5 & Rdd5 & $(END_PACKET) { h:2 = 0; adduSat16(h, rtt5[0,16], rss5[0,16]); @@ -14297,26 +14807,26 @@ define pcodeop vaddubSat; # (v2,13) vaddw -- "Rdd32 = vaddw ( Rss32 , Rtt32 )" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 1 1 0 1 0 0 1 1 0 0 0 s s s s s P P + t t t t t 1 0 1 d d d d d +# 1 1 0 1 0 0 1 1 0 0 0 s s s s s P P - t t t t t 1 0 1 d d d d d -:vaddw Rdd5,rtt5,rss5 EndPacket is iclass=0xd & op2127=0x18 & op13=0 & op0507=5 & rss5 & rtt5 & Rdd5 & $(END_PACKET) +:vaddw Rdd5,rss5,rtt5 EndPacket is iclass=0xd & op2127=0x18 & op0507=5 & rss5 & rtt5 & Rdd5 & $(END_PACKET) { - Rdd5[0,32] = rtt5[0,32] + rss5[0,32]; - Rdd5[32,32] = rtt5[32,32] + rss5[32,32]; + Rdd5[0,32] = rss5[0,32] + rtt5[0,32]; + Rdd5[32,32] = rss5[32,32] + rtt5[32,32]; build EndPacket; } # (v2,13) vaddw -- "Rdd32 = vaddw ( Rss32 , Rtt32 ) :sat" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 1 1 0 1 0 0 1 1 0 0 0 s s s s s P P + t t t t t 1 1 0 d d d d d +# 1 1 0 1 0 0 1 1 0 0 0 s s s s s P P - t t t t t 1 1 0 d d d d d -:vaddw":sat" Rdd5,rtt5,rss5 EndPacket is iclass=0xd & op2127=0x18 & op13=0 & op0507=6 & rss5 & rtt5 & Rdd5 & $(END_PACKET) +:vaddw":sat" Rdd5,rss5,rtt5 EndPacket is iclass=0xd & op2127=0x18 & op0507=6 & rss5 & rtt5 & Rdd5 & $(END_PACKET) { w:4 = 0; - addSat32(w, rtt5[0,32], rss5[0,32]); + addSat32(w, rss5[0,32], rtt5[0,32]); Rdd5[0,32] = w; - addSat32(w, rtt5[32,32], rss5[32,32]); + addSat32(w, rss5[32,32], rtt5[32,32]); Rdd5[32,32] = w; build EndPacket; } @@ -14324,13 +14834,13 @@ define pcodeop vaddubSat; # (v2,12) valignb -- "Rdd32 = valignb ( Rtt32 , Rss32 , #u3 )" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 1 1 0 0 0 0 0 0 0 + + s s s s s P P + t t t t t i i i d d d d d +# 1 1 0 0 0 0 0 0 0 - - s s s s s P P - t t t t t i i i d d d d d macro valignb(d, s, t, align) { d = (s >> (align * 8)) | (t << ((8-align)*8)); } -:valignb Rdd5,rtt5,rss5,Uimm8_0507 EndPacket is iclass=0xc & op2127=0 & rss5 & op13=0 & rtt5 & Rdd5 & Uimm8_0507 & $(END_PACKET) +:valignb Rdd5,rtt5,rss5,Uimm8_0507 EndPacket is iclass=0xc & op2327=0 & rss5 & rtt5 & Rdd5 & Uimm8_0507 & $(END_PACKET) { valignb(Rdd5, rss5, rtt5, Uimm8_0507); build EndPacket; @@ -14339,9 +14849,9 @@ macro valignb(d, s, t, align) { # (v2,12) valignb -- "Rdd32 = valignb ( Rtt32 , Rss32 , Pu4 )" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 1 1 0 0 0 0 1 0 0 + + s s s s s P P + t t t t t + u u d d d d d +# 1 1 0 0 0 0 1 0 0 - - s s s s s P P - t t t t t - u u d d d d d -:valignb Rdd5,rtt5,rss5,pu0506 EndPacket is iclass=0xc & op2127=0x10 & rss5 & op13=0 & op7=0 & rtt5 & Rdd5 & pu0506 & $(END_PACKET) +:valignb Rdd5,rtt5,rss5,pu0506 EndPacket is iclass=0xc & op2327=0x4 & rss5 & rtt5 & Rdd5 & pu0506 & $(END_PACKET) { valignb(Rdd5, rss5, rtt5, pu0506 & 0x7); build EndPacket; @@ -14350,9 +14860,9 @@ macro valignb(d, s, t, align) { # (v2,8) vaslh -- "Rdd32 = vaslh ( Rss32 , #u4 )" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 1 0 0 0 0 0 0 0 1 0 + s s s s s P P 0 0 i i i i 0 1 0 d d d d d +# 1 0 0 0 0 0 0 0 1 0 0 s s s s s P P 0 0 i i i i 0 1 0 d d d d d -:vaslh Rdd5,rss5,Uimm8_0811 EndPacket is iclass=8 & op2127=0x04 & op1213=0 & op0507=2 & rss5 & Uimm8_0811 & Rdd5 & $(END_PACKET) +:vaslh Rdd5,rss5,Uimm8_0811 EndPacket is iclass=8 & op2227=0x2 & op21=0 & op1213=0 & op0507=2 & rss5 & Uimm8_0811 & Rdd5 & $(END_PACKET) { Rdd5[0,16] = rss5[0,16] << Uimm8_0811; Rdd5[16,16] = rss5[16,16] << Uimm8_0811; @@ -14364,11 +14874,11 @@ macro valignb(d, s, t, align) { # (v2,12) vaslh -- "Rdd32 = vaslh ( Rss32 , Rt32 )" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 1 1 0 0 0 0 1 1 0 1 + s s s s s P P + t t t t t 1 0 + d d d d d +# 1 1 0 0 0 0 1 1 0 1 - s s s s s P P - t t t t t 1 0 - d d d d d -:vaslh Rdd5,rss5,rt5 EndPacket is iclass=12 & op2127=0x1a & op13=0 & op0507=4 & rss5 & rt5 & Rdd5 & $(END_PACKET) +:vaslh Rdd5,rss5,rt5 EndPacket is iclass=12 & op2227=0xd & op0607=2 & rss5 & rt5 & Rdd5 & $(END_PACKET) { - # TODO: should we assume positive shift amount to avoid conditional ? + # Rt32 is a signed shift amount: positive = shift left, negative = shift right by |Rt|. right:1 = rt5 s< 0; h:2 = rss5[0,16]; Rdd5[0,16] = (zext(right) * (h s>> -rt5)) + (zext(!right) * (h << rt5)); @@ -14384,9 +14894,9 @@ macro valignb(d, s, t, align) { # (v2,8) vaslw -- "Rdd32 = vaslw ( Rss32 , #u5 )" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 1 0 0 0 0 0 0 0 0 1 + s s s s s P P 0 i i i i i 0 1 0 d d d d d +# 1 0 0 0 0 0 0 0 0 1 0 s s s s s P P 0 i i i i i 0 1 0 d d d d d -:vaslw Rdd5,rss5,Uimm8_0812 EndPacket is iclass=8 & op2127=0x02 & op13=0 & op0507=2 & rss5 & Uimm8_0812 & Rdd5 & $(END_PACKET) +:vaslw Rdd5,rss5,Uimm8_0812 EndPacket is iclass=8 & op2227=0x1 & op21=0 & op13=0 & op0507=2 & rss5 & Uimm8_0812 & Rdd5 & $(END_PACKET) { Rdd5[0,32] = rss5[0,32] << Uimm8_0812; Rdd5[32,32] = rss5[32,32] << Uimm8_0812; @@ -14396,11 +14906,11 @@ macro valignb(d, s, t, align) { # (v2,12) vaslw -- "Rdd32 = vaslw ( Rss32 , Rt32 )" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 1 1 0 0 0 0 1 1 0 0 + s s s s s P P + t t t t t 1 0 + d d d d d +# 1 1 0 0 0 0 1 1 0 0 - s s s s s P P - t t t t t 1 0 - d d d d d -:vaslw Rdd5,rss5,rt5 EndPacket is iclass=12 & op2127=0x18 & op13=0 & op0507=4 & rss5 & rt5 & Rdd5 & $(END_PACKET) +:vaslw Rdd5,rss5,rt5 EndPacket is iclass=12 & op2227=0xc & op0607=2 & rss5 & rt5 & Rdd5 & $(END_PACKET) { - # TODO: should we assume positive shift amount to avoid conditional ? + # Rt32 is a signed shift amount: positive = shift left, negative = shift right by |Rt|. right:1 = rt5 s< 0; w:4 = rss5[0,32]; Rdd5[0,32] = (zext(right) * (w s>> -rt5)) + (zext(!right) * (w << rt5)); @@ -14412,9 +14922,9 @@ macro valignb(d, s, t, align) { # (v2,8) vasrh -- "Rdd32 = vasrh ( Rss32 , #u4 )" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 1 0 0 0 0 0 0 0 1 0 + s s s s s P P 0 0 i i i i 0 0 0 d d d d d +# 1 0 0 0 0 0 0 0 1 0 0 s s s s s P P 0 0 i i i i 0 0 0 d d d d d -:vasrh Rdd5,rss5,Uimm8_0811 EndPacket is iclass=8 & op2127=0x04 & op1213=0 & op0507=0 & rss5 & Uimm8_0811 & Rdd5 & $(END_PACKET) +:vasrh Rdd5,rss5,Uimm8_0811 EndPacket is iclass=8 & op2227=0x2 & op21=0 & op1213=0 & op0507=0 & rss5 & Uimm8_0811 & Rdd5 & $(END_PACKET) { Rdd5[0,16] = rss5[0,16] s>> Uimm8_0811; Rdd5[16,16] = rss5[16,16] s>> Uimm8_0811; @@ -14423,7 +14933,7 @@ macro valignb(d, s, t, align) { build EndPacket; } -# (v?,8) vasrh -- "Rdd32 = vasrh ( Rss32 , #u4 ):raw" +# (v5,8) vasrh -- "Rdd32 = vasrh ( Rss32 , #u4 ):raw" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| # 1 0 0 0 0 0 0 0 0 0 1 s s s s s P P 0 0 i i i i 0 0 0 d d d d d @@ -14440,45 +14950,45 @@ macro valignb(d, s, t, align) { # (v2,12) vasrh -- "Rdd32 = vasrh ( Rss32 , Rt32 )" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 1 1 0 0 0 0 1 1 0 1 + s s s s s P P + t t t t t 0 0 + d d d d d +# 1 1 0 0 0 0 1 1 0 1 - s s s s s P P - t t t t t 0 0 - d d d d d -:vasrh Rdd5,rss5,rt5 EndPacket is iclass=12 & op2127=0x1a & op13=0 & op0507=0 & rss5 & rt5 & Rdd5 & $(END_PACKET) +:vasrh Rdd5,rss5,rt5 EndPacket is iclass=12 & op2227=0xd & op0607=0 & rss5 & rt5 & Rdd5 & $(END_PACKET) { - # TODO: should we assume positive shift amount to avoid conditional ? + # Rt32 is a signed shift amount: positive = shift right, negative = shift left by |Rt|. right:1 = rt5 s>= 0; h:2 = rss5[0,16]; - Rdd5[0,16] = (zext(right) * (h s>> -rt5)) + (zext(!right) * (h << rt5)); + Rdd5[0,16] = (zext(right) * (h s>> rt5)) + (zext(!right) * (h << -rt5)); h = rss5[16,16]; - Rdd5[16,16] = (zext(right) * (h s>> -rt5)) + (zext(!right) * (h << rt5)); + Rdd5[16,16] = (zext(right) * (h s>> rt5)) + (zext(!right) * (h << -rt5)); h = rss5[32,16]; - Rdd5[32,16] = (zext(right) * (h s>> -rt5)) + (zext(!right) * (h << rt5)); + Rdd5[32,16] = (zext(right) * (h s>> rt5)) + (zext(!right) * (h << -rt5)); h = rss5[48,16]; - Rdd5[48,16] = (zext(right) * (h s>> -rt5)) + (zext(!right) * (h << rt5)); + Rdd5[48,16] = (zext(right) * (h s>> rt5)) + (zext(!right) * (h << -rt5)); build EndPacket; } -# (v?,8) vasrhub -- "Rd32 = vasrhub ( Rss32 , #u4 ):raw" +# (v5,8) vasrhub -- "Rd32 = vasrhub ( Rss32 , #u4 ):raw" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 1 0 0 0 1 0 0 0 0 1 1 s s s s s P P 0 0 i i i i 0 0 0 d d d d d +# 1 0 0 0 1 0 0 0 0 1 1 s s s s s P P 0 0 i i i i 1 0 0 d d d d d define pcodeop vasrhub_raw; -:vasrhub":raw" Rd5,rss5,Uimm8_0811 EndPacket is iclass=8 & op2127=0x43 & op1213=0 & op0507=4 & rss5 & rt5 & Rd5 & Uimm8_0811 & $(END_PACKET) +:vasrhub":raw" Rd5,rss5,Uimm8_0811 EndPacket is iclass=8 & op2127=0x43 & op1213=0 & op0507=4 & rss5 & Rd5 & Uimm8_0811 & $(END_PACKET) { Rd5 = vasrhub_raw(rss5, Uimm8_0811); build EndPacket; } -# (v?,8) vasrhub -- "Rd32 = vasrhub ( Rss32 , #u4 ):sat" +# (v5,8) vasrhub -- "Rd32 = vasrhub ( Rss32 , #u4 ):sat" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 1 0 0 0 1 0 0 0 0 1 1 s s s s s P P 0 0 i i i i 0 0 0 d d d d d +# 1 0 0 0 1 0 0 0 0 1 1 s s s s s P P 0 0 i i i i 1 0 1 d d d d d define pcodeop vasrhub_sat; -:vasrhub":sat" Rd5,rss5,Uimm8_0811 EndPacket is iclass=8 & op2127=0x43 & op1213=0 & op0507=5 & rss5 & rt5 & Rd5 & Uimm8_0811 & $(END_PACKET) +:vasrhub":sat" Rd5,rss5,Uimm8_0811 EndPacket is iclass=8 & op2127=0x43 & op1213=0 & op0507=5 & rss5 & Rd5 & Uimm8_0811 & $(END_PACKET) { Rd5 = vasrhub_sat(rss5, Uimm8_0811); build EndPacket; @@ -14487,9 +14997,9 @@ define pcodeop vasrhub_sat; # (v2,8) vasrw -- "Rd32 = vasrw ( Rss32 , #u5 )" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 1 0 0 0 1 0 0 0 1 1 0 s s s s s P P 0 i i i i i 0 1 + d d d d d +# 1 0 0 0 1 0 0 0 1 1 0 s s s s s P P 0 i i i i i 0 1 0 d d d d d -:vasrw Rd5,rss5,Uimm8_0812 EndPacket is iclass=8 & op2127=0x46 & op13=0 & op0507=2 & rss5 & Uimm8_0812 & Rd5 & $(END_PACKET) +:vasrw Rd5,rss5,Uimm8_0812 EndPacket is iclass=8 & op2127=0x46 & op13=0 & op0607=1 & op5=0 & rss5 & Uimm8_0812 & Rd5 & $(END_PACKET) { res:4 = rss5[0,32] s>> Uimm8_0812; Rd5[0,16] = res:2; @@ -14503,15 +15013,15 @@ define pcodeop vasrhub_sat; # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| # 1 1 0 0 0 1 0 1 - - - s s s s s P P - t t t t t 0 1 0 d d d d d -:vasrw Rd5,rss5,rt5 EndPacket is iclass=12 & op2127=0x28 & op13=0 & op0507=2 & rss5 & rt5 & Rd5 & $(END_PACKET) +:vasrw Rd5,rss5,rt5 EndPacket is iclass=12 & op2427=0x5 & op0507=2 & rss5 & rt5 & Rd5 & $(END_PACKET) { - # TODO: should we assume positive shift amount to avoid conditional ? + # Rt32 is a signed shift amount: positive = shift right, negative = shift left by |Rt|. right:1 = rt5 s>= 0; w:4 = rss5[0,32]; - res:4 = (zext(right) * (w s>> -rt5)) + (zext(!right) * (w << rt5)); + res:4 = (zext(right) * (w s>> rt5)) + (zext(!right) * (w << -rt5)); Rd5[0,16] = res:2; w = rss5[32,32]; - res = (zext(right) * (w s>> -rt5)) + (zext(!right) * (w << rt5)); + res = (zext(right) * (w s>> rt5)) + (zext(!right) * (w << -rt5)); Rd5[16,16] = res:2; build EndPacket; } @@ -14519,9 +15029,9 @@ define pcodeop vasrhub_sat; # (v2,8) vasrw -- "Rdd32 = vasrw ( Rss32 , #u5 )" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 1 0 0 0 0 0 0 0 0 1 + s s s s s P P 0 i i i i i 0 0 0 d d d d d +# 1 0 0 0 0 0 0 0 0 1 0 s s s s s P P 0 i i i i i 0 0 0 d d d d d -:vasrw Rdd5,rss5,Uimm8_0812 EndPacket is iclass=8 & op2127=0x02 & op13=0 & op0507=0 & rss5 & Uimm8_0812 & Rdd5 & $(END_PACKET) +:vasrw Rdd5,rss5,Uimm8_0812 EndPacket is iclass=8 & op2227=0x1 & op21=0 & op13=0 & op0507=0 & rss5 & Uimm8_0812 & Rdd5 & $(END_PACKET) { Rdd5[0,32] = rss5[0,32] s>> Uimm8_0812; Rdd5[32,32] = rss5[32,32] s>> Uimm8_0812; @@ -14531,156 +15041,281 @@ define pcodeop vasrhub_sat; # (v2,12) vasrw -- "Rdd32 = vasrw ( Rss32 , Rt32 )" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 1 1 0 0 0 0 1 1 0 0 + s s s s s P P + t t t t t 0 0 + d d d d d +# 1 1 0 0 0 0 1 1 0 0 - s s s s s P P - t t t t t 0 0 - d d d d d -:vasrw Rdd5,rss5,rt5 EndPacket is iclass=12 & op2127=0x18 & op13=0 & op0507=0 & rss5 & rt5 & Rdd5 & $(END_PACKET) +:vasrw Rdd5,rss5,rt5 EndPacket is iclass=12 & op2227=0xc & op0607=0 & rss5 & rt5 & Rdd5 & $(END_PACKET) { - # TODO: should we assume positive shift amount to avoid conditional ? + # Rt32 is a signed shift amount: positive = shift right, negative = shift left by |Rt|. right:1 = rt5 s>= 0; w:4 = rss5[0,32]; - Rdd5[0,32] = (zext(right) * (w s>> -rt5)) + (zext(!right) * (w << rt5)); + Rdd5[0,32] = (zext(right) * (w s>> rt5)) + (zext(!right) * (w << -rt5)); w = rss5[32,32]; - Rdd5[32,32] = (zext(right) * (w s>> -rt5)) + (zext(!right) * (w << rt5)); + Rdd5[32,32] = (zext(right) * (w s>> rt5)) + (zext(!right) * (w << -rt5)); build EndPacket; } # (v2,15) vavgh -- "Rd32 = vavgh ( Rs32 , Rt32 )" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 1 1 1 1 0 1 1 1 + 0 0 s s s s s P P + t t t t t + + + d d d d d +# 1 1 1 1 0 1 1 1 - 0 0 s s s s s P P - t t t t t - - - d d d d d -:vavgh Rd5,rs5,rt5 EndPacket is iclass=15 & op2127=0x38 & op13=0 & op0507=0 & rs5 & rt5 & Rd5 & $(END_PACKET) +:vavgh Rd5,rs5,rt5 EndPacket is iclass=15 & op2427=0x7 & op2122=0x0 & rs5 & rt5 & Rd5 & $(END_PACKET) { - Rd5[0,16] = (rs5[0,16] + rt5[0,16]) >> 1; - Rd5[16,16] = (rs5[16,16] + rt5[16,16]) >> 1; + local s:4; + s = (sext(rs5[0,16]) + sext(rt5[0,16])) >> 1; + Rd5[0,16] = s:2; + s = (sext(rs5[16,16]) + sext(rt5[16,16])) >> 1; + Rd5[16,16] = s:2; build EndPacket; } # (v2,15) vavgh -- "Rd32 = vavgh ( Rs32 , Rt32 ) :rnd" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 1 1 1 1 0 1 1 1 + 0 1 s s s s s P P + t t t t t + + + d d d d d +# 1 1 1 1 0 1 1 1 - 0 1 s s s s s P P - t t t t t - - - d d d d d -:vavgh":rnd" Rd5,rs5,rt5 EndPacket is iclass=15 & op2127=0x39 & op13=0 & op0507=0 & rs5 & rt5 & Rd5 & $(END_PACKET) +:vavgh":rnd" Rd5,rs5,rt5 EndPacket is iclass=15 & op2427=0x7 & op2122=0x1 & rs5 & rt5 & Rd5 & $(END_PACKET) { - Rd5[0,16] = (rs5[0,16] + rt5[0,16] + 1) >> 1; - Rd5[16,16] = (rs5[16,16] + rt5[16,16] + 1) >> 1; + local s:4; + s = (sext(rs5[0,16]) + sext(rt5[0,16]) + 1) >> 1; + Rd5[0,16] = s:2; + s = (sext(rs5[16,16]) + sext(rt5[16,16]) + 1) >> 1; + Rd5[16,16] = s:2; build EndPacket; } # (v2,13) vavgh -- "Rdd32 = vavgh ( Rss32 , Rtt32 )" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 1 1 0 1 0 0 1 1 0 1 0 s s s s s P P + t t t t t 0 1 0 d d d d d +# 1 1 0 1 0 0 1 1 0 1 0 s s s s s P P - t t t t t 0 1 0 d d d d d -:vavgh Rdd5,rss5,rtt5 EndPacket is iclass=13 & op2127=0x1a & op13=0 & op0507=2 & rss5 & rtt5 & Rdd5 & $(END_PACKET) +:vavgh Rdd5,rss5,rtt5 EndPacket is iclass=13 & op2127=0x1a & op0507=2 & rss5 & rtt5 & Rdd5 & $(END_PACKET) { - Rdd5[0,16] = (rss5[0,16] + rtt5[0,16]) >> 1; - Rdd5[16,16] = (rss5[16,16] + rtt5[16,16]) >> 1; - Rdd5[32,16] = (rss5[32,16] + rtt5[32,16]) >> 1; - Rdd5[48,16] = (rss5[48,16] + rtt5[48,16]) >> 1; + local s:4; + s = (sext(rss5[0,16]) + sext(rtt5[0,16])) >> 1; + Rdd5[0,16] = s:2; + s = (sext(rss5[16,16]) + sext(rtt5[16,16])) >> 1; + Rdd5[16,16] = s:2; + s = (sext(rss5[32,16]) + sext(rtt5[32,16])) >> 1; + Rdd5[32,16] = s:2; + s = (sext(rss5[48,16]) + sext(rtt5[48,16])) >> 1; + Rdd5[48,16] = s:2; build EndPacket; } # (v2,13) vavgh -- "Rdd32 = vavgh ( Rss32 , Rtt32 ) :crnd" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 1 1 0 1 0 0 1 1 0 1 0 s s s s s P P + t t t t t 1 0 0 d d d d d +# 1 1 0 1 0 0 1 1 0 1 0 s s s s s P P - t t t t t 1 0 0 d d d d d -:vavgh":crnd" Rdd5,rss5,rtt5 EndPacket is iclass=13 & op2127=0x1a & op13=0 & op0507=4 & rss5 & rtt5 & Rdd5 & $(END_PACKET) +:vavgh":crnd" Rdd5,rss5,rtt5 EndPacket is iclass=13 & op2127=0x1a & op0507=4 & rss5 & rtt5 & Rdd5 & $(END_PACKET) { - Rdd5[0,16] = roundConvergent(rss5[0,16] + rtt5[0,16] + 1, 1:1) >> 1; - Rdd5[16,16] = roundConvergent(rss5[16,16] + rtt5[16,16] + 1, 1:1) >> 1; - Rdd5[32,16] = roundConvergent(rss5[32,16] + rtt5[32,16] + 1, 1:1) >> 1; - Rdd5[48,16] = roundConvergent(rss5[48,16] + rtt5[48,16] + 1, 1:1) >> 1; + local s:4; + s = sext(rss5[0,16]) + sext(rtt5[0,16]); + Rdd5[0,16] = roundConvergent(s, 1:1); + s = sext(rss5[16,16]) + sext(rtt5[16,16]); + Rdd5[16,16] = roundConvergent(s, 1:1); + s = sext(rss5[32,16]) + sext(rtt5[32,16]); + Rdd5[32,16] = roundConvergent(s, 1:1); + s = sext(rss5[48,16]) + sext(rtt5[48,16]); + Rdd5[48,16] = roundConvergent(s, 1:1); build EndPacket; } # (v2,13) vavgh -- "Rdd32 = vavgh ( Rss32 , Rtt32 ) :rnd" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 1 1 0 1 0 0 1 1 0 1 0 s s s s s P P + t t t t t 0 1 1 d d d d d +# 1 1 0 1 0 0 1 1 0 1 0 s s s s s P P - t t t t t 0 1 1 d d d d d -:vavgh":rnd" Rdd5,rss5,rtt5 EndPacket is iclass=13 & op2127=0x1a & op13=0 & op0507=3 & rss5 & rtt5 & Rdd5 & $(END_PACKET) +:vavgh":rnd" Rdd5,rss5,rtt5 EndPacket is iclass=13 & op2127=0x1a & op0507=3 & rss5 & rtt5 & Rdd5 & $(END_PACKET) { - Rdd5[0,16] = (rss5[0,16] + rtt5[0,16] + 1) >> 1; - Rdd5[16,16] = (rss5[16,16] + rtt5[16,16] + 1) >> 1; - Rdd5[32,16] = (rss5[32,16] + rtt5[32,16] + 1) >> 1; - Rdd5[48,16] = (rss5[48,16] + rtt5[48,16] + 1) >> 1; + local s:4; + s = (sext(rss5[0,16]) + sext(rtt5[0,16]) + 1) >> 1; + Rdd5[0,16] = s:2; + s = (sext(rss5[16,16]) + sext(rtt5[16,16]) + 1) >> 1; + Rdd5[16,16] = s:2; + s = (sext(rss5[32,16]) + sext(rtt5[32,16]) + 1) >> 1; + Rdd5[32,16] = s:2; + s = (sext(rss5[48,16]) + sext(rtt5[48,16]) + 1) >> 1; + Rdd5[48,16] = s:2; build EndPacket; } # (v2,13) vavgub -- "Rdd32 = vavgub ( Rss32 , Rtt32 )" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 1 1 0 1 0 0 1 1 0 1 0 s s s s s P P + t t t t t 0 0 0 d d d d d +# 1 1 0 1 0 0 1 1 0 1 0 s s s s s P P - t t t t t 0 0 0 d d d d d -:vavgub Rdd5,rss5,rtt5 EndPacket is iclass=13 & op2127=0x1a & op13=0 & op0507=0 & rss5 & rtt5 & Rdd5 & $(END_PACKET) -unimpl +# Rdd.ub[i] = (Rss.ub[i] + Rtt.ub[i]) >> 1 (8 unsigned byte lanes; truncating) +# Per PRM 80-N2040-60 sec.12.10 XTYPE/ALU "Vector average unsigned bytes" +:vavgub Rdd5,rss5,rtt5 EndPacket is iclass=13 & op2127=0x1a & op0507=0 & rss5 & rtt5 & Rdd5 & $(END_PACKET) { + local s:2; + s = (zext(rss5[0,8]) + zext(rtt5[0,8])) >> 1; + Rdd5[0,8] = s:1; + s = (zext(rss5[8,8]) + zext(rtt5[8,8])) >> 1; + Rdd5[8,8] = s:1; + s = (zext(rss5[16,8]) + zext(rtt5[16,8])) >> 1; + Rdd5[16,8] = s:1; + s = (zext(rss5[24,8]) + zext(rtt5[24,8])) >> 1; + Rdd5[24,8] = s:1; + s = (zext(rss5[32,8]) + zext(rtt5[32,8])) >> 1; + Rdd5[32,8] = s:1; + s = (zext(rss5[40,8]) + zext(rtt5[40,8])) >> 1; + Rdd5[40,8] = s:1; + s = (zext(rss5[48,8]) + zext(rtt5[48,8])) >> 1; + Rdd5[48,8] = s:1; + s = (zext(rss5[56,8]) + zext(rtt5[56,8])) >> 1; + Rdd5[56,8] = s:1; + build EndPacket; +} # (v2,13) vavgub -- "Rdd32 = vavgub ( Rss32 , Rtt32 ) :rnd" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 1 1 0 1 0 0 1 1 0 1 0 s s s s s P P + t t t t t 0 0 1 d d d d d +# 1 1 0 1 0 0 1 1 0 1 0 s s s s s P P - t t t t t 0 0 1 d d d d d -:vavgub":rnd" Rdd5,rss5,rtt5 EndPacket is iclass=13 & op2127=0x1a & op13=0 & op0507=1 & rss5 & rtt5 & Rdd5 & $(END_PACKET) -unimpl +# Rdd.ub[i] = (Rss.ub[i] + Rtt.ub[i] + 1) >> 1 (rounding average) +# Per PRM 80-N2040-60 sec.12.10 XTYPE/ALU "Vector average unsigned bytes" +:vavgub":rnd" Rdd5,rss5,rtt5 EndPacket is iclass=13 & op2127=0x1a & op0507=1 & rss5 & rtt5 & Rdd5 & $(END_PACKET) { + local s:2; + s = (zext(rss5[0,8]) + zext(rtt5[0,8]) + 1) >> 1; + Rdd5[0,8] = s:1; + s = (zext(rss5[8,8]) + zext(rtt5[8,8]) + 1) >> 1; + Rdd5[8,8] = s:1; + s = (zext(rss5[16,8]) + zext(rtt5[16,8]) + 1) >> 1; + Rdd5[16,8] = s:1; + s = (zext(rss5[24,8]) + zext(rtt5[24,8]) + 1) >> 1; + Rdd5[24,8] = s:1; + s = (zext(rss5[32,8]) + zext(rtt5[32,8]) + 1) >> 1; + Rdd5[32,8] = s:1; + s = (zext(rss5[40,8]) + zext(rtt5[40,8]) + 1) >> 1; + Rdd5[40,8] = s:1; + s = (zext(rss5[48,8]) + zext(rtt5[48,8]) + 1) >> 1; + Rdd5[48,8] = s:1; + s = (zext(rss5[56,8]) + zext(rtt5[56,8]) + 1) >> 1; + Rdd5[56,8] = s:1; + build EndPacket; +} # (v2,13) vavguh -- "Rdd32 = vavguh ( Rss32 , Rtt32 )" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 1 1 0 1 0 0 1 1 0 1 0 s s s s s P P + t t t t t 1 0 1 d d d d d +# 1 1 0 1 0 0 1 1 0 1 0 s s s s s P P - t t t t t 1 0 1 d d d d d -:vavguh Rdd5,rss5,rtt5 EndPacket is iclass=13 & op2127=0x1a & op13=0 & op0507=5 & rss5 & rtt5 & Rdd5 & $(END_PACKET) -unimpl +# Rdd.uh[i] = (Rss.uh[i] + Rtt.uh[i]) >> 1 (4 unsigned halfword lanes; truncating) +# Per PRM 80-N2040-60 sec.12.10 XTYPE/ALU "Vector average halfwords" (vavguh variant) +:vavguh Rdd5,rss5,rtt5 EndPacket is iclass=13 & op2127=0x1a & op0507=5 & rss5 & rtt5 & Rdd5 & $(END_PACKET) { + local s:4; + s = (zext(rss5[0,16]) + zext(rtt5[0,16])) >> 1; + Rdd5[0,16] = s:2; + s = (zext(rss5[16,16]) + zext(rtt5[16,16])) >> 1; + Rdd5[16,16] = s:2; + s = (zext(rss5[32,16]) + zext(rtt5[32,16])) >> 1; + Rdd5[32,16] = s:2; + s = (zext(rss5[48,16]) + zext(rtt5[48,16])) >> 1; + Rdd5[48,16] = s:2; + build EndPacket; +} # (v2,13) vavguh -- "Rdd32 = vavguh ( Rss32 , Rtt32 ) :rnd" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 1 1 0 1 0 0 1 1 0 1 0 s s s s s P P + t t t t t 1 1 + d d d d d +# 1 1 0 1 0 0 1 1 0 1 0 s s s s s P P - t t t t t 1 1 - d d d d d -:vavguh":rnd" Rdd5,rss5,rtt5 EndPacket is iclass=13 & op2127=0x1a & op13=0 & op0507=6 & rss5 & rtt5 & Rdd5 & $(END_PACKET) -unimpl +# Rdd.uh[i] = (Rss.uh[i] + Rtt.uh[i] + 1) >> 1 (rounding) +# Per PRM 80-N2040-60 sec.12.10 XTYPE/ALU "Vector average halfwords" (vavguh:rnd variant) +:vavguh":rnd" Rdd5,rss5,rtt5 EndPacket is iclass=13 & op2127=0x1a & op0607=3 & rss5 & rtt5 & Rdd5 & $(END_PACKET) { + local s:4; + s = (zext(rss5[0,16]) + zext(rtt5[0,16]) + 1) >> 1; + Rdd5[0,16] = s:2; + s = (zext(rss5[16,16]) + zext(rtt5[16,16]) + 1) >> 1; + Rdd5[16,16] = s:2; + s = (zext(rss5[32,16]) + zext(rtt5[32,16]) + 1) >> 1; + Rdd5[32,16] = s:2; + s = (zext(rss5[48,16]) + zext(rtt5[48,16]) + 1) >> 1; + Rdd5[48,16] = s:2; + build EndPacket; +} # (v2,13) vavguw -- "Rdd32 = vavguw ( Rss32 , Rtt32 )" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 1 1 0 1 0 0 1 1 0 1 1 s s s s s P P + t t t t t 0 1 1 d d d d d +# 1 1 0 1 0 0 1 1 0 1 1 s s s s s P P - t t t t t 0 1 1 d d d d d -:vavguw Rdd5,rss5,rtt5 EndPacket is iclass=13 & op2127=0x1b & op13=0 & op0507=3 & rss5 & rtt5 & Rdd5 & $(END_PACKET) -unimpl +# Rdd.uw[i] = (Rss.uw[i] + Rtt.uw[i]) >> 1 (2 unsigned word lanes; truncating) +# Per PRM 80-N2040-60 sec.12.10 XTYPE/ALU "Vector average words" (vavguw variant) +:vavguw Rdd5,rss5,rtt5 EndPacket is iclass=13 & op2127=0x1b & op0507=3 & rss5 & rtt5 & Rdd5 & $(END_PACKET) { + local s:8; + s = (zext(rss5[0,32]) + zext(rtt5[0,32])) >> 1; + Rdd5[0,32] = s:4; + s = (zext(rss5[32,32]) + zext(rtt5[32,32])) >> 1; + Rdd5[32,32] = s:4; + build EndPacket; +} # (v2,13) vavguw -- "Rdd32 = vavguw ( Rss32 , Rtt32 ) :rnd" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 1 1 0 1 0 0 1 1 0 1 1 s s s s s P P + t t t t t 1 0 0 d d d d d +# 1 1 0 1 0 0 1 1 0 1 1 s s s s s P P - t t t t t 1 0 0 d d d d d -:vavguw":rnd" Rdd5,rss5,rtt5 EndPacket is iclass=13 & op2127=0x1b & op13=0 & op0507=4 & rss5 & rtt5 & Rdd5 & $(END_PACKET) -unimpl +# Rdd.uw[i] = (Rss.uw[i] + Rtt.uw[i] + 1) >> 1 (rounding) +# Per PRM 80-N2040-60 sec.12.10 XTYPE/ALU "Vector average words" (vavguw:rnd variant) +:vavguw":rnd" Rdd5,rss5,rtt5 EndPacket is iclass=13 & op2127=0x1b & op0507=4 & rss5 & rtt5 & Rdd5 & $(END_PACKET) { + local s:8; + s = (zext(rss5[0,32]) + zext(rtt5[0,32]) + 1) >> 1; + Rdd5[0,32] = s:4; + s = (zext(rss5[32,32]) + zext(rtt5[32,32]) + 1) >> 1; + Rdd5[32,32] = s:4; + build EndPacket; +} # (v2,13) vavgw -- "Rdd32 = vavgw ( Rss32 , Rtt32 )" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 1 1 0 1 0 0 1 1 0 1 1 s s s s s P P + t t t t t 0 0 0 d d d d d +# 1 1 0 1 0 0 1 1 0 1 1 s s s s s P P - t t t t t 0 0 0 d d d d d -:vavgw Rdd5,rss5,rtt5 EndPacket is iclass=13 & op2127=0x1b & op13=0 & op0507=0 & rss5 & rtt5 & Rdd5 & $(END_PACKET) -unimpl +# Rdd.w[i] = (sxt32(Rss.w[i]) + sxt32(Rtt.w[i])) >> 1 (2 signed word lanes; arithmetic shift) +# Per PRM 80-N2040-60 sec.12.10 XTYPE/ALU "Vector average words" +:vavgw Rdd5,rss5,rtt5 EndPacket is iclass=13 & op2127=0x1b & op0507=0 & rss5 & rtt5 & Rdd5 & $(END_PACKET) { + local s:8; + s = (sext(rss5[0,32]) + sext(rtt5[0,32])) >> 1; + Rdd5[0,32] = s:4; + s = (sext(rss5[32,32]) + sext(rtt5[32,32])) >> 1; + Rdd5[32,32] = s:4; + build EndPacket; +} # (v2,13) vavgw -- "Rdd32 = vavgw ( Rss32 , Rtt32 ) :crnd" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 1 1 0 1 0 0 1 1 0 1 1 s s s s s P P + t t t t t 0 1 0 d d d d d +# 1 1 0 1 0 0 1 1 0 1 1 s s s s s P P - t t t t t 0 1 0 d d d d d -:vavgw":crnd" Rdd5,rss5,rtt5 EndPacket is iclass=13 & op2127=0x1b & op13=0 & op0507=2 & rss5 & rtt5 & Rdd5 & $(END_PACKET) -unimpl +# Rdd.w[i] = convround(sxt33(Rss.w[i]) + sxt33(Rtt.w[i])) >> 1 (convergent rounding) +# Per PRM 80-N2040-60 sec.12.10 XTYPE/ALU "Vector average words" +:vavgw":crnd" Rdd5,rss5,rtt5 EndPacket is iclass=13 & op2127=0x1b & op0507=2 & rss5 & rtt5 & Rdd5 & $(END_PACKET) { + local s:8; + s = sext(rss5[0,32]) + sext(rtt5[0,32]); + Rdd5[0,32] = roundConvergent(s, 1:1); + s = sext(rss5[32,32]) + sext(rtt5[32,32]); + Rdd5[32,32] = roundConvergent(s, 1:1); + build EndPacket; +} # (v2,13) vavgw -- "Rdd32 = vavgw ( Rss32 , Rtt32 ) :rnd" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 1 1 0 1 0 0 1 1 0 1 1 s s s s s P P + t t t t t 0 0 1 d d d d d +# 1 1 0 1 0 0 1 1 0 1 1 s s s s s P P - t t t t t 0 0 1 d d d d d -:vavgw":rnd" Rdd5,rss5,rtt5 EndPacket is iclass=13 & op2127=0x1b & op13=0 & op0507=1 & rss5 & rtt5 & Rdd5 & $(END_PACKET) -unimpl +# Rdd.w[i] = (sxt33(Rss.w[i]) + sxt33(Rtt.w[i]) + 1) >> 1 (arithmetic rounding) +# Per PRM 80-N2040-60 sec.12.10 XTYPE/ALU "Vector average words" +:vavgw":rnd" Rdd5,rss5,rtt5 EndPacket is iclass=13 & op2127=0x1b & op0507=1 & rss5 & rtt5 & Rdd5 & $(END_PACKET) { + local s:8; + s = (sext(rss5[0,32]) + sext(rtt5[0,32]) + 1) >> 1; + Rdd5[0,32] = s:4; + s = (sext(rss5[32,32]) + sext(rtt5[32,32]) + 1) >> 1; + Rdd5[32,32] = s:4; + build EndPacket; +} # (v65,8) vclip -- "Rdd32 = vclip ( Rss32 , #u5 )" # _________________________________________________________________________________________________ @@ -14697,9 +15332,9 @@ define pcodeop vclip; # (v4,13) vcmpb.eq -- "Pd4 = vcmpb.eq ( Rss32 , #u8 )" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 1 1 0 1 1 1 0 0 + 0 0 s s s s s P P + i i i i i i i i 0 0 + d d +# 1 1 0 1 1 1 0 0 0 0 0 s s s s s P P - i i i i i i i i 0 0 - d d -:vcmpb.eq Pd2,rss5,Uimm8_0512 EndPacket is iclass=13 & op2127=0x60 & op13=0 & op0204=0 & Uimm8_0512 & rss5 & Pd2 & $(END_PACKET) { +:vcmpb.eq Pd2,rss5,Uimm8_0512 EndPacket is iclass=13 & op2427=0xc & op23=0 & op2122=0x0 & op0304=0 & Uimm8_0512 & rss5 & Pd2 & $(END_PACKET) { Pd2 = Pd2 & vcmpb.eq(rss5,Uimm8_0512); build EndPacket; } @@ -14707,9 +15342,9 @@ define pcodeop vclip; # (v2,13) vcmpb.eq -- "Pd4 = vcmpb.eq ( Rss32 , Rtt32 )" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 1 1 0 1 0 0 1 0 0 + + s s s s s P P 0 t t t t t 1 1 0 + + + d d +# 1 1 0 1 0 0 1 0 0 - - s s s s s P P 0 t t t t t 1 1 0 - - - d d -:vcmpb.eq Pd2,rss5,rtt5 EndPacket is iclass=13 & op2127=0x10 & op13=0 & op0207=0x30 & rtt5 & rss5 & Pd2 & $(END_PACKET) { +:vcmpb.eq Pd2,rss5,rtt5 EndPacket is iclass=13 & op2327=0x4 & op13=0 & op0507=0x6 & rtt5 & rss5 & Pd2 & $(END_PACKET) { Pd2 = Pd2 & vcmpb.eq(rss5,rtt5); build EndPacket; } @@ -14717,11 +15352,11 @@ define pcodeop vclip; # (v4,13) vcmpb.gt -- "Pd4 = vcmpb.gt ( Rss32 , #s8 )" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 1 1 0 1 1 1 0 0 + 0 1 s s s s s P P + i i i i i i i i 0 0 + d d +# 1 1 0 1 1 1 0 0 0 0 1 s s s s s P P - i i i i i i i i 0 0 - d d define pcodeop vcmpb.gt; -:vcmpb.gt Pd2,rss5,Simm8_0512 EndPacket is iclass=13 & op2127=0x61 & op13=0 & op0204=0 & Simm8_0512 & rss5 & Pd2 & $(END_PACKET) { +:vcmpb.gt Pd2,rss5,Simm8_0512 EndPacket is iclass=13 & op2427=0xc & op23=0 & op2122=0x1 & op0304=0 & Simm8_0512 & rss5 & Pd2 & $(END_PACKET) { Pd2 = Pd2 & vcmpb.gt(rss5,Simm8_0512); build EndPacket; } @@ -14729,9 +15364,9 @@ define pcodeop vcmpb.gt; # (v4,13) vcmpb.gt -- "Pd4 = vcmpb.gt ( Rss32 , Rtt32 )" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 1 1 0 1 0 0 1 0 0 + + s s s s s P P 1 t t t t t 0 1 0 + + + d d +# 1 1 0 1 0 0 1 0 0 - - s s s s s P P 1 t t t t t 0 1 0 - - - d d -:vcmpb.gt Pd2,rss5,rtt5 EndPacket is iclass=13 & op2127=0x10 & op13=1 & op0207=0x10 & rtt5 & rss5 & Pd2 & $(END_PACKET) { +:vcmpb.gt Pd2,rss5,rtt5 EndPacket is iclass=13 & op2327=0x4 & op13=1 & op0507=0x2 & rtt5 & rss5 & Pd2 & $(END_PACKET) { Pd2 = Pd2 & vcmpb.gt(rss5,rtt5); build EndPacket; } @@ -14739,11 +15374,11 @@ define pcodeop vcmpb.gt; # (v4,13) vcmpb.gtu -- "Pd4 = vcmpb.gtu ( Rss32 , #u7 )" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 1 1 0 1 1 1 0 0 + 1 0 s s s s s P P + 0 i i i i i i i 0 0 + d d +# 1 1 0 1 1 1 0 0 0 1 0 s s s s s P P - 0 i i i i i i i 0 0 - d d define pcodeop vcmpb.gtu; -:vcmpb.gtu Pd2,rss5,Uimm8_0511 EndPacket is iclass=13 & op2127=0x62 & op1213=0 & op0204=0 & Uimm8_0511 & rss5 & Pd2 & $(END_PACKET) { +:vcmpb.gtu Pd2,rss5,Uimm8_0511 EndPacket is iclass=13 & op2427=0xc & op23=0 & op2122=0x2 & op12=0 & op0304=0 & Uimm8_0511 & rss5 & Pd2 & $(END_PACKET) { Pd2 = Pd2 & vcmpb.gtu(rss5,Uimm8_0511); build EndPacket; } @@ -14751,9 +15386,9 @@ define pcodeop vcmpb.gtu; # (v2,13) vcmpb.gtu -- "Pd4 = vcmpb.gtu ( Rss32 , Rtt32 )" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 1 1 0 1 0 0 1 0 0 + + s s s s s P P 0 t t t t t 1 1 1 + + + d d +# 1 1 0 1 0 0 1 0 0 - - s s s s s P P 0 t t t t t 1 1 1 - - - d d -:vcmpb.gtu Pd2,rss5,rtt5 EndPacket is iclass=13 & op2127=0x10 & op13=0 & op0207=0x38 & rtt5 & rss5 & Pd2 & $(END_PACKET) { +:vcmpb.gtu Pd2,rss5,rtt5 EndPacket is iclass=13 & op2327=0x4 & op13=0 & op0507=0x7 & rtt5 & rss5 & Pd2 & $(END_PACKET) { Pd2 = Pd2 & vcmpb.gtu(rss5,rtt5); build EndPacket; } @@ -14761,11 +15396,11 @@ define pcodeop vcmpb.gtu; # (v4,13) vcmph.eq -- "Pd4 = vcmph.eq ( Rss32 , #s8 )" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 1 1 0 1 1 1 0 0 + 0 0 s s s s s P P - i i i i i i i i 0 1 + d d +# 1 1 0 1 1 1 0 0 0 0 0 s s s s s P P - i i i i i i i i 0 1 - d d define pcodeop vcmph.eq; -:vcmph.eq Pd2,rss5,Simm8_0512 EndPacket is iclass=13 & op2127=0x60 & op13=0 & op0204=2 & Simm8_0512 & rss5 & Pd2 & $(END_PACKET) { +:vcmph.eq Pd2,rss5,Simm8_0512 EndPacket is iclass=13 & op2427=0xc & op23=0 & op2122=0x0 & op0304=1 & Simm8_0512 & rss5 & Pd2 & $(END_PACKET) { Pd2 = Pd2 & vcmph.eq(rss5,Simm8_0512); build EndPacket; } @@ -14773,9 +15408,9 @@ define pcodeop vcmph.eq; # (v2,13) vcmph.eq -- "Pd4 = vcmph.eq ( Rss32 , Rtt32 )" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 1 1 0 1 0 0 1 0 0 + + s s s s s P P 0 t t t t t 0 1 1 + + + d d +# 1 1 0 1 0 0 1 0 0 - - s s s s s P P 0 t t t t t 0 1 1 - - - d d -:vcmph.eq Pd2,rss5,rtt5 EndPacket is iclass=13 & op2127=0x10 & op13=0 & op0207=0x18 & rtt5 & rss5 & Pd2 & $(END_PACKET) { +:vcmph.eq Pd2,rss5,rtt5 EndPacket is iclass=13 & op2327=0x4 & op13=0 & op0507=0x3 & rtt5 & rss5 & Pd2 & $(END_PACKET) { Pd2 = Pd2 & vcmph.eq(rss5,rtt5); build EndPacket; } @@ -14783,11 +15418,11 @@ define pcodeop vcmph.eq; # (v4,13) vcmph.gt -- "Pd4 = vcmph.gt ( Rss32 , #s8 )" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 1 1 0 1 1 1 0 0 + 0 1 s s s s s P P + i i i i i i i i 0 1 + d d +# 1 1 0 1 1 1 0 0 0 0 1 s s s s s P P - i i i i i i i i 0 1 - d d define pcodeop vcmph.gt; -:vcmph.gt Pd2,rss5,Simm8_0512 EndPacket is iclass=13 & op2127=0x61 & op13=0 & op0204=2 & Simm8_0512 & rss5 & Pd2 & $(END_PACKET) { +:vcmph.gt Pd2,rss5,Simm8_0512 EndPacket is iclass=13 & op2427=0xc & op23=0 & op2122=0x1 & op0304=1 & Simm8_0512 & rss5 & Pd2 & $(END_PACKET) { Pd2 = Pd2 & vcmph.gt(rss5,Simm8_0512); build EndPacket; } @@ -14795,9 +15430,9 @@ define pcodeop vcmph.gt; # (v2,13) vcmph.gt -- "Pd4 = vcmph.gt ( Rss32 , Rtt32 )" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 1 1 0 1 0 0 1 0 0 + + s s s s s P P 0 t t t t t 1 0 0 + + + d d +# 1 1 0 1 0 0 1 0 0 - - s s s s s P P 0 t t t t t 1 0 0 - - - d d -:vcmph.gt Pd2,rss5,rtt5 EndPacket is iclass=13 & op2127=0x10 & op13=0 & op0207=0x20 & rtt5 & rss5 & Pd2 & $(END_PACKET) { +:vcmph.gt Pd2,rss5,rtt5 EndPacket is iclass=13 & op2327=0x4 & op13=0 & op0507=0x4 & rtt5 & rss5 & Pd2 & $(END_PACKET) { Pd2 = Pd2 & vcmph.gt(rss5,rtt5); build EndPacket; } @@ -14805,11 +15440,11 @@ define pcodeop vcmph.gt; # (v4,13) vcmph.gtu -- "Pd4 = vcmph.gtu ( Rss32 , #u7 )" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 1 1 0 1 1 1 0 0 + 1 0 s s s s s P P + 0 i i i i i i i 0 1 + d d +# 1 1 0 1 1 1 0 0 0 1 0 s s s s s P P - 0 i i i i i i i 0 1 - d d define pcodeop vcmph.gtu; -:vcmph.gtu Pd2,rss5,Uimm8_0511 EndPacket is iclass=13 & op2127=0x62 & op1213=0 & op0204=2 & Uimm8_0511 & rss5 & Pd2 & $(END_PACKET) { +:vcmph.gtu Pd2,rss5,Uimm8_0511 EndPacket is iclass=13 & op2427=0xc & op23=0 & op2122=0x2 & op12=0 & op0304=1 & Uimm8_0511 & rss5 & Pd2 & $(END_PACKET) { Pd2 = Pd2 & vcmph.gtu(rss5,Uimm8_0511); build EndPacket; } @@ -14817,9 +15452,9 @@ define pcodeop vcmph.gtu; # (v2,13) vcmph.gtu -- "Pd4 = vcmph.gtu ( Rss32 , Rtt32 )" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 1 1 0 1 0 0 1 0 0 + + s s s s s P P 0 t t t t t 1 0 1 + + + d d +# 1 1 0 1 0 0 1 0 0 - - s s s s s P P 0 t t t t t 1 0 1 - - - d d -:vcmph.gtu Pd2,rss5,rtt5 EndPacket is iclass=13 & op2127=0x10 & op13=0 & op0207=0x28 & rtt5 & rss5 & Pd2 & $(END_PACKET) { +:vcmph.gtu Pd2,rss5,rtt5 EndPacket is iclass=13 & op2327=0x4 & op13=0 & op0507=0x5 & rtt5 & rss5 & Pd2 & $(END_PACKET) { Pd2 = Pd2 & vcmph.gtu(rss5,rtt5); build EndPacket; } @@ -14827,11 +15462,11 @@ define pcodeop vcmph.gtu; # (v4,13) vcmpw.eq -- "Pd4 = vcmpw.eq ( Rss32 , #s8 )" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 1 1 0 1 1 1 0 0 + 0 0 s s s s s P P + i i i i i i i i 1 0 + d d +# 1 1 0 1 1 1 0 0 0 0 0 s s s s s P P - i i i i i i i i 1 0 - d d define pcodeop vcmpw.eq; -:vcmpw.eq Pd2,rss5,Simm8_0512 EndPacket is iclass=13 & op2127=0x60 & op13=0 & op0204=4 & Simm8_0512 & rss5 & Pd2 & $(END_PACKET) { +:vcmpw.eq Pd2,rss5,Simm8_0512 EndPacket is iclass=13 & op2427=0xc & op23=0 & op2122=0x0 & op0304=2 & Simm8_0512 & rss5 & Pd2 & $(END_PACKET) { Pd2 = Pd2 & vcmpw.eq(rss5,Simm8_0512); build EndPacket; } @@ -14839,9 +15474,9 @@ define pcodeop vcmpw.eq; # (v2,13) vcmpw.eq -- "Pd4 = vcmpw.eq ( Rss32 , Rtt32 )" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 1 1 0 1 0 0 1 0 0 + + s s s s s P P 0 t t t t t 0 0 0 + + + d d +# 1 1 0 1 0 0 1 0 0 - - s s s s s P P 0 t t t t t 0 0 0 - - - d d -:vcmpw.eq Pd2,rss5,rtt5 EndPacket is iclass=13 & op2127=0x10 & op13=0 & op0207=0 & rtt5 & rss5 & Pd2 & $(END_PACKET) { +:vcmpw.eq Pd2,rss5,rtt5 EndPacket is iclass=13 & op2327=0x4 & op13=0 & op0507=0 & rtt5 & rss5 & Pd2 & $(END_PACKET) { Pd2 = Pd2 & vcmpw.eq(rss5,rtt5); build EndPacket; } @@ -14849,11 +15484,11 @@ define pcodeop vcmpw.eq; # (v4,13) vcmpw.gt -- "Pd4 = vcmpw.gt ( Rss32 , #s8 )" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 1 1 0 1 1 1 0 0 - 0 1 s s s s s P P + i i i i i i i i 1 0 + d d +# 1 1 0 1 1 1 0 0 0 0 1 s s s s s P P - i i i i i i i i 1 0 - d d define pcodeop vcmpw.gt; -:vcmpw.gt Pd2,rss5,Simm8_0512 EndPacket is iclass=13 & op2127=0x61 & op13=0 & op0204=4 & Simm8_0512 & rss5 & Pd2 & $(END_PACKET) { +:vcmpw.gt Pd2,rss5,Simm8_0512 EndPacket is iclass=13 & op2427=0xc & op23=0 & op2122=0x1 & op0304=2 & Simm8_0512 & rss5 & Pd2 & $(END_PACKET) { Pd2 = Pd2 & vcmpw.gt(rss5,Simm8_0512); build EndPacket; } @@ -14861,9 +15496,9 @@ define pcodeop vcmpw.gt; # (v2,13) vcmpw.gt -- "Pd4 = vcmpw.gt ( Rss32 , Rtt32 )" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 1 1 0 1 0 0 1 0 0 + + s s s s s P P 0 t t t t t 0 0 1 + + + d d +# 1 1 0 1 0 0 1 0 0 - - s s s s s P P 0 t t t t t 0 0 1 - - - d d -:vcmpw.gt Pd2,rss5,rtt5 EndPacket is iclass=13 & op2127=0x10 & op13=0 & op0207=0x08 & rtt5 & rss5 & Pd2 & $(END_PACKET) { +:vcmpw.gt Pd2,rss5,rtt5 EndPacket is iclass=13 & op2327=0x4 & op13=0 & op0507=0x1 & rtt5 & rss5 & Pd2 & $(END_PACKET) { Pd2 = Pd2 & vcmpw.gt(rss5,rtt5); build EndPacket; } @@ -14871,11 +15506,11 @@ define pcodeop vcmpw.gt; # (v4,13) vcmpw.gtu -- "Pd4 = vcmpw.gtu ( Rss32 , #u7 )" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 1 1 0 1 1 1 0 0 + 1 0 s s s s s P P + 0 i i i i i i i 1 0 + d d +# 1 1 0 1 1 1 0 0 0 1 0 s s s s s P P - 0 i i i i i i i 1 0 - d d define pcodeop vcmpw.gtu; -:vcmpw.gtu Pd2,rss5,Uimm8_0511 EndPacket is iclass=13 & op2127=0x62 & op1213=0 & op0204=4 & Uimm8_0511 & rss5 & Pd2 & $(END_PACKET) { +:vcmpw.gtu Pd2,rss5,Uimm8_0511 EndPacket is iclass=13 & op2427=0xc & op23=0 & op2122=0x2 & op12=0 & op0304=2 & Uimm8_0511 & rss5 & Pd2 & $(END_PACKET) { Pd2 = Pd2 & vcmpw.gtu(rss5,Uimm8_0511); build EndPacket; } @@ -14883,9 +15518,9 @@ define pcodeop vcmpw.gtu; # (v2,13) vcmpw.gtu -- "Pd4 = vcmpw.gtu ( Rss32 , Rtt32 )" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 1 1 0 1 0 0 1 0 0 + + s s s s s P P 0 t t t t t 0 1 0 + + + d d +# 1 1 0 1 0 0 1 0 0 - - s s s s s P P 0 t t t t t 0 1 0 - - - d d -:vcmpw.gtu Pd2,rss5,rtt5 EndPacket is iclass=13 & op2127=0x10 & op13=0 & op0207=0x10 & rtt5 & rss5 & Pd2 & $(END_PACKET) { +:vcmpw.gtu Pd2,rss5,rtt5 EndPacket is iclass=13 & op2327=0x4 & op13=0 & op0507=0x2 & rtt5 & rss5 & Pd2 & $(END_PACKET) { Pd2 = Pd2 & vcmpw.gtu(rss5,rtt5); build EndPacket; } @@ -14893,31 +15528,43 @@ define pcodeop vcmpw.gtu; # (v2,14) vcmpyi -- "Rdd32 = vcmpyi ( Rss32 , Rtt32 ) :<<1 :sat" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 1 1 1 0 1 0 0 0 1 1 0 s s s s s P P + t t t t t 1 1 0 d d d d d +# 1 1 1 0 1 0 0 0 1 1 0 s s s s s P P 0 t t t t t 1 1 0 d d d d d + +define pcodeop vcmpyiX2Sat; -:vcmpyi":<<1:sat" Rdd5,rss5,rtt5 EndPacket is iclass=14 & op2127=0x46 & op13=0 & op0507=6 & rtt5 & rss5 & Rdd5 & $(END_PACKET) -unimpl +:vcmpyi":<<1:sat" Rdd5,rss5,rtt5 EndPacket is iclass=14 & op2127=0x46 & op13=0 & op0507=6 & rtt5 & rss5 & Rdd5 & $(END_PACKET) { + Rdd5 = vcmpyiX2Sat(rss5, rtt5); + build EndPacket; +} # (v2,14) vcmpyi -- "Rdd32 = vcmpyi ( Rss32 , Rtt32 ) :sat" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 1 1 1 0 1 0 0 0 0 1 0 s s s s s P P + t t t t t 1 1 0 d d d d d +# 1 1 1 0 1 0 0 0 0 1 0 s s s s s P P 0 t t t t t 1 1 0 d d d d d -:vcmpyi":sat" Rdd5,rss5,rtt5 EndPacket is iclass=14 & op2127=0x42 & op13=0 & op0507=6 & rtt5 & rss5 & Rdd5 & $(END_PACKET) -unimpl +define pcodeop vcmpyiSat; + +:vcmpyi":sat" Rdd5,rss5,rtt5 EndPacket is iclass=14 & op2127=0x42 & op13=0 & op0507=6 & rtt5 & rss5 & Rdd5 & $(END_PACKET) { + Rdd5 = vcmpyiSat(rss5, rtt5); + build EndPacket; +} # (v2,14) vcmpyi -- "Rxx32 += vcmpyi ( Rss32 , Rtt32 ) :sat" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 1 1 1 0 1 0 1 0 0 1 0 s s s s s P P + t t t t t 1 0 0 x x x x x +# 1 1 1 0 1 0 1 0 0 1 0 s s s s s P P 0 t t t t t 1 0 0 x x x x x -:vcmpyi+=":sat" Rdd5,rss5,rtt5 EndPacket is iclass=14 & op2127=0x52 & op13=0 & op0507=4 & rtt5 & rss5 & Rdd5 & $(END_PACKET) -unimpl +define pcodeop vcmpyiSatAcc; + +:vcmpyi+=":sat" Rdd5,rss5,rtt5 EndPacket is iclass=14 & op2127=0x52 & op13=0 & op0507=4 & rtt5 & rss5 & rdd5 & Rdd5 & $(END_PACKET) { + Rdd5 = vcmpyiSatAcc(rss5, rtt5, rdd5); + build EndPacket; +} # (v2,14) vcmpyr -- "Rdd32 = vcmpyr ( Rss32 , Rtt32 ) :<<1 :sat" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 1 1 1 0 1 0 0 0 1 0 1 s s s s s P P + t t t t t 1 1 0 d d d d d +# 1 1 1 0 1 0 0 0 1 0 1 s s s s s P P 0 t t t t t 1 1 0 d d d d d define pcodeop vcmpyrX2Sat; @@ -14929,7 +15576,7 @@ define pcodeop vcmpyrX2Sat; # (v2,14) vcmpyr -- "Rdd32 = vcmpyr ( Rss32 , Rtt32 ) :sat" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 1 1 1 0 1 0 0 0 0 0 1 s s s s s P P + t t t t t 1 1 0 d d d d d +# 1 1 1 0 1 0 0 0 0 0 1 s s s s s P P 0 t t t t t 1 1 0 d d d d d define pcodeop vcmpyrSat; @@ -14941,11 +15588,11 @@ define pcodeop vcmpyrSat; # (v2,14) vcmpyr -- "Rxx32 += vcmpyr ( Rss32 , Rtt32 ) :sat" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 1 1 1 0 1 0 1 0 0 0 1 s s s s s P P + t t t t t 1 0 0 x x x x x +# 1 1 1 0 1 0 1 0 0 0 1 s s s s s P P 0 t t t t t 1 0 0 x x x x x define pcodeop vcmpyrSatAdd; -:vcmpyr+=":sat" Rdd5,rss5,rtt5 EndPacket is iclass=14 & op2127=0x51 & op13=0 & op0507=4 & rtt5 & rss5 & rdd5 & Rdd5 & $(END_PACKET) { +:vcmpyr+=":sat" Rdd5,rss5,rtt5 EndPacket is iclass=14 & op2127=0x51 & op13=0 & op0507=4 & rtt5 & rss5 & rdd5 & Rdd5 & $(END_PACKET) { Rdd5 = vcmpyrSat(rss5, rtt5, rdd5); build EndPacket; } @@ -14953,19 +15600,23 @@ define pcodeop vcmpyrSatAdd; # (v4,12) vcnegh -- "Rdd32 = vcnegh ( Rss32 , Rt32 )" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 1 1 0 0 0 0 1 1 1 1 + s s s s s P P + t t t t t 0 1 + d d d d d +# 1 1 0 0 0 0 1 1 1 1 - s s s s s P P - t t t t t 0 1 - d d d d d -:vcnegh Rdd5,rss5,rt5 EndPacket is iclass=12 & op2127=0x1e & op13=0 & op0507=2 & rt5 & rss5 & Rdd5 & $(END_PACKET) -unimpl +define pcodeop vcnegh; + +:vcnegh Rdd5,rss5,rt5 EndPacket is iclass=12 & op2227=0xf & op0607=1 & rt5 & rss5 & Rdd5 & $(END_PACKET) { + Rdd5 = vcnegh(rss5, rt5); + build EndPacket; +} # (v2,8) vconj -- "Rdd32 = vconj ( Rss32 ) :sat" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 1 0 0 0 0 0 0 0 1 0 + s s s s s P P + + + + + + 1 1 1 d d d d d +# 1 0 0 0 0 0 0 0 1 0 0 s s s s s P P - - - - - - 1 1 1 d d d d d define pcodeop vconjSat; -:vconj":sat" Rdd5,rss5 EndPacket is iclass=8 & op2127=0x04 & op0513=0x07 & rss5 & Rdd5 & $(END_PACKET) +:vconj":sat" Rdd5,rss5 EndPacket is iclass=8 & op2227=0x2 & op21=0 & op0507=0x7 & rss5 & Rdd5 & $(END_PACKET) { Rdd5 = vconjSat(rss5); build EndPacket; @@ -14974,11 +15625,11 @@ define pcodeop vconjSat; # (v2,12) vcrotate -- "Rdd32 = vcrotate ( Rss32 , Rt32 )" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 1 1 0 0 0 0 1 1 1 1 + s s s s s P P + t t t t t 0 0 + d d d d d +# 1 1 0 0 0 0 1 1 1 1 - s s s s s P P - t t t t t 0 0 - d d d d d define pcodeop vcrotate; -:vcrotate Rdd5,rss5,rt5 EndPacket is iclass=12 & op2127=0x1e & op13=0 & op0507=0 & rt5 & rss5 & Rdd5 & $(END_PACKET) +:vcrotate Rdd5,rss5,rt5 EndPacket is iclass=12 & op2227=0xf & op0607=0 & rt5 & rss5 & Rdd5 & $(END_PACKET) { Rdd5 = vcrotate(rss5, rt5); build EndPacket; @@ -14987,7 +15638,7 @@ define pcodeop vcrotate; # (v2,14) vdmpy -- "Rd32 = vdmpy ( Rss32 , Rtt32 ) :<<1 :rnd :sat" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 1 1 1 0 1 0 0 1 1 + + s s s s s P P + t t t t t + 0 0 d d d d d +# 1 1 1 0 1 0 0 1 1 0 0 s s s s s P P 0 t t t t t 0 0 0 d d d d d define pcodeop vdmpyX2RndSat; @@ -14999,7 +15650,7 @@ define pcodeop vdmpyX2RndSat; # (v2,14) vdmpy -- "Rd32 = vdmpy ( Rss32 , Rtt32 ) :rnd :sat" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 1 1 1 0 1 0 0 1 0 + + s s s s s P P + t t t t t + 0 0 d d d d d +# 1 1 1 0 1 0 0 1 0 0 0 s s s s s P P 0 t t t t t 0 0 0 d d d d d define pcodeop vdmpyRndSat; @@ -15011,7 +15662,7 @@ define pcodeop vdmpyRndSat; # (v2,14) vdmpy -- "Rdd32 = vdmpy ( Rss32 , Rtt32 ) :<<1 :sat" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 1 1 1 0 1 0 0 0 1 0 0 s s s s s P P + t t t t t 1 0 0 d d d d d +# 1 1 1 0 1 0 0 0 1 0 0 s s s s s P P 0 t t t t t 1 0 0 d d d d d define pcodeop vdmpyX2Sat; @@ -15023,7 +15674,7 @@ define pcodeop vdmpyX2Sat; # (v2,14) vdmpy -- "Rdd32 = vdmpy ( Rss32 , Rtt32 ) :sat" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 1 1 1 0 1 0 0 0 0 0 0 s s s s s P P + t t t t t 1 0 0 d d d d d +# 1 1 1 0 1 0 0 0 0 0 0 s s s s s P P 0 t t t t t 1 0 0 d d d d d define pcodeop vdmpySat; @@ -15035,7 +15686,7 @@ define pcodeop vdmpySat; # (v2,14) vdmpy -- "Rxx32 += vdmpy ( Rss32 , Rtt32 ) :<<1 :sat" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 1 1 1 0 1 0 1 0 1 0 0 s s s s s P P + t t t t t 1 0 0 x x x x x +# 1 1 1 0 1 0 1 0 1 0 0 s s s s s P P 0 t t t t t 1 0 0 x x x x x define pcodeop vdmpyX2SatAdd; @@ -15047,7 +15698,7 @@ define pcodeop vdmpyX2SatAdd; # (v2,14) vdmpy -- "Rxx32 += vdmpy ( Rss32 , Rtt32 ) :sat" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 1 1 1 0 1 0 1 0 0 0 0 s s s s s P P + t t t t t 1 0 0 x x x x x +# 1 1 1 0 1 0 1 0 0 0 0 s s s s s P P 0 t t t t t 1 0 0 x x x x x define pcodeop vdmpySatAdd; @@ -15056,22 +15707,22 @@ define pcodeop vdmpySatAdd; build EndPacket; } -# (v?,14) vdmpybsu -- "Rxx32 = vdmpybsu ( Rss32 , Rtt32 ) :sat" +# (v5,14) vdmpybsu -- "Rxx32 = vdmpybsu ( Rss32 , Rtt32 ) :sat" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 1 1 1 0 1 0 0 0 1 0 1 s s s s s P P + t t t t t 0 0 1 x x x x x +# 1 1 1 0 1 0 0 0 1 0 1 s s s s s P P - t t t t t 0 0 1 x x x x x define pcodeop vdmpybsuSat; -:vdmpybsu=":sat" Rdd5,rss5,rtt5 EndPacket is iclass=14 & op2127=0x45 & op13=0 & op0507=1 & rtt5 & rss5 & Rdd5 & $(END_PACKET) { +:vdmpybsu=":sat" Rdd5,rss5,rtt5 EndPacket is iclass=14 & op2127=0x45 & op0507=1 & rtt5 & rss5 & Rdd5 & $(END_PACKET) { Rdd5 = vdmpybsuSat(rss5, rtt5); build EndPacket; } -# (v?,14) vdmpybsu -- "Rxx32 += vdmpybsu ( Rss32 , Rtt32 ) :sat" +# (v5,14) vdmpybsu -- "Rxx32 += vdmpybsu ( Rss32 , Rtt32 ) :sat" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 1 1 1 0 1 0 1 0 0 0 1 s s s s s P P + t t t t t 0 0 1 x x x x x +# 1 1 1 0 1 0 1 0 0 0 1 s s s s s P P 0 t t t t t 0 0 1 x x x x x define pcodeop vdmpybsuSatAdd; @@ -15083,9 +15734,9 @@ define pcodeop vdmpybsuSatAdd; # (v2,8) vitpack -- "Rd32 = vitpack ( Ps4 , Pt4 )" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 1 0 0 0 1 0 0 1 + 0 + + + + s s P P + + + + t t + + + d d d d d +# 1 0 0 0 1 0 0 1 - 0 0 - - - s s P P - - - - t t - - - d d d d d -:vitpack Rd5,pu1617,pu0809 EndPacket is iclass=8 & op2127=0x48 & op1820=0 & op1013=0 & op0507=0 & pu1617 & pu0809 & Rd5 & $(END_PACKET) +:vitpack Rd5,pu1617,pu0809 EndPacket is iclass=8 & op2427=0x9 & op22=0x0 & op21=0 & pu1617 & pu0809 & Rd5 & $(END_PACKET) { Rd5 = zext((pu1617 & 0x55) | (pu0809 & 0xaa)); build EndPacket; @@ -15094,11 +15745,11 @@ define pcodeop vdmpybsuSatAdd; # (v2,12) vlslh -- "Rdd32 = vlslh ( Rss32 , Rt32 )" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 1 1 0 0 0 0 1 1 0 1 + s s s s s P P + t t t t t 1 1 + d d d d d +# 1 1 0 0 0 0 1 1 0 1 - s s s s s P P - t t t t t 1 1 - d d d d d define pcodeop vlslh; -:vlslh Rdd5,rss5,rt5 EndPacket is iclass=12 & op2127=0x1a & op13=0 & op0507=6 & Rdd5 & rt5 & rss5 & $(END_PACKET) { +:vlslh Rdd5,rss5,rt5 EndPacket is iclass=12 & op2227=0xd & op0607=3 & Rdd5 & rt5 & rss5 & $(END_PACKET) { Rdd5 = vlslh(rss5, rt5); build EndPacket; } @@ -15106,11 +15757,11 @@ define pcodeop vlslh; # (v2,12) vlslw -- "Rdd32 = vlslw ( Rss32 , Rt32 )" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 1 1 0 0 0 0 1 1 0 0 + s s s s s P P + t t t t t 1 1 + d d d d d +# 1 1 0 0 0 0 1 1 0 0 - s s s s s P P - t t t t t 1 1 - d d d d d define pcodeop vlslw; -:vlslw Rdd5,rss5,rt5 EndPacket is iclass=12 & op2127=0x18 & op13=0 & op0507=6 & Rdd5 & rt5 & rss5 & $(END_PACKET) { +:vlslw Rdd5,rss5,rt5 EndPacket is iclass=12 & op2227=0xc & op0607=3 & Rdd5 & rt5 & rss5 & $(END_PACKET) { Rdd5 = vlslw(rss5, rt5); build EndPacket; } @@ -15118,11 +15769,11 @@ define pcodeop vlslw; # (v2,8) vlsrh -- "Rdd32 = vlsrh ( Rss32 , #u4 )" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 1 0 0 0 0 0 0 0 1 0 + s s s s s P P 0 0 i i i i 0 0 1 d d d d d +# 1 0 0 0 0 0 0 0 1 0 0 s s s s s P P 0 0 i i i i 0 0 1 d d d d d define pcodeop vlsrh; -:vlsrh Rdd5,rss5,Uimm8_0811 EndPacket is iclass=8 & op2127=0x04 & op1213=0 & op0507=1 & Rdd5 & Uimm8_0811 & rss5 & $(END_PACKET) { +:vlsrh Rdd5,rss5,Uimm8_0811 EndPacket is iclass=8 & op2227=0x2 & op21=0 & op1213=0 & op0507=1 & Rdd5 & Uimm8_0811 & rss5 & $(END_PACKET) { Rdd5 = vlsrh(rss5, Uimm8_0811); build EndPacket; } @@ -15130,9 +15781,9 @@ define pcodeop vlsrh; # (v2,12) vlsrh -- "Rdd32 = vlsrh ( Rss32 , Rt32 )" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 1 1 0 0 0 0 1 1 0 1 + s s s s s P P + t t t t t 0 1 + d d d d d +# 1 1 0 0 0 0 1 1 0 1 - s s s s s P P - t t t t t 0 1 - d d d d d -:vlsrh Rdd5,rss5,rt5 EndPacket is iclass=12 & op2127=0x1a & op13=0 & op0507=2 & Rdd5 & rt5 & rss5 & $(END_PACKET) { +:vlsrh Rdd5,rss5,rt5 EndPacket is iclass=12 & op2227=0xd & op0607=1 & Rdd5 & rt5 & rss5 & $(END_PACKET) { Rdd5 = vlsrh(rss5, rt5); build EndPacket; } @@ -15140,11 +15791,11 @@ define pcodeop vlsrh; # (v2,8) vlsrw -- "Rdd32 = vlsrw ( Rss32 , #u5 )" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 1 0 0 0 0 0 0 0 0 1 + s s s s s P P 0 i i i i i 0 0 1 d d d d d +# 1 0 0 0 0 0 0 0 0 1 0 s s s s s P P 0 i i i i i 0 0 1 d d d d d define pcodeop vlsrw; -:vlsrw Rdd5,rss5,Uimm8_0812 EndPacket is iclass=8 & op2127=0x02 & op13=0 & op0507=1 & Rdd5 & Uimm8_0812 & rss5 & $(END_PACKET) { +:vlsrw Rdd5,rss5,Uimm8_0812 EndPacket is iclass=8 & op2227=0x1 & op21=0 & op13=0 & op0507=1 & Rdd5 & Uimm8_0812 & rss5 & $(END_PACKET) { Rdd5 = vlsrw(rss5, Uimm8_0812); build EndPacket; } @@ -15152,9 +15803,9 @@ define pcodeop vlsrw; # (v2,12) vlsrw -- "Rdd32 = vlsrw ( Rss32 , Rt32 )" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 1 1 0 0 0 0 1 1 0 0 + s s s s s P P + t t t t t 0 1 + d d d d d +# 1 1 0 0 0 0 1 1 0 0 - s s s s s P P - t t t t t 0 1 - d d d d d -:vlsrw Rdd5,rss5,rt5 EndPacket is iclass=12 & op2127=0x18 & op13=0 & op0507=2 & Rdd5 & rt5 & rss5 & $(END_PACKET) { +:vlsrw Rdd5,rss5,rt5 EndPacket is iclass=12 & op2227=0xc & op0607=1 & Rdd5 & rt5 & rss5 & $(END_PACKET) { Rdd5 = vlsrw(rss5, rt5); build EndPacket; } @@ -15162,151 +15813,163 @@ define pcodeop vlsrw; # (v4,13) vmaxb -- "Rdd32 = vmaxb ( Rtt32 , Rss32 )" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 1 1 0 1 0 0 1 1 1 1 0 s s s s s P P + t t t t t 1 1 0 d d d d d +# 1 1 0 1 0 0 1 1 1 1 0 s s s s s P P - t t t t t 1 1 0 d d d d d define pcodeop vmaxb; -:vmaxb Rdd5,rss5,rtt5 EndPacket is iclass=13 & op2127=0x1e & op13=0 & op0507=6 & Rdd5 & rtt5 & rss5 & $(END_PACKET) { - Rdd5 = vmaxb(rss5, rtt5); +:vmaxb Rdd5,rtt5,rss5 EndPacket is iclass=13 & op2127=0x1e & op0507=6 & Rdd5 & rtt5 & rss5 & $(END_PACKET) { + Rdd5 = vmaxb(rtt5, rss5); build EndPacket; } # (v2,13) vmaxh -- "Rdd32 = vmaxh ( Rtt32 , Rss32 )" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 1 1 0 1 0 0 1 1 1 1 0 s s s s s P P + t t t t t 0 0 1 d d d d d +# 1 1 0 1 0 0 1 1 1 1 0 s s s s s P P - t t t t t 0 0 1 d d d d d define pcodeop vmaxh; -:vmaxh Rdd5,rss5,rtt5 EndPacket is iclass=13 & op2127=0x1e & op13=0 & op0507=1 & Rdd5 & rtt5 & rss5 & $(END_PACKET) { - Rdd5 = vmaxh(rss5, rtt5); +:vmaxh Rdd5,rtt5,rss5 EndPacket is iclass=13 & op2127=0x1e & op0507=1 & Rdd5 & rtt5 & rss5 & $(END_PACKET) { + Rdd5 = vmaxh(rtt5, rss5); build EndPacket; } # (v2,13) vmaxub -- "Rdd32 = vmaxub ( Rtt32 , Rss32 )" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 1 1 0 1 0 0 1 1 1 1 0 s s s s s P P + t t t t t 0 0 0 d d d d d +# 1 1 0 1 0 0 1 1 1 1 0 s s s s s P P - t t t t t 0 0 0 d d d d d define pcodeop vmaxub; -:vmaxub Rdd5,rss5,rtt5 EndPacket is iclass=13 & op2127=0x1e & op13=0 & op0507=0 & Rdd5 & rtt5 & rss5 & $(END_PACKET) { - Rdd5 = vmaxub(rss5, rtt5); +:vmaxub Rdd5,rtt5,rss5 EndPacket is iclass=13 & op2127=0x1e & op0507=0 & Rdd5 & rtt5 & rss5 & $(END_PACKET) { + Rdd5 = vmaxub(rtt5, rss5); build EndPacket; } # (v2,13) vmaxuh -- "Rdd32 = vmaxuh ( Rtt32 , Rss32 )" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 1 1 0 1 0 0 1 1 1 1 0 s s s s s P P + t t t t t 0 1 0 d d d d d +# 1 1 0 1 0 0 1 1 1 1 0 s s s s s P P - t t t t t 0 1 0 d d d d d define pcodeop vmaxuh; -:vmaxuh Rdd5,rss5,rtt5 EndPacket is iclass=13 & op2127=0x1e & op13=0 & op0507=2 & Rdd5 & rtt5 & rss5 & $(END_PACKET) { - Rdd5 = vmaxuh(rss5, rtt5); +:vmaxuh Rdd5,rtt5,rss5 EndPacket is iclass=13 & op2127=0x1e & op0507=2 & Rdd5 & rtt5 & rss5 & $(END_PACKET) { + Rdd5 = vmaxuh(rtt5, rss5); build EndPacket; } # (v2,13) vmaxuw -- "Rdd32 = vmaxuw ( Rtt32 , Rss32 )" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 1 1 0 1 0 0 1 1 1 0 1 s s s s s P P + t t t t t 1 0 1 d d d d d +# 1 1 0 1 0 0 1 1 1 0 1 s s s s s P P - t t t t t 1 0 1 d d d d d define pcodeop vmaxuw; -:vmaxuw Rdd5,rss5,rtt5 EndPacket is iclass=13 & op2127=0x1d & op13=0 & op0507=5 & Rdd5 & rtt5 & rss5 & $(END_PACKET) { - Rdd5 = vmaxuw(rss5, rtt5); +:vmaxuw Rdd5,rtt5,rss5 EndPacket is iclass=13 & op2127=0x1d & op0507=5 & Rdd5 & rtt5 & rss5 & $(END_PACKET) { + Rdd5 = vmaxuw(rtt5, rss5); build EndPacket; } # (v2,13) vmaxw -- "Rdd32 = vmaxw ( Rtt32 , Rss32 )" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 1 1 0 1 0 0 1 1 1 1 0 s s s s s P P + t t t t t 0 1 1 d d d d d +# 1 1 0 1 0 0 1 1 1 1 0 s s s s s P P - t t t t t 0 1 1 d d d d d define pcodeop vmaxw; -:vmaxw Rdd5,rss5,rtt5 EndPacket is iclass=13 & op2127=0x1e & op13=0 & op0507=3 & Rdd5 & rtt5 & rss5 & $(END_PACKET) { - Rdd5 = vmaxw(rss5, rtt5); +:vmaxw Rdd5,rtt5,rss5 EndPacket is iclass=13 & op2127=0x1e & op0507=3 & Rdd5 & rtt5 & rss5 & $(END_PACKET) { + Rdd5 = vmaxw(rtt5, rss5); build EndPacket; } # (v4,13) vminb -- "Rdd32 = vminb ( Rtt32 , Rss32 )" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 1 1 0 1 0 0 1 1 1 1 0 s s s s s P P + t t t t t 1 1 1 d d d d d +# 1 1 0 1 0 0 1 1 1 1 0 s s s s s P P - t t t t t 1 1 1 d d d d d define pcodeop vminb; -:vminb Rdd5,rss5,rtt5 EndPacket is iclass=13 & op2127=0x1e & op13=0 & op0507=7 & Rdd5 & rtt5 & rss5 & $(END_PACKET) { - Rdd5 = vminb(rss5, rtt5); +:vminb Rdd5,rtt5,rss5 EndPacket is iclass=13 & op2127=0x1e & op0507=7 & Rdd5 & rtt5 & rss5 & $(END_PACKET) { + Rdd5 = vminb(rtt5, rss5); build EndPacket; } # (v2,13) vminh -- "Rdd32 = vminh ( Rtt32 , Rss32 )" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 1 1 0 1 0 0 1 1 1 0 1 s s s s s P P + t t t t t 0 0 1 d d d d d +# 1 1 0 1 0 0 1 1 1 0 1 s s s s s P P - t t t t t 0 0 1 d d d d d define pcodeop vminh; -:vminh Rdd5,rss5,rtt5 EndPacket is iclass=13 & op2127=0x1d & op13=0 & op0507=1 & Rdd5 & rtt5 & rss5 & $(END_PACKET) { - Rdd5 = vminh(rss5, rtt5); +:vminh Rdd5,rtt5,rss5 EndPacket is iclass=13 & op2127=0x1d & op0507=1 & Rdd5 & rtt5 & rss5 & $(END_PACKET) { + Rdd5 = vminh(rtt5, rss5); build EndPacket; } # (v2,13) vminub -- "Rdd32 = vminub ( Rtt32 , Rss32 )" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 1 1 0 1 0 0 1 1 1 0 1 s s s s s P P + t t t t t 0 0 0 d d d d d +# 1 1 0 1 0 0 1 1 1 0 1 s s s s s P P - t t t t t 0 0 0 d d d d d define pcodeop vminub; -:vminub Rdd5,rss5,rtt5 EndPacket is iclass=13 & op2127=0x1d & op13=0 & op0507=0 & Rdd5 & rtt5 & rss5 & $(END_PACKET) { - Rdd5 = vminub(rss5, rtt5); +:vminub Rdd5,rtt5,rss5 EndPacket is iclass=13 & op2127=0x1d & op0507=0 & Rdd5 & rtt5 & rss5 & $(END_PACKET) { + Rdd5 = vminub(rtt5, rss5); + build EndPacket; +} + +# (v62,14) vminub -- "Rdd32 , Pe4 = vminub ( Rtt32 , Rss32 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 1 0 1 0 1 0 1 1 1 s s s s s P P 0 t t t t t 0 e e d d d d d + +define pcodeop vminubPred; # per-byte predicate bits: Pe[i] = (first.ub[i] > second.ub[i]) +:vminub Rdd5,Pd0506,rtt5,rss5 EndPacket is iclass=14 & op2127=0x57 & op13=0 & op7=0 & Rdd5 & Pd0506 & rtt5 & rss5 & $(END_PACKET) { + Rdd5 = vminub(rtt5, rss5); + Pd0506 = vminubPred(rtt5, rss5); build EndPacket; } # (v2,13) vminuh -- "Rdd32 = vminuh ( Rtt32 , Rss32 )" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 1 1 0 1 0 0 1 1 1 0 1 s s s s s P P + t t t t t 0 1 0 d d d d d +# 1 1 0 1 0 0 1 1 1 0 1 s s s s s P P - t t t t t 0 1 0 d d d d d define pcodeop vminuh; -:vminuh Rdd5,rss5,rtt5 EndPacket is iclass=13 & op2127=0x1d & op13=0 & op0507=2 & Rdd5 & rtt5 & rss5 & $(END_PACKET) { - Rdd5 = vminuh(rss5, rtt5); +:vminuh Rdd5,rtt5,rss5 EndPacket is iclass=13 & op2127=0x1d & op0507=2 & Rdd5 & rtt5 & rss5 & $(END_PACKET) { + Rdd5 = vminuh(rtt5, rss5); build EndPacket; } # (v2,13) vminuw -- "Rdd32 = vminuw ( Rtt32 , Rss32 )" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 1 1 0 1 0 0 1 1 1 0 1 s s s s s P P + t t t t t 1 0 0 d d d d d +# 1 1 0 1 0 0 1 1 1 0 1 s s s s s P P - t t t t t 1 0 0 d d d d d define pcodeop vminuw; -:vminuw Rdd5,rss5,rtt5 EndPacket is iclass=13 & op2127=0x1d & op13=0 & op0507=4 & Rdd5 & rtt5 & rss5 & $(END_PACKET) { - Rdd5 = vminuw(rss5, rtt5); +:vminuw Rdd5,rtt5,rss5 EndPacket is iclass=13 & op2127=0x1d & op0507=4 & Rdd5 & rtt5 & rss5 & $(END_PACKET) { + Rdd5 = vminuw(rtt5, rss5); build EndPacket; } # (v2,13) vminw -- "Rdd32 = vminw ( Rtt32 , Rss32 )" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 1 1 0 1 0 0 1 1 1 0 1 s s s s s P P + t t t t t 0 1 1 d d d d d +# 1 1 0 1 0 0 1 1 1 0 1 s s s s s P P - t t t t t 0 1 1 d d d d d define pcodeop vminw; -:vminw Rdd5,rss5,rtt5 EndPacket is iclass=13 & op2127=0x1d & op13=0 & op0507=3 & Rdd5 & rtt5 & rss5 & $(END_PACKET) { - Rdd5 = vminw(rss5, rtt5); +:vminw Rdd5,rtt5,rss5 EndPacket is iclass=13 & op2127=0x1d & op0507=3 & Rdd5 & rtt5 & rss5 & $(END_PACKET) { + Rdd5 = vminw(rtt5, rss5); build EndPacket; } # (v4,14) vmpybsu -- "Rdd32 = vmpybsu ( Rs32 , Rt32 )" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 1 1 1 0 0 1 0 1 0 1 0 s s s s s P P + t t t t t 0 0 1 d d d d d +# 1 1 1 0 0 1 0 1 0 1 0 s s s s s P P 0 t t t t t 0 0 1 d d d d d define pcodeop vmpybsu; @@ -15318,15 +15981,19 @@ define pcodeop vmpybsu; # (v4,14) vmpybsu -- "Rxx32 += vmpybsu ( Rs32 , Rt32 )" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 1 1 1 0 0 1 1 1 1 1 0 s s s s s P P + t t t t t 0 0 1 x x x x x +# 1 1 1 0 0 1 1 1 1 1 0 s s s s s P P 0 t t t t t 0 0 1 x x x x x -:vmpybsu+= Rdd5,rs5,rt5 EndPacket is iclass=14 & op2127=0x3e & op13=0 & op0507=1 & Rdd5 & rdd5 & rt5 & rs5 & $(END_PACKET) -unimpl +define pcodeop vmpybsuAcc; + +:vmpybsu+= Rdd5,rs5,rt5 EndPacket is iclass=14 & op2127=0x3e & op13=0 & op0507=1 & Rdd5 & rdd5 & rt5 & rs5 & $(END_PACKET) { + Rdd5 = vmpybsuAcc(rs5, rt5, rdd5); + build EndPacket; +} # (v4,14) vmpybu -- "Rdd32 = vmpybu ( Rs32 , Rt32 )" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 1 1 1 0 0 1 0 1 1 0 0 s s s s s P P + t t t t t 0 0 1 d d d d d +# 1 1 1 0 0 1 0 1 1 0 0 s s s s s P P 0 t t t t t 0 0 1 d d d d d define pcodeop vmpybu; @@ -15338,15 +16005,19 @@ define pcodeop vmpybu; # (v4,14) vmpybu -- "Rxx32 += vmpybu ( Rs32 , Rt32 )" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 1 1 1 0 0 1 1 1 1 0 0 s s s s s P P + t t t t t 0 0 1 x x x x x +# 1 1 1 0 0 1 1 1 1 0 0 s s s s s P P 0 t t t t t 0 0 1 x x x x x -:vmpybu+= Rdd5,rs5,rt5 EndPacket is iclass=14 & op2127=0x3c & op13=0 & op0507=1 & Rdd5 & rdd5 & rt5 & rs5 & $(END_PACKET) -unimpl +define pcodeop vmpybuAdd; + +:vmpybu+= Rdd5,rs5,rt5 EndPacket is iclass=14 & op2127=0x3c & op13=0 & op0507=1 & Rdd5 & rdd5 & rt5 & rs5 & $(END_PACKET) { + Rdd5 = vmpybuAdd(rs5, rt5, rdd5); + build EndPacket; +} # (v2,14) vmpyeh -- "Rdd32 = vmpyeh ( Rss32 , Rtt32 ) :<<1 :sat" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 1 1 1 0 1 0 0 0 1 0 0 s s s s s P P + t t t t t 1 1 0 d d d d d +# 1 1 1 0 1 0 0 0 1 0 0 s s s s s P P 0 t t t t t 1 1 0 d d d d d define pcodeop vmpyehX2Sat; @@ -15358,7 +16029,7 @@ define pcodeop vmpyehX2Sat; # (v2,14) vmpyeh -- "Rdd32 = vmpyeh ( Rss32 , Rtt32 ) :sat" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 1 1 1 0 1 0 0 0 0 0 0 s s s s s P P + t t t t t 1 1 0 d d d d d +# 1 1 1 0 1 0 0 0 0 0 0 s s s s s P P 0 t t t t t 1 1 0 d d d d d define pcodeop vmpyehSat; @@ -15370,7 +16041,7 @@ define pcodeop vmpyehSat; # (v2,14) vmpyeh -- "Rxx32 += vmpyeh ( Rss32 , Rtt32 )" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 1 1 1 0 1 0 1 0 0 0 1 s s s s s P P + t t t t t 0 1 0 x x x x x +# 1 1 1 0 1 0 1 0 0 0 1 s s s s s P P 0 t t t t t 0 1 0 x x x x x define pcodeop vmpyehAdd; @@ -15382,7 +16053,7 @@ define pcodeop vmpyehAdd; # (v2,14) vmpyeh -- "Rxx32 += vmpyeh ( Rss32 , Rtt32 ) :<<1 :sat" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 1 1 1 0 1 0 1 0 1 0 0 s s s s s P P + t t t t t 1 1 0 x x x x x +# 1 1 1 0 1 0 1 0 1 0 0 s s s s s P P 0 t t t t t 1 1 0 x x x x x define pcodeop vmpyehX2SatAdd; @@ -15394,7 +16065,7 @@ define pcodeop vmpyehX2SatAdd; # (v2,14) vmpyeh -- "Rxx32 += vmpyeh ( Rss32 , Rtt32 ) :sat" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 1 1 1 0 1 0 1 0 0 0 0 s s s s s P P + t t t t t 1 1 0 x x x x x +# 1 1 1 0 1 0 1 0 0 0 0 s s s s s P P 0 t t t t t 1 1 0 x x x x x define pcodeop vmpyehSatAdd; @@ -15406,7 +16077,7 @@ define pcodeop vmpyehSatAdd; # (v2,14) vmpyh -- "Rd32 = vmpyh ( Rs32 , Rt32 ) :<<1 :rnd :sat" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 1 1 1 0 1 1 0 1 1 0 1 s s s s s P P + t t t t t 1 1 1 d d d d d +# 1 1 1 0 1 1 0 1 1 0 1 s s s s s P P 0 t t t t t 1 1 1 d d d d d define pcodeop vmpyhX2RndSat; @@ -15418,7 +16089,7 @@ define pcodeop vmpyhX2RndSat; # (v2,14) vmpyh -- "Rd32 = vmpyh ( Rs32 , Rt32 ) :rnd :sat" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 1 1 1 0 1 1 0 1 0 0 1 s s s s s P P + t t t t t 1 1 1 d d d d d +# 1 1 1 0 1 1 0 1 0 0 1 s s s s s P P 0 t t t t t 1 1 1 d d d d d define pcodeop vmpyhRndSat; @@ -15430,7 +16101,7 @@ define pcodeop vmpyhRndSat; # (v2,14) vmpyh -- "Rdd32 = vmpyh ( Rs32 , Rt32 ) :<<1 :sat" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 1 1 1 0 0 1 0 1 1 0 0 s s s s s P P + t t t t t 1 0 1 d d d d d +# 1 1 1 0 0 1 0 1 1 0 0 s s s s s P P 0 t t t t t 1 0 1 d d d d d define pcodeop vmpyhX2Sat; @@ -15442,7 +16113,7 @@ define pcodeop vmpyhX2Sat; # (v2,14) vmpyh -- "Rdd32 = vmpyh ( Rs32 , Rt32 ) :sat" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 1 1 1 0 0 1 0 1 0 0 0 s s s s s P P + t t t t t 1 0 1 d d d d d +# 1 1 1 0 0 1 0 1 0 0 0 s s s s s P P 0 t t t t t 1 0 1 d d d d d define pcodeop vmpyhSat; @@ -15454,7 +16125,7 @@ define pcodeop vmpyhSat; # (v2,14) vmpyh -- "Rxx32 += vmpyh ( Rs32 , Rt32 )" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 1 1 1 0 0 1 1 1 0 0 1 s s s s s P P + t t t t t 0 0 1 x x x x x +# 1 1 1 0 0 1 1 1 0 0 1 s s s s s P P 0 t t t t t 0 0 1 x x x x x define pcodeop vmpyhAdd; @@ -15466,7 +16137,7 @@ define pcodeop vmpyhAdd; # (v2,14) vmpyh -- "Rxx32 += vmpyh ( Rs32 , Rt32 ) :<<1 :sat" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 1 1 1 0 0 1 1 1 1 0 0 s s s s s P P + t t t t t 1 0 1 x x x x x +# 1 1 1 0 0 1 1 1 1 0 0 s s s s s P P 0 t t t t t 1 0 1 x x x x x define pcodeop vmpyhX2SatAdd; @@ -15478,7 +16149,7 @@ define pcodeop vmpyhX2SatAdd; # (v2,14) vmpyh -- "Rxx32 += vmpyh ( Rs32 , Rt32 ) :sat" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 1 1 1 0 0 1 1 1 0 0 0 s s s s s P P + t t t t t 1 0 1 x x x x x +# 1 1 1 0 0 1 1 1 0 0 0 s s s s s P P 0 t t t t t 1 0 1 x x x x x define pcodeop vmpyhSatAdd; @@ -15490,7 +16161,7 @@ define pcodeop vmpyhSatAdd; # (v4,14) vmpyhsu -- "Rdd32 = vmpyhsu ( Rs32 , Rt32 ) :<<1 :sat" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 1 1 1 0 0 1 0 1 1 0 0 s s s s s P P + t t t t t 1 1 1 d d d d d +# 1 1 1 0 0 1 0 1 1 0 0 s s s s s P P 0 t t t t t 1 1 1 d d d d d define pcodeop vmpyhsuX2Sat; @@ -15502,7 +16173,7 @@ define pcodeop vmpyhsuX2Sat; # (v4,14) vmpyhsu -- "Rdd32 = vmpyhsu ( Rs32 , Rt32 ) :sat" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 1 1 1 0 0 1 0 1 0 0 0 s s s s s P P + t t t t t 1 1 1 d d d d d +# 1 1 1 0 0 1 0 1 0 0 0 s s s s s P P 0 t t t t t 1 1 1 d d d d d define pcodeop vmpyhsuSat; @@ -15514,7 +16185,7 @@ define pcodeop vmpyhsuSat; # (v4,14) vmpyhsu -- "Rxx32 += vmpyhsu ( Rs32 , Rt32 ) :<<1 :sat" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 1 1 1 0 0 1 1 1 1 1 1 s s s s s P P + t t t t t 1 0 1 x x x x x +# 1 1 1 0 0 1 1 1 1 1 1 s s s s s P P 0 t t t t t 1 0 1 x x x x x define pcodeop vmpyhsuX2SatAdd; @@ -15526,7 +16197,7 @@ define pcodeop vmpyhsuX2SatAdd; # (v4,14) vmpyhsu -- "Rxx32 += vmpyhsu ( Rs32 , Rt32 ) :sat" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 1 1 1 0 0 1 1 1 0 1 1 s s s s s P P + t t t t t 1 0 1 x x x x x +# 1 1 1 0 0 1 1 1 0 1 1 s s s s s P P 0 t t t t t 1 0 1 x x x x x define pcodeop vmpyhsuSatAdd; @@ -15538,7 +16209,7 @@ define pcodeop vmpyhsuSatAdd; # (v2,14) vmpyweh -- "Rdd32 = vmpyweh ( Rss32 , Rtt32 ) :<<1 :rnd :sat" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 1 1 1 0 1 0 0 0 1 0 1 s s s s s P P + t t t t t 1 0 1 d d d d d +# 1 1 1 0 1 0 0 0 1 0 1 s s s s s P P 0 t t t t t 1 0 1 d d d d d define pcodeop vmpywehX2RndSat; @@ -15550,7 +16221,7 @@ define pcodeop vmpywehX2RndSat; # (v2,14) vmpyweh -- "Rdd32 = vmpyweh ( Rss32 , Rtt32 ) :<<1 :sat" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 1 1 1 0 1 0 0 0 1 0 0 s s s s s P P + t t t t t 1 0 1 d d d d d +# 1 1 1 0 1 0 0 0 1 0 0 s s s s s P P 0 t t t t t 1 0 1 d d d d d define pcodeop vmpywehX2Sat; @@ -15562,7 +16233,7 @@ define pcodeop vmpywehX2Sat; # (v2,14) vmpyweh -- "Rdd32 = vmpyweh ( Rss32 , Rtt32 ) :rnd :sat" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 1 1 1 0 1 0 0 0 0 0 1 s s s s s P P + t t t t t 1 0 1 d d d d d +# 1 1 1 0 1 0 0 0 0 0 1 s s s s s P P 0 t t t t t 1 0 1 d d d d d define pcodeop vmpywehRndSat; @@ -15574,7 +16245,7 @@ define pcodeop vmpywehRndSat; # (v2,14) vmpyweh -- "Rdd32 = vmpyweh ( Rss32 , Rtt32 ) :sat" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 1 1 1 0 1 0 0 0 0 0 0 s s s s s P P + t t t t t 1 0 1 d d d d d +# 1 1 1 0 1 0 0 0 0 0 0 s s s s s P P 0 t t t t t 1 0 1 d d d d d define pcodeop vmpywehSat; @@ -15586,7 +16257,7 @@ define pcodeop vmpywehSat; # (v2,14) vmpyweh -- "Rxx32 += vmpyweh ( Rss32 , Rtt32 ) :<<1 :rnd :sat" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 1 1 1 0 1 0 1 0 1 0 1 s s s s s P P + t t t t t 1 0 1 x x x x x +# 1 1 1 0 1 0 1 0 1 0 1 s s s s s P P 0 t t t t t 1 0 1 x x x x x define pcodeop vmpywehX2RndSatAdd; @@ -15598,7 +16269,7 @@ define pcodeop vmpywehX2RndSatAdd; # (v2,14) vmpyweh -- "Rxx32 += vmpyweh ( Rss32 , Rtt32 ) :<<1 :sat" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 1 1 1 0 1 0 1 0 1 0 0 s s s s s P P + t t t t t 1 0 1 x x x x x +# 1 1 1 0 1 0 1 0 1 0 0 s s s s s P P 0 t t t t t 1 0 1 x x x x x define pcodeop vmpywehX2SatAdd; @@ -15610,7 +16281,7 @@ define pcodeop vmpywehX2SatAdd; # (v2,14) vmpyweh -- "Rxx32 += vmpyweh ( Rss32 , Rtt32 ) :rnd :sat" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 1 1 1 0 1 0 1 0 0 0 1 s s s s s P P + t t t t t 1 0 1 x x x x x +# 1 1 1 0 1 0 1 0 0 0 1 s s s s s P P 0 t t t t t 1 0 1 x x x x x define pcodeop vmpywehRndSatAdd; @@ -15622,7 +16293,7 @@ define pcodeop vmpywehRndSatAdd; # (v2,14) vmpyweh -- "Rxx32 += vmpyweh ( Rss32 , Rtt32 ) :sat" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 1 1 1 0 1 0 1 0 0 0 0 s s s s s P P + t t t t t 1 0 1 x x x x x +# 1 1 1 0 1 0 1 0 0 0 0 s s s s s P P 0 t t t t t 1 0 1 x x x x x define pcodeop vmpywehSatAdd; @@ -15634,7 +16305,7 @@ define pcodeop vmpywehSatAdd; # (v2,14) vmpyweuh -- "Rdd32 = vmpyweuh ( Rss32 , Rtt32 ) :<<1 :rnd :sat" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 1 1 1 0 1 0 0 0 1 1 1 s s s s s P P + t t t t t 1 0 1 d d d d d +# 1 1 1 0 1 0 0 0 1 1 1 s s s s s P P 0 t t t t t 1 0 1 d d d d d define pcodeop vmpyweuhX2RndSat; @@ -15646,7 +16317,7 @@ define pcodeop vmpyweuhX2RndSat; # (v2,14) vmpyweuh -- "Rdd32 = vmpyweuh ( Rss32 , Rtt32 ) :<<1 :sat" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 1 1 1 0 1 0 0 0 1 1 0 s s s s s P P + t t t t t 1 0 1 d d d d d +# 1 1 1 0 1 0 0 0 1 1 0 s s s s s P P 0 t t t t t 1 0 1 d d d d d define pcodeop vmpyweuhX2Sat; @@ -15658,7 +16329,7 @@ define pcodeop vmpyweuhX2Sat; # (v2,14) vmpyweuh -- "Rdd32 = vmpyweuh ( Rss32 , Rtt32 ) :rnd :sat" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 1 1 1 0 1 0 0 0 0 1 1 s s s s s P P + t t t t t 1 0 1 d d d d d +# 1 1 1 0 1 0 0 0 0 1 1 s s s s s P P 0 t t t t t 1 0 1 d d d d d define pcodeop vmpyweuhRndSat; @@ -15670,7 +16341,7 @@ define pcodeop vmpyweuhRndSat; # (v2,14) vmpyweuh -- "Rdd32 = vmpyweuh ( Rss32 , Rtt32 ) :sat" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 1 1 1 0 1 0 0 0 0 1 0 s s s s s P P + t t t t t 1 0 1 d d d d d +# 1 1 1 0 1 0 0 0 0 1 0 s s s s s P P 0 t t t t t 1 0 1 d d d d d define pcodeop vmpyweuhSat; @@ -15682,7 +16353,7 @@ define pcodeop vmpyweuhSat; # (v2,14) vmpyweuh -- "Rxx32 += vmpyweuh ( Rss32 , Rtt32 ) :<<1 :rnd :sat" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 1 1 1 0 1 0 1 0 1 1 1 s s s s s P P + t t t t t 1 0 1 x x x x x +# 1 1 1 0 1 0 1 0 1 1 1 s s s s s P P 0 t t t t t 1 0 1 x x x x x define pcodeop vmpyweuhX2RndSatAdd; @@ -15694,7 +16365,7 @@ define pcodeop vmpyweuhX2RndSatAdd; # (v2,14) vmpyweuh -- "Rxx32 += vmpyweuh ( Rss32 , Rtt32 ) :<<1 :sat" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 1 1 1 0 1 0 1 0 1 1 0 s s s s s P P + t t t t t 1 0 1 x x x x x +# 1 1 1 0 1 0 1 0 1 1 0 s s s s s P P 0 t t t t t 1 0 1 x x x x x define pcodeop vmpyweuhX2SatAdd; @@ -15706,7 +16377,7 @@ define pcodeop vmpyweuhX2SatAdd; # (v2,14) vmpyweuh -- "Rxx32 += vmpyweuh ( Rss32 , Rtt32 ) :rnd :sat" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 1 1 1 0 1 0 1 0 0 1 1 s s s s s P P + t t t t t 1 0 1 x x x x x +# 1 1 1 0 1 0 1 0 0 1 1 s s s s s P P 0 t t t t t 1 0 1 x x x x x define pcodeop vmpyweuhRndSatAdd; @@ -15718,7 +16389,7 @@ define pcodeop vmpyweuhRndSatAdd; # (v2,14) vmpyweuh -- "Rxx32 += vmpyweuh ( Rss32 , Rtt32 ) :sat" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 1 1 1 0 1 0 1 0 0 1 0 s s s s s P P + t t t t t 1 0 1 x x x x x +# 1 1 1 0 1 0 1 0 0 1 0 s s s s s P P 0 t t t t t 1 0 1 x x x x x define pcodeop vmpyweuhSatAdd; @@ -15730,7 +16401,7 @@ define pcodeop vmpyweuhSatAdd; # (v2,14) vmpywoh -- "Rdd32 = vmpywoh ( Rss32 , Rtt32 ) :<<1 :rnd :sat" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 1 1 1 0 1 0 0 0 1 0 1 s s s s s P P + t t t t t 1 1 1 d d d d d +# 1 1 1 0 1 0 0 0 1 0 1 s s s s s P P 0 t t t t t 1 1 1 d d d d d define pcodeop vmpywohX2RndSat; @@ -15742,7 +16413,7 @@ define pcodeop vmpywohX2RndSat; # (v2,14) vmpywoh -- "Rdd32 = vmpywoh ( Rss32 , Rtt32 ) :<<1 :sat" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 1 1 1 0 1 0 0 0 1 0 0 s s s s s P P + t t t t t 1 1 1 d d d d d +# 1 1 1 0 1 0 0 0 1 0 0 s s s s s P P 0 t t t t t 1 1 1 d d d d d define pcodeop vmpywohX2Sat; @@ -15754,7 +16425,7 @@ define pcodeop vmpywohX2Sat; # (v2,14) vmpywoh -- "Rdd32 = vmpywoh ( Rss32 , Rtt32 ) :rnd :sat" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 1 1 1 0 1 0 0 0 0 0 1 s s s s s P P + t t t t t 1 1 1 d d d d d +# 1 1 1 0 1 0 0 0 0 0 1 s s s s s P P 0 t t t t t 1 1 1 d d d d d define pcodeop vmpywohRndSat; @@ -15766,7 +16437,7 @@ define pcodeop vmpywohRndSat; # (v2,14) vmpywoh -- "Rdd32 = vmpywoh ( Rss32 , Rtt32 ) :sat" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 1 1 1 0 1 0 0 0 0 0 0 s s s s s P P + t t t t t 1 1 1 d d d d d +# 1 1 1 0 1 0 0 0 0 0 0 s s s s s P P 0 t t t t t 1 1 1 d d d d d define pcodeop vmpywohSat; @@ -15778,7 +16449,7 @@ define pcodeop vmpywohSat; # (v2,14) vmpywoh -- "Rxx32 += vmpywoh ( Rss32 , Rtt32 ) :<<1 :rnd :sat" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 1 1 1 0 1 0 1 0 1 0 1 s s s s s P P + t t t t t 1 1 1 x x x x x +# 1 1 1 0 1 0 1 0 1 0 1 s s s s s P P 0 t t t t t 1 1 1 x x x x x define pcodeop vmpywohX2RndSatAdd; @@ -15790,7 +16461,7 @@ define pcodeop vmpywohX2RndSatAdd; # (v2,14) vmpywoh -- "Rxx32 += vmpywoh ( Rss32 , Rtt32 ) :<<1 :sat" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 1 1 1 0 1 0 1 0 1 0 0 s s s s s P P + t t t t t 1 1 1 x x x x x +# 1 1 1 0 1 0 1 0 1 0 0 s s s s s P P 0 t t t t t 1 1 1 x x x x x define pcodeop vmpywohX2SatAdd; @@ -15802,7 +16473,7 @@ define pcodeop vmpywohX2SatAdd; # (v2,14) vmpywoh -- "Rxx32 += vmpywoh ( Rss32 , Rtt32 ) :rnd :sat" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 1 1 1 0 1 0 1 0 0 0 1 s s s s s P P + t t t t t 1 1 1 x x x x x +# 1 1 1 0 1 0 1 0 0 0 1 s s s s s P P 0 t t t t t 1 1 1 x x x x x define pcodeop vmpywohRndSatAdd; @@ -15814,7 +16485,7 @@ define pcodeop vmpywohRndSatAdd; # (v2,14) vmpywoh -- "Rxx32 += vmpywoh ( Rss32 , Rtt32 ) :sat" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 1 1 1 0 1 0 1 0 0 0 0 s s s s s P P + t t t t t 1 1 1 x x x x x +# 1 1 1 0 1 0 1 0 0 0 0 s s s s s P P 0 t t t t t 1 1 1 x x x x x define pcodeop vmpywohSatAdd; @@ -15826,75 +16497,107 @@ define pcodeop vmpywohSatAdd; # (v2,14) vmpywouh -- "Rdd32 = vmpywouh ( Rss32 , Rtt32 ) :<<1 :rnd :sat" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 1 1 1 0 1 0 0 0 1 1 1 s s s s s P P + t t t t t 1 1 1 d d d d d +# 1 1 1 0 1 0 0 0 1 1 1 s s s s s P P 0 t t t t t 1 1 1 d d d d d + +define pcodeop vmpywouhX2RndSat; -:vmpywouh":<<1:rnd:sat" Rdd5,rss5,rtt5 EndPacket is iclass=14 & op2127=0x47 & op13=0 & op0507=7 & Rdd5 & rtt5 & rss5 & $(END_PACKET) -unimpl +:vmpywouh":<<1:rnd:sat" Rdd5,rss5,rtt5 EndPacket is iclass=14 & op2127=0x47 & op13=0 & op0507=7 & Rdd5 & rtt5 & rss5 & $(END_PACKET) { + Rdd5 = vmpywouhX2RndSat(rss5, rtt5); + build EndPacket; +} # (v2,14) vmpywouh -- "Rdd32 = vmpywouh ( Rss32 , Rtt32 ) :<<1 :sat" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 1 1 1 0 1 0 0 0 1 1 0 s s s s s P P + t t t t t 1 1 1 d d d d d +# 1 1 1 0 1 0 0 0 1 1 0 s s s s s P P 0 t t t t t 1 1 1 d d d d d -:vmpywouh":<<1:sat" Rdd5,rss5,rtt5 EndPacket is iclass=14 & op2127=0x46 & op13=0 & op0507=7 & Rdd5 & rtt5 & rss5 & $(END_PACKET) -unimpl +define pcodeop vmpywouhX2Sat; + +:vmpywouh":<<1:sat" Rdd5,rss5,rtt5 EndPacket is iclass=14 & op2127=0x46 & op13=0 & op0507=7 & Rdd5 & rtt5 & rss5 & $(END_PACKET) { + Rdd5 = vmpywouhX2Sat(rss5, rtt5); + build EndPacket; +} # (v2,14) vmpywouh -- "Rdd32 = vmpywouh ( Rss32 , Rtt32 ) :rnd :sat" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 1 1 1 0 1 0 0 0 0 1 1 s s s s s P P + t t t t t 1 1 1 d d d d d +# 1 1 1 0 1 0 0 0 0 1 1 s s s s s P P 0 t t t t t 1 1 1 d d d d d + +define pcodeop vmpywouhRndSat; -:vmpywouh":rnd:sat" Rdd5,rss5,rtt5 EndPacket is iclass=14 & op2127=0x43 & op13=0 & op0507=7 & Rdd5 & rtt5 & rss5 & $(END_PACKET) -unimpl +:vmpywouh":rnd:sat" Rdd5,rss5,rtt5 EndPacket is iclass=14 & op2127=0x43 & op13=0 & op0507=7 & Rdd5 & rtt5 & rss5 & $(END_PACKET) { + Rdd5 = vmpywouhRndSat(rss5, rtt5); + build EndPacket; +} # (v2,14) vmpywouh -- "Rdd32 = vmpywouh ( Rss32 , Rtt32 ) :sat" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 1 1 1 0 1 0 0 0 0 1 0 s s s s s P P + t t t t t 1 1 1 d d d d d +# 1 1 1 0 1 0 0 0 0 1 0 s s s s s P P 0 t t t t t 1 1 1 d d d d d -:vmpywouh":sat" Rdd5,rss5,rtt5 EndPacket is iclass=14 & op2127=0x42 & op13=0 & op0507=7 & Rdd5 & rtt5 & rss5 & $(END_PACKET) -unimpl +define pcodeop vmpywouhSat; + +:vmpywouh":sat" Rdd5,rss5,rtt5 EndPacket is iclass=14 & op2127=0x42 & op13=0 & op0507=7 & Rdd5 & rtt5 & rss5 & $(END_PACKET) { + Rdd5 = vmpywouhSat(rss5, rtt5); + build EndPacket; +} # (v2,14) vmpywouh -- "Rxx32 += vmpywouh ( Rss32 , Rtt32 ) :<<1 :rnd :sat" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 1 1 1 0 1 0 1 0 1 1 1 s s s s s P P + t t t t t 1 1 1 x x x x x +# 1 1 1 0 1 0 1 0 1 1 1 s s s s s P P 0 t t t t t 1 1 1 x x x x x -:vmpywouh+=":<<1:rnd:sat" Rdd5,rss5,rtt5 EndPacket is iclass=14 & op2127=0x57 & op13=0 & op0507=7 & Rdd5 & rtt5 & rss5 & $(END_PACKET) -unimpl +define pcodeop vmpywouhX2RndSatAcc; + +:vmpywouh+=":<<1:rnd:sat" Rdd5,rss5,rtt5 EndPacket is iclass=14 & op2127=0x57 & op13=0 & op0507=7 & Rdd5 & rdd5 & rtt5 & rss5 & $(END_PACKET) { + Rdd5 = vmpywouhX2RndSatAcc(rss5, rtt5, rdd5); + build EndPacket; +} # (v2,14) vmpywouh -- "Rxx32 += vmpywouh ( Rss32 , Rtt32 ) :<<1 :sat" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 1 1 1 0 1 0 1 0 1 1 0 s s s s s P P + t t t t t 1 1 1 x x x x x +# 1 1 1 0 1 0 1 0 1 1 0 s s s s s P P 0 t t t t t 1 1 1 x x x x x -:vmpywouh+=":<<1:sat" Rdd5,rss5,rtt5 EndPacket is iclass=14 & op2127=0x56 & op13=0 & op0507=7 & Rdd5 & rtt5 & rss5 & $(END_PACKET) -unimpl +define pcodeop vmpywouhX2SatAcc; + +:vmpywouh+=":<<1:sat" Rdd5,rss5,rtt5 EndPacket is iclass=14 & op2127=0x56 & op13=0 & op0507=7 & Rdd5 & rdd5 & rtt5 & rss5 & $(END_PACKET) { + Rdd5 = vmpywouhX2SatAcc(rss5, rtt5, rdd5); + build EndPacket; +} # (v2,14) vmpywouh -- "Rxx32 += vmpywouh ( Rss32 , Rtt32 ) :rnd :sat" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 1 1 1 0 1 0 1 0 0 1 1 s s s s s P P - t t t t t 1 1 1 x x x x x +# 1 1 1 0 1 0 1 0 0 1 1 s s s s s P P 0 t t t t t 1 1 1 x x x x x + +define pcodeop vmpywouhRndSatAcc; -:vmpywouh+=":rnd:sat" Rdd5,rss5,rtt5 EndPacket is iclass=14 & op2127=0x53 & op13=0 & op0507=7 & Rdd5 & rtt5 & rss5 & $(END_PACKET) -unimpl +:vmpywouh+=":rnd:sat" Rdd5,rss5,rtt5 EndPacket is iclass=14 & op2127=0x53 & op13=0 & op0507=7 & Rdd5 & rdd5 & rtt5 & rss5 & $(END_PACKET) { + Rdd5 = vmpywouhRndSatAcc(rss5, rtt5, rdd5); + build EndPacket; +} # (v2,14) vmpywouh -- "Rxx32 += vmpywouh ( Rss32 , Rtt32 ) :sat" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 1 1 1 0 1 0 1 0 0 1 0 s s s s s P P + t t t t t 1 1 1 x x x x x +# 1 1 1 0 1 0 1 0 0 1 0 s s s s s P P 0 t t t t t 1 1 1 x x x x x + +define pcodeop vmpywouhSatAcc; -:vmpywouh+=":sat" Rdd5,rss5,rtt5 EndPacket is iclass=14 & op2127=0x52 & op13=0 & op0507=7 & Rdd5 & rtt5 & rss5 & $(END_PACKET) -unimpl +:vmpywouh+=":sat" Rdd5,rss5,rtt5 EndPacket is iclass=14 & op2127=0x52 & op13=0 & op0507=7 & Rdd5 & rdd5 & rtt5 & rss5 & $(END_PACKET) { + Rdd5 = vmpywouhSatAcc(rss5, rtt5, rdd5); + build EndPacket; +} # (v2,13) vmux -- "Rdd32 = vmux ( Pu4 , Rss32 , Rtt32 )" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 1 1 0 1 0 0 0 1 + + + s s s s s P P + t t t t t + u u d d d d d +# 1 1 0 1 0 0 0 1 - - - s s s s s P P - t t t t t - u u d d d d d define pcodeop vmux; -:vmux Rdd5,pu0506,rss5,rtt5 EndPacket is iclass=13 & op2127=0x08 & op13=0 & op7=0 & Rdd5 & rss5 & rtt5 & pu0506 & $(END_PACKET) { +:vmux Rdd5,pu0506,rss5,rtt5 EndPacket is iclass=13 & op2427=0x1 & Rdd5 & rss5 & rtt5 & pu0506 & $(END_PACKET) { Rdd5 = vmux(pu0506,rss5,rtt5); build EndPacket; } @@ -15902,9 +16605,9 @@ define pcodeop vmux; # (v2,15) vnavgh -- "Rd32 = vnavgh ( Rt32 , Rs32 )" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 1 1 1 1 0 1 1 1 + 1 1 s s s s s P P + t t t t t + + + d d d d d +# 1 1 1 1 0 1 1 1 - 1 1 s s s s s P P - t t t t t - - - d d d d d -:vnavgh Rd5,rt5,rs5 EndPacket is iclass=15 & op2127=0x3b & op13=0 & op0507=0 & Rd5 & rt5 & rs5 & $(END_PACKET) +:vnavgh Rd5,rt5,rs5 EndPacket is iclass=15 & op2427=0x7 & op2122=0x3 & Rd5 & rt5 & rs5 & $(END_PACKET) { Rd5[0,16] = (rt5[0,16] - rs5[0,16]) >> 1; Rd5[16,16] = (rt5[16,16] - rs5[16,16]) >> 1; @@ -15914,9 +16617,9 @@ define pcodeop vmux; # (v2,13) vnavgh -- "Rdd32 = vnavgh ( Rtt32 , Rss32 )" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 1 1 0 1 0 0 1 1 1 0 0 s s s s s P P + t t t t t 0 0 0 d d d d d +# 1 1 0 1 0 0 1 1 1 0 0 s s s s s P P - t t t t t 0 0 0 d d d d d -:vnavgh Rdd5,rtt5,rss5 EndPacket is iclass=13 & op2127=0x1c & op13=0 & op0507=0 & Rdd5 & rtt5 & rss5 & $(END_PACKET) +:vnavgh Rdd5,rtt5,rss5 EndPacket is iclass=13 & op2127=0x1c & op0507=0 & Rdd5 & rtt5 & rss5 & $(END_PACKET) { Rdd5[0,16] = (rtt5[0,16] - rss5[0,16]) >> 1; Rdd5[16,16] = (rtt5[16,16] - rss5[16,16]) >> 1; @@ -15928,11 +16631,11 @@ define pcodeop vmux; # (v2,13) vnavgh -- "Rdd32 = vnavgh ( Rtt32 , Rss32 ) :crnd :sat" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 1 1 0 1 0 0 1 1 1 0 0 s s s s s P P + t t t t t 0 1 0 d d d d d +# 1 1 0 1 0 0 1 1 1 0 0 s s s s s P P - t t t t t 0 1 0 d d d d d define pcodeop vnavghCrndSat; -:vnavgh":crnd:sat" Rdd5,rtt5,rss5 EndPacket is iclass=13 & op2127=0x1c & op13=0 & op0507=2 & Rdd5 & rtt5 & rss5 & $(END_PACKET) { +:vnavgh":crnd:sat" Rdd5,rtt5,rss5 EndPacket is iclass=13 & op2127=0x1c & op0507=2 & Rdd5 & rtt5 & rss5 & $(END_PACKET) { Rdd5 = vnavghCrndSat(rtt5, rss5); build EndPacket; } @@ -15940,11 +16643,11 @@ define pcodeop vnavghCrndSat; # (v2,13) vnavgh -- "Rdd32 = vnavgh ( Rtt32 , Rss32 ) :rnd :sat" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 1 1 0 1 0 0 1 1 1 0 0 s s s s s P P + t t t t t 0 0 1 d d d d d +# 1 1 0 1 0 0 1 1 1 0 0 s s s s s P P - t t t t t 0 0 1 d d d d d define pcodeop vnavghRndSat; -:vnavgh":rnd:sat" Rdd5,rtt5,rss5 EndPacket is iclass=13 & op2127=0x1c & op13=0 & op0507=1 & Rdd5 & rtt5 & rss5 & $(END_PACKET) { +:vnavgh":rnd:sat" Rdd5,rtt5,rss5 EndPacket is iclass=13 & op2127=0x1c & op0507=1 & Rdd5 & rtt5 & rss5 & $(END_PACKET) { Rdd5 = vnavghRndSat(rtt5, rss5); build EndPacket; } @@ -15952,9 +16655,9 @@ define pcodeop vnavghRndSat; # (v2,13) vnavgw -- "Rdd32 = vnavgw ( Rtt32 , Rss32 )" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 1 1 0 1 0 0 1 1 1 0 0 s s s s s P P + t t t t t 0 1 1 d d d d d +# 1 1 0 1 0 0 1 1 1 0 0 s s s s s P P - t t t t t 0 1 1 d d d d d -:vnavgw Rdd5,rtt5,rss5 EndPacket is iclass=13 & op2127=0x1c & op13=0 & op0507=3 & Rdd5 & rtt5 & rss5 & $(END_PACKET) +:vnavgw Rdd5,rtt5,rss5 EndPacket is iclass=13 & op2127=0x1c & op0507=3 & Rdd5 & rtt5 & rss5 & $(END_PACKET) { Rdd5[0,32] = (rtt5[0,32] - rss5[0,32]) >> 1; Rdd5[32,32] = (rtt5[32,32] - rss5[32,32]) >> 1; @@ -15964,11 +16667,11 @@ define pcodeop vnavghRndSat; # (v2,13) vnavgw -- "Rdd32 = vnavgw ( Rtt32 , Rss32 ) :crnd :sat" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 1 1 0 1 0 0 1 1 1 0 0 s s s s s P P + t t t t t 1 1 + d d d d d +# 1 1 0 1 0 0 1 1 1 0 0 s s s s s P P - t t t t t 1 1 - d d d d d define pcodeop vnavgwCrndSat; -:vnavgw":crnd:sat" Rdd5,rtt5,rss5 EndPacket is iclass=13 & op2127=0x1c & op13=0 & op0507=6 & Rdd5 & rtt5 & rss5 & $(END_PACKET) { +:vnavgw":crnd:sat" Rdd5,rtt5,rss5 EndPacket is iclass=13 & op2127=0x1c & op0607=3 & Rdd5 & rtt5 & rss5 & $(END_PACKET) { Rdd5 = vnavgwCrndSat(rtt5, rss5); build EndPacket; } @@ -15976,11 +16679,11 @@ define pcodeop vnavgwCrndSat; # (v2,13) vnavgw -- "Rdd32 = vnavgw ( Rtt32 , Rss32 ) :rnd :sat" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 1 1 0 1 0 0 1 1 1 0 0 s s s s s P P + t t t t t 1 0 + d d d d d +# 1 1 0 1 0 0 1 1 1 0 0 s s s s s P P - t t t t t 1 0 - d d d d d define pcodeop vnavgwRndSat; -:vnavgw":rnd:sat" Rdd5,rtt5,rss5 EndPacket is iclass=13 & op2127=0x1c & op13=0 & op0507=4 & Rdd5 & rtt5 & rss5 & $(END_PACKET) { +:vnavgw":rnd:sat" Rdd5,rtt5,rss5 EndPacket is iclass=13 & op2127=0x1c & op0607=2 & Rdd5 & rtt5 & rss5 & $(END_PACKET) { Rdd5 = vnavgwRndSat(rtt5, rss5); build EndPacket; } @@ -15988,25 +16691,33 @@ define pcodeop vnavgwRndSat; # (v4,14) vpmpyh -- "Rdd32 = vpmpyh ( Rs32 , Rt32 )" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 1 1 1 0 0 1 0 1 1 1 0 s s s s s P P + t t t t t 1 1 1 d d d d d +# 1 1 1 0 0 1 0 1 1 1 0 s s s s s P P 0 t t t t t 1 1 1 d d d d d -:vpmpyh Rdd5,rs5,rt5 EndPacket is iclass=14 & op2127=0x2e & op13=0 & op0507=7 & Rdd5 & rt5 & rs5 & $(END_PACKET) -unimpl +define pcodeop vpmpyh; + +:vpmpyh Rdd5,rs5,rt5 EndPacket is iclass=14 & op2127=0x2e & op13=0 & op0507=7 & Rdd5 & rt5 & rs5 & $(END_PACKET) { + Rdd5 = vpmpyh(rs5, rt5); + build EndPacket; +} # (v4,14) vpmpyh -- "Rxx32 ^= vpmpyh ( Rs32 , Rt32 )" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 1 1 1 0 0 1 1 1 1 0 1 s s s s s P P + t t t t t 1 1 1 x x x x x +# 1 1 1 0 0 1 1 1 1 0 1 s s s s s P P 0 t t t t t 1 1 1 x x x x x -:vpmpyh"^=" Rdd5,rs5,rt5 EndPacket is iclass=14 & op2127=0x3d & op13=0 & op0507=7 & Rdd5 & rt5 & rs5 & $(END_PACKET) -unimpl +define pcodeop vpmpyhXorAcc; + +:vpmpyh"^=" Rdd5,rs5,rt5 EndPacket is iclass=14 & op2127=0x3d & op13=0 & op0507=7 & Rdd5 & rdd5 & rt5 & rs5 & $(END_PACKET) { + Rdd5 = vpmpyhXorAcc(rs5, rt5, rdd5); + build EndPacket; +} # (v4,14) vraddh -- "Rd32 = vraddh ( Rss32 , Rtt32 )" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 1 1 1 0 1 0 0 1 0 + 1 s s s s s P P + t t t t t 1 1 1 d d d d d +# 1 1 1 0 1 0 0 1 0 - 1 s s s s s P P 0 t t t t t 1 1 1 d d d d d -:vraddh Rd5,rss5,rtt5 EndPacket is iclass=14 & op2127=0x49 & op13=0 & op0507=7 & Rd5 & rtt5 & rss5 & $(END_PACKET) { +:vraddh Rd5,rss5,rtt5 EndPacket is iclass=14 & op2327=0x12 & op21=0x1 & op13=0 & op0507=7 & Rd5 & rtt5 & rss5 & $(END_PACKET) { tmp:4 = sext(rss5[0,16]); tmp = tmp + sext(rss5[16,16]); tmp = tmp + sext(rss5[32,16]); @@ -16022,31 +16733,43 @@ unimpl # (v2,14) vraddub -- "Rdd32 = vraddub ( Rss32 , Rtt32 )" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 1 1 1 0 1 0 0 0 0 1 0 s s s s s P P + t t t t t 0 0 1 d d d d d +# 1 1 1 0 1 0 0 0 0 1 0 s s s s s P P 0 t t t t t 0 0 1 d d d d d -:vraddub Rdd5,rss5,rtt5 EndPacket is iclass=14 & op2127=0x42 & op13=0 & op0507=1 & Rdd5 & rtt5 & rss5 & $(END_PACKET) -unimpl +define pcodeop vraddub; + +:vraddub Rdd5,rss5,rtt5 EndPacket is iclass=14 & op2127=0x42 & op13=0 & op0507=1 & Rdd5 & rtt5 & rss5 & $(END_PACKET) { + Rdd5 = vraddub(rss5, rtt5); + build EndPacket; +} # (v2,14) vraddub -- "Rxx32 += vraddub ( Rss32 , Rtt32 )" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 1 1 1 0 1 0 1 0 0 1 0 s s s s s P P + t t t t t 0 0 1 x x x x x +# 1 1 1 0 1 0 1 0 0 1 0 s s s s s P P 0 t t t t t 0 0 1 x x x x x + +define pcodeop vraddubAcc; -:vraddub+= Rdd5,rss5,rtt5 EndPacket is iclass=14 & op2127=0x52 & op13=0 & op0507=1 & Rdd5 & rtt5 & rss5 & $(END_PACKET) -unimpl +:vraddub+= Rdd5,rss5,rtt5 EndPacket is iclass=14 & op2127=0x52 & op13=0 & op0507=1 & Rdd5 & rdd5 & rtt5 & rss5 & $(END_PACKET) { + Rdd5 = vraddubAcc(rss5, rtt5, rdd5); + build EndPacket; +} # (v4,14) vradduh -- "Rd32 = vradduh ( Rss32 , Rtt32 )" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 1 1 1 0 1 0 0 1 0 + + s s s s s P P + t t t t t + 0 1 d d d d d +# 1 1 1 0 1 0 0 1 0 - - s s s s s P P 0 t t t t t - 0 1 d d d d d -:vradduh Rd5,rss5,rtt5 EndPacket is iclass=14 & op2127=0x48 & op13=0 & op0507=1 & Rd5 & rtt5 & rss5 & $(END_PACKET) -unimpl +define pcodeop vradduh; + +:vradduh Rd5,rss5,rtt5 EndPacket is iclass=14 & op2327=0x12 & op13=0 & op0506=1 & Rd5 & rtt5 & rss5 & $(END_PACKET) { + Rd5 = vradduh(rss5, rtt5); + build EndPacket; +} # (v2,14) vrcmpyi -- "Rdd32 = vrcmpyi ( Rss32 , Rtt32 )" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 1 1 1 0 1 0 0 0 0 0 0 s s s s s P P + t t t t t 0 0 0 d d d d d +# 1 1 1 0 1 0 0 0 0 0 0 s s s s s P P 0 t t t t t 0 0 0 d d d d d define pcodeop vrcmpyi; @@ -16058,7 +16781,7 @@ define pcodeop vrcmpyi; # (v2,14) vrcmpyi -- "Rdd32 = vrcmpyi ( Rss32 , Rtt32 * )" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 1 1 1 0 1 0 0 0 0 1 0 s s s s s P P + t t t t t 0 0 0 d d d d d +# 1 1 1 0 1 0 0 0 0 1 0 s s s s s P P 0 t t t t t 0 0 0 d d d d d :vrcmpyi Rdd5,rss5,Rtt5Conjugate EndPacket is iclass=14 & op2127=0x42 & op13=0 & op0507=0 & Rdd5 & Rtt5Conjugate & rss5 & $(END_PACKET) { Rdd5 = vrcmpyi(rss5, Rtt5Conjugate); @@ -16068,7 +16791,7 @@ define pcodeop vrcmpyi; # (v2,14) vrcmpyi -- "Rxx32 += vrcmpyi ( Rss32 , Rtt32 )" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 1 1 1 0 1 0 1 0 0 0 0 s s s s s P P + t t t t t 0 0 0 x x x x x +# 1 1 1 0 1 0 1 0 0 0 0 s s s s s P P 0 t t t t t 0 0 0 x x x x x define pcodeop vrcmpyiAdd; @@ -16080,7 +16803,7 @@ define pcodeop vrcmpyiAdd; # (v2,14) vrcmpyi -- "Rxx32 += vrcmpyi ( Rss32 , Rtt32 * )" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 1 1 1 0 1 0 1 0 0 1 0 s s s s s P P + t t t t t 0 0 0 x x x x x +# 1 1 1 0 1 0 1 0 0 1 0 s s s s s P P 0 t t t t t 0 0 0 x x x x x :vrcmpyi+= Rdd5,rss5,Rtt5Conjugate EndPacket is iclass=14 & op2127=0x52 & op13=0 & op0507=0 & rdd5 & Rdd5 & Rtt5Conjugate & rss5 & $(END_PACKET) { Rdd5 = vrcmpyiAdd(rss5, Rtt5Conjugate, rdd5); @@ -16090,7 +16813,7 @@ define pcodeop vrcmpyiAdd; # (v2,14) vrcmpyr -- "Rdd32 = vrcmpyr ( Rss32 , Rtt32 )" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 1 1 1 0 1 0 0 0 0 0 0 s s s s s P P + t t t t t 0 0 1 d d d d d +# 1 1 1 0 1 0 0 0 0 0 0 s s s s s P P 0 t t t t t 0 0 1 d d d d d define pcodeop vrcmpyr; @@ -16102,7 +16825,7 @@ define pcodeop vrcmpyr; # (v2,14) vrcmpyr -- "Rdd32 = vrcmpyr ( Rss32 , Rtt32 * )" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 1 1 1 0 1 0 0 0 0 1 1 s s s s s P P + t t t t t 0 0 1 d d d d d +# 1 1 1 0 1 0 0 0 0 1 1 s s s s s P P 0 t t t t t 0 0 1 d d d d d :vrcmpyr Rdd5,rss5,Rtt5Conjugate EndPacket is iclass=14 & op2127=0x43 & op13=0 & op0507=1 & Rdd5 & Rtt5Conjugate & rss5 & $(END_PACKET) { Rdd5 = vrcmpyr(rss5, Rtt5Conjugate); @@ -16112,7 +16835,7 @@ define pcodeop vrcmpyr; # (v2,14) vrcmpyr -- "Rxx32 += vrcmpyr ( Rss32 , Rtt32 )" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 1 1 1 0 1 0 1 0 0 0 0 s s s s s P P + t t t t t 0 0 1 x x x x x +# 1 1 1 0 1 0 1 0 0 0 0 s s s s s P P 0 t t t t t 0 0 1 x x x x x define pcodeop vrcmpyrAdd; @@ -16124,7 +16847,7 @@ define pcodeop vrcmpyrAdd; # (v2,14) vrcmpyr -- "Rxx32 += vrcmpyr ( Rss32 , Rtt32 * )" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 1 1 1 0 1 0 1 0 0 1 1 s s s s s P P + t t t t t 0 0 1 x x x x x +# 1 1 1 0 1 0 1 0 0 1 1 s s s s s P P 0 t t t t t 0 0 1 x x x x x :vrcmpyr+= Rdd5,rss5,Rtt5Conjugate EndPacket is iclass=14 & op2127=0x53 & op13=0 & op0507=1 & rdd5 & Rdd5 & Rtt5Conjugate & rss5 & $(END_PACKET) { Rdd5 = vrcmpyrAdd(rss5, Rtt5Conjugate, rdd5); @@ -16134,175 +16857,259 @@ define pcodeop vrcmpyrAdd; # (v4,14) vrcmpys -- "Rd32 = vrcmpys ( Rss32 , Rtt32 ) :<<1 :rnd :sat :raw :hi" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 1 1 1 0 1 0 0 1 1 + 1 s s s s s P P + t t t t t 1 1 0 d d d d d +# 1 1 1 0 1 0 0 1 1 - 1 s s s s s P P 0 t t t t t 1 1 0 d d d d d -:vrcmpys":<<1:rnd:sat:raw:hi" Rd5,rss5,rtt5 EndPacket is iclass=14 & op2127=0x4d & op13=0 & op0507=6 & Rd5 & rtt5 & rss5 & $(END_PACKET) -unimpl +define pcodeop vrcmpysX2RndSatHi; + +:vrcmpys":<<1:rnd:sat:raw:hi" Rd5,rss5,rtt5 EndPacket is iclass=14 & op2327=0x13 & op21=0x1 & op13=0 & op0507=6 & Rd5 & rtt5 & rss5 & $(END_PACKET) { + Rd5 = vrcmpysX2RndSatHi(rss5, rtt5); + build EndPacket; +} # (v4,14) vrcmpys -- "Rd32 = vrcmpys ( Rss32 , Rtt32 ) :<<1 :rnd :sat :raw :lo" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 1 1 1 0 1 0 0 1 1 + 1 s s s s s P P + t t t t t 1 1 1 d d d d d +# 1 1 1 0 1 0 0 1 1 - 1 s s s s s P P 0 t t t t t 1 1 1 d d d d d + +define pcodeop vrcmpysX2RndSatLo; -:vrcmpys":<<1:rnd:sat:raw:lo" Rd5,rss5,rtt5 EndPacket is iclass=14 & op2127=0x4d & op13=0 & op0507=7 & Rd5 & rtt5 & rss5 & $(END_PACKET) -unimpl +:vrcmpys":<<1:rnd:sat:raw:lo" Rd5,rss5,rtt5 EndPacket is iclass=14 & op2327=0x13 & op21=0x1 & op13=0 & op0507=7 & Rd5 & rtt5 & rss5 & $(END_PACKET) { + Rd5 = vrcmpysX2RndSatLo(rss5, rtt5); + build EndPacket; +} # (v4,14) vrcmpys -- "Rdd32 = vrcmpys ( Rss32 , Rtt32 ) :<<1 :sat :raw :hi" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 1 1 1 0 1 0 0 0 1 0 1 s s s s s P P + t t t t t 1 0 0 d d d d d +# 1 1 1 0 1 0 0 0 1 0 1 s s s s s P P 0 t t t t t 1 0 0 d d d d d -:vrcmpys":<<1:sat:raw:hi" Rdd5,rss5,rtt5 EndPacket is iclass=14 & op2127=0x45 & op13=0 & op0507=4 & Rdd5 & rtt5 & rss5 & $(END_PACKET) -unimpl +define pcodeop vrcmpysX2SatHi; + +:vrcmpys":<<1:sat:raw:hi" Rdd5,rss5,rtt5 EndPacket is iclass=14 & op2127=0x45 & op13=0 & op0507=4 & Rdd5 & rtt5 & rss5 & $(END_PACKET) { + Rdd5 = vrcmpysX2SatHi(rss5, rtt5); + build EndPacket; +} # (v4,14) vrcmpys -- "Rdd32 = vrcmpys ( Rss32 , Rtt32 ) :<<1 :sat :raw :lo" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 1 1 1 0 1 0 0 0 1 1 1 s s s s s P P + t t t t t 1 0 0 d d d d d +# 1 1 1 0 1 0 0 0 1 1 1 s s s s s P P 0 t t t t t 1 0 0 d d d d d -:vrcmpys":<<1:sat:raw:lo" Rdd5,rss5,rtt5 EndPacket is iclass=14 & op2127=0x47 & op13=0 & op0507=4 & Rdd5 & rtt5 & rss5 & $(END_PACKET) -unimpl +define pcodeop vrcmpysX2SatLo; + +:vrcmpys":<<1:sat:raw:lo" Rdd5,rss5,rtt5 EndPacket is iclass=14 & op2127=0x47 & op13=0 & op0507=4 & Rdd5 & rtt5 & rss5 & $(END_PACKET) { + Rdd5 = vrcmpysX2SatLo(rss5, rtt5); + build EndPacket; +} # (v4,14) vrcmpys -- "Rxx32 += vrcmpys ( Rss32 , Rtt32 ) :<<1 :sat :raw :hi" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 1 1 1 0 1 0 1 0 1 0 1 s s s s s P P + t t t t t 1 0 0 x x x x x +# 1 1 1 0 1 0 1 0 1 0 1 s s s s s P P 0 t t t t t 1 0 0 x x x x x -:vrcmpys+=":<<1:sat:raw:hi" Rdd5,rss5,rtt5 EndPacket is iclass=14 & op2127=0x55 & op13=0 & op0507=4 & Rdd5 & rtt5 & rss5 & $(END_PACKET) -unimpl +define pcodeop vrcmpysX2SatAccHi; + +:vrcmpys+=":<<1:sat:raw:hi" Rdd5,rss5,rtt5 EndPacket is iclass=14 & op2127=0x55 & op13=0 & op0507=4 & Rdd5 & rdd5 & rtt5 & rss5 & $(END_PACKET) { + Rdd5 = vrcmpysX2SatAccHi(rss5, rtt5, rdd5); + build EndPacket; +} # (v4,14) vrcmpys -- "Rxx32 += vrcmpys ( Rss32 , Rtt32 ) :<<1 :sat :raw :lo" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 1 1 1 0 1 0 1 0 1 1 1 s s s s s P P + t t t t t 1 0 0 x x x x x +# 1 1 1 0 1 0 1 0 1 1 1 s s s s s P P 0 t t t t t 1 0 0 x x x x x + +define pcodeop vrcmpysX2SatAccLo; -:vrcmpys+=":<<1:sat:raw:lo" Rdd5,rss5,rtt5 EndPacket is iclass=14 & op2127=0x57 & op13=0 & op0507=4 & Rdd5 & rtt5 & rss5 & $(END_PACKET) -unimpl +:vrcmpys+=":<<1:sat:raw:lo" Rdd5,rss5,rtt5 EndPacket is iclass=14 & op2127=0x57 & op13=0 & op0507=4 & Rdd5 & rdd5 & rtt5 & rss5 & $(END_PACKET) { + Rdd5 = vrcmpysX2SatAccLo(rss5, rtt5, rdd5); + build EndPacket; +} # (v4,12) vrcnegh -- "Rxx32 += vrcnegh ( Rss32 , Rt32 )" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 1 1 0 0 1 0 1 1 0 0 1 s s s s s P P 1 t t t t t 1 1 1 x x x x x +# 1 1 0 0 1 0 1 1 0 0 1 s s s s s P P 1 t t t t t 1 1 1 x x x x x -:vrcnegh+= Rdd5,rss5,rt5 EndPacket is iclass=12 & op2127=0x59 & op13=1 & op0507=7 & Rdd5 & rt5 & rss5 & $(END_PACKET) -unimpl +define pcodeop vrcneghAcc; + +:vrcnegh+= Rdd5,rss5,rt5 EndPacket is iclass=12 & op2127=0x59 & op13=1 & op0507=7 & Rdd5 & rdd5 & rt5 & rss5 & $(END_PACKET) { + Rdd5 = vrcneghAcc(rss5, rt5, rdd5); + build EndPacket; +} # (v4,12) vrcrotate -- "Rdd32 = vrcrotate ( Rss32 , Rt32 , #u2 )" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 1 1 0 0 0 0 1 1 1 1 + s s s s s P P i t t t t t 1 1 i d d d d d +# 1 1 0 0 0 0 1 1 1 1 - s s s s s P P i t t t t t 1 1 i d d d d d -:vrcrotate Rdd5,rss5,rt5,Uimm2_13_05 EndPacket is iclass=12 & op2127=0x1e & op0607=3 & Uimm2_13_05 & Rdd5 & rt5 & rss5 & $(END_PACKET) -unimpl +define pcodeop vrcrotate; + +:vrcrotate Rdd5,rss5,rt5,Uimm2_13_05 EndPacket is iclass=12 & op2227=0xf & op0607=3 & Uimm2_13_05 & Rdd5 & rt5 & rss5 & $(END_PACKET) { + Rdd5 = vrcrotate(rss5, rt5, Uimm2_13_05); + build EndPacket; +} # (v4,12) vrcrotate -- "Rxx32 += vrcrotate ( Rss32 , Rt32 , #u2 )" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 1 1 0 0 1 0 1 1 1 0 1 s s s s s P P i t t t t t + + i x x x x x +# 1 1 0 0 1 0 1 1 1 0 1 s s s s s P P i t t t t t - - i x x x x x + +define pcodeop vrcrotateAcc; -:vrcrotate+= Rdd5,rss5,rt5,Uimm2_13_05 EndPacket is iclass=12 & op2127=0x5d & op0607=0 & Uimm2_13_05 & Rdd5 & rt5 & rss5 & $(END_PACKET) -unimpl +:vrcrotate+= Rdd5,rss5,rt5,Uimm2_13_05 EndPacket is iclass=12 & op2127=0x5d & Uimm2_13_05 & Rdd5 & rdd5 & rt5 & rss5 & $(END_PACKET) { + Rdd5 = vrcrotateAcc(rss5, rt5, Uimm2_13_05, rdd5); + build EndPacket; +} # (v4,12) vrmaxh -- "Rxx32 = vrmaxh ( Rss32 , Ru32 )" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 1 1 0 0 1 0 1 1 0 0 1 s s s s s P P 0 x x x x x 0 0 1 u u u u u +# 1 1 0 0 1 0 1 1 0 0 1 s s s s s P P 0 x x x x x 0 0 1 u u u u u -:vrmaxh Rdd0812,rss5,ru5 EndPacket is iclass=12 & op2127=0x59 & op13=0 & op0507=1 & Rdd0812 & ru5 & rss5 & $(END_PACKET) -unimpl +define pcodeop vrmaxh; + +:vrmaxh Rdd0812,rss5,ru5 EndPacket is iclass=12 & op2127=0x59 & op13=0 & op0507=1 & Rdd0812 & ru5 & rss5 & $(END_PACKET) { + Rdd0812 = vrmaxh(rss5, ru5, Rdd0812); + build EndPacket; +} # (v4,12) vrmaxuh -- "Rxx32 = vrmaxuh ( Rss32 , Ru32 )" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 1 1 0 0 1 0 1 1 0 0 1 s s s s s P P 1 x x x x x 0 0 1 u u u u u +# 1 1 0 0 1 0 1 1 0 0 1 s s s s s P P 1 x x x x x 0 0 1 u u u u u -:vrmaxuh Rdd0812,rss5,ru5 EndPacket is iclass=12 & op2127=0x59 & op13=1 & op0507=1 & Rdd0812 & ru5 & rss5 & $(END_PACKET) -unimpl +define pcodeop vrmaxuh; + +:vrmaxuh Rdd0812,rss5,ru5 EndPacket is iclass=12 & op2127=0x59 & op13=1 & op0507=1 & Rdd0812 & ru5 & rss5 & $(END_PACKET) { + Rdd0812 = vrmaxuh(rss5, ru5, Rdd0812); + build EndPacket; +} # (v4,12) vrmaxuw -- "Rxx32 = vrmaxuw ( Rss32 , Ru32 )" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 1 1 0 0 1 0 1 1 0 0 1 s s s s s P P 1 x x x x x 0 1 0 u u u u u +# 1 1 0 0 1 0 1 1 0 0 1 s s s s s P P 1 x x x x x 0 1 0 u u u u u -:vrmaxuw Rdd0812,rss5,ru5 EndPacket is iclass=12 & op2127=0x59 & op13=1 & op0507=2 & Rdd0812 & ru5 & rss5 & $(END_PACKET) -unimpl +define pcodeop vrmaxuw; + +:vrmaxuw Rdd0812,rss5,ru5 EndPacket is iclass=12 & op2127=0x59 & op13=1 & op0507=2 & Rdd0812 & ru5 & rss5 & $(END_PACKET) { + Rdd0812 = vrmaxuw(rss5, ru5, Rdd0812); + build EndPacket; +} # (v4,12) vrmaxw -- "Rxx32 = vrmaxw ( Rss32 , Ru32 )" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| # 1 1 0 0 1 0 1 1 0 0 1 s s s s s P P 0 x x x x x 0 1 0 u u u u u -:vrmaxw Rdd0812,rss5,ru5 EndPacket is iclass=12 & op2127=0x59 & op13=0 & op0507=2 & Rdd0812 & ru5 & rss5 & $(END_PACKET) -unimpl +define pcodeop vrmaxw; + +:vrmaxw Rdd0812,rss5,ru5 EndPacket is iclass=12 & op2127=0x59 & op13=0 & op0507=2 & Rdd0812 & ru5 & rss5 & $(END_PACKET) { + Rdd0812 = vrmaxw(rss5, ru5, Rdd0812); + build EndPacket; +} # (v4,12) vrminh -- "Rxx32 = vrminh ( Rss32 , Ru32 )" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 1 1 0 0 1 0 1 1 0 0 1 s s s s s P P 0 x x x x x 1 0 1 u u u u u +# 1 1 0 0 1 0 1 1 0 0 1 s s s s s P P 0 x x x x x 1 0 1 u u u u u -:vrminh Rdd0812,rss5,ru5 EndPacket is iclass=12 & op2127=0x59 & op13=0 & op0507=5 & Rdd0812 & ru5 & rss5 & $(END_PACKET) -unimpl +define pcodeop vrminh; + +:vrminh Rdd0812,rss5,ru5 EndPacket is iclass=12 & op2127=0x59 & op13=0 & op0507=5 & Rdd0812 & ru5 & rss5 & $(END_PACKET) { + Rdd0812 = vrminh(rss5, ru5, Rdd0812); + build EndPacket; +} # (v4,12) vrminuh -- "Rxx32 = vrminuh ( Rss32 , Ru32 )" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 1 1 0 0 1 0 1 1 0 0 1 s s s s s P P 1 x x x x x 1 0 1 u u u u u +# 1 1 0 0 1 0 1 1 0 0 1 s s s s s P P 1 x x x x x 1 0 1 u u u u u -:vrminuh Rdd0812,rss5,ru5 EndPacket is iclass=12 & op2127=0x59 & op13=1 & op0507=5 & Rdd0812 & ru5 & rss5 & $(END_PACKET) -unimpl +define pcodeop vrminuh; + +:vrminuh Rdd0812,rss5,ru5 EndPacket is iclass=12 & op2127=0x59 & op13=1 & op0507=5 & Rdd0812 & ru5 & rss5 & $(END_PACKET) { + Rdd0812 = vrminuh(rss5, ru5, Rdd0812); + build EndPacket; +} # (v4,12) vrminuw -- "Rxx32 = vrminuw ( Rss32 , Ru32 )" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 1 1 0 0 1 0 1 1 0 0 1 s s s s s P P 1 x x x x x 1 1 0 u u u u u +# 1 1 0 0 1 0 1 1 0 0 1 s s s s s P P 1 x x x x x 1 1 0 u u u u u + +define pcodeop vrminuw; -:vrminuw Rdd0812,rss5,ru5 EndPacket is iclass=12 & op2127=0x59 & op13=1 & op0507=6 & Rdd0812 & ru5 & rss5 & $(END_PACKET) -unimpl +:vrminuw Rdd0812,rss5,ru5 EndPacket is iclass=12 & op2127=0x59 & op13=1 & op0507=6 & Rdd0812 & ru5 & rss5 & $(END_PACKET) { + Rdd0812 = vrminuw(rss5, ru5, Rdd0812); + build EndPacket; +} # (v4,12) vrminw -- "Rxx32 = vrminw ( Rss32 , Ru32 )" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 1 1 0 0 1 0 1 1 0 0 1 s s s s s P P 0 x x x x x 1 1 0 u u u u u +# 1 1 0 0 1 0 1 1 0 0 1 s s s s s P P 0 x x x x x 1 1 0 u u u u u -:vrminw Rdd0812,rss5,ru5 EndPacket is iclass=12 & op2127=0x59 & op13=0 & op0507=6 & Rdd0812 & ru5 & rss5 & $(END_PACKET) -unimpl +define pcodeop vrminw; + +:vrminw Rdd0812,rss5,ru5 EndPacket is iclass=12 & op2127=0x59 & op13=0 & op0507=6 & Rdd0812 & ru5 & rss5 & $(END_PACKET) { + Rdd0812 = vrminw(rss5, ru5, Rdd0812); + build EndPacket; +} # (v4,14) vrmpybsu -- "Rdd32 = vrmpybsu ( Rss32 , Rtt32 )" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 1 1 1 0 1 0 0 0 1 1 0 s s s s s P P + t t t t t 0 0 1 d d d d d +# 1 1 1 0 1 0 0 0 1 1 0 s s s s s P P 0 t t t t t 0 0 1 d d d d d -:vrmpybsu Rdd5,rss5,rtt5 EndPacket is iclass=14 & op2127=0x46 & op13=0 & op0507=1 & Rdd5 & rtt5 & rss5 & $(END_PACKET) -unimpl +define pcodeop vrmpybsu; + +:vrmpybsu Rdd5,rss5,rtt5 EndPacket is iclass=14 & op2127=0x46 & op13=0 & op0507=1 & Rdd5 & rtt5 & rss5 & $(END_PACKET) { + Rdd5 = vrmpybsu(rss5, rtt5); + build EndPacket; +} # (v4,14) vrmpybsu -- "Rxx32 += vrmpybsu ( Rss32 , Rtt32 )" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 1 1 1 0 1 0 1 0 1 1 0 s s s s s P P + t t t t t 0 0 1 x x x x x +# 1 1 1 0 1 0 1 0 1 1 0 s s s s s P P 0 t t t t t 0 0 1 x x x x x -:vrmpybsu+= Rdd5,rss5,rtt5 EndPacket is iclass=14 & op2127=0x56 & op13=0 & op0507=1 & Rdd5 & rtt5 & rss5 & $(END_PACKET) -unimpl +define pcodeop vrmpybsuAcc; + +:vrmpybsu+= Rdd5,rss5,rtt5 EndPacket is iclass=14 & op2127=0x56 & op13=0 & op0507=1 & Rdd5 & rdd5 & rtt5 & rss5 & $(END_PACKET) { + Rdd5 = vrmpybsuAcc(rss5, rtt5, rdd5); + build EndPacket; +} # (v4,14) vrmpybu -- "Rdd32 = vrmpybu ( Rss32 , Rtt32 )" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 1 1 1 0 1 0 0 0 1 0 0 s s s s s P P + t t t t t 0 0 1 d d d d d +# 1 1 1 0 1 0 0 0 1 0 0 s s s s s P P 0 t t t t t 0 0 1 d d d d d + +define pcodeop vrmpybu; -:vrmpybu Rdd5,rss5,rtt5 EndPacket is iclass=14 & op2127=0x44 & op13=0 & op0507=1 & Rdd5 & rtt5 & rss5 & $(END_PACKET) -unimpl +:vrmpybu Rdd5,rss5,rtt5 EndPacket is iclass=14 & op2127=0x44 & op13=0 & op0507=1 & Rdd5 & rtt5 & rss5 & $(END_PACKET) { + Rdd5 = vrmpybu(rss5, rtt5); + build EndPacket; +} # (v4,14) vrmpybu -- "Rxx32 += vrmpybu ( Rss32 , Rtt32 )" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 1 1 1 0 1 0 1 0 1 0 0 s s s s s P P + t t t t t 0 0 1 x x x x x +# 1 1 1 0 1 0 1 0 1 0 0 s s s s s P P 0 t t t t t 0 0 1 x x x x x -:vrmpybu+= Rdd5,rss5,rtt5 EndPacket is iclass=14 & op2127=0x54 & op13=0 & op0507=1 & Rdd5 & rtt5 & rss5 & $(END_PACKET) -unimpl +define pcodeop vrmpybuAcc; + +:vrmpybu+= Rdd5,rss5,rtt5 EndPacket is iclass=14 & op2127=0x54 & op13=0 & op0507=1 & Rdd5 & rdd5 & rtt5 & rss5 & $(END_PACKET) { + Rdd5 = vrmpybuAcc(rss5, rtt5, rdd5); + build EndPacket; +} # (v2,14) vrmpyh -- "Rdd32 = vrmpyh ( Rss32 , Rtt32 )" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 1 1 1 0 1 0 0 0 0 0 0 s s s s s P P + t t t t t 0 1 0 d d d d d +# 1 1 1 0 1 0 0 0 0 0 0 s s s s s P P 0 t t t t t 0 1 0 d d d d d define pcodeop vrmpyh; @@ -16314,7 +17121,7 @@ define pcodeop vrmpyh; # (v2,14) vrmpyh -- "Rxx32 += vrmpyh ( Rss32 , Rtt32 )" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 1 1 1 0 1 0 1 0 0 0 0 s s s s s P P + t t t t t 0 1 0 x x x x x +# 1 1 1 0 1 0 1 0 0 0 0 s s s s s P P 0 t t t t t 0 1 0 x x x x x define pcodeop vrmpyhAdd; @@ -16326,75 +17133,107 @@ define pcodeop vrmpyhAdd; # (v4,14) vrmpyweh -- "Rdd32 = vrmpyweh ( Rss32 , Rtt32 )" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 1 1 1 0 1 0 0 0 0 1 0 s s s s s P P + t t t t t 1 0 0 d d d d d +# 1 1 1 0 1 0 0 0 0 1 0 s s s s s P P 0 t t t t t 1 0 0 d d d d d -:vrmpyweh Rdd5,rss5,rtt5 EndPacket is iclass=14 & op2127=0x42 & op13=0 & op0507=4 & Rdd5 & rtt5 & rss5 & $(END_PACKET) -unimpl +define pcodeop vrmpyweh; + +:vrmpyweh Rdd5,rss5,rtt5 EndPacket is iclass=14 & op2127=0x42 & op13=0 & op0507=4 & Rdd5 & rtt5 & rss5 & $(END_PACKET) { + Rdd5 = vrmpyweh(rss5, rtt5); + build EndPacket; +} # (v4,14) vrmpyweh -- "Rdd32 = vrmpyweh ( Rss32 , Rtt32 ) :<<1" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 1 1 1 0 1 0 0 0 1 1 0 s s s s s P P + t t t t t 1 0 0 d d d d d +# 1 1 1 0 1 0 0 0 1 1 0 s s s s s P P 0 t t t t t 1 0 0 d d d d d + +define pcodeop vrmpywehX2; -:vrmpyweh":<<1" Rdd5,rss5,rtt5 EndPacket is iclass=14 & op2127=0x46 & op13=0 & op0507=4 & Rdd5 & rtt5 & rss5 & $(END_PACKET) -unimpl +:vrmpyweh":<<1" Rdd5,rss5,rtt5 EndPacket is iclass=14 & op2127=0x46 & op13=0 & op0507=4 & Rdd5 & rtt5 & rss5 & $(END_PACKET) { + Rdd5 = vrmpywehX2(rss5, rtt5); + build EndPacket; +} # (v4,14) vrmpyweh -- "Rxx32 += vrmpyweh ( Rss32 , Rtt32 )" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 1 1 1 0 1 0 1 0 0 0 1 s s s s s P P + t t t t t 1 1 0 x x x x x +# 1 1 1 0 1 0 1 0 0 0 1 s s s s s P P 0 t t t t t 1 1 0 x x x x x -:vrmpyweh+= Rdd5,rss5,rtt5 EndPacket is iclass=14 & op2127=0x51 & op13=0 & op0507=6 & Rdd5 & rtt5 & rss5 & $(END_PACKET) -unimpl +define pcodeop vrmpywehAcc; + +:vrmpyweh+= Rdd5,rss5,rtt5 EndPacket is iclass=14 & op2127=0x51 & op13=0 & op0507=6 & Rdd5 & rdd5 & rtt5 & rss5 & $(END_PACKET) { + Rdd5 = vrmpywehAcc(rss5, rtt5, rdd5); + build EndPacket; +} # (v4,14) vrmpyweh -- "Rxx32 += vrmpyweh ( Rss32 , Rtt32 ) :<<1" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 1 1 1 0 1 0 1 0 1 0 1 s s s s s P P + t t t t t 1 1 0 x x x x x +# 1 1 1 0 1 0 1 0 1 0 1 s s s s s P P 0 t t t t t 1 1 0 x x x x x -:vrmpyweh+=":<<1" Rdd5,rss5,rtt5 EndPacket is iclass=14 & op2127=0x55 & op13=0 & op0507=6 & Rdd5 & rtt5 & rss5 & $(END_PACKET) -unimpl +define pcodeop vrmpywehX2Acc; + +:vrmpyweh+=":<<1" Rdd5,rss5,rtt5 EndPacket is iclass=14 & op2127=0x55 & op13=0 & op0507=6 & Rdd5 & rdd5 & rtt5 & rss5 & $(END_PACKET) { + Rdd5 = vrmpywehX2Acc(rss5, rtt5, rdd5); + build EndPacket; +} # (v4,14) vrmpywoh -- "Rdd32 = vrmpywoh ( Rss32 , Rtt32 )" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 1 1 1 0 1 0 0 0 0 0 1 s s s s s P P + t t t t t 0 1 0 d d d d d +# 1 1 1 0 1 0 0 0 0 0 1 s s s s s P P 0 t t t t t 0 1 0 d d d d d -:vrmpywoh Rdd5,rss5,rtt5 EndPacket is iclass=14 & op2127=0x41 & op13=0 & op0507=2 & Rdd5 & rtt5 & rss5 & $(END_PACKET) -unimpl +define pcodeop vrmpywoh; + +:vrmpywoh Rdd5,rss5,rtt5 EndPacket is iclass=14 & op2127=0x41 & op13=0 & op0507=2 & Rdd5 & rtt5 & rss5 & $(END_PACKET) { + Rdd5 = vrmpywoh(rss5, rtt5); + build EndPacket; +} # (v4,14) vrmpywoh -- "Rdd32 = vrmpywoh ( Rss32 , Rtt32 ) :<<1" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 1 1 1 0 1 0 0 0 1 0 1 s s s s s P P + t t t t t 0 1 0 d d d d d +# 1 1 1 0 1 0 0 0 1 0 1 s s s s s P P 0 t t t t t 0 1 0 d d d d d + +define pcodeop vrmpywohX2; -:vrmpywoh":<<1" Rdd5,rss5,rtt5 EndPacket is iclass=14 & op2127=0x45 & op13=0 & op0507=2 & Rdd5 & rtt5 & rss5 & $(END_PACKET) -unimpl +:vrmpywoh":<<1" Rdd5,rss5,rtt5 EndPacket is iclass=14 & op2127=0x45 & op13=0 & op0507=2 & Rdd5 & rtt5 & rss5 & $(END_PACKET) { + Rdd5 = vrmpywohX2(rss5, rtt5); + build EndPacket; +} # (v4,14) vrmpywoh -- "Rxx32 += vrmpywoh ( Rss32 , Rtt32 )" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 1 1 1 0 1 0 1 0 0 1 1 s s s s s P P + t t t t t 1 1 0 x x x x x +# 1 1 1 0 1 0 1 0 0 1 1 s s s s s P P 0 t t t t t 1 1 0 x x x x x -:vrmpywoh+= Rdd5,rss5,rtt5 EndPacket is iclass=14 & op2127=0x53 & op13=0 & op0507=6 & Rdd5 & rtt5 & rss5 & $(END_PACKET) -unimpl +define pcodeop vrmpywohAcc; + +:vrmpywoh+= Rdd5,rss5,rtt5 EndPacket is iclass=14 & op2127=0x53 & op13=0 & op0507=6 & Rdd5 & rdd5 & rtt5 & rss5 & $(END_PACKET) { + Rdd5 = vrmpywohAcc(rss5, rtt5, rdd5); + build EndPacket; +} # (v4,14) vrmpywoh -- "Rxx32 += vrmpywoh ( Rss32 , Rtt32 ) :<<1" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 1 1 1 0 1 0 1 0 1 1 1 s s s s s P P + t t t t t 1 1 0 x x x x x +# 1 1 1 0 1 0 1 0 1 1 1 s s s s s P P 0 t t t t t 1 1 0 x x x x x -:vrmpywoh+=":<<1" Rdd5,rss5,rtt5 EndPacket is iclass=14 & op2127=0x57 & op13=0 & op0507=6 & Rdd5 & rtt5 & rss5 & $(END_PACKET) -unimpl +define pcodeop vrmpywohX2Acc; + +:vrmpywoh+=":<<1" Rdd5,rss5,rtt5 EndPacket is iclass=14 & op2127=0x57 & op13=0 & op0507=6 & Rdd5 & rdd5 & rtt5 & rss5 & $(END_PACKET) { + Rdd5 = vrmpywohX2Acc(rss5, rtt5, rdd5); + build EndPacket; +} # (v2,8) vrndwh -- "Rd32 = vrndwh ( Rss32 )" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 1 0 0 0 1 0 0 0 1 0 0 s s s s s P P + + + + + + 1 0 + d d d d d +# 1 0 0 0 1 0 0 0 1 0 0 s s s s s P P - - - - - - 1 0 0 d d d d d define pcodeop vrndwh; -:vrndwh Rd5,rss5 EndPacket is iclass=8 & op2127=0x44 & op0513=0x04 & Rd5 & rss5 & $(END_PACKET) { +:vrndwh Rd5,rss5 EndPacket is iclass=8 & op2127=0x44 & op0607=0x2 & op5=0 & Rd5 & rss5 & $(END_PACKET) { Rd5 = vrndwh(rss5); build EndPacket; } @@ -16402,11 +17241,11 @@ define pcodeop vrndwh; # (v2,8) vrndwh -- "Rd32 = vrndwh ( Rss32 ) :sat" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 1 0 0 0 1 0 0 0 1 0 0 s s s s s P P + + + + + + 1 1 + d d d d d +# 1 0 0 0 1 0 0 0 1 0 0 s s s s s P P - - - - - - 1 1 0 d d d d d define pcodeop vrndwhSat; -:vrndwh":sat" Rd5,rss5 EndPacket is iclass=8 & op2127=0x44 & op0513=0x06 & Rd5 & rss5 & $(END_PACKET) { +:vrndwh":sat" Rd5,rss5 EndPacket is iclass=8 & op2127=0x44 & op0607=0x3 & op5=0 & Rd5 & rss5 & $(END_PACKET) { Rd5 = vrndwhSat(rss5); build EndPacket; } @@ -16414,27 +17253,35 @@ define pcodeop vrndwhSat; # (v2,14) vrsadub -- "Rdd32 = vrsadub ( Rss32 , Rtt32 )" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 1 1 1 0 1 0 0 0 0 1 0 s s s s s P P + t t t t t 0 1 0 d d d d d +# 1 1 1 0 1 0 0 0 0 1 0 s s s s s P P 0 t t t t t 0 1 0 d d d d d + +define pcodeop vrsadub; -:vrsadub Rdd5,rss5,rtt5 EndPacket is iclass=14 & op2127=0x42 & op13=0 & op0507=2 & Rdd5 & rtt5 & rss5 & $(END_PACKET) -unimpl +:vrsadub Rdd5,rss5,rtt5 EndPacket is iclass=14 & op2127=0x42 & op13=0 & op0507=2 & Rdd5 & rtt5 & rss5 & $(END_PACKET) { + Rdd5 = vrsadub(rss5, rtt5); + build EndPacket; +} # (v2,14) vrsadub -- "Rxx32 += vrsadub ( Rss32 , Rtt32 )" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 1 1 1 0 1 0 1 0 0 1 0 s s s s s P P + t t t t t 0 1 0 x x x x x +# 1 1 1 0 1 0 1 0 0 1 0 s s s s s P P 0 t t t t t 0 1 0 x x x x x -:vrsadub+= Rdd5,rss5,rtt5 EndPacket is iclass=14 & op2127=0x52 & op13=0 & op0507=2 & Rdd5 & rtt5 & rss5 & $(END_PACKET) -unimpl +define pcodeop vrsadubAcc; + +:vrsadub+= Rdd5,rss5,rtt5 EndPacket is iclass=14 & op2127=0x52 & op13=0 & op0507=2 & Rdd5 & rdd5 & rtt5 & rss5 & $(END_PACKET) { + Rdd5 = vrsadubAcc(rss5, rtt5, rdd5); + build EndPacket; +} # (v2,8) vsathb -- "Rd32 = vsathb ( Rs32 )" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 1 0 0 0 1 1 0 0 1 0 + s s s s s P P + + + + + + 0 0 + d d d d d +# 1 0 0 0 1 1 0 0 1 0 - s s s s s P P - - - - - - 0 0 - d d d d d define pcodeop vsathb; -:vsathb Rd5,rs5 EndPacket is iclass=8 & op2127=0x64 & op0513=0 & Rd5 & rs5 & $(END_PACKET) { +:vsathb Rd5,rs5 EndPacket is iclass=8 & op2227=0x32 & op0607=0 & Rd5 & rs5 & $(END_PACKET) { Rd5 = vsathb(rs5); build EndPacket; } @@ -16442,10 +17289,10 @@ define pcodeop vsathb; # (v2,8) vsathb -- "Rd32 = vsathb ( Rss32 )" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 1 0 0 0 1 0 0 0 0 0 0 s s s s s P P + + + + + + 1 1 + d d d d d +# 1 0 0 0 1 0 0 0 0 0 0 s s s s s P P - - - - - - 1 1 0 d d d d d -:vsathb Rd5,rss5 EndPacket is iclass=8 & op2127=0x40 & op0513=0x06 & Rd5 & rss5 & $(END_PACKET) { +:vsathb Rd5,rss5 EndPacket is iclass=8 & op2127=0x40 & op0607=0x3 & op5=0 & Rd5 & rss5 & $(END_PACKET) { Rd5 = vsathb(rss5); build EndPacket; } @@ -16453,9 +17300,9 @@ define pcodeop vsathb; # (v2,8) vsathb -- "Rdd32 = vsathb ( Rss32 )" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 1 0 0 0 0 0 0 0 0 0 + s s s s s P P + + + + + + 1 1 1 d d d d d +# 1 0 0 0 0 0 0 0 0 0 0 s s s s s P P - - - - - - 1 1 1 d d d d d -:vsathb Rdd5,rss5 EndPacket is iclass=8 & op2127=0x00 & op0513=0x07 & Rdd5 & rss5 & $(END_PACKET) { +:vsathb Rdd5,rss5 EndPacket is iclass=8 & op2227=0x0 & op21=0 & op0507=0x7 & Rdd5 & rss5 & $(END_PACKET) { Rdd5 = vsathb(rss5); build EndPacket; } @@ -16463,35 +17310,43 @@ define pcodeop vsathb; # (v2,8) vsathub -- "Rd32 = vsathub ( Rs32 )" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 1 0 0 0 1 1 0 0 1 0 + s s s s s P P + + + + + + 0 1 + d d d d d +# 1 0 0 0 1 1 0 0 1 0 - s s s s s P P - - - - - - 0 1 - d d d d d -:vsathub Rd5,rs5 EndPacket is iclass=8 & op2127=0x64 & op0513=0x02 & Rd5 & rs5 & $(END_PACKET) -unimpl +define pcodeop vsathub; + +:vsathub Rd5,rs5 EndPacket is iclass=8 & op2227=0x32 & op0607=0x1 & Rd5 & rs5 & $(END_PACKET) { + Rd5 = vsathub(rs5); + build EndPacket; +} # (v2,8) vsathub -- "Rd32 = vsathub ( Rss32 )" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 1 0 0 0 1 0 0 0 0 0 0 s s s s s P P + + + + + + 0 0 + d d d d d +# 1 0 0 0 1 0 0 0 0 0 0 s s s s s P P - - - - - - 0 0 - d d d d d -:vsathub Rd5,rss5 EndPacket is iclass=8 & op2127=0x40 & op0513=0 & Rd5 & rss5 & $(END_PACKET) -unimpl +:vsathub Rd5,rss5 EndPacket is iclass=8 & op2127=0x40 & op0607=0 & Rd5 & rss5 & $(END_PACKET) { + Rd5 = vsathub(rss5); + build EndPacket; +} # (v2,8) vsathub -- "Rdd32 = vsathub ( Rss32 )" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 1 0 0 0 0 0 0 0 0 0 + s s s s s P P + + + + + + 1 0 0 d d d d d +# 1 0 0 0 0 0 0 0 0 0 0 s s s s s P P - - - - - - 1 0 0 d d d d d -:vsathub Rdd5,rss5 EndPacket is iclass=8 & op2127=0x00 & op0513=0x04 & Rdd5 & rss5 & $(END_PACKET) -unimpl +:vsathub Rdd5,rss5 EndPacket is iclass=8 & op2227=0x0 & op21=0 & op0507=0x4 & Rdd5 & rss5 & $(END_PACKET) { + Rdd5 = vsathub(rss5); + build EndPacket; +} # (v2,8) vsatwh -- "Rd32 = vsatwh ( Rss32 )" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 1 0 0 0 1 0 0 0 0 0 0 s s s s s P P + + + + + + 0 1 + d d d d d +# 1 0 0 0 1 0 0 0 0 0 0 s s s s s P P - - - - - - 0 1 0 d d d d d define pcodeop vsatwh; -:vsatwh Rd5,rss5 EndPacket is iclass=8 & op2127=0x40 & op0513=0x02 & Rd5 & rss5 & $(END_PACKET) { +:vsatwh Rd5,rss5 EndPacket is iclass=8 & op2127=0x40 & op0607=0x1 & op5=0 & Rd5 & rss5 & $(END_PACKET) { Rd5 = vsatwh(rss5); build EndPacket; } @@ -16499,9 +17354,9 @@ define pcodeop vsatwh; # (v2,8) vsatwh -- "Rdd32 = vsatwh ( Rss32 )" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 1 0 0 0 0 0 0 0 0 0 + s s s s s P P + + + + + + 1 1 0 d d d d d +# 1 0 0 0 0 0 0 0 0 0 0 s s s s s P P - - - - - - 1 1 0 d d d d d -:vsatwh Rdd5,rss5 EndPacket is iclass=8 & op2127=0x00 & op0513=0x06 & Rdd5 & rss5 & $(END_PACKET) { +:vsatwh Rdd5,rss5 EndPacket is iclass=8 & op2227=0x0 & op21=0 & op0507=0x6 & Rdd5 & rss5 & $(END_PACKET) { Rdd5 = vsatwh(rss5); build EndPacket; } @@ -16509,11 +17364,11 @@ define pcodeop vsatwh; # (v2,8) vsatwuh -- "Rd32 = vsatwuh ( Rss32 )" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 1 0 0 0 1 0 0 0 0 0 0 s s s s s P P + + + + + + 1 0 + d d d d d +# 1 0 0 0 1 0 0 0 0 0 0 s s s s s P P - - - - - - 1 0 0 d d d d d define pcodeop vsatwuh; -:vsatwuh Rd5,rss5 EndPacket is iclass=8 & op2127=0x40 & op0513=0x04 & Rd5 & rss5 & $(END_PACKET) { +:vsatwuh Rd5,rss5 EndPacket is iclass=8 & op2127=0x40 & op0607=0x2 & op5=0 & Rd5 & rss5 & $(END_PACKET) { Rd5 = vsatwuh(rss5); build EndPacket; } @@ -16521,9 +17376,9 @@ define pcodeop vsatwuh; # (v2,8) vsatwuh -- "Rdd32 = vsatwuh ( Rss32 )" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 1 0 0 0 0 0 0 0 0 0 + s s s s s P P + + + + + + 1 0 1 d d d d d +# 1 0 0 0 0 0 0 0 0 0 0 s s s s s P P - - - - - - 1 0 1 d d d d d -:vsatwuh Rdd5,rss5 EndPacket is iclass=8 & op2127=0x00 & op0513=0x05 & Rdd5 & rss5 & $(END_PACKET) { +:vsatwuh Rdd5,rss5 EndPacket is iclass=8 & op2227=0x0 & op21=0 & op0507=0x5 & Rdd5 & rss5 & $(END_PACKET) { Rdd5 = vsatwuh(rss5); build EndPacket; } @@ -16531,21 +17386,21 @@ define pcodeop vsatwuh; # (v2,8) vsplatb -- "Rd32 = vsplatb ( Rs32 )" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 1 0 0 0 1 1 0 0 0 1 0 s s s s s P P + + + + + + 1 1 1 d d d d d +# 1 0 0 0 1 1 0 0 0 1 0 s s s s s P P - - - - - - 1 1 1 d d d d d define pcodeop vsplatb; -:vsplatb Rd5,rs5 EndPacket is iclass=8 & op2127=0x62 & op0813=0 & op0507=7 & Rd5 & rs5 & $(END_PACKET) { +:vsplatb Rd5,rs5 EndPacket is iclass=8 & op2127=0x62 & op0507=7 & Rd5 & rs5 & $(END_PACKET) { Rd5 = vsplatb(rs5); build EndPacket; } -# (?,8) vsplatb -- "Rdd32 = vsplatb ( Rs32 )" +# (v2,8) vsplatb -- "Rdd32 = vsplatb ( Rs32 )" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 1 0 0 0 0 1 0 0 0 1 + s s s s s P P + + + + + + 1 0 + d d d d d +# 1 0 0 0 0 1 0 0 0 1 - s s s s s P P - - - - - - 1 0 - d d d d d -:vsplatb Rdd5,rs5 EndPacket is iclass=8 & op2127=0x22 & op0813=0 & op0507=4 & Rdd5 & rs5 & $(END_PACKET) { +:vsplatb Rdd5,rs5 EndPacket is iclass=8 & op2227=0x11 & op0607=2 & Rdd5 & rs5 & $(END_PACKET) { Rdd5 = vsplatb(rs5); build EndPacket; } @@ -16553,11 +17408,11 @@ define pcodeop vsplatb; # (v2,8) vsplath -- "Rdd32 = vsplath ( Rs32 )" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 1 0 0 0 0 1 0 0 0 1 + s s s s s P P + + + + + + 0 1 + d d d d d +# 1 0 0 0 0 1 0 0 0 1 - s s s s s P P - - - - - - 0 1 - d d d d d define pcodeop vsplath; -:vsplath Rdd5,rs5 EndPacket is iclass=8 & op2127=0x22 & op0813=0 & op0507=2 & Rdd5 & rs5 & $(END_PACKET) { +:vsplath Rdd5,rs5 EndPacket is iclass=8 & op2227=0x11 & op0607=1 & Rdd5 & rs5 & $(END_PACKET) { Rdd5 = vsplath(rs5); build EndPacket; } @@ -16565,9 +17420,9 @@ define pcodeop vsplath; # (v2,12) vspliceb -- "Rdd32 = vspliceb ( Rss32 , Rtt32 , #u3 )" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 1 1 0 0 0 0 0 0 1 + + s s s s s P P + t t t t t i i i d d d d d +# 1 1 0 0 0 0 0 0 1 - - s s s s s P P - t t t t t i i i d d d d d -:vspliceb Rdd5,rss5,rtt5,Uimm3_0507 EndPacket is iclass=12 & op2127=0x04 & op13=0 & Uimm3_0507 & Rdd5 & rss5 & rtt5 & $(END_PACKET) { +:vspliceb Rdd5,rss5,rtt5,Uimm3_0507 EndPacket is iclass=12 & op2327=0x1 & Uimm3_0507 & Rdd5 & rss5 & rtt5 & $(END_PACKET) { cnt:1 = 8 * Uimm3_0507; mask:8 = -1 >> (64 - cnt); Rdd5 = (rtt5 << cnt) | (mask & rss5); @@ -16577,9 +17432,9 @@ define pcodeop vsplath; # (v2,12) vspliceb -- "Rdd32 = vspliceb ( Rss32 , Rtt32 , Pu4 )" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 1 1 0 0 0 0 1 0 1 0 + s s s s s P P + t t t t t + u u d d d d d +# 1 1 0 0 0 0 1 0 1 0 0 s s s s s P P - t t t t t - u u d d d d d -:vspliceb Rdd5,rss5,rtt5,pu0506 EndPacket is iclass=12 & op2127=0x14 & op13=0 & op7=0 & pu0506 & Rdd5 & rss5 & rtt5 & $(END_PACKET) { +:vspliceb Rdd5,rss5,rtt5,pu0506 EndPacket is iclass=12 & op2227=0xa & op21=0 & pu0506 & Rdd5 & rss5 & rtt5 & $(END_PACKET) { cnt:1 = 8 * (pu0506 & 0x7); mask:8 = -1 >> (64 - cnt); Rdd5 = (rtt5 << cnt) | (mask & rss5); @@ -16589,9 +17444,9 @@ define pcodeop vsplath; # (v2,15) vsubh -- "Rd32 = vsubh ( Rt32 , Rs32 )" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 1 1 1 1 0 1 1 0 1 0 0 s s s s s P P + t t t t t + + + d d d d d +# 1 1 1 1 0 1 1 0 1 0 0 s s s s s P P - t t t t t - - - d d d d d -:vsubh Rd5,rt5,rs5 EndPacket is iclass=15 & op2127=0x34 & op13=0 & op0507=0 & Rd5 & rt5 & rs5 & $(END_PACKET) { +:vsubh Rd5,rt5,rs5 EndPacket is iclass=15 & op2127=0x34 & Rd5 & rt5 & rs5 & $(END_PACKET) { Rd5[0,16] = rt5[0,16] - rs5[0,16]; Rd5[16,16] = rt5[16,16] - rs5[16,16]; build EndPacket; @@ -16600,9 +17455,9 @@ define pcodeop vsplath; # (v2,15) vsubh -- "Rd32 = vsubh ( Rt32 , Rs32 ) :sat" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 1 1 1 1 0 1 1 0 1 0 1 s s s s s P P + t t t t t + + + d d d d d +# 1 1 1 1 0 1 1 0 1 0 1 s s s s s P P - t t t t t - - - d d d d d -:vsubh":sat" Rd5,rt5,rs5 EndPacket is iclass=15 & op2127=0x35 & op13=0 & op0507=0 & Rd5 & rt5 & rs5 & $(END_PACKET) { +:vsubh":sat" Rd5,rt5,rs5 EndPacket is iclass=15 & op2127=0x35 & Rd5 & rt5 & rs5 & $(END_PACKET) { h:2 = 0; subSat16(h, rt5[0,16], rs5[0,16]); Rd5[0,16] = h; @@ -16614,9 +17469,9 @@ define pcodeop vsplath; # (v2,13) vsubh -- "Rdd32 = vsubh ( Rtt32 , Rss32 )" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 1 1 0 1 0 0 1 1 0 0 1 s s s s s P P + t t t t t 0 1 0 d d d d d +# 1 1 0 1 0 0 1 1 0 0 1 s s s s s P P - t t t t t 0 1 0 d d d d d -:vsubh Rdd5,rtt5,rss5 EndPacket is iclass=13 & op2127=0x19 & op13=0 & op0507=2 & Rdd5 & rtt5 & rss5 & $(END_PACKET) { +:vsubh Rdd5,rtt5,rss5 EndPacket is iclass=13 & op2127=0x19 & op0507=2 & Rdd5 & rtt5 & rss5 & $(END_PACKET) { Rdd5[0,16] = rtt5[0,16] - rss5[0,16]; Rdd5[16,16] = rtt5[16,16] - rss5[16,16]; Rdd5[32,16] = rtt5[32,16] - rss5[32,16]; @@ -16627,9 +17482,9 @@ define pcodeop vsplath; # (v2,13) vsubh -- "Rdd32 = vsubh ( Rtt32 , Rss32 ) :sat" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 1 1 0 1 0 0 1 1 0 0 1 s s s s s P P + t t t t t 0 1 1 d d d d d +# 1 1 0 1 0 0 1 1 0 0 1 s s s s s P P - t t t t t 0 1 1 d d d d d -:vsubh":sat" Rdd5,rtt5,rss5 EndPacket is iclass=13 & op2127=0x19 & op13=0 & op0507=3 & Rdd5 & rtt5 & rss5 & $(END_PACKET) { +:vsubh":sat" Rdd5,rtt5,rss5 EndPacket is iclass=13 & op2127=0x19 & op0507=3 & Rdd5 & rtt5 & rss5 & $(END_PACKET) { h:2 = 0; subSat16(h, rtt5[0,16], rss5[0,16]); Rdd5[0,16] = h; @@ -16645,11 +17500,11 @@ define pcodeop vsplath; # (v2,13) vsubub -- "Rdd32 = vsubub ( Rtt32 , Rss32 )" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 1 1 0 1 0 0 1 1 0 0 1 s s s s s P P + t t t t t 0 0 0 d d d d d +# 1 1 0 1 0 0 1 1 0 0 1 s s s s s P P - t t t t t 0 0 0 d d d d d define pcodeop vsubub; -:vsubub Rdd5,rtt5,rss5 EndPacket is iclass=13 & op2127=0x19 & op13=0 & op0507=0 & Rdd5 & rtt5 & rss5 & $(END_PACKET) { +:vsubub Rdd5,rtt5,rss5 EndPacket is iclass=13 & op2127=0x19 & op0507=0 & Rdd5 & rtt5 & rss5 & $(END_PACKET) { Rdd5 = vsubub(rtt5,rss5); build EndPacket; } @@ -16657,11 +17512,11 @@ define pcodeop vsubub; # (v2,13) vsubub -- "Rdd32 = vsubub ( Rtt32 , Rss32 ) :sat" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 1 1 0 1 0 0 1 1 0 0 1 s s s s s P P + t t t t t 0 0 1 d d d d d +# 1 1 0 1 0 0 1 1 0 0 1 s s s s s P P - t t t t t 0 0 1 d d d d d define pcodeop vsububSat; -:vsubub":sat" Rdd5,rtt5,rss5 EndPacket is iclass=13 & op2127=0x19 & op13=0 & op0507=1 & Rdd5 & rtt5 & rss5 & $(END_PACKET) { +:vsubub":sat" Rdd5,rtt5,rss5 EndPacket is iclass=13 & op2127=0x19 & op0507=1 & Rdd5 & rtt5 & rss5 & $(END_PACKET) { Rdd5 = vsububSat(rtt5,rss5); build EndPacket; } @@ -16669,9 +17524,9 @@ define pcodeop vsububSat; # (v2,15) vsubuh -- "Rd32 = vsubuh ( Rt32 , Rs32 ) :sat" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 1 1 1 1 0 1 1 0 1 1 1 s s s s s P P + t t t t t + + + d d d d d +# 1 1 1 1 0 1 1 0 1 1 1 s s s s s P P - t t t t t - - - d d d d d -:vsubuh":sat" Rd5,rt5,rs5 EndPacket is iclass=15 & op2127=0x37 & op13=0 & op0507=0 & Rd5 & rt5 & rs5 & $(END_PACKET) { +:vsubuh":sat" Rd5,rt5,rs5 EndPacket is iclass=15 & op2127=0x37 & Rd5 & rt5 & rs5 & $(END_PACKET) { h:2 = 0; subuSat16(h, rt5[0,16], rs5[0,16]); Rd5[0,16] = h; @@ -16683,9 +17538,9 @@ define pcodeop vsububSat; # (v2,13) vsubuh -- "Rdd32 = vsubuh ( Rtt32 , Rss32 ) :sat" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 1 1 0 1 0 0 1 1 0 0 1 s s s s s P P + t t t t t 1 0 0 d d d d d +# 1 1 0 1 0 0 1 1 0 0 1 s s s s s P P - t t t t t 1 0 0 d d d d d -:vsubuh":sat" Rdd5,rtt5,rss5 EndPacket is iclass=13 & op2127=0x19 & op13=0 & op0507=4 & Rdd5 & rtt5 & rss5 & $(END_PACKET) { +:vsubuh":sat" Rdd5,rtt5,rss5 EndPacket is iclass=13 & op2127=0x19 & op0507=4 & Rdd5 & rtt5 & rss5 & $(END_PACKET) { h:2 = 0; subuSat16(h, rtt5[0,16], rss5[0,16]); Rdd5[0,16] = h; @@ -16701,9 +17556,9 @@ define pcodeop vsububSat; # (v2,13) vsubw -- "Rdd32 = vsubw ( Rtt32 , Rss32 )" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 1 1 0 1 0 0 1 1 0 0 1 s s s s s P P + t t t t t 1 0 1 d d d d d +# 1 1 0 1 0 0 1 1 0 0 1 s s s s s P P - t t t t t 1 0 1 d d d d d -:vsubw Rdd5,rtt5,rss5 EndPacket is iclass=13 & op2127=0x19 & op13=0 & op0507=5 & Rdd5 & rtt5 & rss5 & $(END_PACKET) { +:vsubw Rdd5,rtt5,rss5 EndPacket is iclass=13 & op2127=0x19 & op0507=5 & Rdd5 & rtt5 & rss5 & $(END_PACKET) { Rdd5[0,32] = rtt5[0,32] - rss5[0,32]; Rdd5[32,32] = rtt5[32,32] - rss5[32,32]; build EndPacket; @@ -16712,9 +17567,9 @@ define pcodeop vsububSat; # (v2,13) vsubw -- "Rdd32 = vsubw ( Rtt32 , Rss32 ) :sat" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 1 1 0 1 0 0 1 1 0 0 1 s s s s s P P + t t t t t 1 1 0 d d d d d +# 1 1 0 1 0 0 1 1 0 0 1 s s s s s P P - t t t t t 1 1 0 d d d d d -:vsubw":sat" Rdd5,rtt5,rss5 EndPacket is iclass=13 & op2127=0x19 & op13=0 & op0507=6 & Rdd5 & rtt5 & rss5 & $(END_PACKET) { +:vsubw":sat" Rdd5,rtt5,rss5 EndPacket is iclass=13 & op2127=0x19 & op0507=6 & Rdd5 & rtt5 & rss5 & $(END_PACKET) { w:4 = 0; subSat32(w, rtt5[0,32], rss5[0,32]); Rdd5[0,32] = w; @@ -16726,11 +17581,11 @@ define pcodeop vsububSat; # (v2,8) vsxtbh -- "Rdd32 = vsxtbh ( Rs32 )" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 1 0 0 0 0 1 0 0 0 0 + s s s s s P P + + + + + + 0 0 + d d d d d +# 1 0 0 0 0 1 0 0 0 0 - s s s s s P P - - - - - - 0 0 - d d d d d define pcodeop vsxtbh; -:vsxtbh Rdd5,rs5 EndPacket is iclass=8 & op2127=0x20 & op0513=0 & Rdd5 & rs5 & $(END_PACKET) { +:vsxtbh Rdd5,rs5 EndPacket is iclass=8 & op2227=0x10 & op0607=0 & Rdd5 & rs5 & $(END_PACKET) { Rdd5 = vsxtbh(rs5); build EndPacket; } @@ -16738,9 +17593,9 @@ define pcodeop vsxtbh; # (v2,8) vsxthw -- "Rdd32 = vsxthw ( Rs32 )" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 1 0 0 0 0 1 0 0 0 0 + s s s s s P P + + + + + + 1 0 + d d d d d +# 1 0 0 0 0 1 0 0 0 0 - s s s s s P P - - - - - - 1 0 - d d d d d -:vsxthw Rdd5,rs5 EndPacket is iclass=8 & op2127=0x20 & op0513=0x04 & Rdd5 & rs5 & $(END_PACKET) { +:vsxthw Rdd5,rs5 EndPacket is iclass=8 & op2227=0x10 & op0607=0x2 & Rdd5 & rs5 & $(END_PACKET) { Rdd5[0,32] = sext(rs5[0,16]); Rdd5[32,32] = sext(rs5[16,16]); build EndPacket; @@ -16749,11 +17604,11 @@ define pcodeop vsxtbh; # (v2,8) vtrunehb -- "Rd32 = vtrunehb ( Rss32 )" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 1 0 0 0 1 0 0 0 1 0 0 s s s s s P P + + + + + + 0 1 + d d d d d +# 1 0 0 0 1 0 0 0 1 0 0 s s s s s P P - - - - - - 0 1 0 d d d d d define pcodeop vtrunehb; -:vtrunehb Rd5,rss5 EndPacket is iclass=8 & op2127=0x44 & op0513=0x02 & Rd5 & rss5 & $(END_PACKET) { +:vtrunehb Rd5,rss5 EndPacket is iclass=8 & op2127=0x44 & op0607=0x1 & op5=0 & Rd5 & rss5 & $(END_PACKET) { Rd5 = vtrunehb(rss5); build EndPacket; } @@ -16761,9 +17616,9 @@ define pcodeop vtrunehb; # (v2,12) vtrunewh -- "Rdd32 = vtrunewh ( Rss32 , Rtt32 )" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 1 1 0 0 0 0 0 1 1 0 + s s s s s P P + t t t t t 0 1 + d d d d d +# 1 1 0 0 0 0 0 1 1 0 - s s s s s P P - t t t t t 0 1 0 d d d d d -:vtrunewh Rdd5,rss5,rtt5 EndPacket is iclass=12 & op2127=0x0c & op13=0 & op0507=2 & Rdd5 & rss5 & rtt5 & $(END_PACKET) { +:vtrunewh Rdd5,rss5,rtt5 EndPacket is iclass=12 & op2227=0x6 & op0507=2 & Rdd5 & rss5 & rtt5 & $(END_PACKET) { Rdd5[0,16] = rtt5[0,16]; Rdd5[16,16] = rtt5[32,16]; Rdd5[32,16] = rss5[0,16]; @@ -16774,11 +17629,11 @@ define pcodeop vtrunehb; # (v2,8) vtrunohb -- "Rd32 = vtrunohb ( Rss32 )" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 1 0 0 0 1 0 0 0 1 0 0 s s s s s P P + + + + + + 0 0 + d d d d d +# 1 0 0 0 1 0 0 0 1 0 0 s s s s s P P - - - - - - 0 0 - d d d d d define pcodeop vtrunohb; -:vtrunohb Rd5,rss5 EndPacket is iclass=8 & op2127=0x44 & op0513=0 & Rd5 & rss5 & $(END_PACKET) { +:vtrunohb Rd5,rss5 EndPacket is iclass=8 & op2127=0x44 & op0607=0 & Rd5 & rss5 & $(END_PACKET) { Rd5 = vtrunohb(rss5); build EndPacket; } @@ -16786,9 +17641,9 @@ define pcodeop vtrunohb; # (v2,12) vtrunowh -- "Rdd32 = vtrunowh ( Rss32 , Rtt32 )" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 1 1 0 0 0 0 0 1 1 0 + s s s s s P P + t t t t t 1 0 + d d d d d +# 1 1 0 0 0 0 0 1 1 0 - s s s s s P P - t t t t t 1 0 0 d d d d d -:vtrunowh Rdd5,rss5,rtt5 EndPacket is iclass=12 & op2127=0x0c & op13=0 & op0507=4 & Rdd5 & rss5 & rtt5 & $(END_PACKET) { +:vtrunowh Rdd5,rss5,rtt5 EndPacket is iclass=12 & op2227=0x6 & op0507=4 & Rdd5 & rss5 & rtt5 & $(END_PACKET) { Rdd5[0,16] = rtt5[16,16]; Rdd5[16,16] = rtt5[48,16]; Rdd5[32,16] = rss5[16,16]; @@ -16796,14 +17651,50 @@ define pcodeop vtrunohb; build EndPacket; } +# (v62,12) vtrunehb -- "Rdd32 = vtrunehb ( Rss32 , Rtt32 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 0 0 0 0 0 1 1 0 - s s s s s P P - t t t t t 0 1 1 d d d d d + +:vtrunehb Rdd5,rss5,rtt5 EndPacket is iclass=12 & op2227=0x6 & op0507=3 & Rdd5 & rss5 & rtt5 & $(END_PACKET) { + # gather the even (low) byte of each source halfword: Rtt halfwords then Rss halfwords + Rdd5[0,8] = rtt5[0,8]; + Rdd5[8,8] = rtt5[16,8]; + Rdd5[16,8] = rtt5[32,8]; + Rdd5[24,8] = rtt5[48,8]; + Rdd5[32,8] = rss5[0,8]; + Rdd5[40,8] = rss5[16,8]; + Rdd5[48,8] = rss5[32,8]; + Rdd5[56,8] = rss5[48,8]; + build EndPacket; +} + +# (v62,12) vtrunohb -- "Rdd32 = vtrunohb ( Rss32 , Rtt32 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 0 0 0 0 0 1 1 0 - s s s s s P P - t t t t t 1 0 1 d d d d d + +:vtrunohb Rdd5,rss5,rtt5 EndPacket is iclass=12 & op2227=0x6 & op0507=5 & Rdd5 & rss5 & rtt5 & $(END_PACKET) { + # gather the odd (high) byte of each source halfword: Rtt halfwords then Rss halfwords + Rdd5[0,8] = rtt5[8,8]; + Rdd5[8,8] = rtt5[24,8]; + Rdd5[16,8] = rtt5[40,8]; + Rdd5[24,8] = rtt5[56,8]; + Rdd5[32,8] = rss5[8,8]; + Rdd5[40,8] = rss5[24,8]; + Rdd5[48,8] = rss5[40,8]; + Rdd5[56,8] = rss5[56,8]; + build EndPacket; +} + # (v4,12) vxaddsubh -- "Rdd32 = vxaddsubh ( Rss32 , Rtt32 ) :rnd :>>1 :sat" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 1 1 0 0 0 0 0 1 1 1 + s s s s s P P + t t t t t 0 0 + d d d d d +# 1 1 0 0 0 0 0 1 1 1 - s s s s s P P - t t t t t 0 0 - d d d d d define pcodeop vxaddsubhRndX2Sat; -:vxaddsubh":rnd:>>1:sat" Rdd5,rss5,rtt5 EndPacket is iclass=12 & op2127=0x0e & op13=0 & op0507=0 & Rdd5 & rss5 & rtt5 & $(END_PACKET) { +:vxaddsubh":rnd:>>1:sat" Rdd5,rss5,rtt5 EndPacket is iclass=12 & op2227=0x7 & op0607=0 & Rdd5 & rss5 & rtt5 & $(END_PACKET) { Rdd5 = vxaddsubhRndX2Sat(rtt5,rss5); build EndPacket; } @@ -16811,11 +17702,11 @@ define pcodeop vxaddsubhRndX2Sat; # (v4,12) vxaddsubh -- "Rdd32 = vxaddsubh ( Rss32 , Rtt32 ) :sat" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 1 1 0 0 0 0 0 1 0 1 + s s s s s P P + t t t t t 1 0 + d d d d d +# 1 1 0 0 0 0 0 1 0 1 - s s s s s P P - t t t t t 1 0 0 d d d d d define pcodeop vxaddsubhSat; -:vxaddsubh":sat" Rdd5,rss5,rtt5 EndPacket is iclass=12 & op2127=0x0a & op13=0 & op0507=4 & Rdd5 & rss5 & rtt5 & $(END_PACKET) { +:vxaddsubh":sat" Rdd5,rss5,rtt5 EndPacket is iclass=12 & op2227=0x5 & op0607=2 & op5=0 & Rdd5 & rss5 & rtt5 & $(END_PACKET) { Rdd5 = vxaddsubhSat(rtt5,rss5); build EndPacket; } @@ -16823,11 +17714,11 @@ define pcodeop vxaddsubhSat; # (v4,12) vxaddsubw -- "Rdd32 = vxaddsubw ( Rss32 , Rtt32 ) :sat" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 1 1 0 0 0 0 0 1 0 1 + s s s s s P P + t t t t t 0 0 + d d d d d +# 1 1 0 0 0 0 0 1 0 1 - s s s s s P P - t t t t t 0 0 0 d d d d d define pcodeop vxaddsubwSat; -:vxaddsubw":sat" Rdd5,rss5,rtt5 EndPacket is iclass=12 & op2127=0x0a & op13=0 & op0507=0 & Rdd5 & rss5 & rtt5 & $(END_PACKET) { +:vxaddsubw":sat" Rdd5,rss5,rtt5 EndPacket is iclass=12 & op2227=0x5 & op0607=0 & op5=0 & Rdd5 & rss5 & rtt5 & $(END_PACKET) { Rdd5 = vxaddsubwSat(rtt5,rss5); build EndPacket; } @@ -16835,11 +17726,11 @@ define pcodeop vxaddsubwSat; # (v4,12) vxsubaddh -- "Rdd32 = vxsubaddh ( Rss32 , Rtt32 ) :rnd :>>1 :sat" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 1 1 0 0 0 0 0 1 1 1 + s s s s s P P + t t t t t 0 1 + d d d d d +# 1 1 0 0 0 0 0 1 1 1 - s s s s s P P - t t t t t 0 1 - d d d d d define pcodeop vxsubaddhRndX2Sat; -:vxsubaddh":rnd:>>1:sat" Rdd5,rss5,rtt5 EndPacket is iclass=12 & op2127=0x0e & op13=0 & op0507=2 & Rdd5 & rss5 & rtt5 & $(END_PACKET) { +:vxsubaddh":rnd:>>1:sat" Rdd5,rss5,rtt5 EndPacket is iclass=12 & op2227=0x7 & op0607=1 & Rdd5 & rss5 & rtt5 & $(END_PACKET) { Rdd5 = vxsubaddhRndX2Sat(rtt5,rss5); build EndPacket; } @@ -16847,11 +17738,11 @@ define pcodeop vxsubaddhRndX2Sat; # (v4,12) vxsubaddh -- "Rdd32 = vxsubaddh ( Rss32 , Rtt32 ) :sat" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 1 1 0 0 0 0 0 1 0 1 + s s s s s P P + t t t t t 1 1 + d d d d d +# 1 1 0 0 0 0 0 1 0 1 - s s s s s P P - t t t t t 1 1 0 d d d d d define pcodeop vxsubaddhSat; -:vxsubaddh":sat" Rdd5,rss5,rtt5 EndPacket is iclass=12 & op2127=0x0a & op13=0 & op0507=6 & Rdd5 & rss5 & rtt5 & $(END_PACKET) { +:vxsubaddh":sat" Rdd5,rss5,rtt5 EndPacket is iclass=12 & op2227=0x5 & op0607=3 & op5=0 & Rdd5 & rss5 & rtt5 & $(END_PACKET) { Rdd5 = vxsubaddhSat(rtt5,rss5); build EndPacket; } @@ -16859,11 +17750,11 @@ define pcodeop vxsubaddhSat; # (v4,12) vxsubaddw -- "Rdd32 = vxsubaddw ( Rss32 , Rtt32 ) :sat" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 1 1 0 0 0 0 0 1 0 1 + s s s s s P P + t t t t t 0 1 + d d d d d +# 1 1 0 0 0 0 0 1 0 1 - s s s s s P P - t t t t t 0 1 0 d d d d d define pcodeop vxsubaddwSat; -:vxsubaddw":sat" Rdd5,rss5,rtt5 EndPacket is iclass=12 & op2127=0x0a & op13=0 & op0507=2 & Rdd5 & rss5 & rtt5 & $(END_PACKET) { +:vxsubaddw":sat" Rdd5,rss5,rtt5 EndPacket is iclass=12 & op2227=0x5 & op0607=1 & op5=0 & Rdd5 & rss5 & rtt5 & $(END_PACKET) { Rdd5 = vxsubaddwSat(rtt5,rss5); build EndPacket; } @@ -16871,11 +17762,11 @@ define pcodeop vxsubaddwSat; # (v2,8) vzxtbh -- "Rdd32 = vzxtbh ( Rs32 )" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 1 0 0 0 0 1 0 0 0 0 + s s s s s P P + + + + + + 0 1 + d d d d d +# 1 0 0 0 0 1 0 0 0 0 - s s s s s P P - - - - - - 0 1 - d d d d d define pcodeop vzxtbh; -:vzxtbh Rdd5,rs5 EndPacket is iclass=8 & op2127=0x20 & op0513=0x02 & Rdd5 & rs5 & $(END_PACKET) { +:vzxtbh Rdd5,rs5 EndPacket is iclass=8 & op2227=0x10 & op0607=0x1 & Rdd5 & rs5 & $(END_PACKET) { Rdd5 = vzxtbh(rs5); build EndPacket; } @@ -16883,9 +17774,9 @@ define pcodeop vzxtbh; # (v2,8) vzxthw -- "Rdd32 = vzxthw ( Rs32 )" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 1 0 0 0 0 1 0 0 0 0 + s s s s s P P + + + + + + 1 1 + d d d d d +# 1 0 0 0 0 1 0 0 0 0 - s s s s s P P - - - - - - 1 1 - d d d d d -:vzxthw Rdd5,rs5 EndPacket is iclass=8 & op2127=0x20 & op0513=0x06 & Rdd5 & rs5 & $(END_PACKET) { +:vzxthw Rdd5,rs5 EndPacket is iclass=8 & op2227=0x10 & op0607=0x3 & Rdd5 & rs5 & $(END_PACKET) { Rdd5[0,32] = zext(rs5[0,16]); Rdd5[32,32] = zext(rs5[16,16]); build EndPacket; @@ -16908,7 +17799,7 @@ define pcodeop wait; # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| # 0 1 1 0 1 0 1 1 0 1 0 0 - - s s P P 0 - - - t t - - - - - - d d -:xor Pd2,pu1617,pu0809 EndPacket is iclass=6 & op2127=0x5a & op1820=0 & op1013=0 & op0207=0 & pu0809 & pu1617 & Pd2 & $(END_PACKET) { +:xor Pd2,pu1617,pu0809 EndPacket is iclass=6 & op2127=0x5a & op20=0 & op13=0 & pu0809 & pu1617 & Pd2 & $(END_PACKET) { Pd2 = Pd2 & (pu1617 ^ pu0809); build EndPacket; } @@ -16936,9 +17827,9 @@ define pcodeop wait; # (v4,14) xor -- "Rx32 &= xor ( Rs32 , Rt32 )" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 1 1 1 0 1 1 1 1 0 1 0 s s s s s P P + t t t t t + 1 0 x x x x x +# 1 1 1 0 1 1 1 1 0 1 0 s s s s s P P 0 t t t t t 0 1 0 x x x x x -:xor&= Rd5,rs5,rt5 EndPacket is iclass=0xe & op2127=0x7a & op13=0 & op0507=2 & rs5 & rt5 & rd5 & Rd5 & $(END_PACKET) +:xor&= Rd5,rs5,rt5 EndPacket is iclass=0xe & op2127=0x7a & op13=0 & op7=0 & op0506=2 & rs5 & rt5 & rd5 & Rd5 & $(END_PACKET) { Rd5 = rd5 & (rs5 ^ rt5); build EndPacket; @@ -16947,9 +17838,9 @@ define pcodeop wait; # (v2,14) xor -- "Rx32 ^= xor ( Rs32 , Rt32 )" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 1 1 1 0 1 1 1 1 1 0 0 s s s s s P P + t t t t t + 1 1 x x x x x +# 1 1 1 0 1 1 1 1 1 0 0 s s s s s P P 0 t t t t t 0 1 1 x x x x x -:xor"^=" Rd5,rs5,rt5 EndPacket is iclass=0xe & op2127=0x7c & op13=0 & op0507=3 & rs5 & rt5 & rd5 & Rd5 & $(END_PACKET) +:xor"^=" Rd5,rs5,rt5 EndPacket is iclass=0xe & op2127=0x7c & op13=0 & op7=0 & op0506=3 & rs5 & rt5 & rd5 & Rd5 & $(END_PACKET) { Rd5 = rd5 ^ (rs5 ^ rt5); build EndPacket; @@ -16958,9 +17849,9 @@ define pcodeop wait; # (v4,14) xor -- "Rx32 |= xor ( Rs32 , Rt32 )" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 1 1 1 0 1 1 1 1 1 1 0 s s s s s P P + t t t t t + 0 1 x x x x x +# 1 1 1 0 1 1 1 1 1 1 0 s s s s s P P 0 t t t t t 0 0 1 x x x x x -:xor|= Rd5,rs5,rt5 EndPacket is iclass=0xe & op2127=0x7e & op13=0 & op0507=1 & rs5 & rt5 & rd5 & Rd5 & $(END_PACKET) +:xor|= Rd5,rs5,rt5 EndPacket is iclass=0xe & op2127=0x7e & op13=0 & op7=0 & op0506=1 & rs5 & rt5 & rd5 & Rd5 & $(END_PACKET) { Rd5 = rd5 | (rs5 ^ rt5); build EndPacket; @@ -16969,9 +17860,9 @@ define pcodeop wait; # (v4,12) xor -- "Rxx32 ^= xor ( Rss32 , Rtt32 )" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 1 1 0 0 1 0 1 0 1 + + s s s s s P P + t t t t t + + + x x x x x +# 1 1 0 0 1 0 1 0 1 0 - s s s s s P P 0 t t t t t 0 0 0 x x x x x -:xor"^=" Rdd5,rss5,rtt5 EndPacket is iclass=0xc & op2127=0x54 & op13=0 & op0507=0 & rss5 & rtt5 & rdd5 & Rdd5 & $(END_PACKET) +:xor"^=" Rdd5,rss5,rtt5 EndPacket is iclass=0xc & op2327=0x15 & op22=0 & op13=0 & op7=0 & op6=0 & op5=0 & rss5 & rtt5 & rdd5 & Rdd5 & $(END_PACKET) { Rdd5 = rdd5 ^ (rss5 ^ rtt5); build EndPacket; @@ -16980,31 +17871,33 @@ define pcodeop wait; # (v2,15) xor -- "if ( Pu4 ) Rd32 = xor ( Rs32 , Rt32 )" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 1 1 1 1 1 0 0 1 + 1 1 s s s s s P P 0 t t t t t 0 u u d d d d d +# 1 1 1 1 1 0 0 1 - 1 1 s s s s s P P 0 t t t t t 0 u u d d d d d # # (v2,15) xor -- "if ( ! Pu4 ) Rd32 = xor ( Rs32 , Rt32 )" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 1 1 1 1 1 0 0 1 + 1 1 s s s s s P P 0 t t t t t 1 u u d d d d d +# 1 1 1 1 1 0 0 1 - 1 1 s s s s s P P 0 t t t t t 1 u u d d d d d # # (v2,15) xor -- "if ( Pu4 .new ) Rd32 = xor ( Rs32 , Rt32 )" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 1 1 1 1 1 0 0 1 + 1 1 s s s s s P P 1 t t t t t 0 u u d d d d d +# 1 1 1 1 1 0 0 1 - 1 1 s s s s s P P 1 t t t t t 0 u u d d d d d # # (v2,15) xor -- "if ( ! Pu4 .new ) Rd32 = xor ( Rs32 , Rt32 )" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 1 1 1 1 1 0 0 1 + 1 1 s s s s s P P 1 t t t t t 1 u u d d d d d +# 1 1 1 1 1 0 0 1 - 1 1 s s s s s P P 1 t t t t t 1 u u d d d d d -:xor^PuCond0506_N13_S07 rd5,rs5,rt5 EndPacket is iclass=15 & op2327=0x12 & op22=1 & op21=1 & PuCond0506_N13_S07 & rs5 & rt5 & rd5 & rd5_ & SetNRegRd5 & $(END_PACKET) { +:xor^PuCond0506_N13_S07 rd5,rs5,rt5 EndPacket is iclass=15 & op2427=0x9 & op22=1 & op21=1 & PuCond0506_N13_S07 & rs5 & rt5 & rd5 & rd5_ & SetNRegRd5 & $(END_PACKET) { build PuCond0506_N13_S07; build EndPacket; <> + build PuCond0506_N13_S07; if (ConditionReg == 0) goto ; rd5_ = rs5 ^ rt5; <> + build PuCond0506_N13_S07; if (ConditionReg == 0) goto ; rd5 = rd5_; @@ -17013,32 +17906,34 @@ define pcodeop wait; # (v4,7) zxtb -- "if ( Pu4 ) Rd32 = zxtb ( Rs32 )" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 0 1 1 1 0 0 0 0 1 0 0 s s s s s P P 1 + 0 0 u u + + + d d d d d +# 0 1 1 1 0 0 0 0 1 0 0 s s s s s P P 1 - 0 0 u u - - - d d d d d # # (v4,7) zxtb -- "if ( ! Pu4 ) Rd32 = zxtb ( Rs32 )" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 0 1 1 1 0 0 0 0 1 0 0 s s s s s P P 1 + 1 0 u u + + + d d d d d +# 0 1 1 1 0 0 0 0 1 0 0 s s s s s P P 1 - 1 0 u u - - - d d d d d # # (v4,7) zxtb -- "if ( Pu4 .new ) Rd32 = zxtb ( Rs32 )" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 0 1 1 1 0 0 0 0 1 0 0 s s s s s P P 1 + 0 1 u u + + + d d d d d +# 0 1 1 1 0 0 0 0 1 0 0 s s s s s P P 1 - 0 1 u u - - - d d d d d # # (v4,7) zxtb -- "if ( ! Pu4 .new ) Rd32 = zxtb ( Rs32 )" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 0 1 1 1 0 0 0 0 1 0 0 s s s s s P P 1 + 1 1 u u + + + d d d d d +# 0 1 1 1 0 0 0 0 1 0 0 s s s s s P P 1 - 1 1 u u - - - d d d d d -:zxtb^PuCond0809_N10_S11 rd5,rs5 EndPacket is iclass=7 & op2127=0x04 & op1213=2 & op0507=0 & rs5 & rd5 & rd5_ & SetNRegRd5 & PuCond0809_N10_S11 & $(END_PACKET) +:zxtb^PuCond0809_N10_S11 rd5,rs5 EndPacket is iclass=7 & op2127=0x04 & op13=1 & rs5 & rd5 & rd5_ & SetNRegRd5 & PuCond0809_N10_S11 & $(END_PACKET) { build PuCond0809_N10_S11; build EndPacket; <> + build PuCond0809_N10_S11; if (ConditionReg == 0) goto ; rd5_ = zext(rs5:1); <> + build PuCond0809_N10_S11; if (ConditionReg == 0) goto ; rd5 = rd5_; @@ -17047,9 +17942,9 @@ define pcodeop wait; # (v2,7) zxth -- "Rd32 = zxth ( Rs32 )" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 0 1 1 1 0 0 0 0 1 1 0 s s s s s P P 0 + + + + + + + + d d d d d +# 0 1 1 1 0 0 0 0 1 1 0 s s s s s P P 0 - - - - - - - - d d d d d -:zxth Rd5,rs5 EndPacket is iclass=7 & op2127=0x06 & op0513=0 & rs5 & Rd5 & $(END_PACKET) +:zxth Rd5,rs5 EndPacket is iclass=7 & op2127=0x06 & op13=0 & rs5 & Rd5 & $(END_PACKET) { Rd5 = zext(rs5:2); build EndPacket; @@ -17058,32 +17953,34 @@ define pcodeop wait; # (v4,7) zxth -- "if ( Pu4 ) Rd32 = zxth ( Rs32 )" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 0 1 1 1 0 0 0 0 1 1 0 s s s s s P P 1 + 0 0 u u + + + d d d d d +# 0 1 1 1 0 0 0 0 1 1 0 s s s s s P P 1 - 0 0 u u - - - d d d d d # # (v4,7) zxth -- "if ( ! Pu4 ) Rd32 = zxth ( Rs32 )" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 0 1 1 1 0 0 0 0 1 1 0 s s s s s P P 1 + 1 0 u u + + + d d d d d +# 0 1 1 1 0 0 0 0 1 1 0 s s s s s P P 1 - 1 0 u u - - - d d d d d # # (v4,7) zxth -- "if ( Pu4 .new ) Rd32 = zxth ( Rs32 )" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 0 1 1 1 0 0 0 0 1 1 0 s s s s s P P 1 + 0 1 u u + + + d d d d d +# 0 1 1 1 0 0 0 0 1 1 0 s s s s s P P 1 - 0 1 u u - - - d d d d d # # (v4,7) zxth -- "if ( ! Pu4 .new ) Rd32 = zxth ( Rs32 )" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 0 1 1 1 0 0 0 0 1 1 0 s s s s s P P 1 + 1 1 u u + + + d d d d d +# 0 1 1 1 0 0 0 0 1 1 0 s s s s s P P 1 - 1 1 u u - - - d d d d d -:zxth^PuCond0809_N10_S11 rd5,rs5 EndPacket is iclass=7 & op2127=0x06 & op1213=2 & op0507=0 & rs5 & rd5 & rd5_ & SetNRegRd5 & PuCond0809_N10_S11 & $(END_PACKET) +:zxth^PuCond0809_N10_S11 rd5,rs5 EndPacket is iclass=7 & op2127=0x06 & op13=1 & rs5 & rd5 & rd5_ & SetNRegRd5 & PuCond0809_N10_S11 & $(END_PACKET) { build PuCond0809_N10_S11; build EndPacket; <> + build PuCond0809_N10_S11; if (ConditionReg == 0) goto ; rd5_ = zext(rs5:2); <> + build PuCond0809_N10_S11; if (ConditionReg == 0) goto ; rd5 = rd5_; @@ -17101,9 +17998,11 @@ JmpRel9: "; jump" RelDest9x is RelDest9x { # (v4,1) jump -- "Rd16 = #U6 ; jump #r9:2x" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 0 0 0 1 - 1 1 0 - - i i d d d d P P I I I I I I i i i i i i i - +# 0 0 0 1 0 1 1 0 - - i i d d d d P P I I I I I I i i i i i i i - +# +# NOTE: jump instruction appears as seperate operand -:assign Rd1619,Uimm8_0813 JmpRel9 EndPacket is iclass=1 & op2426=6 & Uimm8_0813 & Rd1619 & JmpRel9 & $(END_PACKET) { +:assign Rd1619,Uimm8_0813 JmpRel9 EndPacket is iclass=1 & op27=0 & op2426=6 & Uimm8_0813 & Rd1619 & JmpRel9 & $(END_PACKET) { Rd1619 = zext(Uimm8_0813); build EndPacket; } @@ -17111,9 +18010,11 @@ JmpRel9: "; jump" RelDest9x is RelDest9x { # (v4,1) jump -- "Rd16 = Rs16 ; jump #r9:2x" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 0 0 0 1 - 1 1 1 - - i i s s s s P P - - d d d d i i i i i i i - +# 0 0 0 1 0 1 1 1 - - i i s s s s P P - - d d d d i i i i i i i - +# +# NOTE: jump instruction appears as seperate operand -:assign Rd0811,rs4p JmpRel9 EndPacket is iclass=1 & op2426=7 & rs4p & Rd0811 & JmpRel9 & $(END_PACKET) { +:assign Rd0811,rs4p JmpRel9 EndPacket is iclass=1 & op27=0 & op2426=7 & rs4p & Rd0811 & JmpRel9 & $(END_PACKET) { Rd0811 = rs4p; build JmpRel9; build EndPacket; @@ -17122,23 +18023,24 @@ JmpRel9: "; jump" RelDest9x is RelDest9x { # (v4,1) jump:nt -- "Pu1 = cmp.eq ( Rs16 , #-1 ) ; if ( Pu1 .new ) jump:nt #r9:2x" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 0 0 0 1 + 0 u 1 1 0 i i s s s s P P 0 - - - 0 0 i i i i i i i - +# 0 0 0 1 0 0 u 1 1 0 i i s s s s P P 0 - - - 0 0 i i i i i i i - # # (v4,1) jump:nt -- "Pu1 = cmp.eq ( Rs16 , #-1 ) ; if ( ! Pu1 .new ) jump:nt #r9:2x" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 0 0 0 1 + 0 u 1 1 1 i i s s s s P P 0 - - - 0 0 i i i i i i i - +# 0 0 0 1 0 0 u 1 1 1 i i s s s s P P 0 - - - 0 0 i i i i i i i - # # (v4,1) jump:t -- "Pu1 = cmp.eq ( Rs16 , #-1 ) ; if ( Pu1 .new ) jump:t #r9:2x" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 0 0 0 1 + 0 u 1 1 0 i i s s s s P P 1 - - - 0 0 i i i i i i i - +# 0 0 0 1 0 0 u 1 1 0 i i s s s s P P 1 - - - 0 0 i i i i i i i - # # (v4,1) jump:t -- "Pu1 = cmp.eq ( Rs16 , #-1 ) ; if ( ! Pu1 .new ) jump:t #r9:2x" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 0 0 0 1 + 0 u 1 1 1 i i s s s s P P 1 - - - 0 0 i i i i i i i - +# 0 0 0 1 0 0 u 1 1 1 i i s s s s P P 1 - - - 0 0 i i i i i i i - # +# NOTE: jump instruction appears as seperate operand FlowCond_Pu25_S22: ".if("pu25name".new)" is op22=0 & pu25name & pu25_ { tmp:1 = pu25_ & 1; export tmp; } FlowCond_Pu25_S22: ".if(!"pu25name".new)" is op22=1 & pu25name & pu25_ { tmp:1 = !(pu25_ & 1); export tmp; } @@ -17160,22 +18062,24 @@ IfJmpRel9_Pu25_T13_S22: "; jump"^FlowCond_Pu25_S22^Taken13 RelDest9x is FlowCond # (v4,1) jump:nt -- "Pu1 = cmp.eq ( Rs16 , #U5 ) ; if ( Pu1 .new ) jump:nt #r9:2x" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 0 0 0 1 + 0 u 0 0 0 i i s s s s P P 0 I I I I I i i i i i i i - +# 0 0 0 1 0 0 u 0 0 0 i i s s s s P P 0 I I I I I i i i i i i i - # # (v4,1) jump:nt -- "Pu1 = cmp.eq ( Rs16 , #U5 ) ; if ( ! Pu1 .new ) jump:nt #r9:2x" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 0 0 0 1 + 0 u 0 0 1 i i s s s s P P 0 I I I I I i i i i i i i - +# 0 0 0 1 0 0 u 0 0 1 i i s s s s P P 0 I I I I I i i i i i i i - # # (v4,1) jump:t -- "Pu1 = cmp.eq ( Rs16 , #U5 ) ; if ( Pu1 .new ) jump:t #r9:2x" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 0 0 0 1 + 0 u 0 0 0 i i s s s s P P 1 I I I I I i i i i i i i - +# 0 0 0 1 0 0 u 0 0 0 i i s s s s P P 1 I I I I I i i i i i i i - # # (v4,1) jump:t -- "Pu1 = cmp.eq ( Rs16 , #U5 ) ; if ( ! Pu1 .new ) jump:t #r9:2x" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 0 0 0 1 + 0 u 0 0 1 i i s s s s P P 1 I I I I I i i i i i i i - +# 0 0 0 1 0 0 u 0 0 1 i i s s s s P P 1 I I I I I i i i i i i i - +# +# NOTE: jump instruction appears as seperate operand :cmp.eq Pd25,rs4p,Uimm8_0812 IfJmpRel9_Pu25_T13_S22 EndPacket is iclass=1 & op2627=0 & op2324=0 & Pd25 & rs4p & Uimm8_0812 & IfJmpRel9_Pu25_T13_S22 & $(END_PACKET) { bool:1 = (rs4p == zext(Uimm8_0812)); @@ -17187,22 +18091,24 @@ IfJmpRel9_Pu25_T13_S22: "; jump"^FlowCond_Pu25_S22^Taken13 RelDest9x is FlowCond # (v4,1) jump:nt -- "Pu1 = cmp.eq ( Rs16 , Rt16 ) ; if ( Pu1 .new ) jump:nt #r9:2x" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 0 0 0 1 + 1 0 0 0 0 i i s s s s P P 0 u t t t t i i i i i i i - +# 0 0 0 1 - 1 0 0 0 0 i i s s s s P P 0 u t t t t i i i i i i i - # # (v4,1) jump:nt -- "Pu1 = cmp.eq ( Rs16 , Rt16 ) ; if ( ! Pu1 .new ) jump:nt #r9:2x" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 0 0 0 1 + 1 0 0 0 1 i i s s s s P P 0 u t t t t i i i i i i i - +# 0 0 0 1 - 1 0 0 0 1 i i s s s s P P 0 u t t t t i i i i i i i - # # (v4,1) jump:t -- "Pu1 = cmp.eq ( Rs16 , Rt16 ) ; if ( Pu1 .new ) jump:t #r9:2x" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 0 0 0 1 + 1 0 0 0 0 i i s s s s P P 1 u t t t t i i i i i i i - +# 0 0 0 1 - 1 0 0 0 0 i i s s s s P P 1 u t t t t i i i i i i i - # # (v4,1) jump:t -- "Pu1 = cmp.eq ( Rs16 , Rt16 ) ; if ( ! Pu1 .new ) jump:t #r9:2x" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 0 0 0 1 + 1 0 0 0 1 i i s s s s P P 1 u t t t t i i i i i i i - +# 0 0 0 1 - 1 0 0 0 1 i i s s s s P P 1 u t t t t i i i i i i i - +# +# NOTE: jump instruction appears as seperate operand FlowCond_Pu12_S22: ".if("pu12name".new)" is op22=0 & pu12name & pu12_ { tmp:1 = pu12_ & 1; export tmp; } FlowCond_Pu12_S22: ".if(!"pu12name".new)" is op22=1 & pu12name & pu12_ { tmp:1 = !(pu12_ & 1); export tmp; } @@ -17214,7 +18120,7 @@ IfJmpRel9_Pu12_T13_S22: "; jump"^FlowCond_Pu12_S22^Taken13 RelDest9x is FlowCond } -:cmp.eq Pd12,rs4p,rt4p IfJmpRel9_Pu12_T13_S22 EndPacket is iclass=1 & op2327=8 & Pd12 & rs4p & rt4p & IfJmpRel9_Pu12_T13_S22 & $(END_PACKET) { +:cmp.eq Pd12,rs4p,rt4p IfJmpRel9_Pu12_T13_S22 EndPacket is iclass=1 & op2326=8 & Pd12 & rs4p & rt4p & IfJmpRel9_Pu12_T13_S22 & $(END_PACKET) { bool:1 = (rs4p == rt4p); Pd12 = Pd12 & (bool * 0xff); build IfJmpRel9_Pu12_T13_S22; @@ -17224,22 +18130,24 @@ IfJmpRel9_Pu12_T13_S22: "; jump"^FlowCond_Pu12_S22^Taken13 RelDest9x is FlowCond # (v4,1) jump:nt -- "Pu1 = cmp.gt ( Rs16 , #-1 ) ; if ( Pu1 .new ) jump:nt #r9:2x" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 0 0 0 1 + 0 u 1 1 0 i i s s s s P P 0 - - - 0 1 i i i i i i i - +# 0 0 0 1 0 0 u 1 1 0 i i s s s s P P 0 - - - 0 1 i i i i i i i - # # (v4,1) jump:nt -- "Pu1 = cmp.gt ( Rs16 , #-1 ) ; if ( ! Pu1 .new ) jump:nt #r9:2x" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 0 0 0 1 + 0 u 1 1 1 i i s s s s P P 0 - - - 0 1 i i i i i i i - +# 0 0 0 1 0 0 u 1 1 1 i i s s s s P P 0 - - - 0 1 i i i i i i i - # # (v4,1) jump:t -- "Pu1 = cmp.gt ( Rs16 , #-1 ) ; if ( Pu1 .new ) jump:t #r9:2x" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 0 0 0 1 + 0 u 1 1 0 i i s s s s P P 1 - - - 0 1 i i i i i i i - +# 0 0 0 1 0 0 u 1 1 0 i i s s s s P P 1 - - - 0 1 i i i i i i i - # # (v4,1) jump:t -- "Pu1 = cmp.gt ( Rs16 , #-1 ) ; if ( ! Pu1 .new ) jump:t #r9:2x" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 0 0 0 1 + 0 u 1 1 1 i i s s s s P P 1 - - - 0 1 i i i i i i i - +# 0 0 0 1 0 0 u 1 1 1 i i s s s s P P 1 - - - 0 1 i i i i i i i - +# +# NOTE: jump instruction appears as seperate operand :cmp.gt Pd25,rs4p,MinusOne IfJmpRel9_Pu25_T13_S22 EndPacket is iclass=1 & op2627=0 & op2324=3 & op0809=1 & Pd25 & rs4p & MinusOne & IfJmpRel9_Pu25_T13_S22 & $(END_PACKET) { bool:1 = (rs4p s> -1); @@ -17251,22 +18159,24 @@ IfJmpRel9_Pu12_T13_S22: "; jump"^FlowCond_Pu12_S22^Taken13 RelDest9x is FlowCond # (v4,1) jump:nt -- "Pu1 = cmp.gt ( Rs16 , #U5 ) ; if ( Pu1 .new ) jump:nt #r9:2x" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 0 0 0 1 + 0 u 0 1 0 i i s s s s P P 0 I I I I I i i i i i i i - +# 0 0 0 1 0 0 u 0 1 0 i i s s s s P P 0 I I I I I i i i i i i i - # # (v4,1) jump:nt -- "Pu1 = cmp.gt ( Rs16 , #U5 ) ; if ( ! Pu1 .new ) jump:nt #r9:2x" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 0 0 0 1 + 0 u 0 1 1 i i s s s s P P 0 I I I I I i i i i i i i - +# 0 0 0 1 0 0 u 0 1 1 i i s s s s P P 0 I I I I I i i i i i i i - # # (v4,1) jump:t -- "Pu1 = cmp.gt ( Rs16 , #U5 ) ; if ( Pu1 .new ) jump:t #r9:2x" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 0 0 0 1 + 0 u 0 1 0 i i s s s s P P 1 I I I I I i i i i i i i - +# 0 0 0 1 0 0 u 0 1 0 i i s s s s P P 1 I I I I I i i i i i i i - # # (v4,1) jump:t -- "Pu1 = cmp.gt ( Rs16 , #U5 ) ; if ( ! Pu1 .new ) jump:t #r9:2x" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 0 0 0 1 + 0 u 0 1 1 i i s s s s P P 1 I I I I I i i i i i i i - +# 0 0 0 1 0 0 u 0 1 1 i i s s s s P P 1 I I I I I i i i i i i i - +# +# NOTE: jump instruction appears as seperate operand :cmp.gt Pd25,rs4p,Uimm8_0812 IfJmpRel9_Pu25_T13_S22 EndPacket is iclass=1 & op2627=0 & op2324=1 & Pd25 & rs4p & Uimm8_0812 & IfJmpRel9_Pu25_T13_S22 & $(END_PACKET) { bool:1 = (rs4p s> zext(Uimm8_0812)); @@ -17278,24 +18188,26 @@ IfJmpRel9_Pu12_T13_S22: "; jump"^FlowCond_Pu12_S22^Taken13 RelDest9x is FlowCond # (v4,1) jump:nt -- "Pu1 = cmp.gt ( Rs16 , Rt16 ) ; if ( Pu1 .new ) jump:nt #r9:2x" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 0 0 0 1 + 1 0 0 1 0 i i s s s s P P 0 u t t t t i i i i i i i - +# 0 0 0 1 - 1 0 0 1 0 i i s s s s P P 0 u t t t t i i i i i i i - # # (v4,1) jump:nt -- "Pu1 = cmp.gt ( Rs16 , Rt16 ) ; if ( ! Pu1 .new ) jump:nt #r9:2x" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 0 0 0 1 + 1 0 0 1 1 i i s s s s P P 0 u t t t t i i i i i i i - +# 0 0 0 1 - 1 0 0 1 1 i i s s s s P P 0 u t t t t i i i i i i i - # # (v4,1) jump:t -- "Pu1 = cmp.gt ( Rs16 , Rt16 ) ; if ( Pu1 .new ) jump:t #r9:2x" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 0 0 0 1 + 1 0 0 1 0 i i s s s s P P 1 u t t t t i i i i i i i - +# 0 0 0 1 - 1 0 0 1 0 i i s s s s P P 1 u t t t t i i i i i i i - # # (v4,1) jump:t -- "Pu1 = cmp.gt ( Rs16 , Rt16 ) ; if ( ! Pu1 .new ) jump:t #r9:2x" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 0 0 0 1 + 1 0 0 1 1 i i s s s s P P 1 u t t t t i i i i i i i - +# 0 0 0 1 - 1 0 0 1 1 i i s s s s P P 1 u t t t t i i i i i i i - +# +# NOTE: jump instruction appears as seperate operand -:cmp.gt Pd12,rs4p,rt4p IfJmpRel9_Pu12_T13_S22 EndPacket is iclass=1 & op2327=9 & Pd12 & rs4p & rt4p & IfJmpRel9_Pu12_T13_S22 & $(END_PACKET) { +:cmp.gt Pd12,rs4p,rt4p IfJmpRel9_Pu12_T13_S22 EndPacket is iclass=1 & op2326=9 & Pd12 & rs4p & rt4p & IfJmpRel9_Pu12_T13_S22 & $(END_PACKET) { bool:1 = (rs4p s> rt4p); Pd12 = Pd12 & (bool * 0xff); build IfJmpRel9_Pu12_T13_S22; @@ -17305,22 +18217,24 @@ IfJmpRel9_Pu12_T13_S22: "; jump"^FlowCond_Pu12_S22^Taken13 RelDest9x is FlowCond # (v4,1) jump:nt -- "Pu1 = cmp.gtu ( Rs16 , #U5 ) ; if ( Pu1 .new ) jump:nt #r9:2x" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 0 0 0 1 + 0 u 1 0 0 i i s s s s P P 0 I I I I I i i i i i i i - +# 0 0 0 1 0 0 u 1 0 0 i i s s s s P P 0 I I I I I i i i i i i i - # # (v4,1) jump:nt -- "Pu1 = cmp.gtu ( Rs16 , #U5 ) ; if ( ! Pu1 .new ) jump:nt #r9:2x" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 0 0 0 1 + 0 u 1 0 1 i i s s s s P P 0 I I I I I i i i i i i i - +# 0 0 0 1 0 0 u 1 0 1 i i s s s s P P 0 I I I I I i i i i i i i - # # (v4,1) jump:t -- "Pu1 = cmp.gtu ( Rs16 , #U5 ) ; if ( Pu1 .new ) jump:t #r9:2x" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 0 0 0 1 + 0 u 1 0 0 i i s s s s P P 1 I I I I I i i i i i i i - +# 0 0 0 1 0 0 u 1 0 0 i i s s s s P P 1 I I I I I i i i i i i i - # # (v4,1) jump:t -- "Pu1 = cmp.gtu ( Rs16 , #U5 ) ; if ( ! Pu1 .new ) jump:t #r9:2x" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 0 0 0 1 + 0 u 1 0 1 i i s s s s P P 1 I I I I I i i i i i i i - +# 0 0 0 1 0 0 u 1 0 1 i i s s s s P P 1 I I I I I i i i i i i i - +# +# NOTE: jump instruction appears as seperate operand :cmp.gtu Pd25,rs4p,Uimm8_0812 IfJmpRel9_Pu25_T13_S22 EndPacket is iclass=1 & op2627=0 & op2324=2 & Pd25 & rs4p & Uimm8_0812 & IfJmpRel9_Pu25_T13_S22 & $(END_PACKET) { bool:1 = (rs4p > zext(Uimm8_0812)); @@ -17332,24 +18246,26 @@ IfJmpRel9_Pu12_T13_S22: "; jump"^FlowCond_Pu12_S22^Taken13 RelDest9x is FlowCond # (v4,1) jump:nt -- "Pu1 = cmp.gtu ( Rs16 , Rt16 ) ; if ( Pu1 .new ) jump:nt #r9:2x" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 0 0 0 1 + 1 0 1 0 0 i i s s s s P P 0 u t t t t i i i i i i i - +# 0 0 0 1 - 1 0 1 0 0 i i s s s s P P 0 u t t t t i i i i i i i - # # (v4,1) jump:nt -- "Pu1 = cmp.gtu ( Rs16 , Rt16 ) ; if ( ! Pu1 .new ) jump:nt #r9:2x" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 0 0 0 1 + 1 0 1 0 1 i i s s s s P P 0 u t t t t i i i i i i i - +# 0 0 0 1 - 1 0 1 0 1 i i s s s s P P 0 u t t t t i i i i i i i - # # (v4,1) jump:t -- "Pu1 = cmp.gtu ( Rs16 , Rt16 ) ; if ( Pu1 .new ) jump:t #r9:2x" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 0 0 0 1 + 1 0 1 0 0 i i s s s s P P 1 u t t t t i i i i i i i - +# 0 0 0 1 - 1 0 1 0 0 i i s s s s P P 1 u t t t t i i i i i i i - # # (v4,1) jump:t -- "Pu1 = cmp.gtu ( Rs16 , Rt16 ) ; if ( ! Pu1 .new ) jump:t #r9:2x" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 0 0 0 1 + 1 0 1 0 1 i i s s s s P P 1 u t t t t i i i i i i i - +# 0 0 0 1 - 1 0 1 0 1 i i s s s s P P 1 u t t t t i i i i i i i - +# +# NOTE: jump instruction appears as seperate operand -:cmp.gtu Pd12,rs4p,rt4p IfJmpRel9_Pu12_T13_S22 EndPacket is iclass=1 & op2327=0xa & Pd12 & rs4p & rt4p & IfJmpRel9_Pu12_T13_S22 & $(END_PACKET) { +:cmp.gtu Pd12,rs4p,rt4p IfJmpRel9_Pu12_T13_S22 EndPacket is iclass=1 & op2326=0xa & Pd12 & rs4p & rt4p & IfJmpRel9_Pu12_T13_S22 & $(END_PACKET) { bool:1 = (rs4p > rt4p); Pd12 = Pd12 & (bool * 0xff); build IfJmpRel9_Pu12_T13_S22; @@ -17359,22 +18275,24 @@ IfJmpRel9_Pu12_T13_S22: "; jump"^FlowCond_Pu12_S22^Taken13 RelDest9x is FlowCond # (v4,1) jump:nt -- "Pu1 = tstbit ( Rs16 , #0 ) ; if ( Pu1 .new ) jump:nt #r9:2x" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 0 0 0 1 + 0 u 1 1 0 i i s s s s P P 0 - - - 1 1 i i i i i i i - +# 0 0 0 1 0 0 u 1 1 0 i i s s s s P P 0 - - - 1 1 i i i i i i i - # # (v4,1) jump:nt -- "Pu1 = tstbit ( Rs16 , #0 ) ; if ( ! Pu1 .new ) jump:nt #r9:2x" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 0 0 0 1 + 0 u 1 1 1 i i s s s s P P 0 - - - 1 1 i i i i i i i - +# 0 0 0 1 0 0 u 1 1 1 i i s s s s P P 0 - - - 1 1 i i i i i i i - # # (v4,1) jump:t -- "Pu1 = tstbit ( Rs16 , #0 ) ; if ( Pu1 .new ) jump:t #r9:2x" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 0 0 0 1 + 0 u 1 1 0 i i s s s s P P 1 - - - 1 1 i i i i i i i - +# 0 0 0 1 0 0 u 1 1 0 i i s s s s P P 1 - - - 1 1 i i i i i i i - # # (v4,1) jump:t -- "Pu1 = tstbit ( Rs16 , #0 ) ; if ( ! Pu1 .new ) jump:t #r9:2x" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 0 0 0 1 + 0 u 1 1 1 i i s s s s P P 1 - - - 1 1 i i i i i i i - +# 0 0 0 1 0 0 u 1 1 1 i i s s s s P P 1 - - - 1 1 i i i i i i i - +# +# NOTE: jump instruction appears as seperate operand :tstbit Pd25,rs4p,Zero IfJmpRel9_Pu25_T13_S22 EndPacket is iclass=1 & op2627=0 & op2324=3 & op0809=3 & Pd25 & rs4p & Zero & IfJmpRel9_Pu25_T13_S22 & $(END_PACKET) { bool:1 = (rs4p & 1) != 0; diff --git a/pypcode/processors/Hexagon/data/languages/hexagon.slaspec b/pypcode/processors/Hexagon/data/languages/hexagon.slaspec index 778d7a7..1d1e25f 100755 --- a/pypcode/processors/Hexagon/data/languages/hexagon.slaspec +++ b/pypcode/processors/Hexagon/data/languages/hexagon.slaspec @@ -1,13 +1,18 @@ -# Qualcomm Hexagon (V73) and HVX (V69) +# Qualcomm Hexagon (V79) and HVX (V79) ## KNOWN ISSUES -# 1. Shift amounts may be positive or negative, however in some cases no special handling -# is provided for negative shift amounts. +# 1. Shift amounts may be positive or negative. The register-form shifts model the +# 7-bit signed shift amount explicitly; other forms may still assume a positive amount. # 2. There are many complex instructions with unimplemented pcode or simple custom pcodeops # ## NOTES -# 1. Implementation includes V73 system registers, instruction set may be incomplete -# 2. HVX vector register size is 128-bytes (see defines below), paired size is 256-bytes +# 1. Implementation includes V73 system registers, instruction set may be incomplete. +# Decode additionally covers the V66 ZReg matrix extension and V81 valign4 as +# decode-only stubs (unimpl pcode). +# 2. HVX register pairs may be access with a vector-swap mode (lsb of 5-bit field is 1) +# introduced with Hexagon v67. +# 3. HVX vector register size is 128-bytes (see defines below), paired size is 256-bytes, +# and HVX-v2 quad size is 512-bytes. Quads appear only in the V66+ ZReg extension. # ## VERSIONS # 1.x - preliminary versions (pre-release) @@ -18,10 +23,25 @@ # ADD_DP_OPS property has been used to contain these although they may be removed # in the future. # 2.4 - Added EXEC_COND crossbuild (12.0.1) and added HVX support (12.0.2) +# 2.5 - 1) Corrected improper reserved/dont-care-bit use in patterns. Bits documented as +# having a value of '-' are not constrained and will match with either a '0' or '1'; +# although the PRM declares these as "reserved" and states they should be encoded +# as '0' when emitted by a compiler/assembler. +# 2) added many missing instructions, +# 3) add support for vector-pair addressing mode with vector-swap mode, +# 4) expanded HVX support (quad-vector instructions not yet supported). # @define HVX_VECTOR_SIZE "128" +@define HVX_VECTOR_SIZE_BITS "1024" + +# Byte offset of a word within a vector: (Rs & (HVX_VECTOR_SIZE-1)) & ~0x3, pre-folded so the +# p-code is a single INT_AND instead of three ops on constants. Keep in step with HVX_VECTOR_SIZE. +@define HVX_VECTOR_WORD_MASK "0x7c" + @define HVX_VECTOR_PAIR_SIZE "256" +@define HVX_VECTOR_QUAD_SIZE "512" + @define HVX_VECTOR_BASE "0x2000" @define HVX_VECTOR_TMP_BASE "0x3000" @@ -85,6 +105,12 @@ define register offset=0x200 size=4 [ SA0 LC0 SA1 LC1 P3P0 C5 M0 M1 define register offset=0x210 size=1 [ P3 P2 P1 P0 ]; # corresponds to P3P0 # TODO: Do ALL of the control registers need shadows for writing/flushing ?? + +# NOTE/TODO: System registers (S0..S63), guest registers (G0..G31), and supervisor registers lack shadow versions. +# Writes to these registers currently bypass the deferred-commit mechanism. In user-mode programs this is +# rarely an issue; kernel-mode programs that write system registers within a multi-instruction execute +# packet may observe incorrect semantics. + define register offset=0x300 size=8 [ C1C0_ C3C2_ C5C4_ C7C6_ C9C8_ C11C10_ C13C12_ UPCYCLE_ C17C16_ PKTCOUNT_ C21C20_ C23C22_ C25C24_ C27C26_ C29C28_ UTIMER_ ]; @@ -143,6 +169,11 @@ define register offset=0x1000 size=1 [ ConditionReg ]; define register offset=0x1004 size=4 [ ReturnAddr ]; +# Quad-vector registers (not yet supported) +#define register offset=$(HVX_VECTOR_BASE) size=$(HVX_VECTOR_QUAD_SIZE) +# [ V3V0 V7V4 V11V8 V15V12 V19V16 V23V20 V27V24 V31V28 ]; + +# Paired-vector registers define register offset=$(HVX_VECTOR_BASE) size=$(HVX_VECTOR_PAIR_SIZE) [ V1V0 V3V2 V5V4 V7V6 V9V8 V11V10 V13V12 V15V14 V17V16 V19V18 V21V20 V23V22 V25V24 V27V26 V29V28 V31V30 ]; @@ -157,11 +188,15 @@ define register offset=$(HVX_VECTOR_BASE) size=$(HVX_VECTOR_SIZE) # HVX vector temporary / shadow registers # +# Quad-vector registers (not yet supported) +#define register offset=$(HVX_VECTOR_TMP_BASE) size=$(HVX_VECTOR_QUAD_SIZE) +# [ V3V0_ V7V4_ V11V8_ V15V12_ V19V16_ V23V20_ V27V24_ V31V28_ ]; + +# Paired-vector registers define register offset=$(HVX_VECTOR_TMP_BASE) size=$(HVX_VECTOR_PAIR_SIZE) [ V1V0_ V3V2_ V5V4_ V7V6_ V9V8_ V11V10_ V13V12_ V15V14_ V17V16_ V19V18_ V21V20_ V23V22_ V25V24_ V27V26_ V29V28_ V31V30_ ]; - define register offset=$(HVX_VECTOR_TMP_BASE) size=$(HVX_VECTOR_SIZE) [ V0.new V1.new V2.new V3.new V4.new V5.new V6.new V7.new V8.new V9.new V10.new V11.new V12.new V13.new V14.new V15.new @@ -208,7 +243,8 @@ define context contextreg nreg1 = (41,45) noflow #(keep) slot-1 assigned reg (raw reg-number) nreg2 = (46,50) noflow #(keep) slot-2 assigned reg (raw reg-number) - removed1 = (51,55) noflow # no longer used - available for reuse + tmpvreg = (51,55) noflow # .tmp vector register (raw reg-number) + tmpvreg_ = (51,55) noflow # .tmp vector shadow register # xreg - tracks immext use required for Ns8 and Os8 new register tracking xreg = (56,60) noflow #(keep) slot reduction count when identifying nreg assignment slot @@ -280,6 +316,9 @@ define token instr (32) op1820 = (18,20) op1827 = (18,27) op1720 = (17,20) + op1628 = (16,28) + op1619 = (16,19) + op1618 = (16,18) op1620 = (16,20) op1617 = (16,17) op1213 = (12,13) @@ -316,6 +355,7 @@ define token instr (32) op0004 = (0,4) op0002 = (0,2) op0001 = (0,1) + op0102 = (1,2) op27 = (27,27) op26 = (26,26) @@ -421,24 +461,24 @@ define token instr (32) pu2324 = (23,24) # 8-bit predicate reg pu2122 = (21,22) # 8-bit predicate reg - pu2122_ = (21,22) # 8-bit predicate reg (shadow) + pu2122_ = (21,22) # 8-bit predicate reg, shadow pu2122name = (21,22) # 8-bit predicate reg (name) pu1617 = (16,17) # 8-bit predicate reg pu1112 = (11,12) # 8-bit predicate reg - pu1112_ = (11,12) # 8-bit predicate reg (shadow) + pu1112_ = (11,12) # 8-bit predicate reg, shadow pu1112name = (11,12) # 8-bit predicate reg (name) pu0910 = (9,10) # 8-bit predicate reg - pu0910_ = (9,10) # 8-bit predicate reg (shadow) + pu0910_ = (9,10) # 8-bit predicate reg, shadow pu0910name = (9,10) # 8-bit predicate reg (name) pu0809 = (8,9) # 8-bit predicate reg - pu0809_ = (8,9) # 8-bit predicate reg (shadow) + pu0809_ = (8,9) # 8-bit predicate reg, shadow pu0809name = (8,9) # 8-bit predicate reg (name) pu0607 = (6,7) # 8-bit predicate reg pu0506 = (5,6) # 8-bit predicate reg - pu0506_ = (5,6) # 8-bit predicate reg (shadow) + pu0506_ = (5,6) # 8-bit predicate reg, shadow pu0506name = (5,6) # 8-bit predicate reg (name) pu0001 = (0,1) # 8-bit predicate reg - pu0001_ = (0,1) # 8-bit predicate reg (shadow) + pu0001_ = (0,1) # 8-bit predicate reg, shadow pu0001name = (0,1) # 8-bit predicate reg (name) pu25 = (25,25) # P0/P1 @@ -469,17 +509,16 @@ define token instr (32) rss5h = (16,20) # 32-bit high reg for rss5 rxx5 = (16,20) # 64-bit general reg - rxx5_ = (16,20) # 64-bit general reg (shadow) + rxx5_ = (16,20) # 64-bit general reg, shadow rx5 = (16,20) # 32-bit general reg - rx5_ = (16,20) # 32-bit general reg (shadow) + rx5_ = (16,20) # 32-bit general reg, shadow rf5 = (16,20) # 32-bit general reg - rf5_ = (16,20) # 32-bit general reg (shadow) + rf5_ = (16,20) # 32-bit general reg, shadow rx5H = (16,20) # 16-bit general reg (high halfword) rx5H_ = (16,20) # 16-bit general reg (high halfword, shadow) rx5L = (16,20) # 16-bit general reg (low halfword) rx5L_ = (16,20) # 16-bit general reg (low halfword, shadow) - rtt5 = (8,12) # 64-bit general reg rtt5h = (8,12) # 32-bit high reg for rtt5 rt5 = (8,12) # 32-bit general reg @@ -487,23 +526,23 @@ define token instr (32) rt5L = (8,12) # 16-bit general reg (low halfword) rd0812 = (8,12) # 32-bit general reg - rd0812_ = (8,12) # 32-bit general reg (shadow) + rd0812_ = (8,12) # 32-bit general reg, shadow rdd0812 = (8,12) # 64-bit general reg - rdd0812_ = (8,12) # 64-bit general reg (shadow) + rdd0812_ = (8,12) # 64-bit general reg, shadow rd5 = (0,4) # 32-bit general reg - rd5_ = (0,4) # 32-bit general reg (shadow) + rd5_ = (0,4) # 32-bit general reg, shadow rdd5 = (0,4) # 64-bit general reg - rdd5_ = (0,4) # 64-bit general reg (shadow) + rdd5_ = (0,4) # 64-bit general reg, shadow rdd5h = (0,4) # hi (odd) 32-bit reg of a 64-bit general reg (use rd5 for lo/even) - rdd5h_ = (0,4) # hi (odd) 32-bit reg of a 64-bit general reg (use rd5 for lo/even) (shadow) + rdd5h_ = (0,4) # hi (odd) 32-bit reg of a 64-bit general reg (use rd5 for lo/even), shadow - rt1618 = (16,18) # 32-bit general reg (r0..r7) + rt1618 = (16,18) # 32-bit general reg (r0..r7) cd5 = (0,4) # 32-bit control reg - cd5_ = (0,4) # 32-bit control reg (shadow) + cd5_ = (0,4) # 32-bit control reg, shadow cdd5 = (0,4) # dual 32-bit control reg - cdd5_ = (0,4) # dual 32-bit control reg (shadow) + cdd5_ = (0,4) # dual 32-bit control reg, shadow gd5 = (0,4) # 32-bit guest reg gdd5 = (0,4) # dual 32-bit guest regs @@ -513,31 +552,41 @@ define token instr (32) ru5H = (0,4) # 16-bit general reg (high halfword) ru5L = (0,4) # 16-bit general reg (low halfword) - vdd5 = (0,4) # HVX vector register pair - vdd5_ = (0,4) # HVX vector register pair (shadow) - - vss5 = (0,4) # HVX vector register pair + vdddd3 = (2,4) # HVX quad-vector register + vdddd3_ = (2,4) # HVX quad-vector register, shadow + + vssss3 = (2,4) # HVX quad-vector register + vssss3_ = (2,4) # HVX quad-vector register, shadow + + vdd4 = (1,4) # HVX vector register pair (4-msb of 5-bit field) + vdd4h = (1,4) # most-significant vector of a vdd4 vector-pair + vdd4l = (1,4) # least-significant vector of a vdd4 vector-pair + vdd4R = (1,4) # HVX vector register pair reversed name attach + vddM = (0,0) # HVX vector register pair, mode (lsb of 5-bit field; 1=swap vectors) + vdd4_ = (1,4) # HVX vector register pair, shadow (4-msb of 5-bit field) + + vss4 = (1,4) # HVX vector register pair (4-msb of 5-bit field) + vss4R = (1,4) # HVX vector register pair reversed name attach + vssM = (0,0) # HVX vector register pair, mode (lsb of 5-bit field; 1=swap vectors) - vuu5 = (8,12) # HVX vector register pair -# vuu5_ = (8,12) # HVX vector register pair (shadow) + vuu4 = (9,12) # HVX vector register pair (4-msb of 5-bit field) + vuu4R = (9,12) # HVX vector register pair reversed name attach + vuuM = (8,8) # HVX vector register pair, mode (lsb of 5-bit field; 1=swap vectors) - vvv5 = (16,20) # HVX vector register pair -# vvv5_ = (16,20) # HVX vector register pair (shadow) + vvv4 = (17,20) # HVX vector register pair (4-msb of 5-bit field) + vvv4R = (17,20) # HVX vector register pair reversed name attach + vvvM = (16,16) # HVX vector register pair, mode (lsb of 5-bit field; 1=swap vectors) vd5 = (0,4) # HVX vector register - vd5_ = (0,4) # HVX vector register (shadow) + vd5_ = (0,4) # HVX vector register, shadow vs5 = (0,4) # HVX vector register -# vs5_ = (0,4) # HVX vector register (shadow) vu5 = (8,12) # HVX vector register -# vu5_ = (8,12) # HVX vector register (shadow) vv5 = (16,20) # HVX vector register -# vv5_ = (16,20) # HVX vector register (shadow) vz5 = (19,23) # HVX vector register -# vz5_ = (19,23) # HVX vector register (shadow) nreg_1618 = (16,18) # Ns8 32-bit general register .new (3-bit encoded) nreg_0810 = (8,10) # Ns8 32-bit general register .new (3-bit encoded) @@ -554,27 +603,27 @@ define token instr (32) rs4p = (16,19) # 16-bit general reg rt4p = (8,11) # 16-bit general reg rd0811 = (8,11) # 16-bit general reg - rd0811_ = (8,11) # 16-bit general reg (shadow) + rd0811_ = (8,11) # 16-bit general reg, shadow rd1619 = (16,19) # 16-bit general reg - rd1619_ = (16,19) # 16-bit general reg (shadow) + rd1619_ = (16,19) # 16-bit general reg, shadow # duplex/packed fields - left side (register attachments are somewhat assumed) rdd3l = (16,18) # 64-bit general reg - rdd3l_ = (16,18) # 64-bit general reg (shadow) + rdd3l_ = (16,18) # 64-bit general reg, shadow rtt3l = (16,18) # 64-bit general reg rd4l = (16,19) # 32-bit general reg - rd4l_ = (16,19) # 32-bit general reg (shadow) + rd4l_ = (16,19) # 32-bit general reg, shadow rt4l = (16,19) # 32-bit general reg rs4l = (20,23) # 32-bit general reg # duplex/packed fields - right side (register attachments are somewhat assumed) rdd3r = (0,2) # 64-bit general reg - rdd3r_ = (0,2) # 64-bit general reg + rdd3r_ = (0,2) # 64-bit general reg, shadow rtt3r = (0,2) # 64-bit general reg rd4r = (0,3) # 32-bit general reg - rd4r_ = (0,3) # 32-bit general reg (shadow) + rd4r_ = (0,3) # 32-bit general reg, shadow rs4r = (4,7) # 32-bit general reg rt4r = (0,3) # 32-bit general reg ; @@ -734,11 +783,38 @@ attach variables [ gs5 gd5 ] [ # TODO: Shadow reg's not implemented for guest re # We currently do not name lane-access registers and rely on lane access sizes as # defined by the pspec. -# double-vector reg selector is 5-bits - the LS bit must always be 0 (even reg) - -attach variables [ vdd5 vss5 vuu5 vvv5 ] - [ V1V0 _ V3V2 _ V5V4 _ V7V6 _ V9V8 _ V11V10 _ V13V12 _ V15V14 _ - V17V16 _ V19V18 _ V21V20 _ V23V22 _ V25V24 _ V27V26 _ V29V28 _ V31V30 _ ]; +# Double-vector reg selector is 5-bits +# The most-significant 4 bits of the 5-bit field select one of the 16 vector pairs +# The least-significant-bit meaning depends on architecture version, although the +# disassembler follow v67 convention: +# - through V66: the LSB must be 0. Odd encodings are reserved/invalid, and the pair +# is always written high:low as Vodd:Veven (e.g. v1:0). +# - V67 and later: the LSB selects pair order. LSB=0 is the normal pair (v1:0), +# LSB=1 is the reversed pair (v0:1) - the same two registers with the high/low +# roles swapped. +# NOTE: Swapped ordering has issues preserving varnode storage relationship between: +# individual vector regs, normal paired-vector and reversed paired-vector. The +# reversed paired-vector cannot be treated as a single atomic varnode and relies +# on pcode manipulation to perform the vector swap. + +# Quad vector attach (not supported) +#attach variables [ vdddd3 vssss3 ] +# [ V3V0 V7V4 V11V8 V15V12 V19V16 V23V20 V27V24 V31V28 ]; + +attach variables [ vdd4 vss4 vuu4 vvv4 ] + [ V1V0 V3V2 V5V4 V7V6 V9V8 V11V10 V13V12 V15V14 + V17V16 V19V18 V21V20 V23V22 V25V24 V27V26 V29V28 V31V30 ]; + +# Paired vector swapped-mode (reversed name attach) +attach names [ vdd4R vss4R vuu4R vvv4R ] + [ "V0:1" "V2:3" "V4:5" "V6:7" "V8:9" "V10:11" "V12:13" "V14:15" + "V16:17" "V18:19" "V20:21" "V22:23" "V24:25" "V26:27" "V28:29" "V30:31" ]; + +attach variables [ vdd4h ] + [ V1 V3 V5 V7 V9 V11 V13 V15 V17 V19 V21 V23 V25 V27 V29 V31 ]; + +attach variables [ vdd4l ] + [ V0 V2 V4 V6 V8 V10 V12 V14 V16 V18 V20 V22 V24 V26 V28 V30 ]; attach variables [ vd5 vs5 vu5 vv5 vz5 vnreg ] [ V0 V1 V2 V3 V4 V5 V6 V7 @@ -746,11 +822,15 @@ attach variables [ vd5 vs5 vu5 vv5 vz5 vnreg ] V16 V17 V18 V19 V20 V21 V22 V23 V24 V25 V26 V27 V28 V29 V30 V31 ]; -attach variables [ vdd5_ ] # TODO: Removed vuu5_ vvv5_ - [ V1V0_ _ V3V2_ _ V5V4_ _ V7V6_ _ V9V8_ _ V11V10_ _ V13V12_ _ V15V14_ _ - V17V16_ _ V19V18_ _ V21V20_ _ V23V22_ _ V25V24_ _ V27V26_ _ V29V28_ _ V31V30_ _ ]; +# Quad vector attach (not supported) +#attach variables [ vdddd3_ vssss3_ ] +# [ V3V0_ V7V4_ V11V8_ V15V12_ V19V16_ V23V20_ V27V24_ V31V28_ ]; + +attach variables [ vdd4_ ] + [ V1V0_ V3V2_ V5V4_ V7V6_ V9V8_ V11V10_ V13V12_ V15V14_ + V17V16_ V19V18_ V21V20_ V23V22_ V25V24_ V27V26_ V29V28_ V31V30_ ]; -attach variables [ vd5_ vnreg_ ] # TODO: Removed vs5_ vu5_ vv5_ vz5_ +attach variables [ vd5_ vnreg_ tmpvreg_ ] [ V0.new V1.new V2.new V3.new V4.new V5.new V6.new V7.new V8.new V9.new V10.new V11.new V12.new V13.new V14.new V15.new V16.new V17.new V18.new V19.new V20.new V21.new V22.new V23.new @@ -886,3 +966,8 @@ VNreg0002: vnreg_ is GetVNAltReg & vnreg_ & vnreg & nreg_0002lsb=1 & nreg_0002 [ # @include "hexagon_hvx.sinc" + +# +# Vector Instruction Set (V73 extension) +# +@include "hexagon_hvx2.sinc" diff --git a/pypcode/processors/Hexagon/data/languages/hexagon_float.sinc b/pypcode/processors/Hexagon/data/languages/hexagon_float.sinc index de104c1..0341fc5 100644 --- a/pypcode/processors/Hexagon/data/languages/hexagon_float.sinc +++ b/pypcode/processors/Hexagon/data/languages/hexagon_float.sinc @@ -1,25 +1,19 @@ # # Floating Point Instructions -# Added with V5x: -# convert_sf2d, convert_sf2df, convert_sf2ud, convert_sf2uw, convert_sf2w -# convert_d2sf, convert_ud2sf, convert_uw2sf, convert_w2sf -# convert_df2d, convert_df2sf, convert_df2ud, convert_df2uw, convert_df2w -# convert_d2df, convert_ud2df, convert_uw2df, convert_w2df -# sfadd, sfclass, sfcmp.*, sffixupd, sffixupn, sffixupr, sfmake, sfmax, sfmin, sfmpy, sfsub -# dfclass, dfcmp.*, dfmake -# Added with V65: -# sfinvsqrta, sfrecipa -# Added with V66: -# dfadd, dfsub -# Added with V67: -# dfmax, dfmin, dfmpyfix, dfmpyhh, dfmpylh, dfmpyll # -# See bottom of this file for additional instruction patterns found within QEMU source code. -# Use of the undocumented double-precission floating instructions are disabled by default -# due to conflicts with V6 instructions. The option ADD_DP_OPS must be defined to -# to enable the use of these undocumented instructions which will disable the use of -# corresponding V6 instructions which conflict. +# NOTE: See bottom of this file for additional instruction patterns found within QEMU source code. +# Use of the undocumented double-precission floating instructions are disabled by default +# due to conflicts with V6 instructions. The option ADD_DP_OPS must be defined to +# to enable the use of these undocumented instructions which will disable the use of +# corresponding V6 instructions which conflict. # +# NOTE: The SLEIGH built-in float operators (float2float, int2float, float2int) use IEEE-754 +# round-to-nearest-even by default. Hexagon's USR register (bits 2:0 = RND) controls the +# rounding mode, and bits in USR capture FP exception status. For decompilation purposes the +# default rounding mode is acceptable. For emulation, programs that rely on non-default +# rounding or that read exception status from USR after a float operation will produce wrong +# results. +# define pcodeop convertFloat2UInt; define pcodeop chopFloat2UInt; @@ -31,9 +25,9 @@ define pcodeop chopFloat2UInt; # (v5,8) convert_sf2d -- "Rdd = convert_sf2d ( Rs )" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 1 0 0 0 0 1 0 0 1 + + s s s s s P P + + + + + + 1 0 0 d d d d d +# 1 0 0 0 0 1 0 0 1 - - s s s s s P P - - - - - - 1 0 0 d d d d d -:convert_sf2d Rdd5,rs5 EndPacket is iclass=8 & op2127=0x24 & op0813=0 & op0507=4 & rs5 & Rdd5 & $(END_PACKET) { +:convert_sf2d Rdd5,rs5 EndPacket is iclass=8 & op2327=0x9 & op0507=4 & rs5 & Rdd5 & $(END_PACKET) { # TODO: Rounding mode and other exceptional conditions are not implemented Rdd5 = trunc(rs5); build EndPacket; @@ -42,9 +36,9 @@ define pcodeop chopFloat2UInt; # (v5,8) convert_sf2d -- "Rdd = convert_sf2d ( Rs ) :chop" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 1 0 0 0 0 1 0 0 1 + + s s s s s P P + + + + + + 1 1 0 d d d d d +# 1 0 0 0 0 1 0 0 1 - - s s s s s P P - - - - - - 1 1 0 d d d d d -:convert_sf2d^":chop" Rdd5,rs5 EndPacket is iclass=8 & op2127=0x24 & op0813=0 & op0507=6 & rs5 & Rdd5 & $(END_PACKET) { +:convert_sf2d^":chop" Rdd5,rs5 EndPacket is iclass=8 & op2327=0x9 & op0507=6 & rs5 & Rdd5 & $(END_PACKET) { # TODO: Exceptional conditions are not implemented Rdd5 = trunc(rs5); build EndPacket; @@ -53,9 +47,9 @@ define pcodeop chopFloat2UInt; # (v5,8) convert_sf2df -- "Rdd = convert_sf2df ( Rs )" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 1 0 0 0 0 1 0 0 1 + + s s s s s P P + + + + + + 0 0 0 d d d d d +# 1 0 0 0 0 1 0 0 1 - - s s s s s P P - - - - - - 0 0 0 d d d d d -:convert_sf2df Rdd5,rs5 EndPacket is iclass=8 & op2127=0x24 & op0813=0 & op0507=0 & rs5 & Rdd5 & $(END_PACKET) { +:convert_sf2df Rdd5,rs5 EndPacket is iclass=8 & op2327=0x9 & op0507=0 & rs5 & Rdd5 & $(END_PACKET) { Rdd5 = float2float(rs5); build EndPacket; } @@ -63,9 +57,9 @@ define pcodeop chopFloat2UInt; # (v5,8) convert_sf2ud -- "Rdd = convert_sf2ud ( Rs )" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 1 0 0 0 0 1 0 0 1 + + s s s s s P P + + + + + + 0 1 1 d d d d d +# 1 0 0 0 0 1 0 0 1 - - s s s s s P P - - - - - - 0 1 1 d d d d d -:convert_sf2ud Rdd5,rs5 EndPacket is iclass=8 & op2127=0x24 & op0813=0 & op0507=3 & rs5 & Rdd5 & $(END_PACKET) { +:convert_sf2ud Rdd5,rs5 EndPacket is iclass=8 & op2327=0x9 & op0507=3 & rs5 & Rdd5 & $(END_PACKET) { # TODO: Exceptional conditions are not implemented float:4 = float2float(rs5); Rdd5 = convertFloat2UInt(float); @@ -75,9 +69,9 @@ define pcodeop chopFloat2UInt; # (v5,8) convert_sf2ud -- "Rdd = convert_sf2ud ( Rs ) :chop" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 1 0 0 0 0 1 0 0 1 + + s s s s s P P + + + + + + 1 0 1 d d d d d +# 1 0 0 0 0 1 0 0 1 - - s s s s s P P - - - - - - 1 0 1 d d d d d -:convert_sf2ud^":chop" Rdd5,rs5 EndPacket is iclass=8 & op2127=0x24 & op0813=0 & op0507=5 & rs5 & Rdd5 & $(END_PACKET) { +:convert_sf2ud^":chop" Rdd5,rs5 EndPacket is iclass=8 & op2327=0x9 & op0507=5 & rs5 & Rdd5 & $(END_PACKET) { # TODO: Exceptional conditions are not implemented float:4 = float2float(rs5); Rdd5 = chopFloat2UInt(float); @@ -87,9 +81,9 @@ define pcodeop chopFloat2UInt; # (v5,8) convert_sf2uw -- "Rd = convert_sf2uw ( Rs )" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 1 0 0 0 1 0 1 1 0 1 1 s s s s s P P + + + + + + 0 0 0 d d d d d +# 1 0 0 0 1 0 1 1 0 1 1 s s s s s P P - - - - - - 0 0 0 d d d d d -:convert_sf2uw Rd5,rs5 EndPacket is iclass=8 & op2127=0x5b & op0813=0 & op0507=0 & rs5 & Rd5 & $(END_PACKET) { +:convert_sf2uw Rd5,rs5 EndPacket is iclass=8 & op2127=0x5b & op0507=0 & rs5 & Rd5 & $(END_PACKET) { # TODO: Rounding mode and other exceptional conditions are not implemented float:4 = float2float(rs5); Rd5 = convertFloat2UInt(float); @@ -99,9 +93,9 @@ define pcodeop chopFloat2UInt; # (v5,8) convert_sf2uw -- "Rd = convert_sf2uw ( Rs ) :chop" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 1 0 0 0 1 0 1 1 0 1 1 s s s s s P P + + + + + + 0 0 1 d d d d d +# 1 0 0 0 1 0 1 1 0 1 1 s s s s s P P - - - - - - 0 0 1 d d d d d -:convert_sf2uw^":chop" Rd5,rs5 EndPacket is iclass=8 & op2127=0x5b & op0813=0 & op0507=1 & rs5 & Rd5 & $(END_PACKET) { +:convert_sf2uw^":chop" Rd5,rs5 EndPacket is iclass=8 & op2127=0x5b & op0507=1 & rs5 & Rd5 & $(END_PACKET) { # TODO: Exceptional conditions are not implemented float:4 = float2float(rs5); Rd5 = chopFloat2UInt(float); @@ -111,9 +105,9 @@ define pcodeop chopFloat2UInt; # (v5,8) convert_sf2w -- "Rd = convert_sf2w ( Rs )" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 1 0 0 0 1 0 1 1 1 0 0 s s s s s P P + + + + + + 0 0 0 d d d d d +# 1 0 0 0 1 0 1 1 1 0 0 s s s s s P P - - - - - - 0 0 0 d d d d d -:convert_sf2w Rd5,rs5 EndPacket is iclass=8 & op2127=0x5c & op0813=0 & op0507=0 & rs5 & Rd5 & $(END_PACKET) { +:convert_sf2w Rd5,rs5 EndPacket is iclass=8 & op2127=0x5c & op0507=0 & rs5 & Rd5 & $(END_PACKET) { # TODO: Rounding mode and other exceptional conditions are not implemented Rd5 = trunc(rs5); build EndPacket; @@ -122,9 +116,9 @@ define pcodeop chopFloat2UInt; # (v5,8) convert_sf2w -- "Rd = convert_sf2w ( Rs ) :chop" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 1 0 0 0 1 0 1 1 1 0 0 s s s s s P P + + + + + + 0 0 1 d d d d d +# 1 0 0 0 1 0 1 1 1 0 0 s s s s s P P - - - - - - 0 0 1 d d d d d -:convert_sf2w^":chop" Rd5,rs5 EndPacket is iclass=8 & op2127=0x5c & op0813=0 & op0507=1 & rs5 & Rd5 & $(END_PACKET) { +:convert_sf2w^":chop" Rd5,rs5 EndPacket is iclass=8 & op2127=0x5c & op0507=1 & rs5 & Rd5 & $(END_PACKET) { # TODO: Exceptional conditions are not implemented Rd5 = trunc(rs5); build EndPacket; @@ -133,9 +127,9 @@ define pcodeop chopFloat2UInt; # (v5,8) convert_d2sf -- "Rd = convert_d2sf ( Rss )" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 1 0 0 0 1 0 0 0 0 1 0 s s s s s P P + + + + + + 0 0 1 d d d d d +# 1 0 0 0 1 0 0 0 0 1 0 s s s s s P P - - - - - - 0 0 1 d d d d d -:convert_d2sf Rd5,rss5 EndPacket is iclass=8 & op2127=0x42 & op0813=0 & op0507=1 & rss5 & Rd5 & $(END_PACKET) { +:convert_d2sf Rd5,rss5 EndPacket is iclass=8 & op2127=0x42 & op0507=1 & rss5 & Rd5 & $(END_PACKET) { Rd5 = int2float(rss5); build EndPacket; } @@ -143,12 +137,12 @@ define pcodeop chopFloat2UInt; # (v5,8) convert_ud2sf -- "Rd = convert_ud2sf ( Rss )" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 1 0 0 0 1 0 0 0 0 0 1 s s s s s P P + + + + + + 0 0 1 d d d d d +# 1 0 0 0 1 0 0 0 0 0 1 s s s s s P P - - - - - - 0 0 1 d d d d d # TODO: we do not have an unsigned int2float - could zext but not with 8-byte reg if we want to emulate define pcodeop convertUInt2float; -:convert_ud2sf Rd5,rss5 EndPacket is iclass=8 & op2127=0x41 & op0813=0 & op0507=1 & rss5 & Rd5 & $(END_PACKET) { +:convert_ud2sf Rd5,rss5 EndPacket is iclass=8 & op2127=0x41 & op0507=1 & rss5 & Rd5 & $(END_PACKET) { tmp:9 = zext(rss5); Rd5 = int2float(tmp); build EndPacket; @@ -157,9 +151,9 @@ define pcodeop convertUInt2float; # (v5,8) convert_uw2sf -- "Rd = convert_uw2sf ( Rs )" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 1 0 0 0 1 0 1 1 0 0 1 s s s s s P P + + + + + + 0 0 0 d d d d d +# 1 0 0 0 1 0 1 1 0 0 1 s s s s s P P - - - - - - 0 0 0 d d d d d -:convert_uw2sf Rd5,rs5 EndPacket is iclass=8 & op2127=0x59 & op0813=0 & op0507=0 & rs5 & Rd5 & $(END_PACKET) { +:convert_uw2sf Rd5,rs5 EndPacket is iclass=8 & op2127=0x59 & op0507=0 & rs5 & Rd5 & $(END_PACKET) { tmp:8 = zext(rs5); Rd5 = int2float(tmp); build EndPacket; @@ -168,9 +162,9 @@ define pcodeop convertUInt2float; # (v5,8) convert_w2sf -- "Rd = convert_w2sf ( Rs )" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 1 0 0 0 1 0 1 1 0 1 0 s s s s s P P + + + + + + 0 0 0 d d d d d +# 1 0 0 0 1 0 1 1 0 1 0 s s s s s P P - - - - - - 0 0 0 d d d d d -:convert_w2sf Rd5,rs5 EndPacket is iclass=8 & op2127=0x5a & op0813=0 & op0507=0 & rs5 & Rd5 & $(END_PACKET) { +:convert_w2sf Rd5,rs5 EndPacket is iclass=8 & op2127=0x5a & op0507=0 & rs5 & Rd5 & $(END_PACKET) { Rd5 = int2float(rs5); build EndPacket; } @@ -178,9 +172,9 @@ define pcodeop convertUInt2float; # (v5,8) convert_df2d -- "Rdd = convert_df2d ( Rss )" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 1 0 0 0 0 0 0 0 1 1 1 s s s s s P P 0 + + + + + 0 0 0 d d d d d +# 1 0 0 0 0 0 0 0 1 1 1 s s s s s P P 0 - - - - - 0 0 0 d d d d d -:convert_df2d Rdd5,rss5 EndPacket is iclass=8 & op2127=0x07 & op0813=0 & op0507=0 & rss5 & Rdd5 & $(END_PACKET) { +:convert_df2d Rdd5,rss5 EndPacket is iclass=8 & op2127=0x07 & op13=0 & op0507=0 & rss5 & Rdd5 & $(END_PACKET) { # TODO: Rounding mode and other exceptional conditions are not implemented Rdd5 = trunc(rss5); build EndPacket; @@ -189,9 +183,9 @@ define pcodeop convertUInt2float; # (v5,8) convert_df2d -- "Rdd = convert_df2d ( Rss ) :chop" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 1 0 0 0 0 0 0 0 1 1 1 s s s s s P P 0 + + + + + 1 1 0 d d d d d +# 1 0 0 0 0 0 0 0 1 1 1 s s s s s P P 0 - - - - - 1 1 0 d d d d d -:convert_df2d^":chop" Rdd5,rss5 EndPacket is iclass=8 & op2127=0x07 & op0813=0 & op0507=6 & rss5 & Rdd5 & $(END_PACKET) { +:convert_df2d^":chop" Rdd5,rss5 EndPacket is iclass=8 & op2127=0x07 & op13=0 & op0507=6 & rss5 & Rdd5 & $(END_PACKET) { # TODO: Exceptional conditions are not implemented Rdd5 = trunc(rss5); build EndPacket; @@ -200,9 +194,9 @@ define pcodeop convertUInt2float; # (v5,8) convert_df2sf -- "Rd = convert_df2sf ( Rss )" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 1 0 0 0 1 0 0 0 0 0 0 s s s s s P P + + + + + + 0 0 1 d d d d d +# 1 0 0 0 1 0 0 0 0 0 0 s s s s s P P - - - - - - 0 0 1 d d d d d -:convert_df2sf Rd5,rss5 EndPacket is iclass=8 & op2127=0x40 & op0813=0 & op0507=1 & rss5 & Rd5 & $(END_PACKET) { +:convert_df2sf Rd5,rss5 EndPacket is iclass=8 & op2127=0x40 & op0507=1 & rss5 & Rd5 & $(END_PACKET) { Rd5 = float2float(rss5); build EndPacket; } @@ -210,9 +204,9 @@ define pcodeop convertUInt2float; # (v5,8) convert_df2ud -- "Rdd = convert_df2ud ( Rss )" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 1 0 0 0 0 0 0 0 1 1 1 s s s s s P P 0 + + + + + 0 0 1 d d d d d +# 1 0 0 0 0 0 0 0 1 1 1 s s s s s P P 0 - - - - - 0 0 1 d d d d d -:convert_df2ud Rdd5,rss5 EndPacket is iclass=8 & op2127=0x07 & op0813=0 & op0507=1 & rss5 & Rdd5 & $(END_PACKET) { +:convert_df2ud Rdd5,rss5 EndPacket is iclass=8 & op2127=0x07 & op13=0 & op0507=1 & rss5 & Rdd5 & $(END_PACKET) { # TODO: Exceptional conditions are not implemented float:8 = float2float(rss5); Rdd5 = convertFloat2UInt(float); @@ -222,9 +216,9 @@ define pcodeop convertUInt2float; # (v5,8) convert_df2ud -- "Rdd = convert_df2ud ( Rss ) :chop" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 1 0 0 0 0 0 0 0 1 1 1 s s s s s P P 0 + + + + + 1 1 1 d d d d d +# 1 0 0 0 0 0 0 0 1 1 1 s s s s s P P 0 - - - - - 1 1 1 d d d d d -:convert_df2ud^":chop" Rdd5,rss5 EndPacket is iclass=8 & op2127=0x07 & op0813=0 & op0507=7 & rss5 & Rdd5 & $(END_PACKET) { +:convert_df2ud^":chop" Rdd5,rss5 EndPacket is iclass=8 & op2127=0x07 & op13=0 & op0507=7 & rss5 & Rdd5 & $(END_PACKET) { # TODO: Exceptional conditions are not implemented float:8 = float2float(rss5); Rdd5 = chopFloat2UInt(float); @@ -234,9 +228,9 @@ define pcodeop convertUInt2float; # (v5,8) convert_df2uw -- "Rd = convert_df2uw ( Rss )" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 1 0 0 0 1 0 0 0 0 1 1 s s s s s P P + + + + + + 0 0 1 d d d d d +# 1 0 0 0 1 0 0 0 0 1 1 s s s s s P P - - - - - - 0 0 1 d d d d d -:convert_df2uw Rd5,rss5 EndPacket is iclass=8 & op2127=0x43 & op0813=0 & op0507=1 & rss5 & Rd5 & $(END_PACKET) { +:convert_df2uw Rd5,rss5 EndPacket is iclass=8 & op2127=0x43 & op0507=1 & rss5 & Rd5 & $(END_PACKET) { # TODO: Rounding mode and other exceptional conditions are not implemented float:8 = float2float(rss5); Rd5 = convertFloat2UInt(float); @@ -246,9 +240,9 @@ define pcodeop convertUInt2float; # (v5,8) convert_df2uw -- "Rd = convert_df2uw ( Rss ) :chop" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 1 0 0 0 1 0 0 0 1 0 1 s s s s s P P + + + + + + 0 0 1 d d d d d +# 1 0 0 0 1 0 0 0 1 0 1 s s s s s P P - - - - - - 0 0 1 d d d d d -:convert_df2uw^":chop" Rd5,rss5 EndPacket is iclass=8 & op2127=0x45 & op0813=0 & op0507=1 & rss5 & Rd5 & $(END_PACKET) { +:convert_df2uw^":chop" Rd5,rss5 EndPacket is iclass=8 & op2127=0x45 & op0507=1 & rss5 & Rd5 & $(END_PACKET) { # TODO: Exceptional conditions are not implemented float:8 = float2float(rss5); Rd5 = chopFloat2UInt(float); @@ -258,9 +252,9 @@ define pcodeop convertUInt2float; # (v5,8) convert_df2w -- "Rd = convert_df2w ( Rss )" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 1 0 0 0 1 0 0 0 1 0 0 s s s s s P P + + + + + + 0 0 1 d d d d d +# 1 0 0 0 1 0 0 0 1 0 0 s s s s s P P - - - - - - 0 0 1 d d d d d -:convert_df2w Rd5,rss5 EndPacket is iclass=8 & op2127=0x44 & op0813=0 & op0507=1 & rss5 & Rd5 & $(END_PACKET) { +:convert_df2w Rd5,rss5 EndPacket is iclass=8 & op2127=0x44 & op0507=1 & rss5 & Rd5 & $(END_PACKET) { # TODO: Rounding mode and other exceptional conditions are not implemented Rd5 = trunc(rss5); build EndPacket; @@ -269,9 +263,9 @@ define pcodeop convertUInt2float; # (v5,8) convert_df2w -- "Rd = convert_df2w ( Rss ) :chop" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 1 0 0 0 1 0 0 0 1 1 1 s s s s s P P + + + + + + 0 0 1 d d d d d +# 1 0 0 0 1 0 0 0 1 1 1 s s s s s P P - - - - - - 0 0 1 d d d d d -:convert_df2w^":chop" Rd5,rss5 EndPacket is iclass=8 & op2127=0x47 & op0813=0 & op0507=1 & rss5 & Rd5 & $(END_PACKET) { +:convert_df2w^":chop" Rd5,rss5 EndPacket is iclass=8 & op2127=0x47 & op0507=1 & rss5 & Rd5 & $(END_PACKET) { # TODO: Exceptional conditions are not implemented Rd5 = trunc(rss5); build EndPacket; @@ -280,9 +274,9 @@ define pcodeop convertUInt2float; # (v5,8) convert_d2df -- "Rdd = convert_d2df ( Rss )" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 1 0 0 0 0 0 0 0 1 1 1 s s s s s P P 0 + + + + + 0 1 1 d d d d d +# 1 0 0 0 0 0 0 0 1 1 1 s s s s s P P 0 - - - - - 0 1 1 d d d d d -:convert_d2df Rdd5,rss5 EndPacket is iclass=8 & op2127=0x07 & op0813=0 & op0507=3 & rss5 & Rdd5 & $(END_PACKET) { +:convert_d2df Rdd5,rss5 EndPacket is iclass=8 & op2127=0x07 & op13=0 & op0507=3 & rss5 & Rdd5 & $(END_PACKET) { Rdd5 = int2float(rss5); build EndPacket; } @@ -290,9 +284,9 @@ define pcodeop convertUInt2float; # (v5,8) convert_ud2df -- "Rdd = convert_ud2df ( Rss )" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 1 0 0 0 0 0 0 0 1 1 1 s s s s s P P 0 + + + + + 0 1 0 d d d d d +# 1 0 0 0 0 0 0 0 1 1 1 s s s s s P P 0 - - - - - 0 1 0 d d d d d -:convert_ud2df Rdd5,rss5 EndPacket is iclass=8 & op2127=0x07 & op0813=0 & op0507=2 & rss5 & Rdd5 & $(END_PACKET) { +:convert_ud2df Rdd5,rss5 EndPacket is iclass=8 & op2127=0x07 & op13=0 & op0507=2 & rss5 & Rdd5 & $(END_PACKET) { tmp:9 = zext(rss5); Rdd5 = int2float(tmp); build EndPacket; @@ -301,9 +295,9 @@ define pcodeop convertUInt2float; # (v5,8) convert_uw2df -- "Rdd = convert_uw2df ( Rs )" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 1 0 0 0 0 1 0 0 1 + + s s s s s P P + + + + + + 0 0 1 d d d d d +# 1 0 0 0 0 1 0 0 1 - - s s s s s P P - - - - - - 0 0 1 d d d d d -:convert_uw2df Rdd5,rs5 EndPacket is iclass=8 & op2127=0x24 & op0813=0 & op0507=1 & rs5 & Rdd5 & $(END_PACKET) { +:convert_uw2df Rdd5,rs5 EndPacket is iclass=8 & op2327=0x9 & op0507=1 & rs5 & Rdd5 & $(END_PACKET) { tmp:9 = zext(rs5); Rdd5 = int2float(tmp); build EndPacket; @@ -312,9 +306,9 @@ define pcodeop convertUInt2float; # (v5,8) convert_w2df -- "Rdd = convert_w2df ( Rs )" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 1 0 0 0 0 1 0 0 1 + + s s s s s P P + + + + + + 0 1 0 d d d d d +# 1 0 0 0 0 1 0 0 1 - - s s s s s P P - - - - - - 0 1 0 d d d d d -:convert_w2df Rdd5,rs5 EndPacket is iclass=8 & op2127=0x24 & op0813=0 & op0507=2 & rs5 & Rdd5 & $(END_PACKET) { +:convert_w2df Rdd5,rs5 EndPacket is iclass=8 & op2327=0x9 & op0507=2 & rs5 & Rdd5 & $(END_PACKET) { Rdd5 = int2float(rs5); build EndPacket; } @@ -332,11 +326,11 @@ define pcodeop convertUInt2float; # (v5,8) sfclass -- "Pd = sfclass ( Rs, #u5 )" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 1 0 0 0 0 1 0 1 1 1 1 s s s s s P P 0 i i i i i + + + + + + d d +# 1 0 0 0 0 1 0 1 1 1 1 s s s s s P P 0 i i i i i - - - - - - d d define pcodeop isClassifiedFloat; -:sfclass Pd2,rs5,Uimm8_0812 EndPacket is iclass=8 & op2127=0x2f & op13=0 & op0207=0 & Uimm8_0812 & rs5 & Pd2 & $(END_PACKET) { +:sfclass Pd2,rs5,Uimm8_0812 EndPacket is iclass=8 & op2127=0x2f & op13=0 & Uimm8_0812 & rs5 & Pd2 & $(END_PACKET) { float:4 = float2float(rs5); bool:1 = isClassifiedFloat(float,Uimm8_0812); Pd2 = Pd2 & ((bool != 0) * 0xff); @@ -346,9 +340,9 @@ define pcodeop isClassifiedFloat; # (v5,12) sfcmp.ge -- "Pd = sfcmp.ge ( Rs, Rt )" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 1 1 0 0 0 1 1 1 1 1 1 s s s s s P P + t t t t t 0 0 0 + + + d d +# 1 1 0 0 0 1 1 1 1 1 1 s s s s s P P - t t t t t 0 0 0 - - - d d -:sfcmp.ge Pd2,rs5,rt5 EndPacket is iclass=12 & op2127=0x3f & op13=0 & op0507=0 & op0204=0 & rs5 & rt5 & Pd2 & $(END_PACKET) { +:sfcmp.ge Pd2,rs5,rt5 EndPacket is iclass=12 & op2127=0x3f & op0507=0 & rs5 & rt5 & Pd2 & $(END_PACKET) { Pd2 = Pd2 & ((rt5 f<= rs5) * 0xff); build EndPacket; } @@ -356,9 +350,9 @@ define pcodeop isClassifiedFloat; # (v5,12) sfcmp.uo -- "Pd = sfcmp.uo ( Rs, Rt )" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 1 1 0 0 0 1 1 1 1 1 1 s s s s s P P + t t t t t 0 0 1 + + + d d +# 1 1 0 0 0 1 1 1 1 1 1 s s s s s P P - t t t t t 0 0 1 - - - d d -:sfcmp.uo Pd2,rs5,rt5 EndPacket is iclass=12 & op2127=0x3f & op13=0 & op0507=1 & op0204=0 & rs5 & rt5 & Pd2 & $(END_PACKET) { +:sfcmp.uo Pd2,rs5,rt5 EndPacket is iclass=12 & op2127=0x3f & op0507=1 & rs5 & rt5 & Pd2 & $(END_PACKET) { float1:4 = float2float(rs5); float2:4 = float2float(rt5); bool:1 = nan(float1) || nan(float2); @@ -369,9 +363,9 @@ define pcodeop isClassifiedFloat; # (v5,12) sfcmp.eq -- "Pd = sfcmp.eq ( Rs, Rt )" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 1 1 0 0 0 1 1 1 1 1 1 s s s s s P P + t t t t t 0 1 1 + + + d d +# 1 1 0 0 0 1 1 1 1 1 1 s s s s s P P - t t t t t 0 1 1 - - - d d -:sfcmp.eq Pd2,rs5,rt5 EndPacket is iclass=12 & op2127=0x3f & op13=0 & op0507=3 & op0204=0 & rs5 & rt5 & Pd2 & $(END_PACKET) { +:sfcmp.eq Pd2,rs5,rt5 EndPacket is iclass=12 & op2127=0x3f & op0507=3 & rs5 & rt5 & Pd2 & $(END_PACKET) { Pd2 = Pd2 & ((rt5 f== rs5) * 0xff); build EndPacket; } @@ -379,9 +373,9 @@ define pcodeop isClassifiedFloat; # (v5,12) sfcmp.gt -- "Pd = sfcmp.gt ( Rs, Rt )" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 1 1 0 0 0 1 1 1 1 1 1 s s s s s P P + t t t t t 1 0 0 + + + d d +# 1 1 0 0 0 1 1 1 1 1 1 s s s s s P P - t t t t t 1 0 0 - - - d d -:sfcmp.gt Pd2,rs5,rt5 EndPacket is iclass=12 & op2127=0x3f & op13=0 & op0507=4 & op0204=0 & rs5 & rt5 & Pd2 & $(END_PACKET) { +:sfcmp.gt Pd2,rs5,rt5 EndPacket is iclass=12 & op2127=0x3f & op0507=4 & rs5 & rt5 & Pd2 & $(END_PACKET) { Pd2 = Pd2 & ((rs5 f> rt5) * 0xff); build EndPacket; } @@ -409,30 +403,52 @@ define pcodeop sffixupn; # (v5,8) sffixupr -- "Rd = sffixupr ( Rs )" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 1 0 0 0 1 0 1 1 1 0 1 s s s s s P P + + + + + + 0 0 0 d d d d d +# 1 0 0 0 1 0 1 1 1 0 1 s s s s s P P - - - - - - 0 0 0 d d d d d define pcodeop sffixupr; -:sffixupr Rd5,rs5 EndPacket is iclass=8 & op2127=0x5d & op0813=0 & op0507=0 & rs5 & Rd5 & $(END_PACKET) { +:sffixupr Rd5,rs5 EndPacket is iclass=8 & op2127=0x5d & op0507=0 & rs5 & Rd5 & $(END_PACKET) { Rd5 = sffixupr(rs5); build EndPacket; } +# (v5,8) sfinvsqrta -- "Rd,Pe = sfinvsqrta ( Rs )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 0 0 1 0 1 1 1 1 1 s s s s s P P - - - - - - 0 e e d d d d d + +define pcodeop sfinvsqrta; # Rd = float inverse square root approximation of Rs +define pcodeop sfinvsqrtaPred; # Pe = exponent class bits of the approximation + +:sfinvsqrta Rd5,pu0506,rs5 EndPacket is iclass=8 & op2127=0x5f & op7=0 & pu0506_ & pu0506 & rs5 & Rd5 & $(END_PACKET) { + + # NOTE: Per PRM 80-N2040-60 p.594, Rd and Pe are only written when + # invsqrt_common(Rs) returns true (i.e. Rs is a normal-range value). + # For special inputs (NaN, infinity, zero, denormal) the writes are + # suppressed; that conditional is not modelled here. + + Rd5 = sfinvsqrta(rs5); + pu0506_ = sfinvsqrtaPred(rs5); + build EndPacket; + <> + pu0506 = pu0506_; +} + # (v5,13) sfmake -- "Rd = sfmake ( #u10 ) :neg" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 1 1 0 1 0 1 1 0 0 1 i + + + + + P P i i i i i i i i i d d d d d +# 1 1 0 1 0 1 1 0 0 1 i - - - - - P P i i i i i i i i i d d d d d -:sfmake^":neg" Rd5,Uimm16_21_0513 EndPacket is iclass=13 & op2227=0x19 & op1620=0 & Uimm16_21_0513 & Rd5 & $(END_PACKET) { - Rd5 = int2float(-Uimm16_21_0513); # TODO: assumed functionality +:sfmake^":neg" Rd5,Uimm16_21_0513 EndPacket is iclass=13 & op2227=0x19 & Uimm16_21_0513 & Rd5 & $(END_PACKET) { + Rd5 = (1 << 31) | (((127 - 6) << 23) + (zext(Uimm16_21_0513) << 17)); build EndPacket; } # (v5,13) sfmake -- "Rd = sfmake ( #u10 ) :pos" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 1 1 0 1 0 1 1 0 0 0 i + + + + + P P i i i i i i i i i d d d d d +# 1 1 0 1 0 1 1 0 0 0 i - - - - - P P i i i i i i i i i d d d d d -:sfmake^":pos" Rd5,Uimm16_21_0513 EndPacket is iclass=13 & op2227=0x18 & op1620=0 & Uimm16_21_0513 & Rd5 & $(END_PACKET) { - Rd5 = int2float(Uimm16_21_0513); # TODO: assumed functionality +:sfmake^":pos" Rd5,Uimm16_21_0513 EndPacket is iclass=13 & op2227=0x18 & Uimm16_21_0513 & Rd5 & $(END_PACKET) { + Rd5 = ((127 - 6) << 23) + (zext(Uimm16_21_0513) << 17); build EndPacket; } @@ -528,8 +544,18 @@ define pcodeop sffixupr; build EndPacket; } +# (v5,14) sfrecipa -- "Rd,Pe = sfrecipa ( Rs, Rt )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 1 0 1 0 1 1 1 1 1 s s s s s P P 0 t t t t t 1 e e d d d d d - +:sfrecipa Rd5,Pd0506,rs5,rt5 EndPacket is iclass=14 & op2127=0x5f & op13=0 & op7=1 & Pd0506 & rs5 & rt5 & Rd5 & $(END_PACKET) { + src1:4 = rs5; + src2:4 = rt5; + Rd5 = reciprocal(src1, src2); + Pd0506 = Pd0506 & reciprocalAdjust(src1, src2); + build EndPacket; +} # (v5,14) sfsub -- "Rd = sfsub ( Rs, Rt )" # _________________________________________________________________________________________________ @@ -544,9 +570,9 @@ define pcodeop sffixupr; # (v5,13) dfclass -- "Pd = dfclass ( Rss, #u5 )" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 1 1 0 1 1 1 0 0 1 0 0 s s s s s P P + 0 0 0 i i i i i 1 0 + d d +# 1 1 0 1 1 1 0 0 1 0 0 s s s s s P P - 0 0 0 i i i i i 1 0 - d d -:dfclass Pd2,rss5,Uimm8_0509 EndPacket is iclass=13 & op2127=0x64 & op1013=0 & op0204=4 & Uimm8_0509 & rss5 & Pd2 & $(END_PACKET) { +:dfclass Pd2,rss5,Uimm8_0509 EndPacket is iclass=13 & op2127=0x64 & op1012=0 & op0304=2 & Uimm8_0509 & rss5 & Pd2 & $(END_PACKET) { float:8 = float2float(rss5); result:1 = isClassifiedFloat(float,Uimm8_0509); Pd2 = Pd2 & result; @@ -556,9 +582,9 @@ define pcodeop sffixupr; # (v5,13) dfcmp.eq -- "Pd = dfcmp.eq ( Rss, Rtt )" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 1 1 0 1 0 0 1 0 1 1 1 s s s s s P P + t t t t t 0 0 0 + + + d d +# 1 1 0 1 0 0 1 0 1 1 1 s s s s s P P - t t t t t 0 0 0 - - - d d -:dfcmp.eq Pd2,rss5,rtt5 EndPacket is iclass=13 & op2127=0x17 & op13=0 & op0507=0 & op0204=0 & rss5 & rtt5 & Pd2 & $(END_PACKET) { +:dfcmp.eq Pd2,rss5,rtt5 EndPacket is iclass=13 & op2127=0x17 & op0507=0 & rss5 & rtt5 & Pd2 & $(END_PACKET) { Pd2 = Pd2 & ((rtt5 f== rss5) * 0xff); build EndPacket; } @@ -566,9 +592,9 @@ define pcodeop sffixupr; # (v5,13) dfcmp.gt -- "Pd = dfcmp.gt ( Rss, Rtt )" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 1 1 0 1 0 0 1 0 1 1 1 s s s s s P P + t t t t t 0 0 1 + + + d d +# 1 1 0 1 0 0 1 0 1 1 1 s s s s s P P - t t t t t 0 0 1 - - - d d -:dfcmp.gt Pd2,rss5,rtt5 EndPacket is iclass=13 & op2127=0x17 & op13=0 & op0507=1 & op0204=0 & rss5 & rtt5 & Pd2 & $(END_PACKET) { +:dfcmp.gt Pd2,rss5,rtt5 EndPacket is iclass=13 & op2127=0x17 & op0507=1 & rss5 & rtt5 & Pd2 & $(END_PACKET) { Pd2 = Pd2 & ((rss5 f> rtt5) * 0xff); build EndPacket; } @@ -576,9 +602,9 @@ define pcodeop sffixupr; # (v5,13) dfcmp.ge -- "Pd = dfcmp.ge ( Rss, Rtt )" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 1 1 0 1 0 0 1 0 1 1 1 s s s s s P P + t t t t t 0 1 0 + + + d d +# 1 1 0 1 0 0 1 0 1 1 1 s s s s s P P - t t t t t 0 1 0 - - - d d -:dfcmp.ge Pd2,rss5,rtt5 EndPacket is iclass=13 & op2127=0x17 & op13=0 & op0507=2 & op0204=0 & rss5 & rtt5 & Pd2 & $(END_PACKET) { +:dfcmp.ge Pd2,rss5,rtt5 EndPacket is iclass=13 & op2127=0x17 & op0507=2 & rss5 & rtt5 & Pd2 & $(END_PACKET) { Pd2 = Pd2 & ((rtt5 f<= rss5) * 0xff); build EndPacket; } @@ -586,9 +612,9 @@ define pcodeop sffixupr; # (v5,13) dfcmp.uo -- "Pd = dfcmp.uo ( Rss, Rtt )" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 1 1 0 1 0 0 1 0 1 1 1 s s s s s P P + t t t t t 0 1 1 + + + d d +# 1 1 0 1 0 0 1 0 1 1 1 s s s s s P P - t t t t t 0 1 1 - - - d d -:dfcmp.uo Pd2,rss5,rtt5 EndPacket is iclass=13 & op2127=0x17 & op13=0 & op0507=3 & op0204=0 & rss5 & rtt5 & Pd2 & $(END_PACKET) { +:dfcmp.uo Pd2,rss5,rtt5 EndPacket is iclass=13 & op2127=0x17 & op0507=3 & rss5 & rtt5 & Pd2 & $(END_PACKET) { float1:8 = float2float(rss5); float2:8 = float2float(rtt5); bool:1 = nan(float1) || nan(float2); @@ -599,50 +625,25 @@ define pcodeop sffixupr; # (v5,13) dfmake -- "Rdd = dfmake ( #u10 ) :neg" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 1 1 0 1 1 0 0 1 0 1 i + + + + + P P i i i i i i i i i d d d d d +# 1 1 0 1 1 0 0 1 0 1 i - - - - - P P i i i i i i i i i d d d d d -:dfmake^":neg" Rdd5,Uimm16_21_0513 EndPacket is iclass=13 & op2227=0x25 & op1620=0 & Uimm16_21_0513 & Rdd5 & $(END_PACKET) { - Rdd5 = int2float(-Uimm16_21_0513); # TODO: assumed functionality +:dfmake^":neg" Rdd5,Uimm16_21_0513 EndPacket is iclass=13 & op2227=0x25 & Uimm16_21_0513 & Rdd5 & $(END_PACKET) { + Rdd5 = (1:8 << 63) | (((1023:8 - 6) << 52) + (zext(Uimm16_21_0513) << 46)); build EndPacket; } # (v5,13) dfmake -- "Rdd = dfmake ( #u10 ) :pos" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 1 1 0 1 1 0 0 1 0 0 i + + + + + P P i i i i i i i i i d d d d d +# 1 1 0 1 1 0 0 1 0 0 i - - - - - P P i i i i i i i i i d d d d d -:dfmake^":pos" Rdd5,Uimm16_21_0513 EndPacket is iclass=13 & op2227=0x24 & op1620=0 & Uimm16_21_0513 & Rdd5 & $(END_PACKET) { - Rdd5 = int2float(Uimm16_21_0513); # TODO: assumed functionality +:dfmake^":pos" Rdd5,Uimm16_21_0513 EndPacket is iclass=13 & op2227=0x24 & Uimm16_21_0513 & Rdd5 & $(END_PACKET) { + Rdd5 = ((1023:8 - 6) << 52) + (zext(Uimm16_21_0513) << 46); build EndPacket; } # -# V65 Floating Point Instructions -# - -# (v65,8) sfinvsqrta -- "Rd,Pe = sfinvsqrta ( Rs )" -# _________________________________________________________________________________________________ -# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 1 0 0 0 1 0 1 1 1 1 1 s s s s s P P + + + + + + 0 e e d d d d d - -:sfinvsqrta Rd5,pu0506,rs5 EndPacket is iclass=8 & op2127=0x5f & op0813=0 & op7=0 & pu0506_ & pu0506 & rs5 & Rd5 & $(END_PACKET) -unimpl - -# (v65,14) sfrecipa -- "Rd,Pe = sfrecipa ( Rs, Rt )" -# _________________________________________________________________________________________________ -# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 1 1 1 0 1 0 1 1 1 1 1 s s s s s P P 0 t t t t t 1 e e d d d d d - -:sfrecipa Rd5,Pd0506,rs5,rt5 EndPacket is iclass=14 & op2127=0x5f & op13=0 & op7=1 & Pd0506 & rs5 & rt5 & Rd5 & $(END_PACKET) { - src1:4 = rs5; - src2:4 = rt5; - Rd5 = reciprocal(src1, src2); - Pd0506 = Pd0506 & reciprocalAdjust(src1, src2); - build EndPacket; -} - -# -# V66 Floating Point Instructions +# V66 Floating Point Instructions # # (v66,14) dfadd -- "Rdd = dfadd ( Rss, Rtt )" @@ -699,7 +700,7 @@ unimpl build EndPacket; } -# (v5,14) c -- "Rdd = dfmpyfix ( Rss, Rtt )" +# (v67,14) dfmpyfix -- "Rdd = dfmpyfix ( Rss, Rtt )" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| # 1 1 1 0 1 0 0 0 0 1 0 s s s s s P P 0 t t t t t 0 1 1 d d d d d @@ -734,7 +735,7 @@ define pcodeop dfmpylh; build EndPacket; } -# (v5,14) dfmpyll -- "Rdd = dfmpyll ( Rss, Rtt )" +# (v67,14) dfmpyll -- "Rdd = dfmpyll ( Rss, Rtt )" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| # 1 1 1 0 1 0 0 0 1 0 1 s s s s s P P 0 t t t t t 0 1 1 d d d d d @@ -754,6 +755,14 @@ define pcodeop dfmpyll; # specific processor version that we have been able to identify. These instructions are for experimental # use only and may be intended for QEMU development testing only. # +# The "??" version marker below is intentional: no processor version could be established for these +# encodings. QEMU itself guards them with its own ADD_DP_OPS conditional in +# target/hexagon/imported/encode_pp.def (alongside the emulator-only F2_dfdivcheat / F2_dfsqrtcheat +# encodings) without attributing an architecture version, has no corresponding definitions in +# target/hexagon/imported/float.idef, and LLVM's HexagonDepInstrInfo.td has no definitions for them at +# all. They are likewise absent from every PRM checked (V60/V61 through V79), and the Qualcomm +# hexagon-llvm-mc assembler rejects them for every supported -mcpu (hexagonv65 through hexagonv71). +# ############################################################################################################# @ifdef ADD_DP_OPS @@ -786,8 +795,16 @@ define pcodeop dffixupd; # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| # 1 1 1 0 1 0 0 0 1 1 1 s s s s s P P 0 t t t t t 0 e e d d d d d -:dfrecipa Rdd5,pu0506,rss5,rtt5 EndPacket is iclass=14 & op2127=0x47 & op13=0 & op7=0 & pu0506_ & pu0506 & rss5 & rtt5 & Rdd5 & $(END_PACKET) -unimpl +define pcodeop dfrecipa; # Rdd = DF reciprocal approximation +define pcodeop dfrecipaPred; # Pe = exponent class of approximation + +:dfrecipa Rdd5,pu0506,rss5,rtt5 EndPacket is iclass=14 & op2127=0x47 & op13=0 & op7=0 & pu0506_ & pu0506 & rss5 & rtt5 & Rdd5 & $(END_PACKET) { + Rdd5 = dfrecipa(rss5, rtt5); + pu0506_ = dfrecipaPred(rss5, rtt5); + build EndPacket; + <> + pu0506 = pu0506_; +} # (??,14) dfmpyhh -- "Rdd += dfmpyhh ( Rss, Rtt )" # NOTE: unexplained redfinition of V67 dfmpyhh += @@ -854,9 +871,9 @@ unimpl # (??,8) dffixupr -- "Rdd = dffixupr ( Rss )" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 1 0 0 0 0 0 0 0 1 1 1 s s s s s P P 0 + + + + + 1 0 0 d d d d d +# 1 0 0 0 0 0 0 0 1 1 1 s s s s s P P 0 - - - - - 1 0 0 d d d d d define pcodeop dffixupr; -:dffixupr Rdd5,rss5 EndPacket is iclass=8 & op2127=0x07 & op0813=0 & op0507=4 & rss5 & Rdd5 & $(END_PACKET) { +:dffixupr Rdd5,rss5 EndPacket is iclass=8 & op2127=0x07 & op13=0 & op0507=4 & rss5 & Rdd5 & $(END_PACKET) { Rdd5 = dffixupr(rss5); build EndPacket; } @@ -864,9 +881,17 @@ define pcodeop dffixupr; # (??,8) dfinvsqrta -- "Rdd32 , Pe4 = dfinvsqrta ( Rss32 )" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 1 0 0 0 0 0 0 0 1 1 1 s s s s s P P 1 + + + + + 0 e e d d d d d +# 1 0 0 0 0 0 0 0 1 1 1 s s s s s P P 1 - - - - - 0 e e d d d d d + +define pcodeop dfinvsqrta; # Rdd = DF inverse square root approximation +define pcodeop dfinvsqrtaPred; # Pe = exponent class of approximation -:dfinvsqrta Rdd5,pu0506,rss5 EndPacket is iclass=8 & op2127=0x07 & op0813=0x20 & op7=0 & pu0506_ & pu0506 & rss5 & Rdd5 & $(END_PACKET) -unimpl +:dfinvsqrta Rdd5,pu0506,rss5 EndPacket is iclass=8 & op2127=0x07 & op13=0x1 & op7=0 & pu0506_ & pu0506 & rss5 & Rdd5 & $(END_PACKET) { + Rdd5 = dfinvsqrta(rss5); + pu0506_ = dfinvsqrtaPred(rss5); + build EndPacket; + <> + pu0506 = pu0506_; +} @endif # ADD_DP_OPS diff --git a/pypcode/processors/Hexagon/data/languages/hexagon_hvx.sinc b/pypcode/processors/Hexagon/data/languages/hexagon_hvx.sinc index 0b6ede0..b2ba659 100644 --- a/pypcode/processors/Hexagon/data/languages/hexagon_hvx.sinc +++ b/pypcode/processors/Hexagon/data/languages/hexagon_hvx.sinc @@ -1,35 +1,45 @@ -# Qualcomm Hexagon HVX Instruction Set (V69) +# Qualcomm Hexagon HVX Instruction Set # NOTES: -# - HVX implemntation based upon V69 -# - HVX hardware supports either 64-byte or 128-byte vector lengths -# - Vector register write are comitted immediately - we assume assembler enforces read-after-write -# hazzards for vector registers so we do not shadow writes. +# - HVX implementation has been updated through V81 +# - HVX hardware supports either 64-byte or 128-byte vector lengths. See hexagon.slaspec for +# default length of 128-bytes. # UNDERSTANDING / ASSUMPTIONS: # - The term "forwarding" indicates that a vector update immediately modifies a tmp shadow -# register which may be read via a subequent .new access within the same execute packet. +# register which may be read via a subsequent .new access within the same execute packet. # - The vector .cur update is taken to mean a non-forwarding register update that is # committed to the register file at the end of the execute packet and not available for # reading via a .new access. -# - All conditional instructions which are conditional are treated as non-forwarding. +# - All conditional instructions are treated as non-forwarding. # - Unless specified as a .cur update, all unconditional vector register updates are treated -# as "forwarding" and commit to register file and the end of the execute packet. +# as "forwarding" and commit to register file at the end of the execute packet. # -# Vector Pair Operands (e.g., V0V1 ) +# Paired-Vector Operands (e.g., V0V1 ) # -# Vector pair unconditional write (0,4) (new vector store forwarded and comitted) -Vdd5: vdd5 is cond=0 & vdd5 & vdd5_ & SetVNRegVd5 { - export vdd5_; # must be updated unconditionally +# Vector pair unconditional write (0,4) (new vector store forwarded and committed) +# TODO: When vector swap mode is used (vddM=1) should retained nreg be affected? +# NOTE: vdd4_ has normal order and is not swapped until commit based upon vddM +Vdd5: vdd4 is cond=0 & vdd4 & vdd4_ & vddM=0 & SetVNRegVd5 { + export vdd4_; # must be updated unconditionally <> - vdd5 = vdd5_; + vdd4 = vdd4_; +} +Vdd5: vdd4R is cond=0 & vdd4R & vdd4h & vdd4l & vdd4_ & vddM=1 & SetVNRegVd5 { + export vdd4_; # must be updated unconditionally + <> + vdd4l = vdd4_($(HVX_VECTOR_SIZE)); + vdd4h = vdd4_:$(HVX_VECTOR_SIZE); } -# Vector pair temporary write (0,4) (new vector store forwarded, not comitted) -Vdd5tmp: vdd5^".tmp" is vdd5_ & vdd5 & SetVNRegVd5 { - export vdd5_; # must be updated unconditionally +# Vector pair temporary write (0,4) (new vector store forwarded, not committed) +Vdd5tmp: vdd4^".tmp" is vdd4 & vdd4_ & vddM=0 & SetVNRegVd5 { + export vdd4_; # must be updated unconditionally +} +Vdd5tmp: vdd4R^".tmp" is vdd4R & vdd4_ & vddM=1 & SetVNRegVd5 { + export vdd4_; # must be updated unconditionally } # destination vector pair (0,4) - unconditional write-only use - see Vdd5 (used for lane naming only) @@ -42,19 +52,31 @@ VddUB_0004: Vdd5^".ub" is Vdd5 { export Vdd5; } VddQF32_0004: Vdd5^".qf32" is Vdd5 { export Vdd5; } # source vector pair (0,4) - read-only use -Vss_0004:vdd5 is vdd5 { - tmp:$(HVX_VECTOR_PAIR_SIZE) = vdd5; +Vss_0004:vss4 is vss4 & vssM=0 { + tmp:$(HVX_VECTOR_PAIR_SIZE) = vss4; export tmp; } +Vss_0004:vss4R is vss4 & vss4R & vssM=1 { + local tmp:$(HVX_VECTOR_PAIR_SIZE) = 0; + tmp[0,$(HVX_VECTOR_SIZE_BITS)] = vss4[$(HVX_VECTOR_SIZE_BITS),$(HVX_VECTOR_SIZE_BITS)]; + tmp[$(HVX_VECTOR_SIZE_BITS),$(HVX_VECTOR_SIZE_BITS)] = vss4[0,$(HVX_VECTOR_SIZE_BITS)]; + export tmp; +} # read-only use - see Vuu_0812 (used for lane naming only) VssW_0004:Vss_0004^".w" is Vss_0004 { export Vss_0004; } # source vector pair (8,12) - read-only use -Vuu_0812:vuu5 is vuu5 { - tmp:$(HVX_VECTOR_PAIR_SIZE) = vuu5; +Vuu_0812:vuu4 is vuu4 & vuuM=0 { + tmp:$(HVX_VECTOR_PAIR_SIZE) = vuu4; export tmp; } +Vuu_0812:vuu4R is vuu4 & vuu4R & vuuM=1 { + local tmp:$(HVX_VECTOR_PAIR_SIZE) = 0; + tmp[0,$(HVX_VECTOR_SIZE_BITS)] = vuu4[$(HVX_VECTOR_SIZE_BITS),$(HVX_VECTOR_SIZE_BITS)]; + tmp[$(HVX_VECTOR_SIZE_BITS),$(HVX_VECTOR_SIZE_BITS)] = vuu4[0,$(HVX_VECTOR_SIZE_BITS)]; + export tmp; +} # read-only use - see Vuu_0812 (used for lane naming only) VuuW_0812:Vuu_0812^".w" is Vuu_0812 { export Vuu_0812; } @@ -66,10 +88,16 @@ VuuUB_0812:Vuu_0812^".ub" is Vuu_0812 { export Vuu_0812; } VuuQF32_0812: Vuu_0812^".qf32" is Vuu_0812 { export Vuu_0812; } # source vector pair (16,20) - read-only use -Vvv_1620:vvv5 is vvv5 { - tmp:$(HVX_VECTOR_PAIR_SIZE) = vvv5; +Vvv_1620:vvv4 is vvv4 & vvvM=0 { + tmp:$(HVX_VECTOR_PAIR_SIZE) = vvv4; export tmp; } +Vvv_1620:vvv4R is vvv4 & vvv4R & vvvM=1 { + local tmp:$(HVX_VECTOR_PAIR_SIZE) = 0; + tmp[0,$(HVX_VECTOR_SIZE_BITS)] = vvv4[$(HVX_VECTOR_SIZE_BITS),$(HVX_VECTOR_SIZE_BITS)]; + tmp[$(HVX_VECTOR_SIZE_BITS),$(HVX_VECTOR_SIZE_BITS)] = vvv4[0,$(HVX_VECTOR_SIZE_BITS)]; + export tmp; +} # read-only use - see Vvv_1620 (used for lane naming only) VvvW_1620:Vvv_1620^".w" is Vvv_1620 { export Vvv_1620; } @@ -83,7 +111,7 @@ VvvUB_1620:Vvv_1620^".ub" is Vvv_1620 { export Vvv_1620; } # Single Vector Operands (e.g., V0) # -# Vector unconditional write (new vector store forwarded and comitted) +# Vector unconditional write (new vector store forwarded and committed) Vd5: vd5 is cond=0 & vd5 & vd5_ & SetVNRegVd5 { export vd5_; # must be updated unconditionally <> @@ -105,8 +133,9 @@ Vd5cur: vd5^".cur" is cond=1 & vd5 & vd5_ { } -# Vector temporary write (new vector store forwarded, not comitted) -Vd5tmp: vd5^".tmp" is vd5 & vd5_ & SetVNRegVd5 { +# Vector temporary write (new vector store forwarded, not committed) +# .tmp vector is also established for use by vhist... and vwhist... instructions +Vd5tmp: vd5^".tmp" is vd5 & vd5_ & SetVNRegVd5 [ tmpvreg=vd5; ] { export vd5_; } @@ -182,6 +211,11 @@ VzB_1923: Vz_1923^".b" is Vz_1923 { export Vz_1923; } VzUW_1923: Vz_1923^".uw" is Vz_1923 { export Vz_1923; } VzUH_1923: Vz_1923^".uh" is Vz_1923 { export Vz_1923; } +# Base address of vector register Vu within the register space - used by vextract +VuBase_0812: vbase is op0812 [ vbase = $(HVX_VECTOR_BASE) + (op0812 * $(HVX_VECTOR_SIZE)); ] { + export *[const]:4 vbase; +} + # # General register operand w/ lanes # @@ -217,6 +251,18 @@ Qv_1112_S05: "!"^qv1112 is qv1112 & op5=1 { tmp:$(HVX_PREDICATE_SIZE) = ~qv1112; export tmp; } + +# Vector predicate source qv0809 (inverted) +Qv0809Not: "!"^qv0809 is qv0809 { + tmp:$(HVX_PREDICATE_SIZE) = ~qv0809; + export tmp; +} + +# Vector predicate source qv2223 (inverted) +Qv2223Not: "!"^qv2223 is qv2223 { + tmp:$(HVX_PREDICATE_SIZE) = ~qv2223; + export tmp; +} # Predicate Register Condition (least significant bit only) @@ -257,7 +303,6 @@ VPuCond1112_S05: ".if(!"pu1112name")" is op5=1 & pu1112 & pu1112name [cond=1;] ConditionReg = condition; } - # Signed immediate s3 Simm32_0810: "#"^s0810 is s0810 { export *[const]:4 s0810; } @@ -277,7 +322,7 @@ VAlignMemAddrRxAIMu: "("^rx5^"++"^mu^")" is cond=1 & rx5 & rx5_ & mu { tmp:4 = rx5 + mu; ptr:4 = rx5 & ~(0x3F); # align offset export *[ram]:$(HVX_VECTOR_SIZE) ptr; -<> + <> if (ConditionReg == 0) goto ; rx5 = tmp; @@ -286,15 +331,17 @@ VAlignMemAddrRxAIMu: "("^rx5^"++"^mu^")" is cond=1 & rx5 & rx5_ & mu { # Vector memory (rx++Mu) unaligned load/store vector-sized ram address # -- 'cond=1' context must be set by conditional instructions! VMemAddrRxAIMu: "("^rx5^"++"^mu^")" is cond=0 & rx5 & rx5_ & mu { + ptr:4 = rx5; # pre-increment address snapshot -- rx5 may be updated before the access is emitted tmp:4 = rx5 + mu; - export *[ram]:$(HVX_VECTOR_SIZE) rx5; + export *[ram]:$(HVX_VECTOR_SIZE) ptr; <> rx5 = tmp; } VMemAddrRxAIMu: "("^rx5^"++"^mu^")" is cond=1 & rx5 & rx5_ & mu { + ptr:4 = rx5; # pre-increment address snapshot -- rx5 may be updated before the access is emitted tmp:4 = rx5 + mu; - export *[ram]:$(HVX_VECTOR_SIZE) rx5; -<> + export *[ram]:$(HVX_VECTOR_SIZE) ptr; + <> if (ConditionReg == 0) goto ; rx5 = tmp; @@ -313,7 +360,7 @@ VAlignMemAddrRxAIS3: "("^rx5^"++"^Simm32_0810^")" is cond=1 & rx5 & rx5_ & Simm3 tmp:4 = rx5 + (Simm32_0810 * $(HVX_VECTOR_SIZE) ); ptr:4 = rx5 & ~(0x3F); # align offset export *[ram]:$(HVX_VECTOR_SIZE) ptr; -<> + <> if (ConditionReg == 0) goto ; rx5 = tmp; @@ -322,15 +369,17 @@ VAlignMemAddrRxAIS3: "("^rx5^"++"^Simm32_0810^")" is cond=1 & rx5 & rx5_ & Simm3 # Vector memory (rx++#s3) unaligned load/store vector-sized ram address # -- 'cond=1' context must be set by conditional instructions! VMemAddrRxAIS3: "("^rx5^"++"^Simm32_0810^")" is cond=0 & rx5 & rx5_ & Simm32_0810 { + ptr:4 = rx5; # pre-increment address snapshot -- rx5 may be updated before the access is emitted tmp:4 = rx5 + (Simm32_0810 * $(HVX_VECTOR_SIZE) ); - export *[ram]:$(HVX_VECTOR_SIZE) rx5; + export *[ram]:$(HVX_VECTOR_SIZE) ptr; <> rx5 = tmp; } VMemAddrRxAIS3: "("^rx5^"++"^Simm32_0810^")" is cond=1 & rx5 & rx5_ & Simm32_0810 { + ptr:4 = rx5; # pre-increment address snapshot -- rx5 may be updated before the access is emitted tmp:4 = rx5 + (Simm32_0810 * $(HVX_VECTOR_SIZE) ); - export *[ram]:$(HVX_VECTOR_SIZE) rx5; -<> + export *[ram]:$(HVX_VECTOR_SIZE) ptr; + <> if (ConditionReg == 0) goto ; rx5 = tmp; @@ -343,7 +392,7 @@ VAlignMemAddrRxS4: "("^rx5^"+"^Simm32_0810_13^")" is rx5 & Simm32_0810_13 { export *[ram]:$(HVX_VECTOR_SIZE) ptr; } VAlignMemAddrRxS4: "("^rx5^")" is rx5 & op0810=0 & op13=0 { - ptr = rx5 & ~(0x3F); # align offset + local ptr = rx5 & ~(0x3F); # align offset export *[ram]:$(HVX_VECTOR_SIZE) ptr; } @@ -365,63 +414,137 @@ ntHint22:":nt" is op22=1 { } # HVX Instructions # -# (hvx,1) "vwhist256" +# (v60,1) "vwhist256" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| # 0 0 0 1 1 1 1 0 - - 0 - - 0 0 0 P P 1 - 0 0 1 0 1 0 0 - - - - - -:vwhist256 EndPacket is iclass=0x1 & op2427=0xe & op21=0x0 & op18=0x0 & op1617=0x0 & op13=0x1 & op0911=0x1 & op0508=0x4 & $(END_PACKET) unimpl +define pcodeop vwhist256; -# (hvx,1) vwhist256 -- "vwhist256:sat" +:vwhist256 EndPacket is iclass=0x1 & op2427=0xe & op21=0x0 & op18=0x0 & op1617=0x0 & op13=0x1 & op0911=0x1 & op0508=0x4 & tmpvreg_ & $(END_PACKET) { + build EndPacket; + <> + vwhist256(tmpvreg_); # TODO: Does not properly convey vector inputs/outputs +} + +# (v60,1) vwhist256 -- "vwhist256:sat" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| # 0 0 0 1 1 1 1 0 - - 0 - - 0 0 0 P P 1 - 0 0 1 1 1 0 0 - - - - - -:vwhist256^":sat" EndPacket is iclass=0x1 & op2427=0xe & op21=0x0 & op18=0x0 & op1617=0x0 & op13=0x1 & op0911=0x1 & op0508=0xc & $(END_PACKET) unimpl +define pcodeop vwhist256sat; + +:vwhist256^":sat" EndPacket is iclass=0x1 & op2427=0xe & op21=0x0 & op18=0x0 & op1617=0x0 & op13=0x1 & op0911=0x1 & op0508=0xc & tmpvreg_ & $(END_PACKET) { + build EndPacket; + <> + vwhist256sat(tmpvreg_); # TODO: Does not properly convey vector inputs/outputs +} -# (hvx,1) "vwhist128" +# (v60,1) "vwhist128" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| # 0 0 0 1 1 1 1 0 - - 0 - - 0 0 0 P P 1 - 0 1 0 - 1 0 0 - - - - - -:vwhist128 EndPacket is iclass=0x1 & op2427=0xe & op21=0x0 & op18=0x0 & op1617=0x0 & op13=0x1 & op0911=0x2 & op0507=0x4 & $(END_PACKET) unimpl +define pcodeop vwhist128; -# (hvx,1) vwhist128 -- "vwhist128(#u1)" +:vwhist128 EndPacket is iclass=0x1 & op2427=0xe & op21=0x0 & op18=0x0 & op1617=0x0 & op13=0x1 & op0911=0x2 & op0507=0x4 & tmpvreg_ & $(END_PACKET) { + build EndPacket; + <> + vwhist128(tmpvreg_); # TODO: Does not properly convey vector inputs/outputs +} + +# (v60,1) vwhist128 -- "vwhist128(#u1)" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| # 0 0 0 1 1 1 1 0 - - 0 - - 0 0 0 P P 1 - 0 1 1 i 1 0 0 - - - - - -:vwhist128 "#"^i8 EndPacket is iclass=0x1 & op2427=0xe & op21=0x0 & op18=0x0 & op1617=0x0 & op13=0x1 & op0911=0x3 & op0507=0x4 & i8 & $(END_PACKET) unimpl +define pcodeop vwhist128u; + +:vwhist128 "#"^i8 EndPacket is iclass=0x1 & op2427=0xe & op21=0x0 & op18=0x0 & op1617=0x0 & op13=0x1 & op0911=0x3 & op0507=0x4 & i8 & tmpvreg_ & $(END_PACKET) { + build EndPacket; + <> + vwhist128u(tmpvreg_); # TODO: Does not properly convey vector inputs/outputs +} -# (hvx,1) vwhist256 -- "vwhist256(Qv4)" +# (v60,1) vwhist256 -- "vwhist256(Qv4)" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| # 0 0 0 1 1 1 1 0 v v 0 - - 0 1 0 P P 1 - - 0 1 0 1 0 0 - - - - - -:vwhist256 qv2223 EndPacket is iclass=0x1 & op2427=0xe & op21=0x0 & op18=0x0 & op1617=0x2 & op13=0x1 & op0810=0x2 & op0507=0x4 & qv2223 & $(END_PACKET) unimpl +define pcodeop vwhist256q; + +:vwhist256 qv2223 EndPacket is iclass=0x1 & op2427=0xe & op21=0x0 & op18=0x0 & op1617=0x2 & op13=0x1 & op0810=0x2 & op0507=0x4 & qv2223 & tmpvreg_ & $(END_PACKET) { + build EndPacket; + <> + vwhist256q(qv2223, tmpvreg_); # TODO: Does not properly convey vector inputs/outputs +} -# (hvx,1) vwhist256 -- "vwhist256(Qv4):sat" +# (v60,1) vwhist256 -- "vwhist256(Qv4):sat" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| # 0 0 0 1 1 1 1 0 v v 0 - - 0 1 0 P P 1 - - 0 1 1 1 0 0 - - - - - -:vwhist256^":sat" qv2223 EndPacket is iclass=0x1 & op2427=0xe & op21=0x0 & op18=0x0 & op1617=0x2 & op13=0x1 & op0810=0x3 & op0507=0x4 & qv2223 & $(END_PACKET) unimpl +define pcodeop vwhist256qsat; -# (hvx,1) vwhist128 -- "vwhist128(Qv4)" +:vwhist256^":sat" qv2223 EndPacket is iclass=0x1 & op2427=0xe & op21=0x0 & op18=0x0 & op1617=0x2 & op13=0x1 & op0810=0x3 & op0507=0x4 & qv2223 & tmpvreg_ & $(END_PACKET) { + build EndPacket; + <> + vwhist256qsat(qv2223, tmpvreg_); # TODO: Does not properly convey vector inputs/outputs +} + +# (v60,1) vwhist128 -- "vwhist128(Qv4)" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| # 0 0 0 1 1 1 1 0 v v 0 - - 0 1 0 P P 1 - - 1 0 - 1 0 0 - - - - - -:vwhist128 qv2223 EndPacket is iclass=0x1 & op2427=0xe & op21=0x0 & op18=0x0 & op1617=0x2 & op13=0x1 & op0910=0x2 & op0507=0x4 & qv2223 & $(END_PACKET) unimpl +define pcodeop vwhist128q; -# (hvx,1) vwhist128 -- "vwhist128(Qv4,#u1)" +:vwhist128 qv2223 EndPacket is iclass=0x1 & op2427=0xe & op21=0x0 & op18=0x0 & op1617=0x2 & op13=0x1 & op0910=0x2 & op0507=0x4 & qv2223 & tmpvreg_ & $(END_PACKET) { + build EndPacket; + <> + vwhist128q(qv2223, tmpvreg_); # TODO: Does not properly convey vector inputs/outputs +} + +# (v60,1) vwhist128 -- "vwhist128(Qv4,#u1)" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| # 0 0 0 1 1 1 1 0 v v 0 - - 0 1 0 P P 1 - - 1 1 i 1 0 0 - - - - - -:vwhist128 qv2223,"#"^i8 EndPacket is iclass=0x1 & op2427=0xe & op21=0x0 & op18=0x0 & op1617=0x2 & op13=0x1 & op0910=0x3 & op0507=0x4 & qv2223 & i8 & $(END_PACKET) unimpl +define pcodeop vwhist128qu; -# (hvx,1) and -- "Qd4=and(Qs4,Qt4)" +:vwhist128 qv2223,"#"^i8 EndPacket is iclass=0x1 & op2427=0xe & op21=0x0 & op18=0x0 & op1617=0x2 & op13=0x1 & op0910=0x3 & op0507=0x4 & qv2223 & i8 & tmpvreg_ & $(END_PACKET) { + build EndPacket; + <> + vwhist128qu(qv2223, tmpvreg_); # TODO: Does not properly convey vector inputs/outputs +} + +# (v60,1) vhist -- "vhist" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 1 1 1 0 - - 0 - - 0 0 0 P P 1 - 0 0 0 - 1 0 0 - - - - - + +define pcodeop vhist; + +:vhist EndPacket is iclass=0x1 & op2427=0xe & op21=0x0 & op18=0x0 & op1617=0x0 & op13=0x1 & op0911=0x0 & op0507=0x4 & tmpvreg_ & $(END_PACKET) { + build EndPacket; + <> + vhist(tmpvreg_); # TODO: Does not properly convey vector inputs/outputs +} + +# (v60,1) vhist -- "vhist(Qv4)" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 1 1 1 0 v v 0 - - 0 1 0 P P 1 - - 0 0 - 1 0 0 - - - - - + +define pcodeop vhistq; + +:vhist qv2223 EndPacket is iclass=0x1 & op2427=0xe & op21=0x0 & op18=0x0 & op1617=0x2 & op13=0x1 & op0910=0x0 & op0507=0x4 & qv2223 & tmpvreg_ & $(END_PACKET) { + build EndPacket; + <> + vhistq(qv2223, tmpvreg_); # TODO: Does not properly convey vector inputs/outputs +} + +# (v60,1) and -- "Qd4=and(Qs4,Qt4)" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| # 0 0 0 1 1 1 1 0 t t 0 - - - 1 1 P P 0 - - - s s 0 0 0 0 0 0 d d @@ -431,47 +554,47 @@ ntHint22:":nt" is op22=1 { } build EndPacket; } -# (hvx,1) or -- "Qd4=or(Qs4,Qt4)" +# (v60,1) and -- "Qd4=and(Qs4,!Qt4)" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 0 0 0 1 1 1 1 0 t t 0 - - - 1 1 P P 0 - - - s s 0 0 0 0 0 1 d d +# 0 0 0 1 1 1 1 0 t t 0 - - - 1 1 P P 0 - - - s s 0 0 0 1 0 1 d d -:or Qd2,qv0809,qv2223 EndPacket is iclass=0x1 & op2427=0xe & op21=0x0 & op1617=0x3 & op13=0x0 & op0207=0x1 & Qd2 & qv0809 & qv2223 & $(END_PACKET) { - Qd2 = qv0809 | qv2223; +:and Qd2,qv0809,Qv2223Not EndPacket is iclass=0x1 & op2427=0xe & op21=0x0 & op1617=0x3 & op13=0x0 & op0207=0x5 & Qd2 & qv0809 & Qv2223Not & $(END_PACKET) { + Qd2 = qv0809 & Qv2223Not; build EndPacket; } -# (hvx,1) xor -- "Qd4=xor(Qs4,Qt4)" +# (v60,1) or -- "Qd4=or(Qs4,Qt4)" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 0 0 0 1 1 1 1 0 t t 0 - - - 1 1 P P 0 - - - s s 0 0 0 0 1 1 d d +# 0 0 0 1 1 1 1 0 t t 0 - - - 1 1 P P 0 - - - s s 0 0 0 0 0 1 d d -:xor Qd2,qv0809,qv2223 EndPacket is iclass=0x1 & op2427=0xe & op21=0x0 & op1617=0x3 & op13=0x0 & op0207=0x3 & Qd2 & qv0809 & qv2223 & $(END_PACKET) { - Qd2 = qv0809 ^ qv2223; +:or Qd2,qv0809,qv2223 EndPacket is iclass=0x1 & op2427=0xe & op21=0x0 & op1617=0x3 & op13=0x0 & op0207=0x1 & Qd2 & qv0809 & qv2223 & $(END_PACKET) { + Qd2 = qv0809 | qv2223; build EndPacket; } -# (hvx,1) or -- "Qd4=or(Qs4,!Qt4)" +# (v60,1) or -- "Qd4=or(Qs4,!Qt4)" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| # 0 0 0 1 1 1 1 0 t t 0 - - - 1 1 P P 0 - - - s s 0 0 0 1 0 0 d d -:or Qd2,qv0809,"!"^qv2223 EndPacket is iclass=0x1 & op2427=0xe & op21=0x0 & op1617=0x3 & op13=0x0 & op0207=0x4 & Qd2 & qv0809 & qv2223 & $(END_PACKET) { - Qd2 = qv0809 | ~qv2223; +:or Qd2,qv0809,Qv2223Not EndPacket is iclass=0x1 & op2427=0xe & op21=0x0 & op1617=0x3 & op13=0x0 & op0207=0x4 & Qd2 & qv0809 & Qv2223Not & $(END_PACKET) { + Qd2 = qv0809 | Qv2223Not; build EndPacket; } -# (hvx,1) and -- "Qd4=and(Qs4,!Qt4)" +# (v60,1) xor -- "Qd4=xor(Qs4,Qt4)" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 0 0 0 1 1 1 1 0 t t 0 - - - 1 1 P P 0 - - - s s 0 0 0 1 0 1 d d +# 0 0 0 1 1 1 1 0 t t 0 - - - 1 1 P P 0 - - - s s 0 0 0 0 1 1 d d -:and Qd2,qv0809,"!"^qv2223 EndPacket is iclass=0x1 & op2427=0xe & op21=0x0 & op1617=0x3 & op13=0x0 & op0207=0x5 & Qd2 & qv0809 & qv2223 & $(END_PACKET) { - Qd2 = qv0809 & ~qv2223; +:xor Qd2,qv0809,qv2223 EndPacket is iclass=0x1 & op2427=0xe & op21=0x0 & op1617=0x3 & op13=0x0 & op0207=0x3 & Qd2 & qv0809 & qv2223 & $(END_PACKET) { + Qd2 = qv0809 ^ qv2223; build EndPacket; } -# (hvx,1) vshuffe -- "Qd4.b=vshuffe(Qs4.h,Qt4.h)" +# (v60,1) vshuffe -- "Qd4.b=vshuffe(Qs4.h,Qt4.h)" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| # 0 0 0 1 1 1 1 0 t t 0 - - - 1 1 P P 0 - - - s s 0 0 0 1 1 0 d d @@ -483,7 +606,7 @@ define pcodeop vshuffe_QhQh; build EndPacket; } -# (hvx,1) vshuffe -- "Qd4.h=vshuffe(Qs4.w,Qt4.w)" +# (v60,1) vshuffe -- "Qd4.h=vshuffe(Qs4.w,Qt4.w)" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| # 0 0 0 1 1 1 1 0 t t 0 - - - 1 1 P P 0 - - - s s 0 0 0 1 1 1 d d @@ -495,32 +618,54 @@ define pcodeop vshuffe_QwQw; build EndPacket; } -# (hvx,1) vcombine -- "if (!Ps) Vdd=vcombine(Vu,Vv)" +# (v60,1) vcombine -- "if (!Ps) Vdd=vcombine(Vu,Vv)" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| # 0 0 0 1 1 0 1 0 0 1 0 v v v v v P P - u u u u u - s s d d d d d # -# (hvx,1) vcombine -- "if (Ps) Vdd=vcombine(Vu,Vv)" +# (v60,1) vcombine -- "if (Ps) Vdd=vcombine(Vu,Vv)" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| # 0 0 0 1 1 0 1 0 0 1 1 v v v v v P P - u u u u u - s s d d d d d define pcodeop vcombine; -:vcombine^VPuCond0506_S21 vdd5,Vu_0812,Vv_1620 EndPacket is iclass=0x1 & op2227=0x29 & VPuCond0506_S21 & vdd5 & vdd5_ & SetNRegRd5 & Vu_0812 & Vv_1620 & $(END_PACKET) { +:vcombine^VPuCond0506_S21 vdd4,Vu_0812,Vv_1620 EndPacket is iclass=0x1 & op2227=0x29 & vddM=0 & VPuCond0506_S21 & vdd4 & vdd4_ & SetNRegRd5 & Vu_0812 & Vv_1620 & $(END_PACKET) { build VPuCond0506_S21; + build Vu_0812; + build Vv_1620; build EndPacket; <> + build VPuCond0506_S21; if (ConditionReg == 0) goto ; - vdd5_ = vcombine(Vu_0812,Vv_1620); + vdd4_ = vcombine(Vu_0812,Vv_1620); <> + build VPuCond0506_S21; if (ConditionReg == 0) goto ; - vdd5 = vdd5_; - + vdd4 = vdd4_; + +} +# (v67,1) vcombine -- "if ([!]Qv4) Vdd32.swap = vcombine(Vu32,Vv32)" +:vcombine^VPuCond0506_S21 vdd4R,Vu_0812,Vv_1620 EndPacket is iclass=0x1 & op2227=0x29 & vddM=1 & VPuCond0506_S21 & vdd4 & vdd4R & vdd4l & vdd4h & vdd4_ & SetNRegRd5 & Vu_0812 & Vv_1620 & $(END_PACKET) { + build VPuCond0506_S21; + build Vu_0812; + build Vv_1620; + build EndPacket; + <> + build VPuCond0506_S21; + if (ConditionReg == 0) goto ; + vdd4_ = vcombine(Vu_0812,Vv_1620); + + <> + build VPuCond0506_S21; + if (ConditionReg == 0) goto ; + vdd4l = vdd4_($(HVX_VECTOR_SIZE)); + vdd4h = vdd4_:$(HVX_VECTOR_SIZE); + } -# (hvx,1) vcombine -- "Vdd=vcombine(Vu,Vv)" +# (v60,1) vcombine -- "Vdd=vcombine(Vu,Vv)" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| # 0 0 0 1 1 1 1 1 0 1 0 v v v v v P P 0 u u u u u 1 1 1 d d d d d @@ -530,7 +675,7 @@ define pcodeop vcombine; build EndPacket; } -# (hvx,1) vshuffoe -- "Vdd.h=vshuffoe(Vu.h,Vv.h)" +# (v60,1) vshuffoe -- "Vdd.h=vshuffoe(Vu.h,Vv.h)" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| # 0 0 0 1 1 1 1 1 0 1 0 v v v v v P P 0 u u u u u 1 0 1 d d d d d @@ -542,7 +687,7 @@ define pcodeop vshuffoe_VhVh; build EndPacket; } -# (hvx,1) vshuffoe -- "Vdd.b=vshuffoe(Vu.b,Vv.b)" +# (v60,1) vshuffoe -- "Vdd.b=vshuffoe(Vu.b,Vv.b)" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| # 0 0 0 1 1 1 1 1 0 1 0 v v v v v P P 0 u u u u u 1 1 0 d d d d d @@ -554,7 +699,7 @@ define pcodeop vshuffoe_VbVb; build EndPacket; } -# (hvx,1) vswap -- "Vdd=vswap(Qt4,Vu,Vv)" +# (v60,1) vswap -- "Vdd=vswap(Qt4,Vu,Vv)" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| # 0 0 0 1 1 1 1 0 1 0 1 v v v v v P P 1 u u u u u - t t d d d d d @@ -566,7 +711,7 @@ define pcodeop vswap_QVwVw; build EndPacket; } -# (hvx,1) vzxt -- "Vdd.uh=vzxt(Vu.ub)" +# (v60,1) vzxt -- "Vdd.uh=vzxt(Vu.ub)" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| # 0 0 0 1 1 1 1 0 - - 0 - - - 1 0 P P 0 u u u u u 0 0 1 d d d d d @@ -578,7 +723,7 @@ define pcodeop vzxt_Vub; build EndPacket; } -# (hvx,1) vzxt -- "Vdd.uw=vzxt(Vu.uh)" +# (v60,1) vzxt -- "Vdd.uw=vzxt(Vu.uh)" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| # 0 0 0 1 1 1 1 0 - - 0 - - - 1 0 P P 0 u u u u u 0 1 0 d d d d d @@ -590,7 +735,7 @@ define pcodeop vzxt_Vuh; build EndPacket; } -# (hvx,1) vsxt -- "Vdd.h=vsxt(Vu.b)" +# (v60,1) vsxt -- "Vdd.h=vsxt(Vu.b)" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| # 0 0 0 1 1 1 1 0 - - 0 - - - 1 0 P P 0 u u u u u 0 1 1 d d d d d @@ -602,7 +747,7 @@ define pcodeop vsxt_Vb; build EndPacket; } -# (hvx,1) vsxt -- "Vdd.w=vsxt(Vu.h)" +# (v60,1) vsxt -- "Vdd.w=vsxt(Vu.h)" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| # 0 0 0 1 1 1 1 0 - - 0 - - - 1 0 P P 0 u u u u u 1 0 0 d d d d d @@ -614,7 +759,7 @@ define pcodeop Ww_vsxt_Vh; build EndPacket; } -# (hvx,1) vadd -- "Vdd.b=vadd(Vuu.b,Vvv.b)" +# (v60,1) vadd -- "Vdd.b=vadd(Vuu.b,Vvv.b)" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| # 0 0 0 1 1 1 0 0 0 1 1 v v v v v P P 0 u u u u u 1 0 0 d d d d d @@ -626,7 +771,7 @@ define pcodeop vadd_WbWb; build EndPacket; } -# (hvx,1) vadd -- "Vdd.h=vadd(Vuu.h,Vvv.h)" +# (v60,1) vadd -- "Vdd.h=vadd(Vuu.h,Vvv.h)" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| # 0 0 0 1 1 1 0 0 0 1 1 v v v v v P P 0 u u u u u 1 0 1 d d d d d @@ -638,7 +783,7 @@ define pcodeop vadd_WhWh; build EndPacket; } -# (hvx,1) vadd -- "Vdd.w=vadd(Vuu.w,Vvv.w)" +# (v60,1) vadd -- "Vdd.w=vadd(Vuu.w,Vvv.w)" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| # 0 0 0 1 1 1 0 0 0 1 1 v v v v v P P 0 u u u u u 1 1 0 d d d d d @@ -650,7 +795,7 @@ define pcodeop Ww_vadd_WwWw; build EndPacket; } -# (hvx,1) vadd -- "Vdd.ub=vadd(Vuu.ub,Vvv.ub):sat" +# (v60,1) vadd -- "Vdd.ub=vadd(Vuu.ub,Vvv.ub):sat" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| # 0 0 0 1 1 1 0 0 0 1 1 v v v v v P P 0 u u u u u 1 1 1 d d d d d @@ -662,7 +807,7 @@ define pcodeop vadd_WubWub_sat; build EndPacket; } -# (hvx,1) vadd -- "Vdd.uh=vadd(Vuu.uh,Vvv.uh):sat" +# (v60,1) vadd -- "Vdd.uh=vadd(Vuu.uh,Vvv.uh):sat" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| # 0 0 0 1 1 1 0 0 1 0 0 v v v v v P P 0 u u u u u 0 0 0 d d d d d @@ -674,7 +819,7 @@ define pcodeop vadd_WuhWuh_sat; build EndPacket; } -# (hvx,1) vadd -- "Vdd.h=vadd(Vuu.h,Vvv.h):sat" +# (v60,1) vadd -- "Vdd.h=vadd(Vuu.h,Vvv.h):sat" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| # 0 0 0 1 1 1 0 0 1 0 0 v v v v v P P 0 u u u u u 0 0 1 d d d d d @@ -686,7 +831,7 @@ define pcodeop vadd_WhWh_sat; build EndPacket; } -# (hvx,1) vadd -- "Vdd.w=vadd(Vuu.w,Vvv.w):sat" +# (v60,1) vadd -- "Vdd.w=vadd(Vuu.w,Vvv.w):sat" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| # 0 0 0 1 1 1 0 0 1 0 0 v v v v v P P 0 u u u u u 0 1 0 d d d d d @@ -698,7 +843,7 @@ define pcodeop Ww_vadd_WwWw_sat; build EndPacket; } -# (hvx,1) vsub -- "Vdd.b=vsub(Vuu.b,Vvv.b)" +# (v60,1) vsub -- "Vdd.b=vsub(Vuu.b,Vvv.b)" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| # 0 0 0 1 1 1 0 0 1 0 0 v v v v v P P 0 u u u u u 0 1 1 d d d d d @@ -710,7 +855,7 @@ define pcodeop vsub_WbWb; build EndPacket; } -# (hvx,1) vsub -- "Vdd.h=vsub(Vuu.h,Vvv.h)" +# (v60,1) vsub -- "Vdd.h=vsub(Vuu.h,Vvv.h)" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| # 0 0 0 1 1 1 0 0 1 0 0 v v v v v P P 0 u u u u u 1 0 0 d d d d d @@ -722,7 +867,7 @@ define pcodeop vsub_WhWh; build EndPacket; } -# (hvx,1) vsub -- "Vdd.w=vsub(Vuu.w,Vvv.w)" +# (v60,1) vsub -- "Vdd.w=vsub(Vuu.w,Vvv.w)" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| # 0 0 0 1 1 1 0 0 1 0 0 v v v v v P P 0 u u u u u 1 0 1 d d d d d @@ -734,7 +879,7 @@ define pcodeop Ww_vsub_WwWw; build EndPacket; } -# (hvx,1) vsub -- "Vdd.ub=vsub(Vuu.ub,Vvv.ub):sat" +# (v60,1) vsub -- "Vdd.ub=vsub(Vuu.ub,Vvv.ub):sat" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| # 0 0 0 1 1 1 0 0 1 0 0 v v v v v P P 0 u u u u u 1 1 0 d d d d d @@ -746,7 +891,7 @@ define pcodeop vsub_WubWub_sat; build EndPacket; } -# (hvx,1) vsub -- "Vdd.uh=vsub(Vuu.uh,Vvv.uh):sat" +# (v60,1) vsub -- "Vdd.uh=vsub(Vuu.uh,Vvv.uh):sat" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| # 0 0 0 1 1 1 0 0 1 0 0 v v v v v P P 0 u u u u u 1 1 1 d d d d d @@ -758,7 +903,7 @@ define pcodeop vsub_WuhWuh_sat; build EndPacket; } -# (hvx,1) vsub -- "Vdd.h=vsub(Vuu.h,Vvv.h):sat" +# (v60,1) vsub -- "Vdd.h=vsub(Vuu.h,Vvv.h):sat" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| # 0 0 0 1 1 1 0 0 1 0 1 v v v v v P P 0 u u u u u 0 0 0 d d d d d @@ -770,7 +915,7 @@ define pcodeop vsub_WhWh_sat; build EndPacket; } -# (hvx,1) vsub -- "Vdd.w=vsub(Vuu.w,Vvv.w):sat" +# (v60,1) vsub -- "Vdd.w=vsub(Vuu.w,Vvv.w):sat" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| # 0 0 0 1 1 1 0 0 1 0 1 v v v v v P P 0 u u u u u 0 0 1 d d d d d @@ -782,7 +927,7 @@ define pcodeop Ww_vsub_WwWw_sat; build EndPacket; } -# (hvx,1) vadd -- "Vdd.b=vadd(Vuu.b,Vvv.b):sat" +# (v60,1) vadd -- "Vdd.b=vadd(Vuu.b,Vvv.b):sat" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| # 0 0 0 1 1 1 1 0 1 0 1 v v v v v P P 0 u u u u u 0 0 0 d d d d d @@ -794,7 +939,7 @@ define pcodeop vadd_WbWb_sat; build EndPacket; } -# (hvx,1) vsub -- "Vdd.b=vsub(Vuu.b,Vvv.b):sat" +# (v60,1) vsub -- "Vdd.b=vsub(Vuu.b,Vvv.b):sat" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| # 0 0 0 1 1 1 1 0 1 0 1 v v v v v P P 0 u u u u u 0 0 1 d d d d d @@ -806,7 +951,7 @@ define pcodeop vsub_WbWb_sat; build EndPacket; } -# (hvx,1) vadd -- "Vdd.uw=vadd(Vuu.uw,Vvv.uw):sat" +# (v60,1) vadd -- "Vdd.uw=vadd(Vuu.uw,Vvv.uw):sat" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| # 0 0 0 1 1 1 1 0 1 0 1 v v v v v P P 0 u u u u u 0 1 0 d d d d d @@ -818,7 +963,7 @@ define pcodeop vadd_WuwWuw_sat; build EndPacket; } -# (hvx,1) vsub -- "Vdd.uw=vsub(Vuu.uw,Vvv.uw):sat" +# (v60,1) vsub -- "Vdd.uw=vsub(Vuu.uw,Vvv.uw):sat" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| # 0 0 0 1 1 1 1 0 1 0 1 v v v v v P P 0 u u u u u 0 1 1 d d d d d @@ -830,7 +975,7 @@ define pcodeop vsub_WuwWuw_sat; build EndPacket; } -# (hvx,1) not -- "Qd4=not(Qs4)" +# (v60,1) not -- "Qd4=not(Qs4)" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| # 0 0 0 1 1 1 1 0 - - 0 - - - 1 1 P P 0 - - - s s 0 0 0 0 1 0 d d @@ -840,10 +985,11 @@ define pcodeop vsub_WuwWuw_sat; build EndPacket; } -# (hvx,1) vand -- "Vd=vand(Qv4,Vu)" +# (v60,1) vand -- "Vd=vand(Qv4,Vu)" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| # 0 0 0 1 1 1 1 0 v v 0 - - 0 1 1 P P 1 u u u u u 0 0 0 d d d d d +# define pcodeop vand_QV; @@ -852,17 +998,17 @@ define pcodeop vand_QV; build EndPacket; } -# (hvx,1) vand -- "Vd=vand(!Qv4,Vu)" +# (v60,1) vand -- "Vd=vand(!Qv4,Vu)" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| # 0 0 0 1 1 1 1 0 v v 0 - - 0 1 1 P P 1 u u u u u 0 0 1 d d d d d -:vand Vd5,qv2223,Vu_0812 EndPacket is iclass=0x1 & op2427=0xe & op21=0x0 & op18=0x0 & op1617=0x3 & op13=0x1 & op0507=0x1 & Vd5 & qv2223 & Vu_0812 & $(END_PACKET) { - Vd5 = vand_QV(~qv2223,Vu_0812); +:vand Vd5,Qv2223Not,Vu_0812 EndPacket is iclass=0x1 & op2427=0xe & op21=0x0 & op18=0x0 & op1617=0x3 & op13=0x1 & op0507=0x1 & Vd5 & Qv2223Not & Vu_0812 & $(END_PACKET) { + Vd5 = vand_QV(Qv2223Not,Vu_0812); build EndPacket; } -# (hvx,1) vmin -- "Vd.ub=vmin(Vu.ub,Vv.ub)" +# (v60,1) vmin -- "Vd.ub=vmin(Vu.ub,Vv.ub)" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| # 0 0 0 1 1 1 1 1 0 0 0 v v v v v P P 0 u u u u u 0 0 1 d d d d d @@ -874,7 +1020,7 @@ define pcodeop vmin_VubVub; build EndPacket; } -# (hvx,1) vmin -- "Vd.uh=vmin(Vu.uh,Vv.uh)" +# (v60,1) vmin -- "Vd.uh=vmin(Vu.uh,Vv.uh)" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| # 0 0 0 1 1 1 1 1 0 0 0 v v v v v P P 0 u u u u u 0 1 0 d d d d d @@ -886,7 +1032,7 @@ define pcodeop vmin_VuhVuh; build EndPacket; } -# (hvx,1) vmin -- "Vd.h=vmin(Vu.h,Vv.h)" +# (v60,1) vmin -- "Vd.h=vmin(Vu.h,Vv.h)" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| # 0 0 0 1 1 1 1 1 0 0 0 v v v v v P P 0 u u u u u 0 1 1 d d d d d @@ -898,7 +1044,7 @@ define pcodeop vmin_VhVh; build EndPacket; } -# (hvx,1) vmin -- "Vd.w=vmin(Vu.w,Vv.w)" +# (v60,1) vmin -- "Vd.w=vmin(Vu.w,Vv.w)" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| # 0 0 0 1 1 1 1 1 0 0 0 v v v v v P P 0 u u u u u 1 0 0 d d d d d @@ -910,7 +1056,7 @@ define pcodeop vmin_VwVw; build EndPacket; } -# (hvx,1) vmax -- "Vd.ub=vmax(Vu.ub,Vv.ub)" +# (v60,1) vmax -- "Vd.ub=vmax(Vu.ub,Vv.ub)" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| # 0 0 0 1 1 1 1 1 0 0 0 v v v v v P P 0 u u u u u 1 0 1 d d d d d @@ -922,7 +1068,7 @@ define pcodeop vmax_VubVub; build EndPacket; } -# (hvx,1) vmax -- "Vd.uh=vmax(Vu.uh,Vv.uh)" +# (v60,1) vmax -- "Vd.uh=vmax(Vu.uh,Vv.uh)" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| # 0 0 0 1 1 1 1 1 0 0 0 v v v v v P P 0 u u u u u 1 1 0 d d d d d @@ -934,7 +1080,7 @@ define pcodeop vmax_VuhVuh; build EndPacket; } -# (hvx,1) vmax -- "Vd.h=vmax(Vu.h,Vv.h)" +# (v60,1) vmax -- "Vd.h=vmax(Vu.h,Vv.h)" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| # 0 0 0 1 1 1 1 1 0 0 0 v v v v v P P 0 u u u u u 1 1 1 d d d d d @@ -946,7 +1092,7 @@ define pcodeop vmax_VhVh; build EndPacket; } -# (hvx,1) vmax -- "Vd.w=vmax(Vu.w,Vv.w)" +# (v60,1) vmax -- "Vd.w=vmax(Vu.w,Vv.w)" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| # 0 0 0 1 1 1 1 1 0 0 1 v v v v v P P 0 u u u u u 0 0 0 d d d d d @@ -958,7 +1104,7 @@ define pcodeop vmax_VwVw; build EndPacket; } -# (hvx,1) vmin -- "Vd.b=vmin(Vu.b,Vv.b)" +# (v60,1) vmin -- "Vd.b=vmin(Vu.b,Vv.b)" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| # 0 0 0 1 1 1 1 1 0 0 1 v v v v v P P 0 u u u u u 1 0 0 d d d d d @@ -970,7 +1116,7 @@ define pcodeop vmin_VbVb; build EndPacket; } -# (hvx,1) vmax -- "Vd.b=vmax(Vu.b,Vv.b)" +# (v60,1) vmax -- "Vd.b=vmax(Vu.b,Vv.b)" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| # 0 0 0 1 1 1 1 1 0 0 1 v v v v v P P 0 u u u u u 1 0 1 d d d d d @@ -982,7 +1128,7 @@ define pcodeop vmax_VbVb; build EndPacket; } -# (hvx,1) vmax -- "Vd.sf=vmax(Vu.sf,Vv.sf)" +# (v60,1) vmax -- "Vd.sf=vmax(Vu.sf,Vv.sf)" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| # 0 0 0 1 1 1 1 1 1 1 0 v v v v v P P 1 u u u u u 0 0 1 d d d d d @@ -994,7 +1140,7 @@ define pcodeop vmax_VsfVsf; build EndPacket; } -# (hvx,1) vmin -- "Vd.sf=vmin(Vu.sf,Vv.sf)" +# (v60,1) vmin -- "Vd.sf=vmin(Vu.sf,Vv.sf)" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| # 0 0 0 1 1 1 1 1 1 1 0 v v v v v P P 1 u u u u u 0 1 0 d d d d d @@ -1006,7 +1152,7 @@ define pcodeop vmin_VsfVsf; build EndPacket; } -# (hvx,1) vmax -- "Vd.hf=vmax(Vu.hf,Vv.hf)" +# (v60,1) vmax -- "Vd.hf=vmax(Vu.hf,Vv.hf)" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| # 0 0 0 1 1 1 1 1 1 1 0 v v v v v P P 1 u u u u u 0 1 1 d d d d d @@ -1018,7 +1164,7 @@ define pcodeop vmax_VhfVhf; build EndPacket; } -# (hvx,1) vmin -- "Vd.hf=vmin(Vu.hf,Vv.hf)" +# (v60,1) vmin -- "Vd.hf=vmin(Vu.hf,Vv.hf)" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| # 0 0 0 1 1 1 1 1 1 1 0 v v v v v P P 1 u u u u u 1 0 0 d d d d d @@ -1030,7 +1176,7 @@ define pcodeop vmin_VhfVhf; build EndPacket; } -# (hvx,1) vabs -- "Vd.h=vabs(Vu.h)" +# (v60,1) vabs -- "Vd.h=vabs(Vu.h)" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| # 0 0 0 1 1 1 1 0 - - 0 - - - 0 0 P P 0 u u u u u 0 0 0 d d d d d @@ -1042,7 +1188,7 @@ define pcodeop vabs_Vh; build EndPacket; } -# (hvx,1) vabs -- "Vd.h=vabs(Vu.h):sat" +# (v60,1) vabs -- "Vd.h=vabs(Vu.h):sat" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| # 0 0 0 1 1 1 1 0 - - 0 - - - 0 0 P P 0 u u u u u 0 0 1 d d d d d @@ -1054,7 +1200,7 @@ define pcodeop vabs_Vh_sat; build EndPacket; } -# (hvx,1) vabs -- "Vd.w=vabs(Vu.w)" +# (v60,1) vabs -- "Vd.w=vabs(Vu.w)" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| # 0 0 0 1 1 1 1 0 - - 0 - - - 0 0 P P 0 u u u u u 0 1 0 d d d d d @@ -1066,7 +1212,7 @@ define pcodeop vabs_Vw; build EndPacket; } -# (hvx,1) vabs -- "Vd.w=vabs(Vu.w):sat" +# (v60,1) vabs -- "Vd.w=vabs(Vu.w):sat" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| # 0 0 0 1 1 1 1 0 - - 0 - - - 0 0 P P 0 u u u u u 0 1 1 d d d d d @@ -1078,7 +1224,7 @@ define pcodeop vabs_Vw_sat; build EndPacket; } -# (hvx,1) vabs -- "Vd.b=vabs(Vu.b)" +# (v60,1) vabs -- "Vd.b=vabs(Vu.b)" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| # 0 0 0 1 1 1 1 0 - - 0 - - - 0 1 P P 0 u u u u u 1 0 0 d d d d d @@ -1090,7 +1236,7 @@ define pcodeop vabs_Vb; build EndPacket; } -# (hvx,1) vabs -- "Vd.b=vabs(Vu.b):sat" +# (v60,1) vabs -- "Vd.b=vabs(Vu.b):sat" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| # 0 0 0 1 1 1 1 0 - - 0 - - - 0 1 P P 0 u u u u u 1 0 1 d d d d d @@ -1102,7 +1248,7 @@ define pcodeop vabs_Vb_sat; build EndPacket; } -# (hvx,1) vadd -- "Vd.w=vadd(Vu.w,Vv.w)" +# (v60,1) vadd -- "Vd.w=vadd(Vu.w,Vv.w)" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| # 0 0 0 1 1 1 0 0 0 1 0 v v v v v P P 0 u u u u u 0 0 0 d d d d d @@ -1114,7 +1260,7 @@ define pcodeop vadd_VwVw; build EndPacket; } -# (hvx,1) vadd -- "Vd.ub=vadd(Vu.ub,Vv.ub):sat" +# (v60,1) vadd -- "Vd.ub=vadd(Vu.ub,Vv.ub):sat" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| # 0 0 0 1 1 1 0 0 0 1 0 v v v v v P P 0 u u u u u 0 0 1 d d d d d @@ -1126,7 +1272,7 @@ define pcodeop vadd_VubVub_sat; build EndPacket; } -# (hvx,1) vadd -- "Vd.uh=vadd(Vu.uh,Vv.uh):sat" +# (v60,1) vadd -- "Vd.uh=vadd(Vu.uh,Vv.uh):sat" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| # 0 0 0 1 1 1 0 0 0 1 0 v v v v v P P 0 u u u u u 0 1 0 d d d d d @@ -1138,7 +1284,7 @@ define pcodeop vadd_VuhVuh_sat; build EndPacket; } -# (hvx,1) vadd -- "Vd.h=vadd(Vu.h,Vv.h):sat" +# (v60,1) vadd -- "Vd.h=vadd(Vu.h,Vv.h):sat" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| # 0 0 0 1 1 1 0 0 0 1 0 v v v v v P P 0 u u u u u 0 1 1 d d d d d @@ -1150,7 +1296,7 @@ define pcodeop vadd_VhVh_sat; build EndPacket; } -# (hvx,1) vadd -- "Vd.w=vadd(Vu.w,Vv.w):sat" +# (v60,1) vadd -- "Vd.w=vadd(Vu.w,Vv.w):sat" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| # 0 0 0 1 1 1 0 0 0 1 0 v v v v v P P 0 u u u u u 1 0 0 d d d d d @@ -1162,7 +1308,7 @@ define pcodeop vadd_VwVw_sat; build EndPacket; } -# (hvx,1) vsub -- "Vd.b=vsub(Vu.b,Vv.b)" +# (v60,1) vsub -- "Vd.b=vsub(Vu.b,Vv.b)" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| # 0 0 0 1 1 1 0 0 0 1 0 v v v v v P P 0 u u u u u 1 0 1 d d d d d @@ -1174,7 +1320,7 @@ define pcodeop vsub_VbVb; build EndPacket; } -# (hvx,1) vsub -- "Vd.h=vsub(Vu.h,Vv.h)" +# (v60,1) vsub -- "Vd.h=vsub(Vu.h,Vv.h)" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| # 0 0 0 1 1 1 0 0 0 1 0 v v v v v P P 0 u u u u u 1 1 0 d d d d d @@ -1186,7 +1332,7 @@ define pcodeop vsub_VhVh; build EndPacket; } -# (hvx,1) vsub -- "Vd.w=vsub(Vu.w,Vv.w)" +# (v60,1) vsub -- "Vd.w=vsub(Vu.w,Vv.w)" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| # 0 0 0 1 1 1 0 0 0 1 0 v v v v v P P 0 u u u u u 1 1 1 d d d d d @@ -1198,7 +1344,7 @@ define pcodeop vsub_VwVw; build EndPacket; } -# (hvx,1) vsub -- "Vd.ub=vsub(Vu.ub,Vv.ub):sat" +# (v60,1) vsub -- "Vd.ub=vsub(Vu.ub,Vv.ub):sat" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| # 0 0 0 1 1 1 0 0 0 1 1 v v v v v P P 0 u u u u u 0 0 0 d d d d d @@ -1210,7 +1356,7 @@ define pcodeop vsub_VubVub_sat; build EndPacket; } -# (hvx,1) vsub -- "Vd.uh=vsub(Vu.uh,Vv.uh):sat" +# (v60,1) vsub -- "Vd.uh=vsub(Vu.uh,Vv.uh):sat" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| # 0 0 0 1 1 1 0 0 0 1 1 v v v v v P P 0 u u u u u 0 0 1 d d d d d @@ -1222,7 +1368,7 @@ define pcodeop vsub_VuhVuh_sat; build EndPacket; } -# (hvx,1) vsub -- "Vd.h=vsub(Vu.h,Vv.h):sat" +# (v60,1) vsub -- "Vd.h=vsub(Vu.h,Vv.h):sat" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| # 0 0 0 1 1 1 0 0 0 1 1 v v v v v P P 0 u u u u u 0 1 0 d d d d d @@ -1234,7 +1380,7 @@ define pcodeop vsub_VhVh_sat; build EndPacket; } -# (hvx,1) vsub -- "Vd.w=vsub(Vu.w,Vv.w):sat" +# (v60,1) vsub -- "Vd.w=vsub(Vu.w,Vv.w):sat" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| # 0 0 0 1 1 1 0 0 0 1 1 v v v v v P P 0 u u u u u 0 1 1 d d d d d @@ -1246,7 +1392,7 @@ define pcodeop vsub_VwVw_sat; build EndPacket; } -# (hvx,1) vadd -- "Vd.ub=vadd(Vu.ub,Vv.b):sat" +# (v60,1) vadd -- "Vd.ub=vadd(Vu.ub,Vv.b):sat" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| # 0 0 0 1 1 1 1 0 1 0 1 v v v v v P P 0 u u u u u 1 0 0 d d d d d @@ -1258,7 +1404,7 @@ define pcodeop vadd_VubVb_sat; build EndPacket; } -# (hvx,1) vsub -- "Vd.ub=vsub(Vu.ub,Vv.b):sat" +# (v60,1) vsub -- "Vd.ub=vsub(Vu.ub,Vv.b):sat" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| # 0 0 0 1 1 1 1 0 1 0 1 v v v v v P P 0 u u u u u 1 0 1 d d d d d @@ -1270,7 +1416,7 @@ define pcodeop vsub_VubVb_sat; build EndPacket; } -# (hvx,1) vadd -- "Vd.b=vadd(Vu.b,Vv.b):sat" +# (v60,1) vadd -- "Vd.b=vadd(Vu.b,Vv.b):sat" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| # 0 0 0 1 1 1 1 1 0 0 0 v v v v v P P 0 u u u u u 0 0 0 d d d d d @@ -1282,7 +1428,7 @@ define pcodeop vadd_VbVb_sat; build EndPacket; } -# (hvx,1) vsub -- "Vd.b=vsub(Vu.b,Vv.b):sat" +# (v60,1) vsub -- "Vd.b=vsub(Vu.b,Vv.b):sat" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| # 0 0 0 1 1 1 1 1 0 0 1 v v v v v P P 0 u u u u u 0 1 0 d d d d d @@ -1294,7 +1440,7 @@ define pcodeop vsub_VbVb_sat; build EndPacket; } -# (hvx,1) vadd -- "Vd.uw=vadd(Vu.uw,Vv.uw):sat" +# (v60,1) vadd -- "Vd.uw=vadd(Vu.uw,Vv.uw):sat" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| # 0 0 0 1 1 1 1 1 0 1 1 v v v v v P P 0 u u u u u 0 0 1 d d d d d @@ -1306,7 +1452,7 @@ define pcodeop vadd_VuwVuw_sat; build EndPacket; } -# (hvx,1) vadd -- "Vd.b=vadd(Vu.b,Vv.b)" +# (v60,1) vadd -- "Vd.b=vadd(Vu.b,Vv.b)" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| # 0 0 0 1 1 1 1 1 1 0 1 v v v v v P P 0 u u u u u 1 1 0 d d d d d @@ -1318,7 +1464,7 @@ define pcodeop vadd_VbVb; build EndPacket; } -# (hvx,1) vadd -- "Vd.h=vadd(Vu.h,Vv.h)" +# (v60,1) vadd -- "Vd.h=vadd(Vu.h,Vv.h)" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| # 0 0 0 1 1 1 1 1 1 0 1 v v v v v P P 0 u u u u u 1 1 1 d d d d d @@ -1330,7 +1476,7 @@ define pcodeop vadd_VhVh; build EndPacket; } -# (hvx,1) vsub -- "Vd.uw=vsub(Vu.uw,Vv.uw):sat" +# (v60,1) vsub -- "Vd.uw=vsub(Vu.uw,Vv.uw):sat" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| # 0 0 0 1 1 1 1 1 1 1 0 v v v v v P P 0 u u u u u 1 0 0 d d d d d @@ -1342,7 +1488,7 @@ define pcodeop vsub_VuwVuw_sat; build EndPacket; } -# (hvx,1) vadd -- "Vd.w=vadd(Vu.w,Vv.w,Qx4):carry" +# (v60,1) vadd -- "Vd.w=vadd(Vu.w,Vv.w,Qx4):carry" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| # 0 0 0 1 1 1 0 0 1 0 1 v v v v v P P 1 u u u u u 0 x x d d d d d @@ -1354,7 +1500,7 @@ define pcodeop vsub_VwVwQ_carry; build EndPacket; } -# (hvx,1) vsub -- "Vd.w=vsub(Vu.w,Vv.w,Qx4):carry" +# (v60,1) vsub -- "Vd.w=vsub(Vu.w,Vv.w,Qx4):carry" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| # 0 0 0 1 1 1 0 0 1 0 1 v v v v v P P 1 u u u u u 1 x x d d d d d @@ -1366,7 +1512,7 @@ define pcodeop vsub_VwVwQ_carry_sat; build EndPacket; } -# (hvx,1) vadd -- "Vd.w=vadd(Vu.w,Vv.w,Qs4):carry:sat" +# (v60,1) vadd -- "Vd.w=vadd(Vu.w,Vv.w,Qs4):carry:sat" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| # 0 0 0 1 1 1 0 1 1 0 0 v v v v v P P 1 u u u u u 0 s s d d d d d @@ -1378,7 +1524,7 @@ define pcodeop vadd_VwVwQ_carry_sat; build EndPacket; } -# (hvx,1) vadd -- "Vd.w,Qe4=vadd(Vu.w,Vv.w):carry" +# (v60,1) vadd -- "Vd.w,Qe4=vadd(Vu.w,Vv.w):carry" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| # 0 0 0 1 1 1 0 1 1 0 1 v v v v v P P 1 u u u u u 0 e e d d d d d @@ -1393,7 +1539,7 @@ define pcodeop vadd_VwVw_carryResult; qv0506 = tmpQ; } -# (hvx,1) vsub -- "Vd.w,Qe4=vsub(Vu.w,Vv.w):carry" +# (v60,1) vsub -- "Vd.w,Qe4=vsub(Vu.w,Vv.w):carry" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| # 0 0 0 1 1 1 0 1 1 0 1 v v v v v P P 1 u u u u u 1 e e d d d d d @@ -1408,7 +1554,7 @@ define pcodeop vsub_VwVw_carryResult; qv0506 = tmpQ; } -# (hvx,1) vand -- "Vd=vand(Vu,Vv)" +# (v60,1) vand -- "Vd=vand(Vu,Vv)" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| # 0 0 0 1 1 1 0 0 0 0 1 v v v v v P P 0 u u u u u 1 0 1 d d d d d @@ -1418,7 +1564,7 @@ define pcodeop vsub_VwVw_carryResult; build EndPacket; } -# (hvx,1) vor -- "Vd=vor(Vu,Vv)" +# (v60,1) vor -- "Vd=vor(Vu,Vv)" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| # 0 0 0 1 1 1 0 0 0 0 1 v v v v v P P 0 u u u u u 1 1 0 d d d d d @@ -1428,7 +1574,7 @@ define pcodeop vsub_VwVw_carryResult; build EndPacket; } -# (hvx,1) vxor -- "Vd=vxor(Vu,Vv)" +# (v60,1) vxor -- "Vd=vxor(Vu,Vv)" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| # 0 0 0 1 1 1 0 0 0 0 1 v v v v v P P 0 u u u u u 1 1 1 d d d d d @@ -1438,7 +1584,7 @@ define pcodeop vsub_VwVw_carryResult; build EndPacket; } -# (hvx,1) vnot -- "Vd=vnot(Vu)" +# (v60,1) vnot -- "Vd=vnot(Vu)" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| # 0 0 0 1 1 1 1 0 - - 0 - - - 0 0 P P 0 u u u u u 1 0 0 d d d d d @@ -1448,50 +1594,53 @@ define pcodeop vsub_VwVw_carryResult; build EndPacket; } -# (hvx,1) "if (Ps) Vd=Vu" +# (v60,1) "if (Ps) Vd=Vu" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| # 0 0 0 1 1 0 1 0 0 0 0 - - - - - P P - u u u u u - s s d d d d d # -# (hvx,1) "if (!Ps) Vd=Vu" +# (v60,1) "if (!Ps) Vd=Vu" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| # 0 0 0 1 1 0 1 0 0 0 1 - - - - - P P - u u u u u - s s d d d d d :assign^VPuCond0506_S21 vd5,Vu_0812 EndPacket is iclass=0x1 & op2227=0x28 & VPuCond0506_S21 & vd5 & vd5_ & SetVNRegVd5 & Vu_0812 & $(END_PACKET) [ cond=1; ] { build VPuCond0506_S21; + build Vu_0812; build EndPacket; <> + build VPuCond0506_S21; if (ConditionReg == 0) goto ; vd5_ = Vu_0812; - + <> + build VPuCond0506_S21; if (ConditionReg == 0) goto ; vd5 = vd5_; - + } -# (hvx,1) "Vd=Vu" +# (v60,1) "Vd=Vu" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| # 0 0 0 1 1 1 1 0 - - 0 - - 0 1 1 P P 1 u u u u u 1 1 1 d d d d d -:assign Vd5,Vu_0812 EndPacket is iclass=0x1 & op2427=0xe & op21=0x0 & op18=0x0 & op1617=0x3 & op13=0x1 & op0507=0x7 & Vd5 & Vu_0812 & $(END_PACKET) [ cond=0; ] { - Vd5 = Vu_0812; # Vd5 handles unconditional commit +:assign Vd5,Vu_0812 EndPacket is iclass=0x1 & op2427=0xe & op2123=0x0 & op1620=0x3 & op13=0x1 & op0507=0x7 & Vd5 & Vu_0812 & $(END_PACKET) [ cond=0; ] { + Vd5 = Vu_0812; # Vd5 handles unconditional commit build EndPacket; } -# (hvx,1) "Vd.tmp=Vu" +# (v60,1) "Vd.tmp=Vu" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| # 0 0 0 1 1 1 1 0 - - 0 - - - 0 1 P P 0 u u u u u 1 1 0 d d d d d -:assign Vd5tmp,Vu_0812 EndPacket is iclass=0x1 & op2427=0xe & op21=0x0 & op1617=0x1 & op13=0x0 & op0507=0x6 & Vd5tmp & Vu_0812 & $(END_PACKET) { +:assign Vd5tmp,Vu_0812 EndPacket is iclass=0x1 & op2427=0xe & op2123=0x0 & op1620=0x1 & op13=0x0 & op0507=0x6 & Vd5tmp & Vu_0812 & $(END_PACKET) { Vd5tmp = Vu_0812; build EndPacket; } -# (hvx,1) vcombine -- "Vdd.tmp=vcombine(Vu,Vv)" +# (v60,1) vcombine -- "Vdd.tmp=vcombine(Vu,Vv)" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| # 0 0 0 1 1 1 1 0 1 0 1 v v v v v P P 0 u u u u u 1 1 1 d d d d d @@ -1501,7 +1650,7 @@ define pcodeop vsub_VwVw_carryResult; build EndPacket; } -# (hvx,1) vavg -- "Vd.ub=vavg(Vu.ub,Vv.ub)" +# (v60,1) vavg -- "Vd.ub=vavg(Vu.ub,Vv.ub)" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| # 0 0 0 1 1 1 0 0 1 1 0 v v v v v P P 0 u u u u u 1 0 0 d d d d d @@ -1513,7 +1662,7 @@ define pcodeop vavg_VubVub; build EndPacket; } -# (hvx,1) vavg -- "Vd.uh=vavg(Vu.uh,Vv.uh)" +# (v60,1) vavg -- "Vd.uh=vavg(Vu.uh,Vv.uh)" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| # 0 0 0 1 1 1 0 0 1 1 0 v v v v v P P 0 u u u u u 1 0 1 d d d d d @@ -1525,7 +1674,7 @@ define pcodeop vavg_VuhVuh; build EndPacket; } -# (hvx,1) vavg -- "Vd.h=vavg(Vu.h,Vv.h)" +# (v60,1) vavg -- "Vd.h=vavg(Vu.h,Vv.h)" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| # 0 0 0 1 1 1 0 0 1 1 0 v v v v v P P 0 u u u u u 1 1 0 d d d d d @@ -1537,7 +1686,7 @@ define pcodeop vavg_VhVh; build EndPacket; } -# (hvx,1) vavg -- "Vd.w=vavg(Vu.w,Vv.w)" +# (v60,1) vavg -- "Vd.w=vavg(Vu.w,Vv.w)" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| # 0 0 0 1 1 1 0 0 1 1 0 v v v v v P P 0 u u u u u 1 1 1 d d d d d @@ -1549,7 +1698,7 @@ define pcodeop vavg_VwVw; build EndPacket; } -# (hvx,1) vnavg -- "Vd.b=vnavg(Vu.ub,Vv.ub)" +# (v60,1) vnavg -- "Vd.b=vnavg(Vu.ub,Vv.ub)" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| # 0 0 0 1 1 1 0 0 1 1 1 v v v v v P P 0 u u u u u 0 0 0 d d d d d @@ -1561,7 +1710,7 @@ define pcodeop vnavg_VubVub; build EndPacket; } -# (hvx,1) vnavg -- "Vd.h=vnavg(Vu.h,Vv.h)" +# (v60,1) vnavg -- "Vd.h=vnavg(Vu.h,Vv.h)" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| # 0 0 0 1 1 1 0 0 1 1 1 v v v v v P P 0 u u u u u 0 0 1 d d d d d @@ -1573,7 +1722,7 @@ define pcodeop vnavg_VhVh; build EndPacket; } -# (hvx,1) vnavg -- "Vd.w=vnavg(Vu.w,Vv.w)" +# (v60,1) vnavg -- "Vd.w=vnavg(Vu.w,Vv.w)" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| # 0 0 0 1 1 1 0 0 1 1 1 v v v v v P P 0 u u u u u 0 1 0 d d d d d @@ -1585,7 +1734,7 @@ define pcodeop vnavg_VwVw; build EndPacket; } -# (hvx,1) vavg -- "Vd.ub=vavg(Vu.ub,Vv.ub):rnd" +# (v60,1) vavg -- "Vd.ub=vavg(Vu.ub,Vv.ub):rnd" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| # 0 0 0 1 1 1 0 0 1 1 1 v v v v v P P 0 u u u u u 0 1 1 d d d d d @@ -1597,7 +1746,7 @@ define pcodeop vavg_VubVub_rnd; build EndPacket; } -# (hvx,1) vavg -- "Vd.uh=vavg(Vu.uh,Vv.uh):rnd" +# (v60,1) vavg -- "Vd.uh=vavg(Vu.uh,Vv.uh):rnd" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| # 0 0 0 1 1 1 0 0 1 1 1 v v v v v P P 0 u u u u u 1 0 0 d d d d d @@ -1609,7 +1758,7 @@ define pcodeop vavg_VuhVuh_rnd; build EndPacket; } -# (hvx,1) vavg -- "Vd.h=vavg(Vu.h,Vv.h):rnd" +# (v60,1) vavg -- "Vd.h=vavg(Vu.h,Vv.h):rnd" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| # 0 0 0 1 1 1 0 0 1 1 1 v v v v v P P 0 u u u u u 1 0 1 d d d d d @@ -1621,7 +1770,7 @@ define pcodeop vavg_VhVh_rnd; build EndPacket; } -# (hvx,1) vavg -- "Vd.w=vavg(Vu.w,Vv.w):rnd" +# (v60,1) vavg -- "Vd.w=vavg(Vu.w,Vv.w):rnd" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| # 0 0 0 1 1 1 0 0 1 1 1 v v v v v P P 0 u u u u u 1 1 0 d d d d d @@ -1633,7 +1782,7 @@ define pcodeop vavg_VwVw_rnd; build EndPacket; } -# (hvx,1) vavg -- "Vd.uw=vavg(Vu.uw,Vv.uw)" +# (v60,1) vavg -- "Vd.uw=vavg(Vu.uw,Vv.uw)" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| # 0 0 0 1 1 1 1 1 0 0 0 v v v v v P P 1 u u u u u 0 1 0 d d d d d @@ -1645,7 +1794,7 @@ define pcodeop vavg_VuwVuw; build EndPacket; } -# (hvx,1) vavg -- "Vd.uw=vavg(Vu.uw,Vv.uw):rnd" +# (v60,1) vavg -- "Vd.uw=vavg(Vu.uw,Vv.uw):rnd" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| # 0 0 0 1 1 1 1 1 0 0 0 v v v v v P P 1 u u u u u 0 1 1 d d d d d @@ -1657,7 +1806,7 @@ define pcodeop vavg_VuwVuw_rnd; build EndPacket; } -# (hvx,1) vavg -- "Vd.b=vavg(Vu.b,Vv.b)" +# (v60,1) vavg -- "Vd.b=vavg(Vu.b,Vv.b)" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| # 0 0 0 1 1 1 1 1 0 0 0 v v v v v P P 1 u u u u u 1 0 0 d d d d d @@ -1669,7 +1818,7 @@ define pcodeop vavg_VbVb; build EndPacket; } -# (hvx,1) vavg -- "Vd.b=vavg(Vu.b,Vv.b):rnd" +# (v60,1) vavg -- "Vd.b=vavg(Vu.b,Vv.b):rnd" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| # 0 0 0 1 1 1 1 1 0 0 0 v v v v v P P 1 u u u u u 1 0 1 d d d d d @@ -1681,7 +1830,7 @@ define pcodeop vavg_VbVb_rnd; build EndPacket; } -# (hvx,1) vnavg -- "Vd.b=vnavg(Vu.b,Vv.b)" +# (v60,1) vnavg -- "Vd.b=vnavg(Vu.b,Vv.b)" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| # 0 0 0 1 1 1 1 1 0 0 0 v v v v v P P 1 u u u u u 1 1 0 d d d d d @@ -1693,7 +1842,7 @@ define pcodeop vnavg_VbVb; build EndPacket; } -# (hvx,1) vcmp.eq -- "Qd4=vcmp.eq(Vu.b,Vv.b)" +# (v60,1) vcmp.eq -- "Qd4=vcmp.eq(Vu.b,Vv.b)" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| # 0 0 0 1 1 1 1 1 1 0 0 v v v v v P P 0 u u u u u 0 0 0 0 0 0 d d @@ -1705,7 +1854,7 @@ define pcodeop vcmp_eq_VbVb; build EndPacket; } -# (hvx,1) vcmp.eq -- "Qd4=vcmp.eq(Vu.h,Vv.h)" +# (v60,1) vcmp.eq -- "Qd4=vcmp.eq(Vu.h,Vv.h)" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| # 0 0 0 1 1 1 1 1 1 0 0 v v v v v P P 0 u u u u u 0 0 0 0 0 1 d d @@ -1717,7 +1866,7 @@ define pcodeop vcmp_eq_VhVh; build EndPacket; } -# (hvx,1) vcmp.eq -- "Qd4=vcmp.eq(Vu.w,Vv.w)" +# (v60,1) vcmp.eq -- "Qd4=vcmp.eq(Vu.w,Vv.w)" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| # 0 0 0 1 1 1 1 1 1 0 0 v v v v v P P 0 u u u u u 0 0 0 0 1 0 d d @@ -1729,7 +1878,7 @@ define pcodeop vcmp_eq_VwVw; build EndPacket; } -# (hvx,1) vcmp.gt -- "Qd4=vcmp.gt(Vu.b,Vv.b)" +# (v60,1) vcmp.gt -- "Qd4=vcmp.gt(Vu.b,Vv.b)" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| # 0 0 0 1 1 1 1 1 1 0 0 v v v v v P P 0 u u u u u 0 0 0 1 0 0 d d @@ -1741,7 +1890,7 @@ define pcodeop vcmp_gt_VbVb; build EndPacket; } -# (hvx,1) vcmp.gt -- "Qd4=vcmp.gt(Vu.h,Vv.h)" +# (v60,1) vcmp.gt -- "Qd4=vcmp.gt(Vu.h,Vv.h)" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| # 0 0 0 1 1 1 1 1 1 0 0 v v v v v P P 0 u u u u u 0 0 0 1 0 1 d d @@ -1753,7 +1902,7 @@ define pcodeop vcmp_gt_VhVh; build EndPacket; } -# (hvx,1) vcmp.gt -- "Qd4=vcmp.gt(Vu.w,Vv.w)" +# (v60,1) vcmp.gt -- "Qd4=vcmp.gt(Vu.w,Vv.w)" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| # 0 0 0 1 1 1 1 1 1 0 0 v v v v v P P 0 u u u u u 0 0 0 1 1 0 d d @@ -1765,7 +1914,7 @@ define pcodeop vcmp_gt_VwVw; build EndPacket; } -# (hvx,1) vcmp.gt -- "Qd4=vcmp.gt(Vu.ub,Vv.ub)" +# (v60,1) vcmp.gt -- "Qd4=vcmp.gt(Vu.ub,Vv.ub)" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| # 0 0 0 1 1 1 1 1 1 0 0 v v v v v P P 0 u u u u u 0 0 1 0 0 0 d d @@ -1777,7 +1926,7 @@ define pcodeop vcmp_gt_VubVub; build EndPacket; } -# (hvx,1) vcmp.gt -- "Qd4=vcmp.gt(Vu.uh,Vv.uh)" +# (v60,1) vcmp.gt -- "Qd4=vcmp.gt(Vu.uh,Vv.uh)" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| # 0 0 0 1 1 1 1 1 1 0 0 v v v v v P P 0 u u u u u 0 0 1 0 0 1 d d @@ -1789,7 +1938,7 @@ define pcodeop vcmp_gt_VuhVuh; build EndPacket; } -# (hvx,1) vcmp.gt -- "Qd4=vcmp.gt(Vu.uw,Vv.uw)" +# (v60,1) vcmp.gt -- "Qd4=vcmp.gt(Vu.uw,Vv.uw)" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| # 0 0 0 1 1 1 1 1 1 0 0 v v v v v P P 0 u u u u u 0 0 1 0 1 0 d d @@ -1801,115 +1950,115 @@ define pcodeop vcmp_gt_VuwVuw; build EndPacket; } -# (hvx,1) vcmp.eq -- "Qx4&=vcmp.eq(Vu.b,Vv.b)" +# (v60,1) vcmp.eq -- "Qx4&=vcmp.eq(Vu.b,Vv.b)" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| # 0 0 0 1 1 1 0 0 1 0 0 v v v v v P P 1 u u u u u 0 0 0 0 0 0 x x define pcodeop vcmp_eqand_QVbVb; -:vcmp.eq Qd2,VuB_0812,VvB_1620 EndPacket is iclass=0x1 & op2127=0x64 & op13=0x1 & op0207=0x0 & Qd2 & VuB_0812 & VvB_1620 & $(END_PACKET) { +:vcmp.eq&= Qd2,VuB_0812,VvB_1620 EndPacket is iclass=0x1 & op2127=0x64 & op13=0x1 & op0207=0x0 & Qd2 & VuB_0812 & VvB_1620 & $(END_PACKET) { Qd2 = vcmp_eqand_QVbVb(Qd2,VuB_0812,VvB_1620); build EndPacket; } -# (hvx,1) vcmp.eq -- "Qx4&=vcmp.eq(Vu.h,Vv.h)" +# (v60,1) vcmp.eq -- "Qx4&=vcmp.eq(Vu.h,Vv.h)" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| # 0 0 0 1 1 1 0 0 1 0 0 v v v v v P P 1 u u u u u 0 0 0 0 0 1 x x define pcodeop vcmp_eqand_QVhVh; -:vcmp.eq Qd2,VuH_0812,VvH_1620 EndPacket is iclass=0x1 & op2127=0x64 & op13=0x1 & op0207=0x1 & Qd2 & VuH_0812 & VvH_1620 & $(END_PACKET) { +:vcmp.eq&= Qd2,VuH_0812,VvH_1620 EndPacket is iclass=0x1 & op2127=0x64 & op13=0x1 & op0207=0x1 & Qd2 & VuH_0812 & VvH_1620 & $(END_PACKET) { Qd2 = vcmp_eqand_QVhVh(Qd2,VuH_0812,VvH_1620); build EndPacket; } -# (hvx,1) vcmp.eq -- "Qx4&=vcmp.eq(Vu.w,Vv.w)" +# (v60,1) vcmp.eq -- "Qx4&=vcmp.eq(Vu.w,Vv.w)" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| # 0 0 0 1 1 1 0 0 1 0 0 v v v v v P P 1 u u u u u 0 0 0 0 1 0 x x define pcodeop vcmp_eqand_QVwVw; -:vcmp.eq Qd2,VuW_0812,VvW_1620 EndPacket is iclass=0x1 & op2127=0x64 & op13=0x1 & op0207=0x2 & Qd2 & VuW_0812 & VvW_1620 & $(END_PACKET) { +:vcmp.eq&= Qd2,VuW_0812,VvW_1620 EndPacket is iclass=0x1 & op2127=0x64 & op13=0x1 & op0207=0x2 & Qd2 & VuW_0812 & VvW_1620 & $(END_PACKET) { Qd2 = vcmp_eqand_QVwVw(Qd2,VuW_0812,VvW_1620); build EndPacket; } -# (hvx,1) vcmp.gt -- "Qx4&=vcmp.gt(Vu.b,Vv.b)" +# (v60,1) vcmp.gt -- "Qx4&=vcmp.gt(Vu.b,Vv.b)" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| # 0 0 0 1 1 1 0 0 1 0 0 v v v v v P P 1 u u u u u 0 0 0 1 0 0 x x define pcodeop vcmp_gtand_QVbVb; -:vcmp.gt Qd2,VuB_0812,VvB_1620 EndPacket is iclass=0x1 & op2127=0x64 & op13=0x1 & op0207=0x4 & Qd2 & VuB_0812 & VvB_1620 & $(END_PACKET) { +:vcmp.gt&= Qd2,VuB_0812,VvB_1620 EndPacket is iclass=0x1 & op2127=0x64 & op13=0x1 & op0207=0x4 & Qd2 & VuB_0812 & VvB_1620 & $(END_PACKET) { Qd2 = vcmp_gtand_QVbVb(Qd2,VuB_0812,VvB_1620); build EndPacket; } -# (hvx,1) vcmp.gt -- "Qx4&=vcmp.gt(Vu.h,Vv.h)" +# (v60,1) vcmp.gt -- "Qx4&=vcmp.gt(Vu.h,Vv.h)" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| # 0 0 0 1 1 1 0 0 1 0 0 v v v v v P P 1 u u u u u 0 0 0 1 0 1 x x define pcodeop vcmp_gtand_QVhVh; -:vcmp.gt Qd2,VuH_0812,VvH_1620 EndPacket is iclass=0x1 & op2127=0x64 & op13=0x1 & op0207=0x5 & Qd2 & VuH_0812 & VvH_1620 & $(END_PACKET) { +:vcmp.gt&= Qd2,VuH_0812,VvH_1620 EndPacket is iclass=0x1 & op2127=0x64 & op13=0x1 & op0207=0x5 & Qd2 & VuH_0812 & VvH_1620 & $(END_PACKET) { Qd2 = vcmp_gtand_QVhVh(Qd2,VuH_0812,VvH_1620); build EndPacket; } -# (hvx,1) vcmp.gt -- "Qx4&=vcmp.gt(Vu.w,Vv.w)" +# (v60,1) vcmp.gt -- "Qx4&=vcmp.gt(Vu.w,Vv.w)" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| # 0 0 0 1 1 1 0 0 1 0 0 v v v v v P P 1 u u u u u 0 0 0 1 1 0 x x define pcodeop vcmp_gtand_QVwVw; -:vcmp.gt Qd2,VuW_0812,VvW_1620 EndPacket is iclass=0x1 & op2127=0x64 & op13=0x1 & op0207=0x6 & Qd2 & VuW_0812 & VvW_1620 & $(END_PACKET) { +:vcmp.gt&= Qd2,VuW_0812,VvW_1620 EndPacket is iclass=0x1 & op2127=0x64 & op13=0x1 & op0207=0x6 & Qd2 & VuW_0812 & VvW_1620 & $(END_PACKET) { Qd2 = vcmp_gtand_QVwVw(Qd2,VuW_0812,VvW_1620); build EndPacket; } -# (hvx,1) vcmp.gt -- "Qx4&=vcmp.gt(Vu.ub,Vv.ub)" +# (v60,1) vcmp.gt -- "Qx4&=vcmp.gt(Vu.ub,Vv.ub)" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| # 0 0 0 1 1 1 0 0 1 0 0 v v v v v P P 1 u u u u u 0 0 1 0 0 0 x x define pcodeop vcmp_gtand_QVubVub; -:vcmp.gt Qd2,VuUB_0812,VvUB_1620 EndPacket is iclass=0x1 & op2127=0x64 & op13=0x1 & op0207=0x8 & Qd2 & VuUB_0812 & VvUB_1620 & $(END_PACKET) { +:vcmp.gt&= Qd2,VuUB_0812,VvUB_1620 EndPacket is iclass=0x1 & op2127=0x64 & op13=0x1 & op0207=0x8 & Qd2 & VuUB_0812 & VvUB_1620 & $(END_PACKET) { Qd2 = vcmp_gtand_QVubVub(Qd2,VuUB_0812,VvUB_1620); build EndPacket; } -# (hvx,1) vcmp.gt -- "Qx4&=vcmp.gt(Vu.uh,Vv.uh)" +# (v60,1) vcmp.gt -- "Qx4&=vcmp.gt(Vu.uh,Vv.uh)" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| # 0 0 0 1 1 1 0 0 1 0 0 v v v v v P P 1 u u u u u 0 0 1 0 0 1 x x define pcodeop vcmp_gtand_QVuhVuh; -:vcmp.gt Qd2,VuUH_0812,VvUH_1620 EndPacket is iclass=0x1 & op2127=0x64 & op13=0x1 & op0207=0x9 & Qd2 & VuUH_0812 & VvUH_1620 & $(END_PACKET) { +:vcmp.gt&= Qd2,VuUH_0812,VvUH_1620 EndPacket is iclass=0x1 & op2127=0x64 & op13=0x1 & op0207=0x9 & Qd2 & VuUH_0812 & VvUH_1620 & $(END_PACKET) { Qd2 = vcmp_gtand_QVuhVuh(Qd2,VuUH_0812,VvUH_1620); build EndPacket; } -# (hvx,1) vcmp.gt -- "Qx4&=vcmp.gt(Vu.uw,Vv.uw)" +# (v60,1) vcmp.gt -- "Qx4&=vcmp.gt(Vu.uw,Vv.uw)" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| # 0 0 0 1 1 1 0 0 1 0 0 v v v v v P P 1 u u u u u 0 0 1 0 1 0 x x define pcodeop vcmp_gtand_QVuwVuw; -:vcmp.gt Qd2,VuUW_0812,VvUW_1620 EndPacket is iclass=0x1 & op2127=0x64 & op13=0x1 & op0207=0xa & Qd2 & VuUW_0812 & VvUW_1620 & $(END_PACKET) { +:vcmp.gt&= Qd2,VuUW_0812,VvUW_1620 EndPacket is iclass=0x1 & op2127=0x64 & op13=0x1 & op0207=0xa & Qd2 & VuUW_0812 & VvUW_1620 & $(END_PACKET) { Qd2 = vcmp_gtand_QVuwVuw(Qd2,VuUW_0812,VvUW_1620); build EndPacket; } -# (hvx,1) vcmp.gt -- "Qx4|=vcmp.gt(Vu.sf,Vv.sf)" +# (v60,1) vcmp.gt -- "Qx4|=vcmp.gt(Vu.sf,Vv.sf)" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| # 0 0 0 1 1 1 0 0 1 0 0 v v v v v P P 1 u u u u u 0 0 1 1 0 0 x x @@ -1921,7 +2070,7 @@ define pcodeop vcmp_gtor_QVsfVsf; build EndPacket; } -# (hvx,1) vcmp.gt -- "Qx4|=vcmp.gt(Vu.hf,Vv.hf)" +# (v60,1) vcmp.gt -- "Qx4|=vcmp.gt(Vu.hf,Vv.hf)" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| # 0 0 0 1 1 1 0 0 1 0 0 v v v v v P P 1 u u u u u 0 0 1 1 0 1 x x @@ -1933,7 +2082,7 @@ define pcodeop vcmp_gtor_QVhfVhf; build EndPacket; } -# (hvx,1) vcmp.eq -- "Qx4|=vcmp.eq(Vu.b,Vv.b)" +# (v60,1) vcmp.eq -- "Qx4|=vcmp.eq(Vu.b,Vv.b)" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| # 0 0 0 1 1 1 0 0 1 0 0 v v v v v P P 1 u u u u u 0 1 0 0 0 0 x x @@ -1945,7 +2094,7 @@ define pcodeop vcmp_eqor_QVbVb; build EndPacket; } -# (hvx,1) vcmp.eq -- "Qx4|=vcmp.eq(Vu.h,Vv.h)" +# (v60,1) vcmp.eq -- "Qx4|=vcmp.eq(Vu.h,Vv.h)" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| # 0 0 0 1 1 1 0 0 1 0 0 v v v v v P P 1 u u u u u 0 1 0 0 0 1 x x @@ -1957,7 +2106,7 @@ define pcodeop vcmp_eqor_QVhVh; build EndPacket; } -# (hvx,1) vcmp.eq -- "Qx4|=vcmp.eq(Vu.w,Vv.w)" +# (v60,1) vcmp.eq -- "Qx4|=vcmp.eq(Vu.w,Vv.w)" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| # 0 0 0 1 1 1 0 0 1 0 0 v v v v v P P 1 u u u u u 0 1 0 0 1 0 x x @@ -1969,7 +2118,7 @@ define pcodeop vcmp_eqor_QVwVw; build EndPacket; } -# (hvx,1) vcmp.gt -- "Qx4|=vcmp.gt(Vu.b,Vv.b)" +# (v60,1) vcmp.gt -- "Qx4|=vcmp.gt(Vu.b,Vv.b)" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| # 0 0 0 1 1 1 0 0 1 0 0 v v v v v P P 1 u u u u u 0 1 0 1 0 0 x x @@ -1981,7 +2130,7 @@ define pcodeop vcmp_gtor_QVbVb; build EndPacket; } -# (hvx,1) vcmp.gt -- "Qx4|=vcmp.gt(Vu.h,Vv.h)" +# (v60,1) vcmp.gt -- "Qx4|=vcmp.gt(Vu.h,Vv.h)" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| # 0 0 0 1 1 1 0 0 1 0 0 v v v v v P P 1 u u u u u 0 1 0 1 0 1 x x @@ -1993,7 +2142,7 @@ define pcodeop vcmp_gtor_QVhVh; build EndPacket; } -# (hvx,1) vcmp.gt -- "Qx4|=vcmp.gt(Vu.w,Vv.w)" +# (v60,1) vcmp.gt -- "Qx4|=vcmp.gt(Vu.w,Vv.w)" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| # 0 0 0 1 1 1 0 0 1 0 0 v v v v v P P 1 u u u u u 0 1 0 1 1 0 x x @@ -2005,7 +2154,7 @@ define pcodeop vcmp_gtor_QVwVw; build EndPacket; } -# (hvx,1) vcmp.gt -- "Qx4|=vcmp.gt(Vu.ub,Vv.ub)" +# (v60,1) vcmp.gt -- "Qx4|=vcmp.gt(Vu.ub,Vv.ub)" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| # 0 0 0 1 1 1 0 0 1 0 0 v v v v v P P 1 u u u u u 0 1 1 0 0 0 x x @@ -2017,7 +2166,7 @@ define pcodeop vcmp_gtor_QVubVub; build EndPacket; } -# (hvx,1) vcmp.gt -- "Qx4|=vcmp.gt(Vu.uh,Vv.uh)" +# (v60,1) vcmp.gt -- "Qx4|=vcmp.gt(Vu.uh,Vv.uh)" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| # 0 0 0 1 1 1 0 0 1 0 0 v v v v v P P 1 u u u u u 0 1 1 0 0 1 x x @@ -2029,7 +2178,7 @@ define pcodeop vcmp_gtor_QVuhVuh; build EndPacket; } -# (hvx,1) vcmp.gt -- "Qx4|=vcmp.gt(Vu.uw,Vv.uw)" +# (v60,1) vcmp.gt -- "Qx4|=vcmp.gt(Vu.uw,Vv.uw)" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| # 0 0 0 1 1 1 0 0 1 0 0 v v v v v P P 1 u u u u u 0 1 1 0 1 0 x x @@ -2041,7 +2190,7 @@ define pcodeop vcmp_gtor_QVuwVuw; build EndPacket; } -# (hvx,1) vcmp.gt -- "Qd4=vcmp.gt(Vu.sf,Vv.sf)" +# (v60,1) vcmp.gt -- "Qd4=vcmp.gt(Vu.sf,Vv.sf)" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| # 0 0 0 1 1 1 0 0 1 0 0 v v v v v P P 1 u u u u u 0 1 1 1 0 0 d d @@ -2053,7 +2202,7 @@ define pcodeop vcmp_gt_VsfVsf; build EndPacket; } -# (hvx,1) vcmp.gt -- "Qd4=vcmp.gt(Vu.hf,Vv.hf)" +# (v60,1) vcmp.gt -- "Qd4=vcmp.gt(Vu.hf,Vv.hf)" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| # 0 0 0 1 1 1 0 0 1 0 0 v v v v v P P 1 u u u u u 0 1 1 1 0 1 d d @@ -2065,7 +2214,7 @@ define pcodeop vcmp_gt_VhfVhf; build EndPacket; } -# (hvx,1) vcmp.eq -- "Qx4^=vcmp.eq(Vu.b,Vv.b)" +# (v60,1) vcmp.eq -- "Qx4^=vcmp.eq(Vu.b,Vv.b)" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| # 0 0 0 1 1 1 0 0 1 0 0 v v v v v P P 1 u u u u u 1 0 0 0 0 0 x x @@ -2077,7 +2226,7 @@ define pcodeop vcmp_eqxacc_QVbVb; build EndPacket; } -# (hvx,1) vcmp.eq -- "Qx4^=vcmp.eq(Vu.h,Vv.h)" +# (v60,1) vcmp.eq -- "Qx4^=vcmp.eq(Vu.h,Vv.h)" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| # 0 0 0 1 1 1 0 0 1 0 0 v v v v v P P 1 u u u u u 1 0 0 0 0 1 x x @@ -2089,7 +2238,7 @@ define pcodeop vcmp_eqxacc_QVhVh; build EndPacket; } -# (hvx,1) vcmp.eq -- "Qx4^=vcmp.eq(Vu.w,Vv.w)" +# (v60,1) vcmp.eq -- "Qx4^=vcmp.eq(Vu.w,Vv.w)" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| # 0 0 0 1 1 1 0 0 1 0 0 v v v v v P P 1 u u u u u 1 0 0 0 1 0 x x @@ -2101,7 +2250,7 @@ define pcodeop vcmp_eqxacc_QVwVw; build EndPacket; } -# (hvx,1) vcmp.gt -- "Qx4^=vcmp.gt(Vu.b,Vv.b)" +# (v60,1) vcmp.gt -- "Qx4^=vcmp.gt(Vu.b,Vv.b)" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| # 0 0 0 1 1 1 0 0 1 0 0 v v v v v P P 1 u u u u u 1 0 0 1 0 0 x x @@ -2113,7 +2262,7 @@ define pcodeop vcmp_gtxacc_QVbVb; build EndPacket; } -# (hvx,1) vcmp.gt -- "Qx4^=vcmp.gt(Vu.h,Vv.h)" +# (v60,1) vcmp.gt -- "Qx4^=vcmp.gt(Vu.h,Vv.h)" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| # 0 0 0 1 1 1 0 0 1 0 0 v v v v v P P 1 u u u u u 1 0 0 1 0 1 x x @@ -2125,7 +2274,7 @@ define pcodeop vcmp_gtxacc_QVhVh; build EndPacket; } -# (hvx,1) vcmp.gt -- "Qx4^=vcmp.gt(Vu.w,Vv.w)" +# (v60,1) vcmp.gt -- "Qx4^=vcmp.gt(Vu.w,Vv.w)" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| # 0 0 0 1 1 1 0 0 1 0 0 v v v v v P P 1 u u u u u 1 0 0 1 1 0 x x @@ -2137,7 +2286,7 @@ define pcodeop vcmp_gtxacc_QVwVw; build EndPacket; } -# (hvx,1) vcmp.gt -- "Qx4^=vcmp.gt(Vu.ub,Vv.ub)" +# (v60,1) vcmp.gt -- "Qx4^=vcmp.gt(Vu.ub,Vv.ub)" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| # 0 0 0 1 1 1 0 0 1 0 0 v v v v v P P 1 u u u u u 1 0 1 0 0 0 x x @@ -2149,7 +2298,7 @@ define pcodeop vcmp_gtxacc_QVubVub; build EndPacket; } -# (hvx,1) vcmp.gt -- "Qx4^=vcmp.gt(Vu.uh,Vv.uh)" +# (v60,1) vcmp.gt -- "Qx4^=vcmp.gt(Vu.uh,Vv.uh)" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| # 0 0 0 1 1 1 0 0 1 0 0 v v v v v P P 1 u u u u u 1 0 1 0 0 1 x x @@ -2161,7 +2310,7 @@ define pcodeop vcmp_gtxacc_QVuhVuh; build EndPacket; } -# (hvx,1) vcmp.gt -- "Qx4^=vcmp.gt(Vu.uw,Vv.uw)" +# (v60,1) vcmp.gt -- "Qx4^=vcmp.gt(Vu.uw,Vv.uw)" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| # 0 0 0 1 1 1 0 0 1 0 0 v v v v v P P 1 u u u u u 1 0 1 0 1 0 x x @@ -2173,7 +2322,7 @@ define pcodeop vcmp_gtxacc_QVuwVuw; build EndPacket; } -# (hvx,1) vcmp.gt -- "Qx4&=vcmp.gt(Vu.sf,Vv.sf)" +# (v60,1) vcmp.gt -- "Qx4&=vcmp.gt(Vu.sf,Vv.sf)" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| # 0 0 0 1 1 1 0 0 1 0 0 v v v v v P P 1 u u u u u 1 1 0 0 1 0 x x @@ -2185,7 +2334,7 @@ define pcodeop vcmp_gtand_QVsfVsf; build EndPacket; } -# (hvx,1) vcmp.gt -- "Qx4&=vcmp.gt(Vu.hf,Vv.hf)" +# (v60,1) vcmp.gt -- "Qx4&=vcmp.gt(Vu.hf,Vv.hf)" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| # 0 0 0 1 1 1 0 0 1 0 0 v v v v v P P 1 u u u u u 1 1 0 0 1 1 x x @@ -2197,7 +2346,7 @@ define pcodeop vcmp_gtand_QVhfVhf; build EndPacket; } -# (hvx,1) vcmp.gt -- "Qx4^=vcmp.gt(Vu.sf,Vv.sf)" +# (v60,1) vcmp.gt -- "Qx4^=vcmp.gt(Vu.sf,Vv.sf)" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| # 0 0 0 1 1 1 0 0 1 0 0 v v v v v P P 1 u u u u u 1 1 1 0 1 0 x x @@ -2209,7 +2358,7 @@ define pcodeop vcmp_gtxacc_QVsfVsf; build EndPacket; } -# (hvx,1) vcmp.gt -- "Qx4^=vcmp.gt(Vu.hf,Vv.hf)" +# (v60,1) vcmp.gt -- "Qx4^=vcmp.gt(Vu.hf,Vv.hf)" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| # 0 0 0 1 1 1 0 0 1 0 0 v v v v v P P 1 u u u u u 1 1 1 0 1 1 x x @@ -2221,63 +2370,65 @@ define pcodeop vcmp_gtxacc_QVhfVhf; build EndPacket; } -# (hvx,1) "if (Qv4) Vx.b+=Vu.b" +# (v60,1) "if (Qv4) Vx.b+=Vu.b" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| # 0 0 0 1 1 1 1 0 v v 0 - - 0 0 1 P P 1 u u u u u 0 0 0 x x x x x define pcodeop condnac_QnVbVb; +# TODO: Verify that Ghidra renders properly (other cases like this exist) :accum^".if("^qv2223^")+=" VsB_0004,VuB_0812 EndPacket is iclass=0x1 & op2427=0xe & op21=0x0 & op18=0x0 & op1617=0x1 & op13=0x1 & op0507=0x0 & qv2223 & Vd5 & VsB_0004 & VuB_0812 & $(END_PACKET) { Vd5 = condnac_QnVbVb(qv2223,VsB_0004,VuB_0812); build EndPacket; } -# (hvx,1) "if (Qv4) Vx.h+=Vu.h" +# (v60,1) "if (!Qv4) Vx.b+=Vu.b" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 0 0 0 1 1 1 1 0 v v 0 - - 0 0 1 P P 1 u u u u u 0 0 1 x x x x x - -define pcodeop condnac_QnVhVh; +# 0 0 0 1 1 1 1 0 v v 0 - - 0 0 1 P P 1 u u u u u 0 1 1 x x x x x -:accum^".if("^qv2223^")+=" VsH_0004,VuH_0812 EndPacket is iclass=0x1 & op2427=0xe & op21=0x0 & op18=0x0 & op1617=0x1 & op13=0x1 & op0507=0x1 & qv2223 & Vd5 & VsH_0004 & VuH_0812 & $(END_PACKET) { - Vd5 = condnac_QnVhVh(qv2223,VsH_0004,VuH_0812); +# TODO: Verify that Ghidra renders properly (other cases like this exist) +:accum^".if(!"^qv2223^")+=" VsB_0004,VuB_0812 EndPacket is iclass=0x1 & op2427=0xe & op21=0x0 & op18=0x0 & op1617=0x1 & op13=0x1 & op0507=0x3 & qv2223 & Vd5 & VsB_0004 & VuB_0812 & $(END_PACKET) { + Vd5 = condnac_QnVbVb(~qv2223,VsB_0004,VuB_0812); build EndPacket; } -# (hvx,1) "if (Qv4) Vx.w+=Vu.w" +# (v60,1) "if (Qv4) Vx.h+=Vu.h" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 0 0 0 1 1 1 1 0 v v 0 - - 0 0 1 P P 1 u u u u u 0 1 0 x x x x x +# 0 0 0 1 1 1 1 0 v v 0 - - 0 0 1 P P 1 u u u u u 0 0 1 x x x x x -define pcodeop condnac_QnVwVw; +define pcodeop condnac_QnVhVh; -:accum^".if("^qv2223^")+=" VsW_0004,VuW_0812 EndPacket is iclass=0x1 & op2427=0xe & op21=0x0 & op18=0x0 & op1617=0x1 & op13=0x1 & op0507=0x2 & qv2223 & Vd5 & VsW_0004 & VuW_0812 & $(END_PACKET) { - Vd5 = condnac_QnVwVw(qv2223,VsW_0004,VuW_0812); +:accum^".if("^qv2223^")+=" VsH_0004,VuH_0812 EndPacket is iclass=0x1 & op2427=0xe & op21=0x0 & op18=0x0 & op1617=0x1 & op13=0x1 & op0507=0x1 & qv2223 & Vd5 & VsH_0004 & VuH_0812 & $(END_PACKET) { + Vd5 = condnac_QnVhVh(qv2223,VsH_0004,VuH_0812); build EndPacket; } -# (hvx,1) "if (!Qv4) Vx.b+=Vu.b" +# (v60,1) "if (!Qv4) Vx.h+=Vu.h" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 0 0 0 1 1 1 1 0 v v 0 - - 0 0 1 P P 1 u u u u u 0 1 1 x x x x x +# 0 0 0 1 1 1 1 0 v v 0 - - 0 0 1 P P 1 u u u u u 1 0 0 x x x x x -:accum^".if(!"^qv2223^")+=" VsB_0004,VuB_0812 EndPacket is iclass=0x1 & op2427=0xe & op21=0x0 & op18=0x0 & op1617=0x1 & op13=0x1 & op0507=0x3 & qv2223 & Vd5 & VsB_0004 & VuB_0812 & $(END_PACKET) { - Vd5 = condnac_QnVbVb(~qv2223,VsB_0004,VuB_0812); +:accum^".if(!"^qv2223^")+=" VsH_0004,VuH_0812 EndPacket is iclass=0x1 & op2427=0xe & op21=0x0 & op18=0x0 & op1617=0x1 & op13=0x1 & op0507=0x4 & qv2223 & Vd5 & VsH_0004 & VuH_0812 & $(END_PACKET) { + Vd5 = condnac_QnVhVh(~qv2223,VsH_0004,VuH_0812); build EndPacket; } -# (hvx,1) "if (!Qv4) Vx.h+=Vu.h" +# (v60,1) "if (Qv4) Vx.w+=Vu.w" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 0 0 0 1 1 1 1 0 v v 0 - - 0 0 1 P P 1 u u u u u 1 0 0 x x x x x +# 0 0 0 1 1 1 1 0 v v 0 - - 0 0 1 P P 1 u u u u u 0 1 0 x x x x x -:accum^".if(!"^qv2223^")+=" VsH_0004,VuH_0812 EndPacket is iclass=0x1 & op2427=0xe & op21=0x0 & op18=0x0 & op1617=0x1 & op13=0x1 & op0507=0x4 & qv2223 & Vd5 & VsH_0004 & VuH_0812 & $(END_PACKET) { - Vd5 = condnac_QnVhVh(~qv2223,VsH_0004,VuH_0812); +define pcodeop condnac_QnVwVw; + +:accum^".if("^qv2223^")+=" VsW_0004,VuW_0812 EndPacket is iclass=0x1 & op2427=0xe & op21=0x0 & op18=0x0 & op1617=0x1 & op13=0x1 & op0507=0x2 & qv2223 & Vd5 & VsW_0004 & VuW_0812 & $(END_PACKET) { + Vd5 = condnac_QnVwVw(qv2223,VsW_0004,VuW_0812); build EndPacket; } -# (hvx,1) "if (!Qv4) Vx.w+=Vu.w" +# (v60,1) "if (!Qv4) Vx.w+=Vu.w" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| # 0 0 0 1 1 1 1 0 v v 0 - - 0 0 1 P P 1 u u u u u 1 0 1 x x x x x @@ -2287,7 +2438,7 @@ define pcodeop condnac_QnVwVw; build EndPacket; } -# (hvx,1) "if (Qv4) Vx.b-=Vu.b" +# (v60,1) "if (Qv4) Vx.b-=Vu.b" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| # 0 0 0 1 1 1 1 0 v v 0 - - 0 0 1 P P 1 u u u u u 1 1 0 x x x x x @@ -2299,7 +2450,7 @@ define pcodeop condnac_QVbVb; build EndPacket; } -# (hvx,1) "if (!Qv4) Vx.b-=Vu.b" +# (v60,1) "if (!Qv4) Vx.b-=Vu.b" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| # 0 0 0 1 1 1 1 0 v v 0 - - 0 1 0 P P 1 u u u u u 0 0 1 x x x x x @@ -2309,7 +2460,7 @@ define pcodeop condnac_QVbVb; build EndPacket; } -# (hvx,1) "if (Qv4) Vx.h-=Vu.h" +# (v60,1) "if (Qv4) Vx.h-=Vu.h" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| # 0 0 0 1 1 1 1 0 v v 0 - - 0 0 1 P P 1 u u u u u 1 1 1 x x x x x @@ -2321,7 +2472,7 @@ define pcodeop condnac_QVhVh; build EndPacket; } -# (hvx,1) "if (!Qv4) Vx.h-=Vu.h" +# (v60,1) "if (!Qv4) Vx.h-=Vu.h" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| # 0 0 0 1 1 1 1 0 v v 0 - - 0 1 0 P P 1 u u u u u 0 1 0 x x x x x @@ -2332,7 +2483,7 @@ define pcodeop condnac_QVhVh; } -# (hvx,1) "if (Qv4) Vx.w-=Vu.w" +# (v60,1) "if (Qv4) Vx.w-=Vu.w" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| # 0 0 0 1 1 1 1 0 v v 0 - - 0 1 0 P P 1 u u u u u 0 0 0 x x x x x @@ -2344,7 +2495,7 @@ define pcodeop condnac_QVwVw; build EndPacket; } -# (hvx,1) "if (!Qv4) Vx.w-=Vu.w" +# (v60,1) "if (!Qv4) Vx.w-=Vu.w" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| # 0 0 0 1 1 1 1 0 v v 0 - - 0 1 0 P P 1 u u u u u 0 1 1 x x x x x @@ -2354,7 +2505,7 @@ define pcodeop condnac_QVwVw; build EndPacket; } -# (hvx,1) vmux -- "Vd=vmux(Qt4,Vu,Vv)" +# (v60,1) vmux -- "Vd=vmux(Qt4,Vu,Vv)" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| # 0 0 0 1 1 1 1 0 1 1 1 v v v v v P P 1 u u u u u - t t d d d d d @@ -2366,7 +2517,7 @@ define pcodeop vmux_QVV; build EndPacket; } -# (hvx,1) vsatdw -- "Vd.w=vsatdw(Vu.w,Vv.w)" +# (v60,1) vsatdw -- "Vd.w=vsatdw(Vu.w,Vv.w)" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| # 0 0 0 1 1 1 0 1 1 0 0 v v v v v P P 1 u u u u u 1 1 1 d d d d d @@ -2378,7 +2529,7 @@ define pcodeop vsatdw_VwVw; build EndPacket; } -# (hvx,1) vsat -- "Vd.uh=vsat(Vu.uw,Vv.uw)" +# (v60,1) vsat -- "Vd.uh=vsat(Vu.uw,Vv.uw)" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| # 0 0 0 1 1 1 1 1 0 0 1 v v v v v P P 0 u u u u u 1 1 0 d d d d d @@ -2390,7 +2541,7 @@ define pcodeop Vuh_vsat_VuwVuw; build EndPacket; } -# (hvx,1) vsat -- "Vd.ub=vsat(Vu.h,Vv.h)" +# (v60,1) vsat -- "Vd.ub=vsat(Vu.h,Vv.h)" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| # 0 0 0 1 1 1 1 1 0 1 1 v v v v v P P 0 u u u u u 0 1 0 d d d d d @@ -2402,7 +2553,7 @@ define pcodeop Vub_vsat_VhVh; build EndPacket; } -# (hvx,1) vsat -- "Vd.h=vsat(Vu.w,Vv.w)" +# (v60,1) vsat -- "Vd.h=vsat(Vu.w,Vv.w)" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| # 0 0 0 1 1 1 1 1 0 1 1 v v v v v P P 0 u u u u u 0 1 1 d d d d d @@ -2414,7 +2565,7 @@ define pcodeop Vh_vsat_VwVw; build EndPacket; } -# (hvx,1) vshuffe -- "Vd.b=vshuffe(Vu.b,Vv.b)" +# (v60,1) vshuffe -- "Vd.b=vshuffe(Vu.b,Vv.b)" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| # 0 0 0 1 1 1 1 1 0 1 0 v v v v v P P 0 u u u u u 0 0 1 d d d d d @@ -2426,7 +2577,7 @@ define pcodeop vshuffe_VbVb; build EndPacket; } -# (hvx,1) vshuffo -- "Vd.b=vshuffo(Vu.b,Vv.b)" +# (v60,1) vshuffo -- "Vd.b=vshuffo(Vu.b,Vv.b)" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| # 0 0 0 1 1 1 1 1 0 1 0 v v v v v P P 0 u u u u u 0 1 0 d d d d d @@ -2438,7 +2589,7 @@ define pcodeop vshuffo_VbVb; build EndPacket; } -# (hvx,1) vshuffe -- "Vd.h=vshuffe(Vu.h,Vv.h)" +# (v60,1) vshuffe -- "Vd.h=vshuffe(Vu.h,Vv.h)" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| # 0 0 0 1 1 1 1 1 0 1 0 v v v v v P P 0 u u u u u 0 1 1 d d d d d @@ -2450,7 +2601,7 @@ define pcodeop vshuffe_VhVh; build EndPacket; } -# (hvx,1) vshuffo -- "Vd.h=vshuffo(Vu.h,Vv.h)" +# (v60,1) vshuffo -- "Vd.h=vshuffo(Vu.h,Vv.h)" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| # 0 0 0 1 1 1 1 1 0 1 0 v v v v v P P 0 u u u u u 1 0 0 d d d d d @@ -2462,20 +2613,21 @@ define pcodeop vshuffo_VhVh; build EndPacket; } -# (hvx,9) vextract -- "Rd=vextract(Vu,Rs)" +# (v60,9) vextract -- "Rd=vextract(Vu,Rs)" +# Solo instruction in packet +# Behavior: Rd = Vu.uw[ (Rs & (VWIDTH-1)) >> 2 ] # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| # 1 0 0 1 0 0 1 0 0 0 0 s s s s s P P 0 u u u u u 0 0 1 d d d d d -:vextract Rd5,Vu_0812,rx5 EndPacket is iclass=0x9 & op2127=0x10 & op13=0x0 & op0507=0x1 & Rd5 & Vu_0812 & rx5 & $(END_PACKET) { - # solo instruction in packet - assume .tmp vector not relavent - wordOff:4 = rx5 & ($(HVX_VECTOR_SIZE) - 1) & ~0x3; - vptr:4 = $(HVX_VECTOR_BASE) + wordOff; +:vextract Rd5,vu5,rs5 EndPacket is iclass=0x9 & op2127=0x10 & op13=0x0 & op0507=0x1 & Rd5 & vu5 & VuBase_0812 & rs5 & $(END_PACKET) { + wordOff:4 = rs5 & $(HVX_VECTOR_WORD_MASK); # (Rs & (VWIDTH-1)) >> 2, kept as a byte offset + vptr:4 = VuBase_0812 + wordOff; Rd5 = *[register]:4 vptr; build EndPacket; } -# (hvx,2) vgather -- "vtmp.h=vgather(Rt,Mu,Vvv.w).h" +# (v60,2) vgather -- "vtmp.h=vgather(Rt,Mu,Vvv.w).h" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| # 0 0 1 0 1 1 1 1 0 0 0 t t t t t P P u - - 0 1 0 - - - v v v v v @@ -2487,7 +2639,7 @@ define pcodeop vgather_RMWw; build EndPacket; } -# (hvx,2) vgather -- "if (Qs4) vtmp.h=vgather(Rt,Mu,Vvv.w).h" +# (v60,2) vgather -- "if (Qs4) vtmp.h=vgather(Rt,Mu,Vvv.w).h" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| # 0 0 1 0 1 1 1 1 0 0 0 t t t t t P P u - - 1 1 0 - s s v v v v v @@ -2499,7 +2651,7 @@ define pcodeop vgather_QRMWw; build EndPacket; } -# (hvx,2) vgather -- "vtmp.w=vgather(Rt,Mu,Vv.w).w" +# (v60,2) vgather -- "vtmp.w=vgather(Rt,Mu,Vv.w).w" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| # 0 0 1 0 1 1 1 1 0 0 0 t t t t t P P u - - 0 0 0 - - - v v v v v @@ -2511,7 +2663,7 @@ define pcodeop vgather_RMVw; build EndPacket; } -# (hvx,2) vgather -- "vtmp.h=vgather(Rt,Mu,Vv.h).h" +# (v60,2) vgather -- "vtmp.h=vgather(Rt,Mu,Vv.h).h" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| # 0 0 1 0 1 1 1 1 0 0 0 t t t t t P P u - - 0 0 1 - - - v v v v v @@ -2523,7 +2675,7 @@ define pcodeop vgather_RMVh; build EndPacket; } -# (hvx,2) vgather -- "if (Qs4) vtmp.w=vgather(Rt,Mu,Vv.w).w" +# (v60,2) vgather -- "if (Qs4) vtmp.w=vgather(Rt,Mu,Vv.w).w" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| # 0 0 1 0 1 1 1 1 0 0 0 t t t t t P P u - - 1 0 0 - s s v v v v v @@ -2541,7 +2693,7 @@ define pcodeop vgather_QRMVw; build EndPacket; } -# (hvx,2) vgather -- "if (Qs4) vtmp.h=vgather(Rt,Mu,Vv.h).h" +# (v60,2) vgather -- "if (Qs4) vtmp.h=vgather(Rt,Mu,Vv.h).h" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| # 0 0 1 0 1 1 1 1 0 0 0 t t t t t P P u - - 1 0 1 - s s v v v v v @@ -2553,415 +2705,458 @@ define pcodeop vgather_QRMVh; build EndPacket; } -# (hvx,2) vmem -- "Vd=vmem(Rt+#s4)" +# (v60,2) vmem -- "Vd=vmem(Rt+#s4)" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| # 0 0 1 0 1 0 0 0 0 0 0 t t t t t P P i 0 0 i i i 0 0 0 d d d d d # -# (hvx,2) vmem -- "Vd=vmem(Rt+#s4):nt" +# (v60,2) vmem -- "Vd=vmem(Rt+#s4):nt" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| # 0 0 1 0 1 0 0 0 0 1 0 t t t t t P P i 0 0 i i i 0 0 0 d d d d d -:vmem^ntHint22 Vd5,VAlignMemAddrRxS4 EndPacket is iclass=0x2 & op21=0 & op2327=0x10 & op1112=0x0 & op0507=0x0 & ntHint22 & Vd5 & VAlignMemAddrRxS4 & $(END_PACKET) [ cond=0; ] { +:vmem^ntHint22 Vd5,VAlignMemAddrRxS4 EndPacket is iclass=0x2 & op2327=0x10 & op21=0 & op1112=0x0 & op0507=0x0 & ntHint22 & Vd5 & VAlignMemAddrRxS4 & $(END_PACKET) [ cond=0; ] { Vd5 = VAlignMemAddrRxS4; # Vd5 handles forwarding commit build EndPacket; } -# (hvx,2) vmem -- "if (Pv) Vd=vmem(Rt+#s4)" +# (v60,2) vmem -- "if (Pv) Vd=vmem(Rt+#s4)" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| # 0 0 1 0 1 0 0 0 1 0 0 t t t t t P P i v v i i i 0 1 0 d d d d d # -# (hvx,2) vmem -- "if (!Pv) Vd=vmem(Rt+#s4)" +# (v60,2) vmem -- "if (!Pv) Vd=vmem(Rt+#s4)" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| # 0 0 1 0 1 0 0 0 1 0 0 t t t t t P P i v v i i i 0 1 1 d d d d d # -# (hvx,2) vmem -- "if (Pv) Vd=vmem(Rt+#s4):nt" +# (v60,2) vmem -- "if (Pv) Vd=vmem(Rt+#s4):nt" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| # 0 0 1 0 1 0 0 0 1 1 0 t t t t t P P i v v i i i 0 1 0 d d d d d # -# (hvx,2) vmem -- "if (!Pv) Vd=vmem(Rt+#s4):nt" +# (v60,2) vmem -- "if (!Pv) Vd=vmem(Rt+#s4):nt" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| # 0 0 1 0 1 0 0 0 1 1 0 t t t t t P P i v v i i i 0 1 1 d d d d d -:vmem^VPuCond1112_S05^ntHint22 vd5,VAlignMemAddrRxS4 EndPacket is iclass=0x2 & op21=0 & op2327=0x11 & op0607=0x1 & VPuCond1112_S05 & ntHint22 & vd5 & vd5_ & SetVNRegVd5 & VAlignMemAddrRxS4 & $(END_PACKET) { +:vmem^VPuCond1112_S05^ntHint22 vd5,VAlignMemAddrRxS4 EndPacket is iclass=0x2 & op2327=0x11 & op21=0 & op0607=0x1 & VPuCond1112_S05 & ntHint22 & vd5 & vd5_ & SetVNRegVd5 & VAlignMemAddrRxS4 & $(END_PACKET) { build VPuCond1112_S05; + build VAlignMemAddrRxS4; build EndPacket; <> + build VPuCond1112_S05; if (ConditionReg == 0) goto ; vd5_ = VAlignMemAddrRxS4; - + <> + build VPuCond1112_S05; if (ConditionReg == 0) goto ; vd5 = vd5_; - + } -# (hvx,2) vmem -- "Vd=vmem(Rx++#s3)" +# (v60,2) vmem -- "Vd=vmem(Rx++#s3)" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| # 0 0 1 0 1 0 0 1 0 0 0 x x x x x P P - 0 0 i i i 0 0 0 d d d d d # -# (hvx,2) vmem -- "Vd=vmem(Rx++#s3):nt" +# (v60,2) vmem -- "Vd=vmem(Rx++#s3):nt" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| # 0 0 1 0 1 0 0 1 0 1 0 x x x x x P P - 0 0 i i i 0 0 0 d d d d d -:vmem^ntHint22 Vd5,VAlignMemAddrRxAIS3 EndPacket is iclass=0x2 & op21=0 & op2327=0x12 & op1112=0x0 & op0507=0x0 & ntHint22 & Vd5 & VAlignMemAddrRxAIS3 & $(END_PACKET) [ cond=0; ] { +:vmem^ntHint22 Vd5,VAlignMemAddrRxAIS3 EndPacket is iclass=0x2 & op2327=0x12 & op21=0 & op1112=0x0 & op0507=0x0 & ntHint22 & Vd5 & VAlignMemAddrRxAIS3 & $(END_PACKET) [ cond=0; ] { Vd5 = VAlignMemAddrRxAIS3; # Vd5 handles forwarding commit build EndPacket; } -# (hvx,2) vmem -- "if (Pv) Vd=vmem(Rx++#s3)" +# (v60,2) vmem -- "if (Pv) Vd=vmem(Rx++#s3)" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| # 0 0 1 0 1 0 0 1 1 0 0 x x x x x P P - v v i i i 0 1 0 d d d d d # -# (hvx,2) vmem -- "if (!Pv) Vd=vmem(Rx++#s3)" +# (v60,2) vmem -- "if (!Pv) Vd=vmem(Rx++#s3)" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| # 0 0 1 0 1 0 0 1 1 0 0 x x x x x P P - v v i i i 0 1 1 d d d d d # -# (hvx,2) vmem -- "if (Pv) Vd=vmem(Rx++#s3):nt" +# (v60,2) vmem -- "if (Pv) Vd=vmem(Rx++#s3):nt" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| # 0 0 1 0 1 0 0 1 1 1 0 x x x x x P P - v v i i i 0 1 0 d d d d d # -# (hvx,2) vmem -- "if (!Pv) Vd=vmem(Rx++#s3):nt" +# (v60,2) vmem -- "if (!Pv) Vd=vmem(Rx++#s3):nt" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| # 0 0 1 0 1 0 0 1 1 1 0 x x x x x P P - v v i i i 0 1 1 d d d d d -:vmem^VPuCond1112_S05^ntHint22 vd5,VAlignMemAddrRxAIS3 EndPacket is iclass=0x2 & op21=0 & op2327=0x13 & op0607=0x1 & VPuCond1112_S05 & ntHint22 & vd5 & vd5_ & SetVNRegVd5 & VAlignMemAddrRxAIS3 & $(END_PACKET) [ cond=1; ] { +:vmem^VPuCond1112_S05^ntHint22 vd5,VAlignMemAddrRxAIS3 EndPacket is iclass=0x2 & op2327=0x13 & op21=0 & op0607=0x1 & VPuCond1112_S05 & ntHint22 & vd5 & vd5_ & SetVNRegVd5 & VAlignMemAddrRxAIS3 & $(END_PACKET) [ cond=1; ] { build VPuCond1112_S05; + build VAlignMemAddrRxAIS3; build EndPacket; <> + build VPuCond1112_S05; + build VAlignMemAddrRxAIS3; if (ConditionReg == 0) goto ; vd5_ = VAlignMemAddrRxAIS3; <> + build VPuCond1112_S05; # set ConditionReg before any conditional commit below + build VAlignMemAddrRxAIS3; # conditional Rx post-increment if (ConditionReg == 0) goto ; vd5 = vd5_; } -# (hvx,2) vmem -- "Vd=vmem(Rx++Mu)" +# (v60,2) vmem -- "Vd=vmem(Rx++Mu)" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| # 0 0 1 0 1 0 1 1 0 0 0 x x x x x P P u 0 0 - - - 0 0 0 d d d d d # -# (hvx,2) vmem -- "Vd=vmem(Rx++Mu):nt" +# (v60,2) vmem -- "Vd=vmem(Rx++Mu):nt" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| # 0 0 1 0 1 0 1 1 0 1 0 x x x x x P P u 0 0 - - - 0 0 0 d d d d d -:vmem^ntHint22 Vd5,VAlignMemAddrRxAIMu EndPacket is iclass=0x2 & op21=0 & op2327=0x16 & op1112=0x0 & op0507=0x0 & ntHint22 & Vd5 & VAlignMemAddrRxAIMu & $(END_PACKET) [ cond=0; ] { +:vmem^ntHint22 Vd5,VAlignMemAddrRxAIMu EndPacket is iclass=0x2 & op2327=0x16 & op21=0 & op1112=0x0 & op0507=0x0 & ntHint22 & Vd5 & VAlignMemAddrRxAIMu & $(END_PACKET) [ cond=0; ] { Vd5 = VAlignMemAddrRxAIMu; # Vd5 handles forwarding commit build EndPacket; } -# (hvx,2) vmem -- "if (Pv) Vd=vmem(Rx++Mu)" +# (v60,2) vmem -- "if (Pv) Vd=vmem(Rx++Mu)" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| # 0 0 1 0 1 0 1 1 1 0 0 x x x x x P P u v v - - - 0 1 0 d d d d d # -# (hvx,2) vmem -- "if (!Pv) Vd=vmem(Rx++Mu)" +# (v60,2) vmem -- "if (!Pv) Vd=vmem(Rx++Mu)" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| # 0 0 1 0 1 0 1 1 1 0 0 x x x x x P P u v v - - - 0 1 1 d d d d d # -# (hvx,2) vmem -- "if (Pv) Vd=vmem(Rx++Mu):nt" +# (v60,2) vmem -- "if (Pv) Vd=vmem(Rx++Mu):nt" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| # 0 0 1 0 1 0 1 1 1 1 0 x x x x x P P u v v - - - 0 1 0 d d d d d # -# (hvx,2) vmem -- "if (!Pv) Vd=vmem(Rx++Mu):nt" +# (v60,2) vmem -- "if (!Pv) Vd=vmem(Rx++Mu):nt" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| # 0 0 1 0 1 0 1 1 1 1 0 x x x x x P P u v v - - - 0 1 1 d d d d d -:vmem^VPuCond1112_S05^ntHint22 vd5,VAlignMemAddrRxAIMu EndPacket is iclass=0x2 & op21=0 & op2327=0x17 & op0607=0x1 & VPuCond1112_S05 & ntHint22 & vd5 & vd5_ & SetVNRegVd5 & VAlignMemAddrRxAIMu & $(END_PACKET) [ cond=1; ] { +:vmem^VPuCond1112_S05^ntHint22 vd5,VAlignMemAddrRxAIMu EndPacket is iclass=0x2 & op2327=0x17 & op21=0 & op0607=0x1 & VPuCond1112_S05 & ntHint22 & vd5 & vd5_ & SetVNRegVd5 & VAlignMemAddrRxAIMu & $(END_PACKET) [ cond=1; ] { build VPuCond1112_S05; + build VAlignMemAddrRxAIMu; build EndPacket; <> + build VPuCond1112_S05; + build VAlignMemAddrRxAIMu; if (ConditionReg == 0) goto ; vd5_ = VAlignMemAddrRxAIMu; <> + build VPuCond1112_S05; + build VAlignMemAddrRxAIMu; # conditionally commit Rx post-increment update if (ConditionReg == 0) goto ; vd5 = vd5_; } -# (hvx,2) vmem -- "Vd.cur=vmem(Rt+#s4)" +# (v60,2) vmem -- "Vd.cur=vmem(Rt+#s4)" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| # 0 0 1 0 1 0 0 0 0 0 0 t t t t t P P i 0 0 i i i 0 0 1 d d d d d # -# (hvx,2) vmem -- "Vd.cur=vmem(Rt+#s4):nt" +# (v60,2) vmem -- "Vd.cur=vmem(Rt+#s4):nt" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| # 0 0 1 0 1 0 0 0 0 1 0 t t t t t P P i 0 0 i i i 0 0 1 d d d d d -:vmem^ntHint22 Vd5cur,VAlignMemAddrRxS4 EndPacket is iclass=0x2 & op21=0 & op2327=0x10 & op1112=0x0 & op0507=0x1 & ntHint22 & Vd5cur & VAlignMemAddrRxS4 & $(END_PACKET) [ cond = 0; ] { +:vmem^ntHint22 Vd5cur,VAlignMemAddrRxS4 EndPacket is iclass=0x2 & op2327=0x10 & op21=0 & op1112=0x0 & op0507=0x1 & ntHint22 & Vd5cur & VAlignMemAddrRxS4 & $(END_PACKET) [ cond = 0; ] { Vd5cur = VAlignMemAddrRxS4; build EndPacket; } -# (hvx,2) vmem -- "if (Pv) Vd.cur=vmem(Rt+#s4)" +# (v60,2) vmem -- "if (Pv) Vd.cur=vmem(Rt+#s4)" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| # 0 0 1 0 1 0 0 0 1 0 0 t t t t t P P i v v i i i 1 0 0 d d d d d # -# (hvx,2) vmem -- "if (!Pv) Vd.cur=vmem(Rt+#s4)" +# (v60,2) vmem -- "if (!Pv) Vd.cur=vmem(Rt+#s4)" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| # 0 0 1 0 1 0 0 0 1 0 0 t t t t t P P i v v i i i 1 0 1 d d d d d # -# (hvx,2) vmem -- "if (Pv) Vd.cur=vmem(Rt+#s4):nt" +# (v60,2) vmem -- "if (Pv) Vd.cur=vmem(Rt+#s4):nt" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| # 0 0 1 0 1 0 0 0 1 1 0 t t t t t P P i v v i i i 1 0 0 d d d d d # -# (hvx,2) vmem -- "if (!Pv) Vd.cur=vmem(Rt+#s4):nt" +# (v60,2) vmem -- "if (!Pv) Vd.cur=vmem(Rt+#s4):nt" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| # 0 0 1 0 1 0 0 0 1 1 0 t t t t t P P i v v i i i 1 0 1 d d d d d -:vmem^VPuCond1112_S05^ntHint22 Vd5cur,VAlignMemAddrRxS4 EndPacket is iclass=0x2 & op21=0 & op2327=0x11 & op0607=0x2 & VPuCond1112_S05 & ntHint22 & Vd5cur & VAlignMemAddrRxS4 & $(END_PACKET) [ cond=1; ] { +:vmem^VPuCond1112_S05^ntHint22 Vd5cur,VAlignMemAddrRxS4 EndPacket is iclass=0x2 & op2327=0x11 & op21=0 & op0607=0x2 & VPuCond1112_S05 & ntHint22 & Vd5cur & VAlignMemAddrRxS4 & $(END_PACKET) [ cond=1; ] { build VPuCond1112_S05; + build VAlignMemAddrRxS4; build EndPacket; <> + build VPuCond1112_S05; if (ConditionReg == 0) goto ; Vd5cur = VAlignMemAddrRxS4; } -# (hvx,2) vmem -- "Vd.cur=vmem(Rx++#s3)" +# (v60,2) vmem -- "Vd.cur=vmem(Rx++#s3)" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| # 0 0 1 0 1 0 0 1 0 0 0 x x x x x P P - 0 0 i i i 0 0 1 d d d d d # -# (hvx,2) vmem -- "Vd.cur=vmem(Rx++#s3):nt" +# (v60,2) vmem -- "Vd.cur=vmem(Rx++#s3):nt" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| # 0 0 1 0 1 0 0 1 0 1 0 x x x x x P P - 0 0 i i i 0 0 1 d d d d d # -:vmem^ntHint22 Vd5cur,VAlignMemAddrRxAIS3 EndPacket is iclass=0x2 & op21=0 & op2327=0x12 & op1112=0x0 & op0507=0x1 & ntHint22 & Vd5cur & VAlignMemAddrRxAIS3 & $(END_PACKET) [ cond=0; ] { +:vmem^ntHint22 Vd5cur,VAlignMemAddrRxAIS3 EndPacket is iclass=0x2 & op2327=0x12 & op21=0 & op1112=0x0 & op0507=0x1 & ntHint22 & Vd5cur & VAlignMemAddrRxAIS3 & $(END_PACKET) [ cond=0; ] { Vd5cur = VAlignMemAddrRxAIS3; build EndPacket; } -# (hvx,2) vmem -- "if (Pv) Vd.cur=vmem(Rx++#s3)" +# (v60,2) vmem -- "if (Pv) Vd.cur=vmem(Rx++#s3)" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| # 0 0 1 0 1 0 0 1 1 0 0 x x x x x P P - v v i i i 1 0 0 d d d d d # -# (hvx,2) vmem -- "if (!Pv) Vd.cur=vmem(Rx++#s3)" +# (v60,2) vmem -- "if (!Pv) Vd.cur=vmem(Rx++#s3)" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| # 0 0 1 0 1 0 0 1 1 0 0 x x x x x P P - v v i i i 1 0 1 d d d d d # -# (hvx,2) vmem -- "if (Pv) Vd.cur=vmem(Rx++#s3):nt" +# (v60,2) vmem -- "if (Pv) Vd.cur=vmem(Rx++#s3):nt" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| # 0 0 1 0 1 0 0 1 1 1 0 x x x x x P P - v v i i i 1 0 0 d d d d d # -# (hvx,2) vmem -- "if (!Pv) Vd.cur=vmem(Rx++#s3):nt" +# (v60,2) vmem -- "if (!Pv) Vd.cur=vmem(Rx++#s3):nt" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| # 0 0 1 0 1 0 0 1 1 1 0 x x x x x P P - v v i i i 1 0 1 d d d d d -:vmem^VPuCond1112_S05^ntHint22 Vd5cur,VAlignMemAddrRxAIS3 EndPacket is iclass=0x2 & op21=0 & op2327=0x13 & op0607=0x2 & VPuCond1112_S05 & ntHint22 & Vd5cur & VAlignMemAddrRxAIS3 & $(END_PACKET) [ cond=1; ] { +:vmem^VPuCond1112_S05^ntHint22 Vd5cur,VAlignMemAddrRxAIS3 EndPacket is iclass=0x2 & op2327=0x13 & op21=0 & op0607=0x2 & VPuCond1112_S05 & ntHint22 & Vd5cur & VAlignMemAddrRxAIS3 & $(END_PACKET) [ cond=1; ] { build VPuCond1112_S05; + build VAlignMemAddrRxAIS3; build EndPacket; <> + build VPuCond1112_S05; + build VAlignMemAddrRxAIS3; if (ConditionReg == 0) goto ; Vd5cur = VAlignMemAddrRxAIS3; + <> + build VPuCond1112_S05; + build Vd5cur; # conditionally commit Vd + build VAlignMemAddrRxAIS3; # conditionally commit Rx post-increment update } -# (hvx,2) vmem -- "Vd.cur=vmem(Rx++Mu)" +# (v60,2) vmem -- "Vd.cur=vmem(Rx++Mu)" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| # 0 0 1 0 1 0 1 1 0 0 0 x x x x x P P u 0 0 - - - 0 0 1 d d d d d # -# (hvx,2) vmem -- "Vd.cur=vmem(Rx++Mu):nt" +# (v60,2) vmem -- "Vd.cur=vmem(Rx++Mu):nt" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| # 0 0 1 0 1 0 1 1 0 1 0 x x x x x P P u 0 0 - - - 0 0 1 d d d d d -:vmem^ntHint22 Vd5cur,VAlignMemAddrRxAIMu EndPacket is iclass=0x2 & op21=0 & op2327=0x16 & op1112=0x0 & op0507=0x1 & ntHint22 & Vd5cur & VAlignMemAddrRxAIMu & $(END_PACKET) [ cond=0;] { +:vmem^ntHint22 Vd5cur,VAlignMemAddrRxAIMu EndPacket is iclass=0x2 & op2327=0x16 & op21=0 & op1112=0x0 & op0507=0x1 & ntHint22 & Vd5cur & VAlignMemAddrRxAIMu & $(END_PACKET) [ cond=0;] { Vd5cur = VAlignMemAddrRxAIMu; build EndPacket; } -# (hvx,2) vmem -- "if (Pv) Vd.cur=vmem(Rx++Mu)" +# (v60,2) vmem -- "if (Pv) Vd.cur=vmem(Rx++Mu)" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| # 0 0 1 0 1 0 1 1 1 0 0 x x x x x P P u v v - - - 1 0 0 d d d d d # -# (hvx,2) vmem -- "if (!Pv) Vd.cur=vmem(Rx++Mu)" +# (v60,2) vmem -- "if (!Pv) Vd.cur=vmem(Rx++Mu)" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| # 0 0 1 0 1 0 1 1 1 0 0 x x x x x P P u v v - - - 1 0 1 d d d d d # -# (hvx,2) vmem -- "if (Pv) Vd.cur=vmem(Rx++Mu):nt" +# (v60,2) vmem -- "if (Pv) Vd.cur=vmem(Rx++Mu):nt" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| # 0 0 1 0 1 0 1 1 1 1 0 x x x x x P P u v v - - - 1 0 0 d d d d d # -# (hvx,2) vmem -- "if (!Pv) Vd.cur=vmem(Rx++Mu):nt" +# (v60,2) vmem -- "if (!Pv) Vd.cur=vmem(Rx++Mu):nt" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| # 0 0 1 0 1 0 1 1 1 1 0 x x x x x P P u v v - - - 1 0 1 d d d d d -:vmem^VPuCond1112_S05^ntHint22 Vd5cur,VAlignMemAddrRxAIMu EndPacket is iclass=0x2 & op21=0 & op2327=0x17 & op0607=0x2 & VPuCond1112_S05 & ntHint22 & Vd5cur & VAlignMemAddrRxAIMu & $(END_PACKET) [ cond=1; ] { +:vmem^VPuCond1112_S05^ntHint22 Vd5cur,VAlignMemAddrRxAIMu EndPacket is iclass=0x2 & op2327=0x17 & op21=0 & op0607=0x2 & VPuCond1112_S05 & ntHint22 & Vd5cur & VAlignMemAddrRxAIMu & $(END_PACKET) [ cond=1; ] { build VPuCond1112_S05; + build VAlignMemAddrRxAIMu; build EndPacket; <> + build VPuCond1112_S05; + build VAlignMemAddrRxAIMu; if (ConditionReg == 0) goto ; Vd5cur = VAlignMemAddrRxAIMu; + <> + build VPuCond1112_S05; + build Vd5cur; # conditionally commit Vd + build VAlignMemAddrRxAIMu; # conditionally commit Rx post-increment update } -# (hvx,2) vmem -- "Vd.tmp=vmem(Rt+#s4)" +# (v60,2) vmem -- "Vd.tmp=vmem(Rt+#s4)" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| # 0 0 1 0 1 0 0 0 0 0 0 t t t t t P P i 0 0 i i i 0 1 0 d d d d d # -# (hvx,2) vmem -- "Vd.tmp=vmem(Rt+#s4):nt" +# (v60,2) vmem -- "Vd.tmp=vmem(Rt+#s4):nt" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| # 0 0 1 0 1 0 0 0 0 1 0 t t t t t P P i 0 0 i i i 0 1 0 d d d d d -:vmem^ntHint22 Vd5tmp,VAlignMemAddrRxS4 EndPacket is iclass=0x2 & op21=0 & op2327=0x10 & op1112=0x0 & op0507=0x2 & ntHint22 & Vd5tmp & VAlignMemAddrRxS4 & $(END_PACKET) { +:vmem^ntHint22 Vd5tmp,VAlignMemAddrRxS4 EndPacket is iclass=0x2 & op2327=0x10 & op21=0 & op1112=0x0 & op0507=0x2 & ntHint22 & Vd5tmp & VAlignMemAddrRxS4 & $(END_PACKET) { Vd5tmp = VAlignMemAddrRxS4; build EndPacket; } -# (hvx,2) vmem -- "if (Pv) Vd.tmp=vmem(Rt+#s4)" +# (v60,2) vmem -- "if (Pv) Vd.tmp=vmem(Rt+#s4)" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| # 0 0 1 0 1 0 0 0 1 0 0 t t t t t P P i v v i i i 1 1 0 d d d d d # -# (hvx,2) vmem -- "if (!Pv) Vd.tmp=vmem(Rt+#s4)" +# (v60,2) vmem -- "if (!Pv) Vd.tmp=vmem(Rt+#s4)" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| # 0 0 1 0 1 0 0 0 1 0 0 t t t t t P P i v v i i i 1 1 1 d d d d d # -# (hvx,2) vmem -- "if (Pv) Vd.tmp=vmem(Rt+#s4):nt" +# (v60,2) vmem -- "if (Pv) Vd.tmp=vmem(Rt+#s4):nt" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| # 0 0 1 0 1 0 0 0 1 1 0 t t t t t P P i v v i i i 1 1 0 d d d d d -# (hvx,2) vmem -- "if (!Pv) Vd.tmp=vmem(Rt+#s4):nt" +# (v60,2) vmem -- "if (!Pv) Vd.tmp=vmem(Rt+#s4):nt" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| # 0 0 1 0 1 0 0 0 1 1 0 t t t t t P P i v v i i i 1 1 1 d d d d d -:vmem^VPuCond1112_S05^ntHint22 Vd5tmp,VAlignMemAddrRxS4 EndPacket is iclass=0x2 & op21=0 & op2327=0x11 & op0607=0x3 & VPuCond1112_S05 & ntHint22 & Vd5tmp & VAlignMemAddrRxS4 & $(END_PACKET) { +:vmem^VPuCond1112_S05^ntHint22 Vd5tmp,VAlignMemAddrRxS4 EndPacket is iclass=0x2 & op2327=0x11 & op21=0 & op0607=0x3 & VPuCond1112_S05 & ntHint22 & Vd5tmp & VAlignMemAddrRxS4 & $(END_PACKET) { build VPuCond1112_S05; + build VAlignMemAddrRxS4; build EndPacket; <> + build VPuCond1112_S05; if (ConditionReg == 0) goto ; Vd5tmp = VAlignMemAddrRxS4; - + } -# (hvx,2) vmem -- "Vd.tmp=vmem(Rx++#s3)" +# (v60,2) vmem -- "Vd.tmp=vmem(Rx++#s3)" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| # 0 0 1 0 1 0 0 1 0 0 0 x x x x x P P - 0 0 i i i 0 1 0 d d d d d # -# (hvx,2) vmem -- "Vd.tmp=vmem(Rx++#s3):nt" +# (v60,2) vmem -- "Vd.tmp=vmem(Rx++#s3):nt" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| # 0 0 1 0 1 0 0 1 0 1 0 x x x x x P P - 0 0 i i i 0 1 0 d d d d d -:vmem^ntHint22 Vd5tmp,VAlignMemAddrRxAIS3 EndPacket is iclass=0x2 & op21=0 & op2327=0x12 & op1112=0x0 & op0507=0x2 & ntHint22 & Vd5tmp & VAlignMemAddrRxAIS3 & $(END_PACKET) [ cond=0; ] { +:vmem^ntHint22 Vd5tmp,VAlignMemAddrRxAIS3 EndPacket is iclass=0x2 & op2327=0x12 & op21=0 & op1112=0x0 & op0507=0x2 & ntHint22 & Vd5tmp & VAlignMemAddrRxAIS3 & $(END_PACKET) [ cond=0; ] { Vd5tmp = VAlignMemAddrRxAIS3; build EndPacket; } -# (hvx,2) vmem -- "if (Pv) Vd.tmp=vmem(Rx++#s3)" +# (v60,2) vmem -- "if (Pv) Vd.tmp=vmem(Rx++#s3)" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| # 0 0 1 0 1 0 0 1 1 0 0 x x x x x P P - v v i i i 1 1 0 d d d d d # -# (hvx,2) vmem -- "if (!Pv) Vd.tmp=vmem(Rx++#s3)" +# (v60,2) vmem -- "if (!Pv) Vd.tmp=vmem(Rx++#s3)" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| # 0 0 1 0 1 0 0 1 1 0 0 x x x x x P P - v v i i i 1 1 1 d d d d d # -# (hvx,2) vmem -- "if (Pv) Vd.tmp=vmem(Rx++#s3):nt" +# (v60,2) vmem -- "if (Pv) Vd.tmp=vmem(Rx++#s3):nt" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| # 0 0 1 0 1 0 0 1 1 1 0 x x x x x P P - v v i i i 1 1 0 d d d d d # -# (hvx,2) vmem -- "if (!Pv) Vd.tmp=vmem(Rx++#s3):nt" +# (v60,2) vmem -- "if (!Pv) Vd.tmp=vmem(Rx++#s3):nt" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| # 0 0 1 0 1 0 0 1 1 1 0 x x x x x P P - v v i i i 1 1 1 d d d d d -:vmem^VPuCond1112_S05^ntHint22 Vd5tmp,VAlignMemAddrRxAIS3 EndPacket is iclass=0x2 & op21=0 & op2327=0x13 & op0607=0x3 & VPuCond1112_S05 & ntHint22 & Vd5tmp & VAlignMemAddrRxAIS3 & $(END_PACKET) [ cond=1; ] { +:vmem^VPuCond1112_S05^ntHint22 Vd5tmp,VAlignMemAddrRxAIS3 EndPacket is iclass=0x2 & op2327=0x13 & op21=0 & op0607=0x3 & VPuCond1112_S05 & ntHint22 & Vd5tmp & VAlignMemAddrRxAIS3 & $(END_PACKET) [ cond=1; ] { build VPuCond1112_S05; + build VAlignMemAddrRxAIS3; build EndPacket; <> + build VPuCond1112_S05; + build VAlignMemAddrRxAIS3; if (ConditionReg == 0) goto ; Vd5tmp = VAlignMemAddrRxAIS3; - + + <> + build VPuCond1112_S05; + build VAlignMemAddrRxAIS3; # conditionally commit Rx post-increment update } -# (hvx,2) vmem -- "Vd.tmp=vmem(Rx++Mu)" +# (v60,2) vmem -- "Vd.tmp=vmem(Rx++Mu)" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| # 0 0 1 0 1 0 1 1 0 0 0 x x x x x P P u 0 0 - - - 0 1 0 d d d d d # -# (hvx,2) vmem -- "Vd.tmp=vmem(Rx++Mu):nt" +# (v60,2) vmem -- "Vd.tmp=vmem(Rx++Mu):nt" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| # 0 0 1 0 1 0 1 1 0 1 0 x x x x x P P u 0 0 - - - 0 1 0 d d d d d -:vmem^ntHint22 Vd5tmp,VAlignMemAddrRxAIMu EndPacket is iclass=0x2 & op21=0 & op2327=0x16 & op1112=0x0 & op0507=0x2 & ntHint22 & Vd5tmp & VAlignMemAddrRxAIMu & $(END_PACKET) [ cond=0; ] { +:vmem^ntHint22 Vd5tmp,VAlignMemAddrRxAIMu EndPacket is iclass=0x2 & op2327=0x16 & op21=0 & op1112=0x0 & op0507=0x2 & ntHint22 & Vd5tmp & VAlignMemAddrRxAIMu & $(END_PACKET) [ cond=0; ] { Vd5tmp = VAlignMemAddrRxAIMu; build EndPacket; } -# (hvx,2) vmem -- "if (Pv) Vd.tmp=vmem(Rx++Mu)" +# (v60,2) vmem -- "if (Pv) Vd.tmp=vmem(Rx++Mu)" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| # 0 0 1 0 1 0 1 1 1 0 0 x x x x x P P u v v - - - 1 1 0 d d d d d # -# (hvx,2) vmem -- "if (!Pv) Vd.tmp=vmem(Rx++Mu)" +# (v60,2) vmem -- "if (!Pv) Vd.tmp=vmem(Rx++Mu)" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| # 0 0 1 0 1 0 1 1 1 0 0 x x x x x P P u v v - - - 1 1 1 d d d d d # -# (hvx,2) vmem -- "if (Pv) Vd.tmp=vmem(Rx++Mu):nt" +# (v60,2) vmem -- "if (Pv) Vd.tmp=vmem(Rx++Mu):nt" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| # 0 0 1 0 1 0 1 1 1 1 0 x x x x x P P u v v - - - 1 1 0 d d d d d # -# (hvx,2) vmem -- "if (!Pv) Vd.tmp=vmem(Rx++Mu):nt" +# (v60,2) vmem -- "if (!Pv) Vd.tmp=vmem(Rx++Mu):nt" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| # 0 0 1 0 1 0 1 1 1 1 0 x x x x x P P u v v - - - 1 1 1 d d d d d -:vmem^VPuCond1112_S05^ntHint22 Vd5tmp,VAlignMemAddrRxAIMu EndPacket is iclass=0x2 & op21=0 & op2327=0x17 & op0607=0x3 & VPuCond1112_S05 & ntHint22 & Vd5tmp & VAlignMemAddrRxAIMu & $(END_PACKET) [ cond=1; ] { +:vmem^VPuCond1112_S05^ntHint22 Vd5tmp,VAlignMemAddrRxAIMu EndPacket is iclass=0x2 & op2327=0x17 & op21=0 & op0607=0x3 & VPuCond1112_S05 & ntHint22 & Vd5tmp & VAlignMemAddrRxAIMu & $(END_PACKET) [ cond=1; ] { build VPuCond1112_S05; + build VAlignMemAddrRxAIMu; build EndPacket; <> + build VPuCond1112_S05; + build VAlignMemAddrRxAIMu; if (ConditionReg == 0) goto ; Vd5tmp = VAlignMemAddrRxAIMu; + <> + build VPuCond1112_S05; + build VAlignMemAddrRxAIMu; # conditionally commit Rx post-increment update } -# (hvx,2) vmemu -- "Vd=vmemu(Rt+#s4)" +# (v60,2) vmemu -- "Vd=vmemu(Rt+#s4)" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| # 0 0 1 0 1 0 0 0 0 0 0 t t t t t P P i 0 0 i i i 1 1 1 d d d d d @@ -2971,7 +3166,7 @@ define pcodeop vgather_QRMVh; build EndPacket; } -# (hvx,2) vmemu -- "Vd=vmemu(Rx++#s3)" +# (v60,2) vmemu -- "Vd=vmemu(Rx++#s3)" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| # 0 0 1 0 1 0 0 1 0 0 0 x x x x x P P - 0 0 i i i 1 1 1 d d d d d @@ -2981,7 +3176,7 @@ define pcodeop vgather_QRMVh; build EndPacket; } -# (hvx,2) vmemu -- "Vd=vmemu(Rx++Mu)" +# (v60,2) vmemu -- "Vd=vmemu(Rx++Mu)" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| # 0 0 1 0 1 0 1 1 0 0 0 x x x x x P P u 0 0 - - - 1 1 1 d d d d d @@ -2991,31 +3186,31 @@ define pcodeop vgather_QRMVh; build EndPacket; } -# (hvx,1) v6mpy -- "Vxx.w+=v6mpy(Vuu.ub,Vvv.b,#u2):v" +# (v60,1) v6mpy -- "Vxx.w+=v6mpy(Vuu.ub,Vvv.b,#u2):v" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| # 0 0 0 1 1 1 1 1 0 0 1 v v v v v P P 1 u u u u u 0 i i x x x x x define pcodeop Ww_v6mpyacc_WwWubWbI_v; -:v6mpy+=^":v" VddW_0004,VuuUB_0812,VvvB_1620,Uimm2_0506 EndPacket is iclass=0x1 & op2127=0x79 & op13=0x1 & op7=0x0 & vss5 & VddW_0004 & VuuUB_0812 & VvvB_1620 & Uimm2_0506 & $(END_PACKET) { - VddW_0004 = Ww_v6mpyacc_WwWubWbI_v(vss5,VuuUB_0812,VvvB_1620,Uimm2_0506); +:v6mpy+=^":v" VddW_0004,VuuUB_0812,VvvB_1620,Uimm2_0506 EndPacket is iclass=0x1 & op2127=0x79 & op13=0x1 & op7=0x0 & Vss_0004 & VddW_0004 & VuuUB_0812 & VvvB_1620 & Uimm2_0506 & $(END_PACKET) { + VddW_0004 = Ww_v6mpyacc_WwWubWbI_v(Vss_0004,VuuUB_0812,VvvB_1620,Uimm2_0506); build EndPacket; } -# (hvx,1) v6mpy -- "Vxx.w+=v6mpy(Vuu.ub,Vvv.b,#u2):h" +# (v60,1) v6mpy -- "Vxx.w+=v6mpy(Vuu.ub,Vvv.b,#u2):h" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| # 0 0 0 1 1 1 1 1 0 0 1 v v v v v P P 1 u u u u u 1 i i x x x x x define pcodeop Ww_v6mpyacc_WwWubWbI_h; -:v6mpy+=^":h" VddW_0004,VuuUB_0812,VvvB_1620,Uimm2_0506 EndPacket is iclass=0x1 & op2127=0x79 & op13=0x1 & op7=0x1 & vss5 & VddW_0004 & VuuUB_0812 & VvvB_1620 & Uimm2_0506 & $(END_PACKET) { - VddW_0004 = Ww_v6mpyacc_WwWubWbI_h(vss5,VuuUB_0812,VvvB_1620,Uimm2_0506); +:v6mpy+=^":h" VddW_0004,VuuUB_0812,VvvB_1620,Uimm2_0506 EndPacket is iclass=0x1 & op2127=0x79 & op13=0x1 & op7=0x1 & Vss_0004 & VddW_0004 & VuuUB_0812 & VvvB_1620 & Uimm2_0506 & $(END_PACKET) { + VddW_0004 = Ww_v6mpyacc_WwWubWbI_h(Vss_0004,VuuUB_0812,VvvB_1620,Uimm2_0506); build EndPacket; } -# (hvx,1) v6mpy -- "Vdd.w=v6mpy(Vuu.ub,Vvv.b,#u2):v" +# (v60,1) v6mpy -- "Vdd.w=v6mpy(Vuu.ub,Vvv.b,#u2):v" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| # 0 0 0 1 1 1 1 1 0 1 0 v v v v v P P 1 u u u u u 0 i i d d d d d @@ -3027,7 +3222,7 @@ define pcodeop Ww_v6mpy_WubWbI_v; build EndPacket; } -# (hvx,1) v6mpy -- "Vdd.w=v6mpy(Vuu.ub,Vvv.b,#u2):h" +# (v60,1) v6mpy -- "Vdd.w=v6mpy(Vuu.ub,Vvv.b,#u2):h" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| # 0 0 0 1 1 1 1 1 0 1 0 v v v v v P P 1 u u u u u 1 i i d d d d d @@ -3039,43 +3234,43 @@ define pcodeop Ww_v6mpy_WubWbI_h; build EndPacket; } -# (hvx,1) vadd -- "Vxx.w+=vadd(Vu.h,Vv.h)" +# (v60,1) vadd -- "Vxx.w+=vadd(Vu.h,Vv.h)" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| # 0 0 0 1 1 1 0 0 0 0 1 v v v v v P P 1 u u u u u 0 1 0 x x x x x define pcodeop Ww_vaddacc_WwVhVh; -:vadd+= VddW_0004,VuH_0812,VvH_1620 EndPacket is iclass=0x1 & op2127=0x61 & op13=0x1 & op0507=0x2 & vss5 & VddW_0004 & VuH_0812 & VvH_1620 & $(END_PACKET) { - VddW_0004 = Ww_vaddacc_WwVhVh(vss5,VuH_0812,VvH_1620); +:vadd+= VddW_0004,VuH_0812,VvH_1620 EndPacket is iclass=0x1 & op2127=0x61 & op13=0x1 & op0507=0x2 & Vss_0004 & VddW_0004 & VuH_0812 & VvH_1620 & $(END_PACKET) { + VddW_0004 = Ww_vaddacc_WwVhVh(Vss_0004,VuH_0812,VvH_1620); build EndPacket; } -# (hvx,1) vadd -- "Vxx.w+=vadd(Vu.uh,Vv.uh)" +# (v60,1) vadd -- "Vxx.w+=vadd(Vu.uh,Vv.uh)" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| # 0 0 0 1 1 1 0 0 0 1 0 v v v v v P P 1 u u u u u 1 0 0 x x x x x define pcodeop Ww_vaddacc_WwVuhVuh; -:vadd+= VddW_0004,VuUH_0812,VvUH_1620 EndPacket is iclass=0x1 & op2127=0x62 & op13=0x1 & op0507=0x4 & vss5 & VddW_0004 & VuUH_0812 & VvUH_1620 & $(END_PACKET) { - VddW_0004 = Ww_vaddacc_WwVuhVuh(vss5,VuUH_0812,VvUH_1620); +:vadd+= VddW_0004,VuUH_0812,VvUH_1620 EndPacket is iclass=0x1 & op2127=0x62 & op13=0x1 & op0507=0x4 & Vss_0004 & VddW_0004 & VuUH_0812 & VvUH_1620 & $(END_PACKET) { + VddW_0004 = Ww_vaddacc_WwVuhVuh(Vss_0004,VuUH_0812,VvUH_1620); build EndPacket; } -# (hvx,1) vadd -- "Vxx.h+=vadd(Vu.ub,Vv.ub)" +# (v60,1) vadd -- "Vxx.h+=vadd(Vu.ub,Vv.ub)" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| # 0 0 0 1 1 1 0 0 0 1 0 v v v v v P P 1 u u u u u 1 0 1 x x x x x define pcodeop Wh_vaddacc_WhVubVub; -:vadd+= VddH_0004,VuUB_0812,VvUB_1620 EndPacket is iclass=0x1 & op2127=0x62 & op13=0x1 & op0507=0x5 & vss5 & VddH_0004 & VuUB_0812 & VvUB_1620 & $(END_PACKET) { - VddH_0004 = Wh_vaddacc_WhVubVub(vss5,VuUB_0812,VvUB_1620); +:vadd+= VddH_0004,VuUB_0812,VvUB_1620 EndPacket is iclass=0x1 & op2127=0x62 & op13=0x1 & op0507=0x5 & Vss_0004 & VddH_0004 & VuUB_0812 & VvUB_1620 & $(END_PACKET) { + VddH_0004 = Wh_vaddacc_WhVubVub(Vss_0004,VuUB_0812,VvUB_1620); build EndPacket; } -# (hvx,1) vadd -- "Vdd.h=vadd(Vu.ub,Vv.ub)" +# (v60,1) vadd -- "Vdd.h=vadd(Vu.ub,Vv.ub)" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| # 0 0 0 1 1 1 0 0 1 0 1 v v v v v P P 0 u u u u u 0 1 0 d d d d d @@ -3087,7 +3282,7 @@ define pcodeop Wh_vadd_VubVub; build EndPacket; } -# (hvx,1) vadd -- "Vdd.w=vadd(Vu.uh,Vv.uh)" +# (v60,1) vadd -- "Vdd.w=vadd(Vu.uh,Vv.uh)" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| # 0 0 0 1 1 1 0 0 1 0 1 v v v v v P P 0 u u u u u 0 1 1 d d d d d @@ -3099,7 +3294,7 @@ define pcodeop Ww_vadd_VuhVuh; build EndPacket; } -# (hvx,1) vadd -- "Vdd.w=vadd(Vu.h,Vv.h)" +# (v60,1) vadd -- "Vdd.w=vadd(Vu.h,Vv.h)" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| # 0 0 0 1 1 1 0 0 1 0 1 v v v v v P P 0 u u u u u 1 0 0 d d d d d @@ -3111,7 +3306,7 @@ define pcodeop Ww_vadd_VhVh; build EndPacket; } -# (hvx,1) vsub -- "Vdd.h=vsub(Vu.ub,Vv.ub)" +# (v60,1) vsub -- "Vdd.h=vsub(Vu.ub,Vv.ub)" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| # 0 0 0 1 1 1 0 0 1 0 1 v v v v v P P 0 u u u u u 1 0 1 d d d d d @@ -3123,7 +3318,7 @@ define pcodeop Wh_vsub_VubVub; build EndPacket; } -# (hvx,1) vsub -- "Vdd.w=vsub(Vu.uh,Vv.uh)" +# (v60,1) vsub -- "Vdd.w=vsub(Vu.uh,Vv.uh)" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| # 0 0 0 1 1 1 0 0 1 0 1 v v v v v P P 0 u u u u u 1 1 0 d d d d d @@ -3135,7 +3330,7 @@ define pcodeop Ww_vsub_VuhVuh; build EndPacket; } -# (hvx,1) vsub -- "Vdd.w=vsub(Vu.h,Vv.h)" +# (v60,1) vsub -- "Vdd.w=vsub(Vu.h,Vv.h)" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| # 0 0 0 1 1 1 0 0 1 0 1 v v v v v P P 0 u u u u u 1 1 1 d d d d d @@ -3147,7 +3342,7 @@ define pcodeop Ww_vsub_VhVh; build EndPacket; } -# (hvx,1) vdmpy -- "Vdd.h=vdmpy(Vuu.ub,Rt.b)" +# (v60,1) vdmpy -- "Vdd.h=vdmpy(Vuu.ub,Rt.b)" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| # 0 0 0 1 1 0 0 1 0 0 0 t t t t t P P 0 u u u u u 1 1 1 d d d d d @@ -3159,19 +3354,19 @@ define pcodeop Ww_vdmpy_WubRb; build EndPacket; } -# (hvx,1) vdmpy -- "Vxx.h+=vdmpy(Vuu.ub,Rt.b)" +# (v60,1) vdmpy -- "Vxx.h+=vdmpy(Vuu.ub,Rt.b)" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| # 0 0 0 1 1 0 0 1 0 0 0 t t t t t P P 1 u u u u u 1 1 1 x x x x x define pcodeop vdmpyacc_WhWubRb; -:vdmpy+= VddH_0004,VuuUB_0812,RtB_1620 EndPacket is iclass=0x1 & op2127=0x48 & op13=0x1 & op0507=0x7 & vss5 & VddH_0004 & VuuUB_0812 & RtB_1620 & $(END_PACKET) { - VddH_0004 = vdmpyacc_WhWubRb(vss5,VuuUB_0812,RtB_1620); +:vdmpy+= VddH_0004,VuuUB_0812,RtB_1620 EndPacket is iclass=0x1 & op2127=0x48 & op13=0x1 & op0507=0x7 & Vss_0004 & VddH_0004 & VuuUB_0812 & RtB_1620 & $(END_PACKET) { + VddH_0004 = vdmpyacc_WhWubRb(Vss_0004,VuuUB_0812,RtB_1620); build EndPacket; } -# (hvx,1) vdmpy -- "Vd.w=vdmpy(Vuu.h,Rt.uh,#1):sat" +# (v60,1) vdmpy -- "Vd.w=vdmpy(Vuu.h,Rt.uh,#1):sat" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| # 0 0 0 1 1 0 0 1 0 0 1 t t t t t P P 0 u u u u u 0 0 1 d d d d d @@ -3183,7 +3378,7 @@ define pcodeop Vw_vdmpy_WhRuh_sat; build EndPacket; } -# (hvx,1) vdmpy -- "Vd.w=vdmpy(Vuu.h,Rt.h):sat" +# (v60,1) vdmpy -- "Vd.w=vdmpy(Vuu.h,Rt.h):sat" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| # 0 0 0 1 1 0 0 1 0 0 1 t t t t t P P 0 u u u u u 0 1 1 d d d d d @@ -3195,7 +3390,7 @@ define pcodeop Vw_vdmpy_WhRh_sat; build EndPacket; } -# (hvx,1) vdmpy -- "Vdd.w=vdmpy(Vuu.h,Rt.b)" +# (v60,1) vdmpy -- "Vdd.w=vdmpy(Vuu.h,Rt.b)" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| # 0 0 0 1 1 0 0 1 0 0 1 t t t t t P P 0 u u u u u 1 0 0 d d d d d @@ -3207,7 +3402,7 @@ define pcodeop Ww_vdmpy_WhRb; build EndPacket; } -# (hvx,1) vdmpy -- "Vx.w+=vdmpy(Vuu.h,Rt.uh,#1):sat" +# (v60,1) vdmpy -- "Vx.w+=vdmpy(Vuu.h,Rt.uh,#1):sat" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| # 0 0 0 1 1 0 0 1 0 0 1 t t t t t P P 1 u u u u u 0 0 1 x x x x x @@ -3219,7 +3414,7 @@ define pcodeop vdmpyacc_VwWhRuh_sat; build EndPacket; } -# (hvx,1) vdmpy -- "Vx.w+=vdmpy(Vuu.h,Rt.h):sat" +# (v60,1) vdmpy -- "Vx.w+=vdmpy(Vuu.h,Rt.h):sat" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| # 0 0 0 1 1 0 0 1 0 0 1 t t t t t P P 1 u u u u u 0 1 0 x x x x x @@ -3231,19 +3426,19 @@ define pcodeop vdmpyacc_VwWhRh_sat; build EndPacket; } -# (hvx,1) vdmpy -- "Vxx.w+=vdmpy(Vuu.h,Rt.b)" +# (v60,1) vdmpy -- "Vxx.w+=vdmpy(Vuu.h,Rt.b)" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| # 0 0 0 1 1 0 0 1 0 0 1 t t t t t P P 1 u u u u u 1 0 0 x x x x x define pcodeop vdmpyacc_WwWhRb; -:vdmpy+= VddW_0004,VuuH_0812,RtB_1620 EndPacket is iclass=0x1 & op2127=0x49 & op13=0x1 & op0507=0x4 & vss5 & VddW_0004 & VuuH_0812 & RtB_1620 & $(END_PACKET) { - VddW_0004 = vdmpyacc_WwWhRb(vss5,VuuH_0812,RtB_1620); +:vdmpy+= VddW_0004,VuuH_0812,RtB_1620 EndPacket is iclass=0x1 & op2127=0x49 & op13=0x1 & op0507=0x4 & Vss_0004 & VddW_0004 & VuuH_0812 & RtB_1620 & $(END_PACKET) { + VddW_0004 = vdmpyacc_WwWhRb(Vss_0004,VuuH_0812,RtB_1620); build EndPacket; } -# (hvx,1) vdmpy -- "Vx.w+=vdmpy(Vu.h,Vv.h):sat" +# (v60,1) vdmpy -- "Vx.w+=vdmpy(Vu.h,Vv.h):sat" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| # 0 0 0 1 1 1 0 0 0 0 0 v v v v v P P 1 u u u u u 0 1 1 x x x x x @@ -3255,7 +3450,7 @@ define pcodeop vdmpyacc_VwVhVh_sat; build EndPacket; } -# (hvx,1) vlut4 -- "Vd.h=vlut4(Vu.uh,Rtt.h)" +# (v60,1) vlut4 -- "Vd.h=vlut4(Vu.uh,Rtt.h)" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| # 0 0 0 1 1 0 0 1 0 1 1 t t t t t P P 0 u u u u u 1 0 0 d d d d d @@ -3267,7 +3462,7 @@ define pcodeop vlut4_VuhPh; build EndPacket; } -# (hvx,1) vmpa -- "Vx.h=vmpa(Vx.h,Vu.h,Rtt.h):sat" +# (v60,1) vmpa -- "Vx.h=vmpa(Vx.h,Vu.h,Rtt.h):sat" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| # 0 0 0 1 1 0 0 1 1 0 0 t t t t t P P 1 u u u u u 1 0 0 x x x x x @@ -3279,7 +3474,7 @@ define pcodeop vmpa_VhVhVhPh_sat; build EndPacket; } -# (hvx,1) vmpa -- "Vx.h=vmpa(Vx.h,Vu.uh,Rtt.uh):sat" +# (v60,1) vmpa -- "Vx.h=vmpa(Vx.h,Vu.uh,Rtt.uh):sat" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| # 0 0 0 1 1 0 0 1 1 0 0 t t t t t P P 1 u u u u u 1 0 1 x x x x x @@ -3291,7 +3486,7 @@ define pcodeop vmpa_VhVhVuhPuh_sat; build EndPacket; } -# (hvx,1) vmps -- "Vx.h=vmps(Vx.h,Vu.uh,Rtt.uh):sat" +# (v60,1) vmps -- "Vx.h=vmps(Vx.h,Vu.uh,Rtt.uh):sat" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| # 0 0 0 1 1 0 0 1 1 0 0 t t t t t P P 1 u u u u u 1 1 0 x x x x x @@ -3303,7 +3498,7 @@ define pcodeop vmps_VhVhVuhPuh_sat; build EndPacket; } -# (hvx,1) vmpa -- "Vdd.h=vmpa(Vuu.ub,Rt.b)" +# (v60,1) vmpa -- "Vdd.h=vmpa(Vuu.ub,Rt.b)" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| # 0 0 0 1 1 0 0 1 0 0 1 t t t t t P P 0 u u u u u 1 1 0 d d d d d @@ -3315,7 +3510,7 @@ define pcodeop vmpa_WubRb; build EndPacket; } -# (hvx,1) vmpa -- "Vdd.w=vmpa(Vuu.h,Rt.b)" +# (v60,1) vmpa -- "Vdd.w=vmpa(Vuu.h,Rt.b)" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| # 0 0 0 1 1 0 0 1 0 0 1 t t t t t P P 0 u u u u u 1 1 1 d d d d d @@ -3327,31 +3522,31 @@ define pcodeop vmpa_WhRb; build EndPacket; } -# (hvx,1) vmpa -- "Vxx.h+=vmpa(Vuu.ub,Rt.b)" +# (v60,1) vmpa -- "Vxx.h+=vmpa(Vuu.ub,Rt.b)" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| # 0 0 0 1 1 0 0 1 0 0 1 t t t t t P P 1 u u u u u 1 1 0 x x x x x define pcodeop vmpaacc_WhWubRb; -:vmpa+= VddH_0004,VuuUB_0812,RtB_1620 EndPacket is iclass=0x1 & op2127=0x49 & op13=0x1 & op0507=0x6 & vss5 & VddH_0004 & VuuUB_0812 & RtB_1620 & $(END_PACKET) { - VddH_0004 = vmpaacc_WhWubRb(vss5,VuuUB_0812,RtB_1620); +:vmpa+= VddH_0004,VuuUB_0812,RtB_1620 EndPacket is iclass=0x1 & op2127=0x49 & op13=0x1 & op0507=0x6 & Vss_0004 & VddH_0004 & VuuUB_0812 & RtB_1620 & $(END_PACKET) { + VddH_0004 = vmpaacc_WhWubRb(Vss_0004,VuuUB_0812,RtB_1620); build EndPacket; } -# (hvx,1) vmpa -- "Vxx.w+=vmpa(Vuu.h,Rt.b)" +# (v60,1) vmpa -- "Vxx.w+=vmpa(Vuu.h,Rt.b)" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| # 0 0 0 1 1 0 0 1 0 0 1 t t t t t P P 1 u u u u u 1 1 1 x x x x x define pcodeop vmpaacc_WwWhRb; -:vmpa+= VddW_0004,VuuH_0812,RtB_1620 EndPacket is iclass=0x1 & op2127=0x49 & op13=0x1 & op0507=0x7 & vss5 & VddW_0004 & VuuH_0812 & RtB_1620 & $(END_PACKET) { - VddW_0004 = vmpaacc_WwWhRb(vss5,VuuH_0812,RtB_1620); +:vmpa+= VddW_0004,VuuH_0812,RtB_1620 EndPacket is iclass=0x1 & op2127=0x49 & op13=0x1 & op0507=0x7 & Vss_0004 & VddW_0004 & VuuH_0812 & RtB_1620 & $(END_PACKET) { + VddW_0004 = vmpaacc_WwWhRb(Vss_0004,VuuH_0812,RtB_1620); build EndPacket; } -# (hvx,1) vmpa -- "Vdd.h=vmpa(Vuu.ub,Rt.ub)" +# (v60,1) vmpa -- "Vdd.h=vmpa(Vuu.ub,Rt.ub)" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| # 0 0 0 1 1 0 0 1 0 1 1 t t t t t P P 0 u u u u u 0 1 1 d d d d d @@ -3363,7 +3558,7 @@ define pcodeop vmpa_WubRub; build EndPacket; } -# (hvx,1) vmpa -- "Vdd.w=vmpa(Vuu.uh,Rt.b)" +# (v60,1) vmpa -- "Vdd.w=vmpa(Vuu.uh,Rt.b)" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| # 0 0 0 1 1 0 0 1 1 0 0 t t t t t P P 0 u u u u u 1 0 1 d d d d d @@ -3375,31 +3570,31 @@ define pcodeop vmpa_WuhRb; build EndPacket; } -# (hvx,1) vmpa -- "Vxx.w+=vmpa(Vuu.uh,Rt.b)" +# (v60,1) vmpa -- "Vxx.w+=vmpa(Vuu.uh,Rt.b)" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| # 0 0 0 1 1 0 0 1 1 0 0 t t t t t P P 1 u u u u u 0 1 0 x x x x x define pcodeop vmpaacc_WwWuhRb; -:vmpa+= VddW_0004,VuuUH_0812,RtB_1620 EndPacket is iclass=0x1 & op2127=0x4c & op13=0x1 & op0507=0x2 & vss5 & VddW_0004 & VuuUH_0812 & RtB_1620 & $(END_PACKET) { - VddW_0004 = vmpaacc_WwWuhRb(vss5,VuuUH_0812,RtB_1620); +:vmpa+= VddW_0004,VuuUH_0812,RtB_1620 EndPacket is iclass=0x1 & op2127=0x4c & op13=0x1 & op0507=0x2 & Vss_0004 & VddW_0004 & VuuUH_0812 & RtB_1620 & $(END_PACKET) { + VddW_0004 = vmpaacc_WwWuhRb(Vss_0004,VuuUH_0812,RtB_1620); build EndPacket; } -# (hvx,1) vmpa -- "Vxx.h+=vmpa(Vuu.ub,Rt.ub)" +# (v60,1) vmpa -- "Vxx.h+=vmpa(Vuu.ub,Rt.ub)" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| # 0 0 0 1 1 0 0 1 1 0 1 t t t t t P P 1 u u u u u 1 0 0 x x x x x define pcodeop vmpaacc_WhWubRub; -:vmpa+= VddH_0004,VuuUB_0812,RtUB_1620 EndPacket is iclass=0x1 & op2127=0x4d & op13=0x1 & op0507=0x4 & vss5 & VddH_0004 & VuuUB_0812 & RtUB_1620 & $(END_PACKET) { - VddH_0004 = vmpaacc_WhWubRub(vss5,VuuUB_0812,RtUB_1620); +:vmpa+= VddH_0004,VuuUB_0812,RtUB_1620 EndPacket is iclass=0x1 & op2127=0x4d & op13=0x1 & op0507=0x4 & Vss_0004 & VddH_0004 & VuuUB_0812 & RtUB_1620 & $(END_PACKET) { + VddH_0004 = vmpaacc_WhWubRub(Vss_0004,VuuUB_0812,RtUB_1620); build EndPacket; } -# (hvx,1) vmpa -- "Vdd.h=vmpa(Vuu.ub,Vvv.b)" +# (v60,1) vmpa -- "Vdd.h=vmpa(Vuu.ub,Vvv.b)" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| # 0 0 0 1 1 1 0 0 0 0 1 v v v v v P P 0 u u u u u 0 1 1 d d d d d @@ -3411,7 +3606,7 @@ define pcodeop vmpa_WubWb; build EndPacket; } -# (hvx,1) vmpa -- "Vdd.h=vmpa(Vuu.ub,Vvv.ub)" +# (v60,1) vmpa -- "Vdd.h=vmpa(Vuu.ub,Vvv.ub)" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| # 0 0 0 1 1 1 0 0 1 1 1 v v v v v P P 0 u u u u u 1 1 1 d d d d d @@ -3423,7 +3618,7 @@ define pcodeop vmpa_WubWub; build EndPacket; } -# (hvx,1) vmpy -- "Vdd.h=vmpy(Vu.ub,Rt.b)" +# (v60,1) vmpy -- "Vdd.h=vmpy(Vu.ub,Rt.b)" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| # 0 0 0 1 1 0 0 1 0 0 1 t t t t t P P 0 u u u u u 1 0 1 d d d d d @@ -3435,19 +3630,19 @@ define pcodeop vmpy_VubRb; build EndPacket; } -# (hvx,1) vmpy -- "Vxx.h+=vmpy(Vu.ub,Rt.b)" +# (v60,1) vmpy -- "Vxx.h+=vmpy(Vu.ub,Rt.b)" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| # 0 0 0 1 1 0 0 1 0 0 1 t t t t t P P 1 u u u u u 1 0 1 x x x x x define pcodeop vmpyacc_WhVubRb; -:vmpy+= VddH_0004,VuUB_0812,RtB_1620 EndPacket is iclass=0x1 & op2127=0x49 & op13=0x1 & op0507=0x5 & vss5 & VddH_0004 & VuUB_0812 & RtB_1620 & $(END_PACKET) { - VddH_0004 = vmpyacc_WhVubRb(vss5,VuUB_0812,RtB_1620); +:vmpy+= VddH_0004,VuUB_0812,RtB_1620 EndPacket is iclass=0x1 & op2127=0x49 & op13=0x1 & op0507=0x5 & Vss_0004 & VddH_0004 & VuUB_0812 & RtB_1620 & $(END_PACKET) { + VddH_0004 = vmpyacc_WhVubRb(Vss_0004,VuUB_0812,RtB_1620); build EndPacket; } -# (hvx,1) vmpy -- "Vdd.w=vmpy(Vu.h,Rt.h)" +# (v60,1) vmpy -- "Vdd.w=vmpy(Vu.h,Rt.h)" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| # 0 0 0 1 1 0 0 1 0 1 0 t t t t t P P 0 u u u u u 0 0 0 d d d d d @@ -3459,7 +3654,7 @@ define pcodeop vmpy_VhRh; build EndPacket; } -# (hvx,1) vmpy -- "Vdd.uw=vmpy(Vu.uh,Rt.uh)" +# (v60,1) vmpy -- "Vdd.uw=vmpy(Vu.uh,Rt.uh)" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| # 0 0 0 1 1 0 0 1 0 1 0 t t t t t P P 0 u u u u u 0 1 1 d d d d d @@ -3471,55 +3666,55 @@ define pcodeop vmpy_VuhRuh; build EndPacket; } -# (hvx,1) vmpy -- "Vxx.w+=vmpy(Vu.h,Rt.h):sat" +# (v60,1) vmpy -- "Vxx.w+=vmpy(Vu.h,Rt.h):sat" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| # 0 0 0 1 1 0 0 1 0 1 0 t t t t t P P 1 u u u u u 0 0 0 x x x x x define pcodeop vmpyacc_WwVhRh_sat; -:vmpy+=^":sat" VddW_0004,VuH_0812,RtH_1620 EndPacket is iclass=0x1 & op2127=0x4a & op13=0x1 & op0507=0x0 & vss5 & VddW_0004 & VuH_0812 & RtH_1620 & $(END_PACKET) { - VddW_0004 = vmpyacc_WwVhRh_sat(vss5,VuH_0812,RtH_1620); +:vmpy+=^":sat" VddW_0004,VuH_0812,RtH_1620 EndPacket is iclass=0x1 & op2127=0x4a & op13=0x1 & op0507=0x0 & Vss_0004 & VddW_0004 & VuH_0812 & RtH_1620 & $(END_PACKET) { + VddW_0004 = vmpyacc_WwVhRh_sat(Vss_0004,VuH_0812,RtH_1620); build EndPacket; } -# (hvx,1) vmpy -- "Vxx.uw+=vmpy(Vu.uh,Rt.uh)" +# (v60,1) vmpy -- "Vxx.uw+=vmpy(Vu.uh,Rt.uh)" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| # 0 0 0 1 1 0 0 1 0 1 0 t t t t t P P 1 u u u u u 0 0 1 x x x x x define pcodeop vmpyacc_WuwVuhRuh; -:vmpy+= VddUW_0004,VuUH_0812,RtUH_1620 EndPacket is iclass=0x1 & op2127=0x4a & op13=0x1 & op0507=0x1 & vss5 & VddUW_0004 & VuUH_0812 & RtUH_1620 & $(END_PACKET) { - VddUW_0004 = vmpyacc_WuwVuhRuh(vss5,VuUH_0812,RtUH_1620); +:vmpy+= VddUW_0004,VuUH_0812,RtUH_1620 EndPacket is iclass=0x1 & op2127=0x4a & op13=0x1 & op0507=0x1 & Vss_0004 & VddUW_0004 & VuUH_0812 & RtUH_1620 & $(END_PACKET) { + VddUW_0004 = vmpyacc_WuwVuhRuh(Vss_0004,VuUH_0812,RtUH_1620); build EndPacket; } -# (hvx,1) vmpy -- "Vxx.uh+=vmpy(Vu.ub,Rt.ub)" +# (v60,1) vmpy -- "Vxx.uh+=vmpy(Vu.ub,Rt.ub)" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| # 0 0 0 1 1 0 0 1 1 0 0 t t t t t P P 1 u u u u u 0 0 0 x x x x x define pcodeop vmpyacc_WuhVubRub; -:vmpy+= VddUH_0004,VuUB_0812,RtUB_1620 EndPacket is iclass=0x1 & op2127=0x4c & op13=0x1 & op0507=0x0 & vss5 & VddUH_0004 & VuUB_0812 & RtUB_1620 & $(END_PACKET) { - VddUH_0004 = vmpyacc_WuhVubRub(vss5,VuUB_0812,RtUB_1620); +:vmpy+= VddUH_0004,VuUB_0812,RtUB_1620 EndPacket is iclass=0x1 & op2127=0x4c & op13=0x1 & op0507=0x0 & Vss_0004 & VddUH_0004 & VuUB_0812 & RtUB_1620 & $(END_PACKET) { + VddUH_0004 = vmpyacc_WuhVubRub(Vss_0004,VuUB_0812,RtUB_1620); build EndPacket; } -# (hvx,1) vmpy -- "Vxx.w+=vmpy(Vu.h,Rt.h)" +# (v60,1) vmpy -- "Vxx.w+=vmpy(Vu.h,Rt.h)" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| # 0 0 0 1 1 0 0 1 1 0 1 t t t t t P P 1 u u u u u 1 1 0 x x x x x define pcodeop vmpyacc_WwVhRh; -:vmpy+= VddW_0004,VuH_0812,RtH_1620 EndPacket is iclass=0x1 & op2127=0x4d & op13=0x1 & op0507=0x6 & vss5 & VddW_0004 & VuH_0812 & RtH_1620 & $(END_PACKET) { - VddW_0004 = vmpyacc_WwVhRh(vss5,VuH_0812,RtH_1620); +:vmpy+= VddW_0004,VuH_0812,RtH_1620 EndPacket is iclass=0x1 & op2127=0x4d & op13=0x1 & op0507=0x6 & Vss_0004 & VddW_0004 & VuH_0812 & RtH_1620 & $(END_PACKET) { + VddW_0004 = vmpyacc_WwVhRh(Vss_0004,VuH_0812,RtH_1620); build EndPacket; } -# (hvx,1) vmpy -- "Vdd.uh=vmpy(Vu.ub,Rt.ub)" +# (v60,1) vmpy -- "Vdd.uh=vmpy(Vu.ub,Rt.ub)" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| # 0 0 0 1 1 0 0 1 1 1 0 t t t t t P P 0 u u u u u 0 0 0 d d d d d @@ -3531,7 +3726,7 @@ define pcodeop vmpy_VubRub; build EndPacket; } -# (hvx,1) vmpy -- "Vdd.h=vmpy(Vu.b,Vv.b)" +# (v60,1) vmpy -- "Vdd.h=vmpy(Vu.b,Vv.b)" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| # 0 0 0 1 1 1 0 0 0 0 0 v v v v v P P 0 u u u u u 1 0 0 d d d d d @@ -3543,7 +3738,7 @@ define pcodeop vmpy_VbVb; build EndPacket; } -# (hvx,1) vmpy -- "Vdd.uh=vmpy(Vu.ub,Vv.ub)" +# (v60,1) vmpy -- "Vdd.uh=vmpy(Vu.ub,Vv.ub)" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| # 0 0 0 1 1 1 0 0 0 0 0 v v v v v P P 0 u u u u u 1 0 1 d d d d d @@ -3555,7 +3750,7 @@ define pcodeop vmpy_VubVub; build EndPacket; } -# (hvx,1) vmpy -- "Vdd.h=vmpy(Vu.ub,Vv.b)" +# (v60,1) vmpy -- "Vdd.h=vmpy(Vu.ub,Vv.b)" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| # 0 0 0 1 1 1 0 0 0 0 0 v v v v v P P 0 u u u u u 1 1 0 d d d d d @@ -3567,43 +3762,103 @@ define pcodeop vmpy_VubVb; build EndPacket; } -# (hvx,1) vmpy -- "Vxx.h+=vmpy(Vu.b,Vv.b)" +# (v60,1) vmpy -- "Vxx.h+=vmpy(Vu.b,Vv.b)" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| # 0 0 0 1 1 1 0 0 0 0 0 v v v v v P P 1 u u u u u 1 0 0 x x x x x define pcodeop vmpyacc_WhVbVb; -:vmpy+= VddH_0004,VuB_0812,VvB_1620 EndPacket is iclass=0x1 & op2127=0x60 & op13=0x1 & op0507=0x4 & vss5 & VddH_0004 & VuB_0812 & VvB_1620 & $(END_PACKET) { - VddH_0004 = vmpyacc_WhVbVb(vss5,VuB_0812,VvB_1620); +:vmpy+= VddH_0004,VuB_0812,VvB_1620 EndPacket is iclass=0x1 & op2127=0x60 & op13=0x1 & op0507=0x4 & Vss_0004 & VddH_0004 & VuB_0812 & VvB_1620 & $(END_PACKET) { + VddH_0004 = vmpyacc_WhVbVb(Vss_0004,VuB_0812,VvB_1620); build EndPacket; } -# (hvx,1) vmpy -- "Vxx.uh+=vmpy(Vu.ub,Vv.ub)" +# (v60,1) vmpy -- "Vxx.uh+=vmpy(Vu.ub,Vv.ub)" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| # 0 0 0 1 1 1 0 0 0 0 0 v v v v v P P 1 u u u u u 1 0 1 x x x x x define pcodeop vmpyacc_WuhVubVub; -:vmpy+= VddUH_0004,VuUB_0812,VvUB_1620 EndPacket is iclass=0x1 & op2127=0x60 & op13=0x1 & op0507=0x5 & vss5 & VddUH_0004 & VuUB_0812 & VvUB_1620 & $(END_PACKET) { - VddUH_0004 = vmpyacc_WuhVubVub(vss5,VuUB_0812,VvUB_1620); +:vmpy+= VddUH_0004,VuUB_0812,VvUB_1620 EndPacket is iclass=0x1 & op2127=0x60 & op13=0x1 & op0507=0x5 & Vss_0004 & VddUH_0004 & VuUB_0812 & VvUB_1620 & $(END_PACKET) { + VddUH_0004 = vmpyacc_WuhVubVub(Vss_0004,VuUB_0812,VvUB_1620); build EndPacket; } -# (hvx,1) vmpy -- "Vxx.h+=vmpy(Vu.ub,Vv.b)" +# (v60,1) vmpy -- "Vxx.h+=vmpy(Vu.ub,Vv.b)" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| # 0 0 0 1 1 1 0 0 0 0 0 v v v v v P P 1 u u u u u 1 1 0 x x x x x define pcodeop vmpyacc_WhVubVb; -:vmpy+= VddH_0004,VuUB_0812,VvB_1620 EndPacket is iclass=0x1 & op2127=0x60 & op13=0x1 & op0507=0x6 & vss5 & VddH_0004 & VuUB_0812 & VvB_1620 & $(END_PACKET) { - VddH_0004 = vmpyacc_WhVubVb(vss5,VuUB_0812,VvB_1620); +:vmpy+= VddH_0004,VuUB_0812,VvB_1620 EndPacket is iclass=0x1 & op2127=0x60 & op13=0x1 & op0507=0x6 & Vss_0004 & VddH_0004 & VuUB_0812 & VvB_1620 & $(END_PACKET) { + VddH_0004 = vmpyacc_WhVubVb(Vss_0004,VuUB_0812,VvB_1620); + build EndPacket; +} + +# (v60,1) vmpy -- "Vdd.w=vmpy(Vu.h,Vv.h)" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 1 1 0 0 0 0 0 v v v v v P P 0 u u u u u 1 1 1 d d d d d + +define pcodeop vmpy_VhVh; + +:vmpy VddW_0004,VuH_0812,VvH_1620 EndPacket is iclass=0x1 & op2127=0x60 & op13=0x0 & op0507=0x7 & VddW_0004 & VuH_0812 & VvH_1620 & $(END_PACKET) { + VddW_0004 = vmpy_VhVh(VuH_0812,VvH_1620); + build EndPacket; +} + +# (v60,1) vmpy -- "Vxx.w+=vmpy(Vu.h,Vv.h)" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 1 1 0 0 0 0 0 v v v v v P P 1 u u u u u 1 1 1 x x x x x + +define pcodeop vmpyacc_WwVhVh; + +:vmpy+= VddW_0004,VuH_0812,VvH_1620 EndPacket is iclass=0x1 & op2127=0x60 & op13=0x1 & op0507=0x7 & Vss_0004 & VddW_0004 & VuH_0812 & VvH_1620 & $(END_PACKET) { + VddW_0004 = vmpyacc_WwVhVh(Vss_0004,VuH_0812,VvH_1620); + build EndPacket; +} + +# (v60,1) vmpy -- "Vdd.w=vmpy(Vu.h,Vv.uh)" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 1 1 0 0 0 0 1 v v v v v P P 0 u u u u u 0 1 0 d d d d d + +define pcodeop vmpy_VhVuh; + +:vmpy VddW_0004,VuH_0812,VvUH_1620 EndPacket is iclass=0x1 & op2127=0x61 & op13=0x0 & op0507=0x2 & VddW_0004 & VuH_0812 & VvUH_1620 & $(END_PACKET) { + VddW_0004 = vmpy_VhVuh(VuH_0812,VvUH_1620); + build EndPacket; +} + +# (v60,1) vmpy -- "Vxx.w+=vmpy(Vu.h,Vv.uh)" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 1 1 0 0 0 0 1 v v v v v P P 1 u u u u u 0 0 1 x x x x x + +define pcodeop vmpyacc_WwVhVuh; + +:vmpy+= VddW_0004,VuH_0812,VvUH_1620 EndPacket is iclass=0x1 & op2127=0x61 & op13=0x1 & op0507=0x1 & Vss_0004 & VddW_0004 & VuH_0812 & VvUH_1620 & $(END_PACKET) { + VddW_0004 = vmpyacc_WwVhVuh(Vss_0004,VuH_0812,VvUH_1620); build EndPacket; } -# (hvx,1) vmpy -- "Vdd.uw=vmpy(Vu.uh,Vv.uh)" +# (v60,1) vmpy -- "Vd.h=vmpy(Vu.h,Vv.h):<<1:rnd:sat" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 1 1 0 0 0 0 1 v v v v v P P 0 u u u u u 0 0 1 d d d d d + +define pcodeop vmpy_VhVh_rndsat; + +:vmpy^":<<1:rnd:sat" VdH_0004,VuH_0812,VvH_1620 EndPacket is iclass=0x1 & op2127=0x61 & op13=0x0 & op0507=0x1 & VdH_0004 & VuH_0812 & VvH_1620 & $(END_PACKET) { + VdH_0004 = vmpy_VhVh_rndsat(VuH_0812,VvH_1620); + build EndPacket; +} + +# (v60,1) vmpy -- "Vdd.uw=vmpy(Vu.uh,Vv.uh)" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| # 0 0 0 1 1 1 0 0 0 0 1 v v v v v P P 0 u u u u u 0 0 0 d d d d d @@ -3615,19 +3870,19 @@ define pcodeop vmpy_VuhVuh; build EndPacket; } -# (hvx,1) vmpy -- "Vxx.uw+=vmpy(Vu.uh,Vv.uh)" +# (v60,1) vmpy -- "Vxx.uw+=vmpy(Vu.uh,Vv.uh)" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| # 0 0 0 1 1 1 0 0 0 0 1 v v v v v P P 1 u u u u u 0 0 0 x x x x x define pcodeop vmpyacc_WuwVuhVuh; -:vmpy+= VddUW_0004,VuUH_0812,VvUH_1620 EndPacket is iclass=0x1 & op2127=0x61 & op13=0x1 & op0507=0x0 & vss5 & VddUW_0004 & VuUH_0812 & VvUH_1620 & $(END_PACKET) { - VddUW_0004 = vmpyacc_WuwVuhVuh(vss5,VuUH_0812,VvUH_1620); +:vmpy+= VddUW_0004,VuUH_0812,VvUH_1620 EndPacket is iclass=0x1 & op2127=0x61 & op13=0x1 & op0507=0x0 & Vss_0004 & VddUW_0004 & VuUH_0812 & VvUH_1620 & $(END_PACKET) { + VddUW_0004 = vmpyacc_WuwVuhVuh(Vss_0004,VuUH_0812,VvUH_1620); build EndPacket; } -# (hvx,1) vmpy -- "Vdd.qf32=vmpy(Vu.qf16,Vv.hf)" +# (v60,1) vmpy -- "Vdd.qf32=vmpy(Vu.qf16,Vv.hf)" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| # 0 0 0 1 1 1 1 1 1 0 0 v v v v v P P 1 u u u u u 0 0 0 d d d d d @@ -3639,7 +3894,7 @@ define pcodeop Wqf32_vmpy_Vqf16Vhf; build EndPacket; } -# (hvx,1) vmpy -- "Vd.qf16=vmpy(Vu.qf16,Vv.qf16)" +# (v60,1) vmpy -- "Vd.qf16=vmpy(Vu.qf16,Vv.qf16)" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| # 0 0 0 1 1 1 1 1 1 1 1 v v v v v P P 1 u u u u u 0 1 1 d d d d d @@ -3651,7 +3906,7 @@ define pcodeop vmpy_Vqf16Vqf16; build EndPacket; } -# (hvx,1) vmpy -- "Vd.qf16=vmpy(Vu.hf,Vv.hf)" +# (v60,1) vmpy -- "Vd.qf16=vmpy(Vu.hf,Vv.hf)" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| # 0 0 0 1 1 1 1 1 1 1 1 v v v v v P P 1 u u u u u 1 0 0 d d d d d @@ -3663,7 +3918,7 @@ define pcodeop vmpy_VhfVhf; build EndPacket; } -# (hvx,1) vmpy -- "Vd.qf16=vmpy(Vu.qf16,Vv.hf)" +# (v60,1) vmpy -- "Vd.qf16=vmpy(Vu.qf16,Vv.hf)" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| # 0 0 0 1 1 1 1 1 1 1 1 v v v v v P P 1 u u u u u 1 0 1 d d d d d @@ -3675,7 +3930,7 @@ define pcodeop vmpy_Vqf16Vhf; build EndPacket; } -# (hvx,1) vmpy -- "Vdd.qf32=vmpy(Vu.qf16,Vv.qf16)" +# (v60,1) vmpy -- "Vdd.qf32=vmpy(Vu.qf16,Vv.qf16)" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| # 0 0 0 1 1 1 1 1 1 1 1 v v v v v P P 1 u u u u u 1 1 0 d d d d d @@ -3687,7 +3942,7 @@ define pcodeop Wqf32_vmpy_Vqf16Vqf16; build EndPacket; } -# (hvx,1) vmpy -- "Vdd.qf32=vmpy(Vu.hf,Vv.hf)" +# (v60,1) vmpy -- "Vdd.qf32=vmpy(Vu.hf,Vv.hf)" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| # 0 0 0 1 1 1 1 1 1 1 1 v v v v v P P 1 u u u u u 1 1 1 d d d d d @@ -3699,7 +3954,7 @@ define pcodeop Wqf32_vmpy_VhfVhf; build EndPacket; } -# (hvx,1) vmpyi -- "Vd.h=vmpyi(Vu.h,Vv.h)" +# (v60,1) vmpyi -- "Vd.h=vmpyi(Vu.h,Vv.h)" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| # 0 0 0 1 1 1 0 0 0 0 1 v v v v v P P 0 u u u u u 1 0 0 d d d d d @@ -3711,7 +3966,7 @@ define pcodeop vmpyi_VhVh; build EndPacket; } -# (hvx,1) vmpyi -- "Vx.h+=vmpyi(Vu.h,Vv.h)" +# (v60,1) vmpyi -- "Vx.h+=vmpyi(Vu.h,Vv.h)" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| # 0 0 0 1 1 1 0 0 0 0 1 v v v v v P P 1 u u u u u 1 0 0 x x x x x @@ -3723,7 +3978,7 @@ define pcodeop vmpyiacc_VhVhVh; build EndPacket; } -# (hvx,1) vmpyie -- "Vx.w+=vmpyie(Vu.w,Vv.uh)" +# (v60,1) vmpyie -- "Vx.w+=vmpyie(Vu.w,Vv.uh)" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| # 0 0 0 1 1 1 0 0 0 0 1 v v v v v P P 1 u u u u u 1 0 1 x x x x x @@ -3735,7 +3990,7 @@ define pcodeop vmpyieacc_VwVwVuh; build EndPacket; } -# (hvx,1) vmpyie -- "Vx.w+=vmpyie(Vu.w,Vv.h)" +# (v60,1) vmpyie -- "Vx.w+=vmpyie(Vu.w,Vv.h)" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| # 0 0 0 1 1 1 0 0 0 1 0 v v v v v P P 1 u u u u u 0 0 0 x x x x x @@ -3747,7 +4002,7 @@ define pcodeop vmpyieacc_VwVwVh; build EndPacket; } -# (hvx,1) vmpyie -- "Vd.w=vmpyie(Vu.w,Vv.uh)" +# (v60,1) vmpyie -- "Vd.w=vmpyie(Vu.w,Vv.uh)" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| # 0 0 0 1 1 1 1 1 1 1 0 v v v v v P P 0 u u u u u 0 0 0 d d d d d @@ -3759,7 +4014,7 @@ define pcodeop vmpyie_VwVuh; build EndPacket; } -# (hvx,1) vmpyio -- "Vd.w=vmpyio(Vu.w,Vv.h)" +# (v60,1) vmpyio -- "Vd.w=vmpyio(Vu.w,Vv.h)" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| # 0 0 0 1 1 1 1 1 1 1 0 v v v v v P P 0 u u u u u 0 0 1 d d d d d @@ -3771,7 +4026,7 @@ define pcodeop vmpyio_VwVh; build EndPacket; } -# (hvx,1) vmpyi -- "Vx.w+=vmpyi(Vu.w,Rt.h)" +# (v60,1) vmpyi -- "Vx.w+=vmpyi(Vu.w,Rt.h)" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| # 0 0 0 1 1 0 0 1 0 1 0 t t t t t P P 1 u u u u u 0 1 1 x x x x x @@ -3783,7 +4038,7 @@ define pcodeop vmpyiacc_VwVwRh; build EndPacket; } -# (hvx,1) vmpyi -- "Vd.w=vmpyi(Vu.w,Rt.h)" +# (v60,1) vmpyi -- "Vd.w=vmpyi(Vu.w,Rt.h)" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| # 0 0 0 1 1 0 0 1 1 0 0 t t t t t P P 0 u u u u u 1 1 1 d d d d d @@ -3795,7 +4050,7 @@ define pcodeop vmpyi_VwRh; build EndPacket; } -# (hvx,1) vmpy -- "Vd.qf32=vmpy(Vu.qf32,Vv.qf32)" +# (v60,1) vmpy -- "Vd.qf32=vmpy(Vu.qf32,Vv.qf32)" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| # 0 0 0 1 1 1 1 1 1 1 1 v v v v v P P 1 u u u u u 0 0 0 d d d d d @@ -3807,7 +4062,7 @@ define pcodeop vmpy_Vqf32Vqf32; build EndPacket; } -# (hvx,1) vmpy -- "Vd.qf32=vmpy(Vu.sf,Vv.sf)" +# (v60,1) vmpy -- "Vd.qf32=vmpy(Vu.sf,Vv.sf)" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| # 0 0 0 1 1 1 1 1 1 1 1 v v v v v P P 1 u u u u u 0 0 1 d d d d d @@ -3819,19 +4074,19 @@ define pcodeop vmpy_VsfVsf; build EndPacket; } -# (hvx,1) vmpyo -- "Vxx+=vmpyo(Vu.w,Vv.h)" +# (v60,1) vmpyo -- "Vxx+=vmpyo(Vu.w,Vv.h)" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| # 0 0 0 1 1 1 0 0 0 0 1 v v v v v P P 1 u u u u u 0 1 1 x x x x x define pcodeop vmpyoacc_WVwVh; -:vmpyo+= Vdd5,VuW_0812,VvH_1620 EndPacket is iclass=0x1 & op2127=0x61 & op13=0x1 & op0507=0x3 & vss5 & Vdd5 & VuW_0812 & VvH_1620 & $(END_PACKET) { - Vdd5 = vmpyoacc_WVwVh(vss5,VuW_0812,VvH_1620); +:vmpyo+= Vdd5,VuW_0812,VvH_1620 EndPacket is iclass=0x1 & op2127=0x61 & op13=0x1 & op0507=0x3 & Vss_0004 & Vdd5 & VuW_0812 & VvH_1620 & $(END_PACKET) { + Vdd5 = vmpyoacc_WVwVh(Vss_0004,VuW_0812,VvH_1620); build EndPacket; } -# (hvx,1) vmpyo -- "Vx.w+=vmpyo(Vu.w,Vv.h):<<1:sat:shift" +# (v60,1) vmpyo -- "Vx.w+=vmpyo(Vu.w,Vv.h):<<1:sat:shift" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| # 0 0 0 1 1 1 0 0 0 0 1 v v v v v P P 1 u u u u u 1 1 0 x x x x x @@ -3843,7 +4098,7 @@ define pcodeop vmpyoacc_VwVwVh_s1_sat_shift; build EndPacket; } -# (hvx,1) vmpyo -- "Vx.w+=vmpyo(Vu.w,Vv.h):<<1:rnd:sat:shift" +# (v60,1) vmpyo -- "Vx.w+=vmpyo(Vu.w,Vv.h):<<1:rnd:sat:shift" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| # 0 0 0 1 1 1 0 0 0 0 1 v v v v v P P 1 u u u u u 1 1 1 x x x x x @@ -3855,7 +4110,7 @@ define pcodeop vmpyoacc_VwVwVh_s1_rnd_sat_shift; build EndPacket; } -# (hvx,1) vmpye -- "Vdd=vmpye(Vu.w,Vv.uh)" +# (v60,1) vmpye -- "Vdd=vmpye(Vu.w,Vv.uh)" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| # 0 0 0 1 1 1 1 0 1 0 1 v v v v v P P 0 u u u u u 1 1 0 d d d d d @@ -3867,7 +4122,7 @@ define pcodeop W_vmpye_VwVuh; build EndPacket; } -# (hvx,1) vmpyo -- "Vd.w=vmpyo(Vu.w,Vv.h):<<1:rnd:sat" +# (v60,1) vmpyo -- "Vd.w=vmpyo(Vu.w,Vv.h):<<1:rnd:sat" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| # 0 0 0 1 1 1 1 1 0 1 0 v v v v v P P 0 u u u u u 0 0 0 d d d d d @@ -3879,7 +4134,7 @@ define pcodeop vmpyo_VwVh_s1_rnd_sat; build EndPacket; } -# (hvx,1) vmpye -- "Vd.w=vmpye(Vu.w,Vv.uh)" +# (v60,1) vmpye -- "Vd.w=vmpye(Vu.w,Vv.uh)" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| # 0 0 0 1 1 1 1 1 1 1 1 v v v v v P P 0 u u u u u 1 0 1 d d d d d @@ -3891,7 +4146,7 @@ define pcodeop vmpye_VwVuh; build EndPacket; } -# (hvx,1) vmpyo -- "Vd.w=vmpyo(Vu.w,Vv.h):<<1:sat" +# (v60,1) vmpyo -- "Vd.w=vmpyo(Vu.w,Vv.h):<<1:sat" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| # 0 0 0 1 1 1 1 1 1 1 1 v v v v v P P 0 u u u u u 1 1 1 d d d d d @@ -3903,7 +4158,7 @@ define pcodeop vmpyo_VwVh_s1_sat; build EndPacket; } -# (hvx,1) vrmpy -- "Vdd.w=vrmpy(Vuu.ub,Rt.b,#u1)" +# (v60,1) vrmpy -- "Vdd.w=vrmpy(Vuu.ub,Rt.b,#u1)" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| # 0 0 0 1 1 0 0 1 0 1 0 t t t t t P P 0 u u u u u 1 0 i d d d d d @@ -3915,31 +4170,31 @@ define pcodeop vrmpy_WubRbI; build EndPacket; } -# (hvx,1) vrmpy -- "Vxx.w+=vrmpy(Vuu.ub,Rt.b,#u1)" +# (v60,1) vrmpy -- "Vxx.w+=vrmpy(Vuu.ub,Rt.b,#u1)" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| # 0 0 0 1 1 0 0 1 0 1 0 t t t t t P P 1 u u u u u 1 0 i x x x x x define pcodeop vrmpyacc_WwWubRbI; -:vrmpy+= VddW_0004,VuuUB_0812,RtB_1620,Uimm1_05 EndPacket is iclass=0x1 & op2127=0x4a & op13=0x1 & op0607=0x2 & vss5 & VddW_0004 & VuuUB_0812 & RtB_1620 & Uimm1_05 & $(END_PACKET) { - VddW_0004 = vrmpyacc_WwWubRbI(vss5,VuuUB_0812,RtB_1620,Uimm1_05); +:vrmpy+= VddW_0004,VuuUB_0812,RtB_1620,Uimm1_05 EndPacket is iclass=0x1 & op2127=0x4a & op13=0x1 & op0607=0x2 & Vss_0004 & VddW_0004 & VuuUB_0812 & RtB_1620 & Uimm1_05 & $(END_PACKET) { + VddW_0004 = vrmpyacc_WwWubRbI(Vss_0004,VuuUB_0812,RtB_1620,Uimm1_05); build EndPacket; } -# (hvx,1) vrmpy -- "Vxx.uw+=vrmpy(Vuu.ub,Rt.ub,#u1)" +# (v60,1) vrmpy -- "Vxx.uw+=vrmpy(Vuu.ub,Rt.ub,#u1)" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| # 0 0 0 1 1 0 0 1 0 1 1 t t t t t P P 1 u u u u u 1 1 i x x x x x define pcodeop vrmpyacc_WuwWubRubI; -:vrmpy+= VddUW_0004,VuuUB_0812,RtUB_1620,Uimm1_05 EndPacket is iclass=0x1 & op2127=0x4b & op13=0x1 & op0607=0x3 & vss5 & VddUW_0004 & VuuUB_0812 & RtUB_1620 & Uimm1_05 & $(END_PACKET) { - VddUW_0004 = vrmpyacc_WuwWubRubI(vss5,VuuUB_0812,RtUB_1620,Uimm1_05); +:vrmpy+= VddUW_0004,VuuUB_0812,RtUB_1620,Uimm1_05 EndPacket is iclass=0x1 & op2127=0x4b & op13=0x1 & op0607=0x3 & Vss_0004 & VddUW_0004 & VuuUB_0812 & RtUB_1620 & Uimm1_05 & $(END_PACKET) { + VddUW_0004 = vrmpyacc_WuwWubRubI(Vss_0004,VuuUB_0812,RtUB_1620,Uimm1_05); build EndPacket; } -# (hvx,1) vrmpy -- "Vdd.uw=vrmpy(Vuu.ub,Rt.ub,#u1)" +# (v60,1) vrmpy -- "Vdd.uw=vrmpy(Vuu.ub,Rt.ub,#u1)" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| # 0 0 0 1 1 0 0 1 1 0 1 t t t t t P P 0 u u u u u 1 1 i d d d d d @@ -3951,7 +4206,7 @@ define pcodeop vrmpy_WubRubI; build EndPacket; } -# (hvx,1) vrmpy -- "Vx.uw+=vrmpy(Vu.ub,Vv.ub)" +# (v60,1) vrmpy -- "Vx.uw+=vrmpy(Vu.ub,Vv.ub)" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| # 0 0 0 1 1 1 0 0 0 0 0 v v v v v P P 1 u u u u u 0 0 0 x x x x x @@ -3963,7 +4218,7 @@ define pcodeop vrmpyacc_VuwVubVub; build EndPacket; } -# (hvx,1) vrmpy -- "Vx.w+=vrmpy(Vu.b,Vv.b)" +# (v60,1) vrmpy -- "Vx.w+=vrmpy(Vu.b,Vv.b)" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| # 0 0 0 1 1 1 0 0 0 0 0 v v v v v P P 1 u u u u u 0 0 1 x x x x x @@ -3975,7 +4230,7 @@ define pcodeop vrmpyacc_VwVbVb; build EndPacket; } -# (hvx,1) vrmpy -- "Vx.w+=vrmpy(Vu.ub,Vv.b)" +# (v60,1) vrmpy -- "Vx.w+=vrmpy(Vu.ub,Vv.b)" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| # 0 0 0 1 1 1 0 0 0 0 0 v v v v v P P 1 u u u u u 0 1 0 x x x x x @@ -3987,7 +4242,7 @@ define pcodeop vrmpyacc_VwVubVb; build EndPacket; } -# (hvx,1) vtmpy -- "Vdd.h=vtmpy(Vuu.b,Rt.b)" +# (v60,1) vtmpy -- "Vdd.h=vtmpy(Vuu.b,Rt.b)" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| # 0 0 0 1 1 0 0 1 0 0 0 t t t t t P P 0 u u u u u 0 0 0 d d d d d @@ -3999,7 +4254,7 @@ define pcodeop vtmpy_WbRb; build EndPacket; } -# (hvx,1) vtmpy -- "Vdd.h=vtmpy(Vuu.ub,Rt.b)" +# (v60,1) vtmpy -- "Vdd.h=vtmpy(Vuu.ub,Rt.b)" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| # 0 0 0 1 1 0 0 1 0 0 0 t t t t t P P 0 u u u u u 0 0 1 d d d d d @@ -4011,43 +4266,43 @@ define pcodeop vtmpy_WubRb; build EndPacket; } -# (hvx,1) vtmpy -- "Vxx.h+=vtmpy(Vuu.b,Rt.b)" +# (v60,1) vtmpy -- "Vxx.h+=vtmpy(Vuu.b,Rt.b)" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| # 0 0 0 1 1 0 0 1 0 0 0 t t t t t P P 1 u u u u u 0 0 0 x x x x x define pcodeop vtmpyacc_WhWbRb; -:vtmpy+= VddH_0004,VuuB_0812,RtB_1620 EndPacket is iclass=0x1 & op2127=0x48 & op13=0x1 & op0507=0x0 & vss5 & VddH_0004 & VuuB_0812 & RtB_1620 & $(END_PACKET) { - VddH_0004 = vtmpyacc_WhWbRb(vss5,VuuB_0812,RtB_1620); +:vtmpy+= VddH_0004,VuuB_0812,RtB_1620 EndPacket is iclass=0x1 & op2127=0x48 & op13=0x1 & op0507=0x0 & Vss_0004 & VddH_0004 & VuuB_0812 & RtB_1620 & $(END_PACKET) { + VddH_0004 = vtmpyacc_WhWbRb(Vss_0004,VuuB_0812,RtB_1620); build EndPacket; } -# (hvx,1) vtmpy -- "Vxx.h+=vtmpy(Vuu.ub,Rt.b)" +# (v60,1) vtmpy -- "Vxx.h+=vtmpy(Vuu.ub,Rt.b)" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| # 0 0 0 1 1 0 0 1 0 0 0 t t t t t P P 1 u u u u u 0 0 1 x x x x x define pcodeop vtmpyacc_WhWubRb; -:vtmpy+= VddH_0004,VuuUB_0812,RtB_1620 EndPacket is iclass=0x1 & op2127=0x48 & op13=0x1 & op0507=0x1 & vss5 & VddH_0004 & VuuUB_0812 & RtB_1620 & $(END_PACKET) { - VddH_0004 = vtmpyacc_WhWubRb(vss5,VuuUB_0812,RtB_1620); +:vtmpy+= VddH_0004,VuuUB_0812,RtB_1620 EndPacket is iclass=0x1 & op2127=0x48 & op13=0x1 & op0507=0x1 & Vss_0004 & VddH_0004 & VuuUB_0812 & RtB_1620 & $(END_PACKET) { + VddH_0004 = vtmpyacc_WhWubRb(Vss_0004,VuuUB_0812,RtB_1620); build EndPacket; } -# (hvx,1) vtmpy -- "Vxx.w+=vtmpy(Vuu.h,Rt.b)" +# (v60,1) vtmpy -- "Vxx.w+=vtmpy(Vuu.h,Rt.b)" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| # 0 0 0 1 1 0 0 1 0 0 0 t t t t t P P 1 u u u u u 0 1 0 x x x x x define pcodeop vtmpyacc_WwWhRb; -:vtmpy+= VddW_0004,VuuH_0812,RtB_1620 EndPacket is iclass=0x1 & op2127=0x48 & op13=0x1 & op0507=0x2 & vss5 & VddW_0004 & VuuH_0812 & RtB_1620 & $(END_PACKET) { - VddW_0004 = vtmpyacc_WwWhRb(vss5,VuuH_0812,RtB_1620); +:vtmpy+= VddW_0004,VuuH_0812,RtB_1620 EndPacket is iclass=0x1 & op2127=0x48 & op13=0x1 & op0507=0x2 & Vss_0004 & VddW_0004 & VuuH_0812 & RtB_1620 & $(END_PACKET) { + VddW_0004 = vtmpyacc_WwWhRb(Vss_0004,VuuH_0812,RtB_1620); build EndPacket; } -# (hvx,1) vtmpy -- "Vdd.w=vtmpy(Vuu.h,Rt.b)" +# (v60,1) vtmpy -- "Vdd.w=vtmpy(Vuu.h,Rt.b)" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| # 0 0 0 1 1 0 0 1 1 0 1 t t t t t P P 0 u u u u u 1 0 0 d d d d d @@ -4059,7 +4314,7 @@ define pcodeop vtmpy_WhRb; build EndPacket; } -# (hvx,1) vdsad -- "Vdd.uw=vdsad(Vuu.uh,Rt.uh)" +# (v60,1) vdsad -- "Vdd.uw=vdsad(Vuu.uh,Rt.uh)" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| # 0 0 0 1 1 0 0 1 0 0 0 t t t t t P P 0 u u u u u 1 0 1 d d d d d @@ -4071,19 +4326,19 @@ define pcodeop vdsad_WuhRuh; build EndPacket; } -# (hvx,1) vdsad -- "Vxx.uw+=vdsad(Vuu.uh,Rt.uh)" +# (v60,1) vdsad -- "Vxx.uw+=vdsad(Vuu.uh,Rt.uh)" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| # 0 0 0 1 1 0 0 1 0 1 1 t t t t t P P 1 u u u u u 0 0 0 x x x x x define pcodeop vdsadacc_WuwWuhRuh; -:vdsad+= VddUW_0004,VuuUH_0812,RtUH_1620 EndPacket is iclass=0x1 & op2127=0x4b & op13=0x1 & op0507=0x0 & vss5 & VddUW_0004 & VuuUH_0812 & RtUH_1620 & $(END_PACKET) { - VddUW_0004 = vdsadacc_WuwWuhRuh(vss5,VuuUH_0812,RtUH_1620); +:vdsad+= VddUW_0004,VuuUH_0812,RtUH_1620 EndPacket is iclass=0x1 & op2127=0x4b & op13=0x1 & op0507=0x0 & Vss_0004 & VddUW_0004 & VuuUH_0812 & RtUH_1620 & $(END_PACKET) { + VddUW_0004 = vdsadacc_WuwWuhRuh(Vss_0004,VuuUH_0812,RtUH_1620); build EndPacket; } -# (hvx,1) vrsad -- "Vdd.uw=vrsad(Vuu.ub,Rt.ub,#u1)" +# (v60,1) vrsad -- "Vdd.uw=vrsad(Vuu.ub,Rt.ub,#u1)" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| # 0 0 0 1 1 0 0 1 0 1 0 t t t t t P P 0 u u u u u 1 1 i d d d d d @@ -4095,19 +4350,19 @@ define pcodeop vrsad_WubRubI; build EndPacket; } -# (hvx,1) vrsad -- "Vxx.uw+=vrsad(Vuu.ub,Rt.ub,#u1)" +# (v60,1) vrsad -- "Vxx.uw+=vrsad(Vuu.ub,Rt.ub,#u1)" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| # 0 0 0 1 1 0 0 1 0 1 0 t t t t t P P 1 u u u u u 1 1 i x x x x x define pcodeop vrsadacc_WuwWubRubI; -:vrsad+= VddUW_0004,VuuUB_0812,RtUB_1620,Uimm1_05 EndPacket is iclass=0x1 & op2127=0x4a & op13=0x1 & op0607=0x3 & vss5 & VddUW_0004 & VuuUB_0812 & RtUB_1620 & Uimm1_05 & $(END_PACKET) { - VddUW_0004 = vrsadacc_WuwWubRubI(vss5,VuuUB_0812,RtUB_1620,Uimm1_05); +:vrsad+= VddUW_0004,VuuUB_0812,RtUB_1620,Uimm1_05 EndPacket is iclass=0x1 & op2127=0x4a & op13=0x1 & op0607=0x3 & Vss_0004 & VddUW_0004 & VuuUB_0812 & RtUB_1620 & Uimm1_05 & $(END_PACKET) { + VddUW_0004 = vrsadacc_WuwWubRubI(Vss_0004,VuuUB_0812,RtUB_1620,Uimm1_05); build EndPacket; } -# (hvx,1) vdmpy -- "Vd.w=vdmpy(Vu.h,Rt.b)" +# (v60,1) vdmpy -- "Vd.w=vdmpy(Vu.h,Rt.b)" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| # 0 0 0 1 1 0 0 1 0 0 0 t t t t t P P 0 u u u u u 0 1 0 d d d d d @@ -4119,7 +4374,7 @@ define pcodeop vdmpy_VhRb; build EndPacket; } -# (hvx,1) vdmpy -- "Vd.h=vdmpy(Vu.ub,Rt.b)" +# (v60,1) vdmpy -- "Vd.h=vdmpy(Vu.ub,Rt.b)" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| # 0 0 0 1 1 0 0 1 0 0 0 t t t t t P P 0 u u u u u 1 1 0 d d d d d @@ -4131,7 +4386,7 @@ define pcodeop vdmpy_VubRb; build EndPacket; } -# (hvx,1) vdmpy -- "Vx.w+=vdmpy(Vu.h,Rt.b)" +# (v60,1) vdmpy -- "Vx.w+=vdmpy(Vu.h,Rt.b)" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| # 0 0 0 1 1 0 0 1 0 0 0 t t t t t P P 1 u u u u u 0 1 1 x x x x x @@ -4143,7 +4398,7 @@ define pcodeop vdmpyacc_VwVhRb; build EndPacket; } -# (hvx,1) vdmpy -- "Vx.h+=vdmpy(Vu.ub,Rt.b)" +# (v60,1) vdmpy -- "Vx.h+=vdmpy(Vu.ub,Rt.b)" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| # 0 0 0 1 1 0 0 1 0 0 0 t t t t t P P 1 u u u u u 1 1 0 x x x x x @@ -4155,7 +4410,7 @@ define pcodeop vdmpyacc_VhVubRb; build EndPacket; } -# (hvx,1) vdmpy -- "Vd.w=vdmpy(Vu.h,Rt.uh):sat" +# (v60,1) vdmpy -- "Vd.w=vdmpy(Vu.h,Rt.uh):sat" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| # 0 0 0 1 1 0 0 1 0 0 1 t t t t t P P 0 u u u u u 0 0 0 d d d d d @@ -4167,7 +4422,7 @@ define pcodeop vdmpy_VhRuh_sat; build EndPacket; } -# (hvx,1) vdmpy -- "Vd.w=vdmpy(Vu.h,Rt.h):sat" +# (v60,1) vdmpy -- "Vd.w=vdmpy(Vu.h,Rt.h):sat" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| # 0 0 0 1 1 0 0 1 0 0 1 t t t t t P P 0 u u u u u 0 1 0 d d d d d @@ -4179,7 +4434,7 @@ define pcodeop vdmpy_VhRh_sat; build EndPacket; } -# (hvx,1) vdmpy -- "Vx.w+=vdmpy(Vu.h,Rt.uh):sat" +# (v60,1) vdmpy -- "Vx.w+=vdmpy(Vu.h,Rt.uh):sat" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| # 0 0 0 1 1 0 0 1 0 0 1 t t t t t P P 1 u u u u u 0 0 0 x x x x x @@ -4191,7 +4446,7 @@ define pcodeop vdmpyacc_VwVhRuh_sat; build EndPacket; } -# (hvx,1) vdmpy -- "Vx.w+=vdmpy(Vu.h,Rt.h):sat" +# (v60,1) vdmpy -- "Vx.w+=vdmpy(Vu.h,Rt.h):sat" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| # 0 0 0 1 1 0 0 1 0 0 1 t t t t t P P 1 u u u u u 0 1 1 x x x x x @@ -4203,7 +4458,7 @@ define pcodeop vdmpyacc_VwVhRh_sat; build EndPacket; } -# (hvx,1) vdmpy -- "Vd.w=vdmpy(Vu.h,Vv.h):sat" +# (v60,1) vdmpy -- "Vd.w=vdmpy(Vu.h,Vv.h):sat" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| # 0 0 0 1 1 1 0 0 0 0 0 v v v v v P P 0 u u u u u 0 1 1 d d d d d @@ -4215,7 +4470,7 @@ define pcodeop vdmpy_VhVh_sat; build EndPacket; } -# (hvx,1) vmpy -- "Vd.h=vmpy(Vu.h,Rt.h):<<1:sat" +# (v60,1) vmpy -- "Vd.h=vmpy(Vu.h,Rt.h):<<1:sat" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| # 0 0 0 1 1 0 0 1 0 1 0 t t t t t P P 0 u u u u u 0 0 1 d d d d d @@ -4227,7 +4482,7 @@ define pcodeop vmpy_VhRh_s1_sat; build EndPacket; } -# (hvx,1) vmpy -- "Vd.h=vmpy(Vu.h,Rt.h):<<1:rnd:sat" +# (v60,1) vmpy -- "Vd.h=vmpy(Vu.h,Rt.h):<<1:rnd:sat" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| # 0 0 0 1 1 0 0 1 0 1 0 t t t t t P P 0 u u u u u 0 1 0 d d d d d @@ -4239,7 +4494,7 @@ define pcodeop vmpy_VhRh_s1_rnd_sat; build EndPacket; } -# (hvx,1) vmpy -- "Vd.uh=vmpy(Vu.uh,Vv.uh):>>16" +# (v60,1) vmpy -- "Vd.uh=vmpy(Vu.uh,Vv.uh):>>16" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| # 0 0 0 1 1 1 1 1 1 1 0 v v v v v P P 1 u u u u u 1 1 1 d d d d d @@ -4251,7 +4506,7 @@ define pcodeop vmpy_VuhVuh_rs16; build EndPacket; } -# (hvx,1) vmpyieo -- "Vd.w=vmpyieo(Vu.h,Vv.h)" +# (v60,1) vmpyieo -- "Vd.w=vmpyieo(Vu.h,Vv.h)" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| # 0 0 0 1 1 1 1 1 0 1 1 v v v v v P P 0 u u u u u 0 0 0 d d d d d @@ -4263,7 +4518,7 @@ define pcodeop vmpyieo_VhVh; build EndPacket; } -# (hvx,1) vmpyi -- "Vx.w+=vmpyi(Vu.w,Rt.b)" +# (v60,1) vmpyi -- "Vx.w+=vmpyi(Vu.w,Rt.b)" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| # 0 0 0 1 1 0 0 1 0 1 0 t t t t t P P 1 u u u u u 0 1 0 x x x x x @@ -4275,7 +4530,7 @@ define pcodeop vmpyiacc_VwVwRb; build EndPacket; } -# (hvx,1) vmpyi -- "Vd.h=vmpyi(Vu.h,Rt.b)" +# (v60,1) vmpyi -- "Vd.h=vmpyi(Vu.h,Rt.b)" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| # 0 0 0 1 1 0 0 1 0 1 1 t t t t t P P 0 u u u u u 0 0 0 d d d d d @@ -4287,7 +4542,7 @@ define pcodeop vmpyi_VhRb; build EndPacket; } -# (hvx,1) vmpyi -- "Vx.h+=vmpyi(Vu.h,Rt.b)" +# (v60,1) vmpyi -- "Vx.h+=vmpyi(Vu.h,Rt.b)" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| # 0 0 0 1 1 0 0 1 0 1 1 t t t t t P P 1 u u u u u 0 0 1 x x x x x @@ -4299,7 +4554,7 @@ define pcodeop vmpyiacc_VhVhRb; build EndPacket; } -# (hvx,1) vmpyi -- "Vd.w=vmpyi(Vu.w,Rt.ub)" +# (v60,1) vmpyi -- "Vd.w=vmpyi(Vu.w,Rt.ub)" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| # 0 0 0 1 1 0 0 1 1 0 0 t t t t t P P 0 u u u u u 1 1 0 d d d d d @@ -4311,7 +4566,7 @@ define pcodeop vmpyi_VwRub; build EndPacket; } -# (hvx,1) vmpyi -- "Vx.w+=vmpyi(Vu.w,Rt.ub)" +# (v60,1) vmpyi -- "Vx.w+=vmpyi(Vu.w,Rt.ub)" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| # 0 0 0 1 1 0 0 1 1 0 0 t t t t t P P 1 u u u u u 0 0 1 x x x x x @@ -4323,7 +4578,7 @@ define pcodeop vmpyiacc_VwVwRub; build EndPacket; } -# (hvx,1) vmpyi -- "Vd.w=vmpyi(Vu.w,Rt.b)" +# (v60,1) vmpyi -- "Vd.w=vmpyi(Vu.w,Rt.b)" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| # 0 0 0 1 1 0 0 1 1 0 1 t t t t t P P 0 u u u u u 0 0 0 d d d d d @@ -4335,7 +4590,7 @@ define pcodeop vmpyi_VwRb; build EndPacket; } -# (hvx,1) vmpye -- "Vd.uw=vmpye(Vu.uh,Rt.uh)" +# (v60,1) vmpye -- "Vd.uw=vmpye(Vu.uh,Rt.uh)" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| # 0 0 0 1 1 0 0 1 0 1 1 t t t t t P P 0 u u u u u 0 1 0 d d d d d @@ -4347,7 +4602,7 @@ define pcodeop vmpye_VuhRuh; build EndPacket; } -# (hvx,1) vmpye -- "Vx.uw+=vmpye(Vu.uh,Rt.uh)" +# (v60,1) vmpye -- "Vx.uw+=vmpye(Vu.uh,Rt.uh)" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| # 0 0 0 1 1 0 0 1 1 0 0 t t t t t P P 1 u u u u u 0 1 1 x x x x x @@ -4359,7 +4614,7 @@ define pcodeop vmpyeacc_VuwVuhRuh; build EndPacket; } -# (hvx,1) vrmpy -- "Vd.uw=vrmpy(Vu.ub,Rt.ub)" +# (v60,1) vrmpy -- "Vd.uw=vrmpy(Vu.ub,Rt.ub)" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| # 0 0 0 1 1 0 0 1 0 0 0 t t t t t P P 0 u u u u u 0 1 1 d d d d d @@ -4371,7 +4626,7 @@ define pcodeop vrmpy_VubRub; build EndPacket; } -# (hvx,1) vrmpy -- "Vd.w=vrmpy(Vu.ub,Rt.b)" +# (v60,1) vrmpy -- "Vd.w=vrmpy(Vu.ub,Rt.b)" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| # 0 0 0 1 1 0 0 1 0 0 0 t t t t t P P 0 u u u u u 1 0 0 d d d d d @@ -4383,7 +4638,7 @@ define pcodeop Vw_vrmpy_VubRb; build EndPacket; } -# (hvx,1) vrmpy -- "Vx.uw+=vrmpy(Vu.ub,Rt.ub)" +# (v60,1) vrmpy -- "Vx.uw+=vrmpy(Vu.ub,Rt.ub)" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| # 0 0 0 1 1 0 0 1 0 0 0 t t t t t P P 1 u u u u u 1 0 0 x x x x x @@ -4395,7 +4650,7 @@ define pcodeop vrmpyacc_VuwVubRub; build EndPacket; } -# (hvx,1) vrmpy -- "Vx.w+=vrmpy(Vu.ub,Rt.b)" +# (v60,1) vrmpy -- "Vx.w+=vrmpy(Vu.ub,Rt.b)" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| # 0 0 0 1 1 0 0 1 0 0 0 t t t t t P P 1 u u u u u 1 0 1 x x x x x @@ -4407,7 +4662,7 @@ define pcodeop vrmpyacc_VwVubRb; build EndPacket; } -# (hvx,1) vrmpy -- "Vd.uw=vrmpy(Vu.ub,Vv.ub)" +# (v60,1) vrmpy -- "Vd.uw=vrmpy(Vu.ub,Vv.ub)" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| # 0 0 0 1 1 1 0 0 0 0 0 v v v v v P P 0 u u u u u 0 0 0 d d d d d @@ -4419,7 +4674,7 @@ define pcodeop Vuw_vrmpy_VubVub; build EndPacket; } -# (hvx,1) vrmpy -- "Vd.w=vrmpy(Vu.b,Vv.b)" +# (v60,1) vrmpy -- "Vd.w=vrmpy(Vu.b,Vv.b)" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| # 0 0 0 1 1 1 0 0 0 0 0 v v v v v P P 0 u u u u u 0 0 1 d d d d d @@ -4431,7 +4686,7 @@ define pcodeop Vw_vrmpy_VbVb; build EndPacket; } -# (hvx,1) vrmpy -- "Vd.w=vrmpy(Vu.ub,Vv.b)" +# (v60,1) vrmpy -- "Vd.w=vrmpy(Vu.ub,Vv.b)" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| # 0 0 0 1 1 1 0 0 0 0 0 v v v v v P P 0 u u u u u 0 1 0 d d d d d @@ -4447,7 +4702,7 @@ define pcodeop Vw_vrmpy_VubVb; # NOTE: The vsplat instruction from V60 was removed in later versions # -# (hvx,1) vsplat -- "Vd=vsplat(Rt)" +# (v60,1) vsplat -- "Vd=vsplat(Rt)" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| # 0 0 0 1 1 0 0 1 1 0 1 t t t t t P P 0 - - - - 0 0 0 1 d d d d d @@ -4459,7 +4714,7 @@ define pcodeop V_vsplat_R; build EndPacket; } -# (hvx,1) vsplat -- "Vd.h=vsplat(Rt)" +# (v60,1) vsplat -- "Vd.h=vsplat(Rt)" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| # 0 0 0 1 1 0 0 1 1 1 0 t t t t t P P 0 - - - - - 0 0 1 d d d d d @@ -4471,7 +4726,7 @@ define pcodeop Vh_vsplat_R; build EndPacket; } -# (hvx,1) vsplat -- "Vd.b=vsplat(Rt)" +# (v60,1) vsplat -- "Vd.b=vsplat(Rt)" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| # 0 0 0 1 1 0 0 1 1 1 0 t t t t t P P 0 - - - - - 0 1 0 d d d d d @@ -4483,7 +4738,7 @@ define pcodeop Vb_vsplat_R; build EndPacket; } -# (hvx,1) vand -- "Qx4|=vand(Vu,Rt)" +# (v60,1) vand -- "Qx4|=vand(Vu,Rt)" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| # 0 0 0 1 1 0 0 1 0 1 1 t t t t t P P 1 u u u u u 1 0 0 - - - x x @@ -4495,7 +4750,7 @@ define pcodeop Q_vandor_QVR; build EndPacket; } -# (hvx,1) vand -- "Qd4=vand(Vu,Rt)" +# (v60,1) vand -- "Qd4=vand(Vu,Rt)" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| # 0 0 0 1 1 0 0 1 1 0 1 t t t t t P P 0 u u u u u 0 1 0 - 1 0 d d @@ -4507,7 +4762,7 @@ define pcodeop Q_vand_VR; build EndPacket; } -# (hvx,1) vand -- "Vx|=vand(Qu4,Rt)" +# (v60,1) vand -- "Vx|=vand(Qu4,Rt)" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| # 0 0 0 1 1 0 0 1 0 1 1 t t t t t P P 1 - - 0 u u 0 1 1 x x x x x @@ -4519,17 +4774,17 @@ define pcodeop V_vandor_VQR; build EndPacket; } -# (hvx,1) vand -- "Vx|=vand(!Qu4,Rt)" +# (v60,1) vand -- "Vx|=vand(!Qu4,Rt)" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| # 0 0 0 1 1 0 0 1 0 1 1 t t t t t P P 1 - - 1 u u 0 1 1 x x x x x -:vand|= Vd5,qv0809,rx5 EndPacket is iclass=0x1 & op2127=0x4b & op13=0x1 & op10=0x1 & op0507=0x3 & Vd5 & vs5 & qv0809 & rx5 & $(END_PACKET) { - Vd5 = V_vandor_VQR(vs5,~qv0809,rx5); +:vand|= Vd5,Qv0809Not,rx5 EndPacket is iclass=0x1 & op2127=0x4b & op13=0x1 & op10=0x1 & op0507=0x3 & Vd5 & vs5 & Qv0809Not & rx5 & $(END_PACKET) { + Vd5 = V_vandor_VQR(vs5,Qv0809Not,rx5); build EndPacket; } -# (hvx,1) vand -- "Vd=vand(Qu4,Rt)" +# (v60,1) vand -- "Vd=vand(Qu4,Rt)" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| # 0 0 0 1 1 0 0 1 1 0 1 t t t t t P P 0 - - 0 u u 1 0 1 d d d d d @@ -4541,17 +4796,17 @@ define pcodeop V_vand_QR; build EndPacket; } -# (hvx,1) vand -- "Vd=vand(!Qu4,Rt)" +# (v60,1) vand -- "Vd=vand(!Qu4,Rt)" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| # 0 0 0 1 1 0 0 1 1 0 1 t t t t t P P 0 - - 1 u u 1 0 1 d d d d d -:vand Vd5,qv0809,rx5 EndPacket is iclass=0x1 & op2127=0x4d & op13=0x0 & op10=0x1 & op0507=0x5 & Vd5 & qv0809 & rx5 & $(END_PACKET) { - Vd5 = V_vand_QR(~qv0809,rx5); +:vand Vd5,Qv0809Not,rx5 EndPacket is iclass=0x1 & op2127=0x4d & op13=0x0 & op10=0x1 & op0507=0x5 & Vd5 & Qv0809Not & rx5 & $(END_PACKET) { + Vd5 = V_vand_QR(Qv0809Not,rx5); build EndPacket; } -# (hvx,1) vabsdiff -- "Vd.ub=vabsdiff(Vu.ub,Vv.ub)" +# (v60,1) vabsdiff -- "Vd.ub=vabsdiff(Vu.ub,Vv.ub)" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| # 0 0 0 1 1 1 0 0 1 1 0 v v v v v P P 0 u u u u u 0 0 0 d d d d d @@ -4563,7 +4818,7 @@ define pcodeop Vub_vabsdiff_VubVub; build EndPacket; } -# (hvx,1) vabsdiff -- "Vd.uh=vabsdiff(Vu.h,Vv.h)" +# (v60,1) vabsdiff -- "Vd.uh=vabsdiff(Vu.h,Vv.h)" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| # 0 0 0 1 1 1 0 0 1 1 0 v v v v v P P 0 u u u u u 0 0 1 d d d d d @@ -4575,7 +4830,7 @@ define pcodeop Vuh_vabsdiff_VhVh; build EndPacket; } -# (hvx,1) vabsdiff -- "Vd.uh=vabsdiff(Vu.uh,Vv.uh)" +# (v60,1) vabsdiff -- "Vd.uh=vabsdiff(Vu.uh,Vv.uh)" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| # 0 0 0 1 1 1 0 0 1 1 0 v v v v v P P 0 u u u u u 0 1 0 d d d d d @@ -4587,7 +4842,7 @@ define pcodeop Vuh_vabsdiff_VuhVuh; build EndPacket; } -# (hvx,1) vabsdiff -- "Vd.uw=vabsdiff(Vu.w,Vv.w)" +# (v60,1) vabsdiff -- "Vd.uw=vabsdiff(Vu.w,Vv.w)" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| # 0 0 0 1 1 1 0 0 1 1 0 v v v v v P P 0 u u u u u 0 1 1 d d d d d @@ -4599,7 +4854,7 @@ define pcodeop Vuw_vabsdiff_VwVw; build EndPacket; } -# (hvx,1) vinsert -- "Vx.w=vinsert(Rt)" +# (v60,1) vinsert -- "Vx.w=vinsert(Rt)" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| # 0 0 0 1 1 0 0 1 1 0 1 t t t t t P P 1 - - - - - 0 0 1 x x x x x @@ -4611,7 +4866,7 @@ define pcodeop vinsert_VwR; build EndPacket; } -# (hvx,1) vror -- "Vd=vror(Vu,Rt)" +# (v60,1) vror -- "Vd=vror(Vu,Rt)" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| # 0 0 0 1 1 0 0 1 0 1 1 t t t t t P P 0 u u u u u 0 0 1 d d d d d @@ -4623,7 +4878,7 @@ define pcodeop vror_VR; build EndPacket; } -# (hvx,1) valign -- "Vd=valign(Vu,Vv,Rt)" +# (v60,1) valign -- "Vd=valign(Vu,Vv,Rt)" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| # 0 0 0 1 1 0 1 1 v v v v v t t t P P 0 u u u u u 0 0 0 d d d d d @@ -4635,7 +4890,7 @@ define pcodeop valign_VVR; build EndPacket; } -# (hvx,1) vlalign -- "Vd=vlalign(Vu,Vv,Rt)" +# (v60,1) vlalign -- "Vd=vlalign(Vu,Vv,Rt)" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| # 0 0 0 1 1 0 1 1 v v v v v t t t P P 0 u u u u u 0 0 1 d d d d d @@ -4647,7 +4902,7 @@ define pcodeop vlalign_VVR; build EndPacket; } -# (hvx,1) valign -- "Vd=valign(Vu,Vv,#u3)" +# (v60,1) valign -- "Vd=valign(Vu,Vv,#u3)" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| # 0 0 0 1 1 1 1 0 0 0 1 v v v v v P P 1 u u u u u i i i d d d d d @@ -4659,7 +4914,7 @@ define pcodeop V_valign_VVI; build EndPacket; } -# (hvx,1) vlalign -- "Vd=vlalign(Vu,Vv,#u3)" +# (v60,1) vlalign -- "Vd=vlalign(Vu,Vv,#u3)" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| # 0 0 0 1 1 1 1 0 0 1 1 v v v v v P P 1 u u u u u i i i d d d d d @@ -4671,7 +4926,7 @@ define pcodeop V_vlalign_VVI; build EndPacket; } -# (hvx,1) vdelta -- "Vd=vdelta(Vu,Vv)" +# (v60,1) vdelta -- "Vd=vdelta(Vu,Vv)" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| # 0 0 0 1 1 1 1 1 0 0 1 v v v v v P P 0 u u u u u 0 0 1 d d d d d @@ -4683,7 +4938,7 @@ define pcodeop vdelta_VV; build EndPacket; } -# (hvx,1) vrdelta -- "Vd=vrdelta(Vu,Vv)" +# (v60,1) vrdelta -- "Vd=vrdelta(Vu,Vv)" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| # 0 0 0 1 1 1 1 1 0 0 1 v v v v v P P 0 u u u u u 0 1 1 d d d d d @@ -4695,7 +4950,7 @@ define pcodeop vrdelta_VV; build EndPacket; } -# (hvx,1) vdeal -- "Vd.h=vdeal(Vu.h)" +# (v60,1) vdeal -- "Vd.h=vdeal(Vu.h)" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| # 0 0 0 1 1 1 1 0 - - 0 - - - 0 0 P P 0 u u u u u 1 1 0 d d d d d @@ -4707,7 +4962,7 @@ define pcodeop vdeal_Vh; build EndPacket; } -# (hvx,1) vdeal -- "Vd.b=vdeal(Vu.b)" +# (v60,1) vdeal -- "Vd.b=vdeal(Vu.b)" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| # 0 0 0 1 1 1 1 0 - - 0 - - - 0 0 P P 0 u u u u u 1 1 1 d d d d d @@ -4719,7 +4974,7 @@ define pcodeop vdeal_Vb; build EndPacket; } -# (hvx,1) vshuff -- "Vd.h=vshuff(Vu.h)" +# (v60,1) vshuff -- "Vd.h=vshuff(Vu.h)" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| # 0 0 0 1 1 1 1 0 - - 0 - - - 0 1 P P 0 u u u u u 1 1 1 d d d d d @@ -4731,7 +4986,7 @@ define pcodeop vshuff_Vh; build EndPacket; } -# (hvx,1) vshuff -- "Vd.b=vshuff(Vu.b)" +# (v60,1) vshuff -- "Vd.b=vshuff(Vu.b)" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| # 0 0 0 1 1 1 1 0 - - 0 - - - 1 0 P P 0 u u u u u 0 0 0 d d d d d @@ -4743,7 +4998,7 @@ define pcodeop vshuff_Vb; build EndPacket; } -# (hvx,1) vdeale -- "Vd.b=vdeale(Vu.b,Vv.b)" +# (v60,1) vdeale -- "Vd.b=vdeale(Vu.b,Vv.b)" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| # 0 0 0 1 1 1 1 1 0 0 1 v v v v v P P 0 u u u u u 1 1 1 d d d d d @@ -4755,7 +5010,7 @@ define pcodeop vdeale_VbVb; build EndPacket; } -# (hvx,1) vpacke -- "Vd.b=vpacke(Vu.h,Vv.h)" +# (v60,1) vpacke -- "Vd.b=vpacke(Vu.h,Vv.h)" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| # 0 0 0 1 1 1 1 1 1 1 0 v v v v v P P 0 u u u u u 0 1 0 d d d d d @@ -4767,7 +5022,7 @@ define pcodeop Vb_vpacke_VhVh; build EndPacket; } -# (hvx,1) vpacke -- "Vd.h=vpacke(Vu.w,Vv.w)" +# (v60,1) vpacke -- "Vd.h=vpacke(Vu.w,Vv.w)" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| # 0 0 0 1 1 1 1 1 1 1 0 v v v v v P P 0 u u u u u 0 1 1 d d d d d @@ -4779,7 +5034,7 @@ define pcodeop Vh_vpacke_VwVw; build EndPacket; } -# (hvx,1) vpack -- "Vd.ub=vpack(Vu.h,Vv.h):sat" +# (v60,1) vpack -- "Vd.ub=vpack(Vu.h,Vv.h):sat" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| # 0 0 0 1 1 1 1 1 1 1 0 v v v v v P P 0 u u u u u 1 0 1 d d d d d @@ -4791,7 +5046,7 @@ define pcodeop Vb_vpack_VhVh_sat; build EndPacket; } -# (hvx,1) vpack -- "Vd.b=vpack(Vu.h,Vv.h):sat" +# (v60,1) vpack -- "Vd.b=vpack(Vu.h,Vv.h):sat" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| # 0 0 0 1 1 1 1 1 1 1 0 v v v v v P P 0 u u u u u 1 1 0 d d d d d @@ -4803,7 +5058,7 @@ define pcodeop Vb_vpacko_VhVh_sat; build EndPacket; } -# (hvx,1) vpack -- "Vd.uh=vpack(Vu.w,Vv.w):sat" +# (v60,1) vpack -- "Vd.uh=vpack(Vu.w,Vv.w):sat" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| # 0 0 0 1 1 1 1 1 1 1 0 v v v v v P P 0 u u u u u 1 1 1 d d d d d @@ -4815,7 +5070,7 @@ define pcodeop Vuh_vpack_VwVw_sat; build EndPacket; } -# (hvx,1) vpack -- "Vd.h=vpack(Vu.w,Vv.w):sat" +# (v60,1) vpack -- "Vd.h=vpack(Vu.w,Vv.w):sat" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| # 0 0 0 1 1 1 1 1 1 1 1 v v v v v P P 0 u u u u u 0 0 0 d d d d d @@ -4827,7 +5082,7 @@ define pcodeop Vh_vpack_VwVw_sat; build EndPacket; } -# (hvx,1) vpacko -- "Vd.b=vpacko(Vu.h,Vv.h)" +# (v60,1) vpacko -- "Vd.b=vpacko(Vu.h,Vv.h)" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| # 0 0 0 1 1 1 1 1 1 1 1 v v v v v P P 0 u u u u u 0 0 1 d d d d d @@ -4839,7 +5094,7 @@ define pcodeop Vb_vpacko_VhVh; build EndPacket; } -# (hvx,1) vpacko -- "Vd.h=vpacko(Vu.w,Vv.w)" +# (v60,1) vpacko -- "Vd.h=vpacko(Vu.w,Vv.w)" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| # 0 0 0 1 1 1 1 1 1 1 1 v v v v v P P 0 u u u u u 0 1 0 d d d d d @@ -4851,7 +5106,7 @@ define pcodeop Vh_vpacko_VwVw; build EndPacket; } -# (hvx,1) vsetq -- "Qd4=vsetq(Rt)" +# (v60,1) vsetq -- "Qd4=vsetq(Rt)" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| # 0 0 0 1 1 0 0 1 1 0 1 t t t t t P P 0 - - - - - 0 1 0 - 0 1 d d @@ -4863,7 +5118,7 @@ define pcodeop Q_vsetq_R; build EndPacket; } -# (hvx,1) vsetq2 -- "Qd4=vsetq2(Rt)" +# (v60,1) vsetq2 -- "Qd4=vsetq2(Rt)" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| # 0 0 0 1 1 0 0 1 1 0 1 t t t t t P P 0 - - - - - 0 1 0 - 1 1 d d @@ -4875,7 +5130,7 @@ define pcodeop Q_vsetq2_R; build EndPacket; } -# (hvx,1) vlut32 -- "Vd.b=vlut32(Vu.b,Vv.b,Rt):nomatch" +# (v60,1) vlut32 -- "Vd.b=vlut32(Vu.b,Vv.b,Rt):nomatch" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| # 0 0 0 1 1 0 0 0 v v v v v t t t P P 0 u u u u u 0 1 1 d d d d d @@ -4887,7 +5142,7 @@ define pcodeop Vb_vlut32_VbVbR_nomatch; build EndPacket; } -# (hvx,1) vlut32 -- "Vd.b=vlut32(Vu.b,Vv.b,Rt)" +# (v60,1) vlut32 -- "Vd.b=vlut32(Vu.b,Vv.b,Rt)" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| # 0 0 0 1 1 0 1 1 v v v v v t t t P P 1 u u u u u 0 0 1 d d d d d @@ -4899,7 +5154,7 @@ define pcodeop Vb_vlut32_VbVbR; build EndPacket; } -# (hvx,1) vlut32 -- "Vd.b=vlut32(Vu.b,Vv.b,#u3)" +# (v60,1) vlut32 -- "Vd.b=vlut32(Vu.b,Vv.b,#u3)" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| # 0 0 0 1 1 1 1 0 0 0 1 v v v v v P P 0 u u u u u i i i d d d d d @@ -4911,19 +5166,19 @@ define pcodeop Vb_vlut32_VbVbI; build EndPacket; } -# (hvx,1) vasrinto -- "Vxx.w=vasrinto(Vu.w,Vv.w)" +# (v60,1) vasrinto -- "Vxx.w=vasrinto(Vu.w,Vv.w)" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| # 0 0 0 1 1 0 1 0 1 0 1 v v v v v P P 1 u u u u u 1 1 1 x x x x x define pcodeop vasrinto_WwVwVw; -:vasrinto VddW_0004,VuW_0812,VvW_1620 EndPacket is iclass=0x1 & op2127=0x55 & op13=0x1 & op0507=0x7 & vss5 & VddW_0004 & VuW_0812 & VvW_1620 & $(END_PACKET) { - VddW_0004 = vasrinto_WwVwVw(vss5,VuW_0812,VvW_1620); +:vasrinto VddW_0004,VuW_0812,VvW_1620 EndPacket is iclass=0x1 & op2127=0x55 & op13=0x1 & op0507=0x7 & Vss_0004 & VddW_0004 & VuW_0812 & VvW_1620 & $(END_PACKET) { + VddW_0004 = vasrinto_WwVwVw(Vss_0004,VuW_0812,VvW_1620); build EndPacket; } -# (hvx,1) vshuff -- "vshuff(Vy,Vx,Rt)" +# (v60,1) vshuff -- "vshuff(Vy,Vx,Rt)" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| # 0 0 0 1 1 0 0 1 1 1 1 t t t t t P P 1 y y y y y 0 0 1 x x x x x @@ -4940,7 +5195,7 @@ define pcodeop vshuff_VwVwR; vs5 = pair:$(HVX_VECTOR_SIZE); } -# (hvx,1) vdeal -- "vdeal(Vy,Vx,Rt)" +# (v60,1) vdeal -- "vdeal(Vy,Vx,Rt)" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| # 0 0 0 1 1 0 0 1 1 1 1 t t t t t P P 1 y y y y y 0 1 0 x x x x x @@ -4957,7 +5212,7 @@ define pcodeop vdeal_VwVwR; vs5 = pair:$(HVX_VECTOR_SIZE); } -# (hvx,1) vshuff -- "Vdd=vshuff(Vu,Vv,Rt)" +# (v60,1) vshuff -- "Vdd=vshuff(Vu,Vv,Rt)" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| # 0 0 0 1 1 0 1 1 v v v v v t t t P P 1 u u u u u 0 1 1 d d d d d @@ -4967,7 +5222,7 @@ define pcodeop vdeal_VwVwR; build EndPacket; } -# (hvx,1) vdeal -- "Vdd=vdeal(Vu,Vv,Rt)" +# (v60,1) vdeal -- "Vdd=vdeal(Vu,Vv,Rt)" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| # 0 0 0 1 1 0 1 1 v v v v v t t t P P 1 u u u u u 1 0 0 d d d d d @@ -4977,19 +5232,19 @@ define pcodeop vdeal_VwVwR; build EndPacket; } -# (hvx,1) vlut16 -- "Vdd.h=vlut16(Vu.b,Vv.h,Rt):nomatch" +# (v60,1) vlut16 -- "Vdd.h=vlut16(Vu.b,Vv.h,Rt):nomatch" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| # 0 0 0 1 1 0 0 0 v v v v v t t t P P 0 u u u u u 1 0 0 d d d d d define pcodeop vlut16_VbVhR_nomatch; -:vlut16^":nomatch" VddH_0004,VuB_0812,VzH_1923,rt1618 EndPacket is iclass=0x1 & op2427=0x8 & op13=0x0 & op0507=0x4 & vss5 & VddH_0004 & VuB_0812 & VzH_1923 & rt1618 & $(END_PACKET) { - VddH_0004 = vlut16_VbVhR_nomatch(vss5,VuB_0812,VzH_1923,rt1618); +:vlut16^":nomatch" VddH_0004,VuB_0812,VzH_1923,rt1618 EndPacket is iclass=0x1 & op2427=0x8 & op13=0x0 & op0507=0x4 & Vss_0004 & VddH_0004 & VuB_0812 & VzH_1923 & rt1618 & $(END_PACKET) { + VddH_0004 = vlut16_VbVhR_nomatch(Vss_0004,VuB_0812,VzH_1923,rt1618); build EndPacket; } -# (hvx,1) vlut32 -- "Vx.b|=vlut32(Vu.b,Vv.b,Rt)" +# (v60,1) vlut32 -- "Vx.b|=vlut32(Vu.b,Vv.b,Rt)" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| # 0 0 0 1 1 0 1 1 v v v v v t t t P P 1 u u u u u 1 0 1 x x x x x @@ -5001,7 +5256,7 @@ define pcodeop vlut32or_VbVbVbR; build EndPacket; } -# (hvx,1) vlut16 -- "Vdd.h=vlut16(Vu.b,Vv.h,Rt)" +# (v60,1) vlut16 -- "Vdd.h=vlut16(Vu.b,Vv.h,Rt)" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| # 0 0 0 1 1 0 1 1 v v v v v t t t P P 1 u u u u u 1 1 0 d d d d d @@ -5013,19 +5268,19 @@ define pcodeop vlut16_VbVhR; build EndPacket; } -# (hvx,1) vlut16 -- "Vxx.h|=vlut16(Vu.b,Vv.h,Rt)" +# (v60,1) vlut16 -- "Vxx.h|=vlut16(Vu.b,Vv.h,Rt)" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| # 0 0 0 1 1 0 1 1 v v v v v t t t P P 1 u u u u u 1 1 1 x x x x x define pcodeop vlut16or_WhVbVhR; -:vlut16|= VddH_0004,VuB_0812,VzH_1923,rt1618 EndPacket is iclass=0x1 & op2427=0xb & op13=0x1 & op0507=0x7 & vss5 & VddH_0004 & VuB_0812 & VzH_1923 & rt1618 & $(END_PACKET) { - VddH_0004 = vlut16or_WhVbVhR(vss5,VuB_0812,VzH_1923,rt1618); +:vlut16|= VddH_0004,VuB_0812,VzH_1923,rt1618 EndPacket is iclass=0x1 & op2427=0xb & op13=0x1 & op0507=0x7 & Vss_0004 & VddH_0004 & VuB_0812 & VzH_1923 & rt1618 & $(END_PACKET) { + VddH_0004 = vlut16or_WhVbVhR(Vss_0004,VuB_0812,VzH_1923,rt1618); build EndPacket; } -# (hvx,1) vlut32 -- "Vx.b|=vlut32(Vu.b,Vv.b,#u3)" +# (v60,1) vlut32 -- "Vx.b|=vlut32(Vu.b,Vv.b,#u3)" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| # 0 0 0 1 1 1 0 0 1 1 0 v v v v v P P 1 u u u u u i i i x x x x x @@ -5037,31 +5292,31 @@ define pcodeop vlut32or_VbVbVbI; build EndPacket; } -# (hvx,1) vlut16 -- "Vxx.h|=vlut16(Vu.b,Vv.h,#u3)" +# (v60,1) vlut16 -- "Vxx.h|=vlut16(Vu.b,Vv.h,#u3)" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| # 0 0 0 1 1 1 0 0 1 1 1 v v v v v P P 1 u u u u u i i i x x x x x define pcodeop vlut16or_WhVbVhI; -:vlut16|= VddH_0004,VuB_0812,VvH_1620,Uimm8_0507 EndPacket is iclass=0x1 & op2127=0x67 & op13=0x1 & vss5 & VddH_0004 & VuB_0812 & VvH_1620 & Uimm8_0507 & $(END_PACKET) { - VddH_0004 = vlut16or_WhVbVhI(vss5,VuB_0812,VvH_1620,Uimm8_0507); +:vlut16|= VddH_0004,VuB_0812,VvH_1620,Uimm8_0507 EndPacket is iclass=0x1 & op2127=0x67 & op13=0x1 & Vss_0004 & VddH_0004 & VuB_0812 & VvH_1620 & Uimm8_0507 & $(END_PACKET) { + VddH_0004 = vlut16or_WhVbVhI(Vss_0004,VuB_0812,VvH_1620,Uimm8_0507); build EndPacket; } -# (hvx,1) vlut16 -- "Vdd.h=vlut16(Vu.b,Vv.h,#u3)" +# (v60,1) vlut16 -- "Vdd.h=vlut16(Vu.b,Vv.h,#u3)" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| # 0 0 0 1 1 1 1 0 0 1 1 v v v v v P P 0 u u u u u i i i d d d d d define pcodeop vlut16_VbVhI; -:vlut16 VddH_0004,VuB_0812,VvH_1620,Uimm8_0507 EndPacket is iclass=0x1 & op2127=0x73 & op13=0x0 & vss5 & VddH_0004 & VuB_0812 & VvH_1620 & Uimm8_0507 & $(END_PACKET) { - VddH_0004 = vlut16_VbVhI(vss5,VuB_0812,VvH_1620,Uimm8_0507); +:vlut16 VddH_0004,VuB_0812,VvH_1620,Uimm8_0507 EndPacket is iclass=0x1 & op2127=0x73 & op13=0x0 & Vss_0004 & VddH_0004 & VuB_0812 & VvH_1620 & Uimm8_0507 & $(END_PACKET) { + VddH_0004 = vlut16_VbVhI(Vss_0004,VuB_0812,VvH_1620,Uimm8_0507); build EndPacket; } -# (hvx,1) vunpack -- "Vdd.uh=vunpack(Vu.ub)" +# (v60,1) vunpack -- "Vdd.uh=vunpack(Vu.ub)" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| # 0 0 0 1 1 1 1 0 - - 0 - - - 0 1 P P 0 u u u u u 0 0 0 d d d d d @@ -5073,7 +5328,7 @@ define pcodeop Wuh_vunpack_Vub; build EndPacket; } -# (hvx,1) vunpack -- "Vdd.uw=vunpack(Vu.uh)" +# (v60,1) vunpack -- "Vdd.uw=vunpack(Vu.uh)" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| # 0 0 0 1 1 1 1 0 - - 0 - - - 0 1 P P 0 u u u u u 0 0 1 d d d d d @@ -5085,7 +5340,7 @@ define pcodeop Wuw_vunpack_Vuh; build EndPacket; } -# (hvx,1) vunpack -- "Vdd.h=vunpack(Vu.b)" +# (v60,1) vunpack -- "Vdd.h=vunpack(Vu.b)" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| # 0 0 0 1 1 1 1 0 - - 0 - - - 0 1 P P 0 u u u u u 0 1 0 d d d d d @@ -5097,7 +5352,7 @@ define pcodeop Wh_vunpack_Vb; build EndPacket; } -# (hvx,1) vunpack -- "Vdd.w=vunpack(Vu.h)" +# (v60,1) vunpack -- "Vdd.w=vunpack(Vu.h)" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| # 0 0 0 1 1 1 1 0 - - 0 - - - 0 1 P P 0 u u u u u 0 1 1 d d d d d @@ -5109,31 +5364,31 @@ define pcodeop Ww_vunpack_Vh; build EndPacket; } -# (hvx,1) vunpacko -- "Vxx.h|=vunpacko(Vu.b)" +# (v60,1) vunpacko -- "Vxx.h|=vunpacko(Vu.b)" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| # 0 0 0 1 1 1 1 0 - - 0 - - 0 0 0 P P 1 u u u u u 0 0 0 x x x x x define pcodeop vunpackoor_WhVb; -:vunpacko|= VddH_0004,VuB_0812 EndPacket is iclass=0x1 & op2427=0xe & op21=0x0 & op18=0x0 & op1617=0x0 & op13=0x1 & op0507=0x0 & vss5 & VddH_0004 & VuB_0812 & $(END_PACKET) { - VddH_0004 = vunpackoor_WhVb(vss5,VuB_0812); +:vunpacko|= VddH_0004,VuB_0812 EndPacket is iclass=0x1 & op2427=0xe & op21=0x0 & op18=0x0 & op1617=0x0 & op13=0x1 & op0507=0x0 & Vss_0004 & VddH_0004 & VuB_0812 & $(END_PACKET) { + VddH_0004 = vunpackoor_WhVb(Vss_0004,VuB_0812); build EndPacket; } -# (hvx,1) vunpacko -- "Vxx.w|=vunpacko(Vu.h)" +# (v60,1) vunpacko -- "Vxx.w|=vunpacko(Vu.h)" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| # 0 0 0 1 1 1 1 0 - - 0 - - 0 0 0 P P 1 u u u u u 0 0 1 x x x x x define pcodeop vunpackoor_WwVh; -:vunpacko|= VddW_0004,VuH_0812 EndPacket is iclass=0x1 & op2427=0xe & op21=0x0 & op18=0x0 & op1617=0x0 & op13=0x1 & op0507=0x1 & vss5 & VddW_0004 & VuH_0812 & $(END_PACKET) { - VddW_0004 = vunpackoor_WwVh(vss5,VuH_0812); +:vunpacko|= VddW_0004,VuH_0812 EndPacket is iclass=0x1 & op2427=0xe & op21=0x0 & op18=0x0 & op1617=0x0 & op13=0x1 & op0507=0x1 & Vss_0004 & VddW_0004 & VuH_0812 & $(END_PACKET) { + VddW_0004 = vunpackoor_WwVh(Vss_0004,VuH_0812); build EndPacket; } -# (hvx,2) "vscatter(Rt,Mu,Vvv.w).h=Vw32" +# (v60,2) "vscatter(Rt,Mu,Vvv.w).h=Vw32" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| # 0 0 1 0 1 1 1 1 0 0 1 t t t t t P P u v v v v v 0 1 0 w w w w w @@ -5146,7 +5401,7 @@ define pcodeop vscatter_RMWwV; build EndPacket; } -# (hvx,2) "vscatter(Rt,Mu,Vvv.w).h+=Vw32" +# (v60,2) "vscatter(Rt,Mu,Vvv.w).h+=Vw32" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| # 0 0 1 0 1 1 1 1 0 0 1 t t t t t P P u v v v v v 1 1 0 w w w w w @@ -5159,7 +5414,7 @@ define pcodeop vscatteracc_RMWwV; build EndPacket; } -# (hvx,2) "if (Qs4) vscatter(Rt,Mu,Vvv.w).h=Vw32" +# (v60,2) "if (Qs4) vscatter(Rt,Mu,Vvv.w).h=Vw32" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| # 0 0 1 0 1 1 1 1 1 0 1 t t t t t P P u v v v v v 0 s s w w w w w @@ -5172,7 +5427,7 @@ define pcodeop vscatter_QRMWwV; build EndPacket; } -# (hvx,2) "vscatter(Rt,Mu,Vv.w).w=Vw32" +# (v60,2) "vscatter(Rt,Mu,Vv.w).w=Vw32" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| # 0 0 1 0 1 1 1 1 0 0 1 t t t t t P P u v v v v v 0 0 0 w w w w w @@ -5185,7 +5440,7 @@ define pcodeop vscatter_RMVwV; build EndPacket; } -# (hvx,2) "vscatter(Rt,Mu,Vv.h).h=Vw32" +# (v60,2) "vscatter(Rt,Mu,Vv.h).h=Vw32" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| # 0 0 1 0 1 1 1 1 0 0 1 t t t t t P P u v v v v v 0 0 1 w w w w w @@ -5198,7 +5453,7 @@ define pcodeop vscatter_RMVhV; build EndPacket; } -# (hvx,2) "vscatter(Rt,Mu,Vv.w).w+=Vw32" +# (v60,2) "vscatter(Rt,Mu,Vv.w).w+=Vw32" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| # 0 0 1 0 1 1 1 1 0 0 1 t t t t t P P u v v v v v 1 0 0 w w w w w @@ -5211,7 +5466,7 @@ define pcodeop vscatteracc_RMVwV; build EndPacket; } -# (hvx,2) "vscatter(Rt,Mu,Vv.h).h+=Vw32" +# (v60,2) "vscatter(Rt,Mu,Vv.h).h+=Vw32" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| # 0 0 1 0 1 1 1 1 0 0 1 t t t t t P P u v v v v v 1 0 1 w w w w w @@ -5224,7 +5479,7 @@ define pcodeop vscatteracc_RMVhV; build EndPacket; } -# (hvx,2) "if (Qs4) vscatter(Rt,Mu,Vv.w).w=Vw32" +# (v60,2) "if (Qs4) vscatter(Rt,Mu,Vv.w).w=Vw32" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| # 0 0 1 0 1 1 1 1 1 0 0 t t t t t P P u v v v v v 0 s s w w w w w @@ -5237,7 +5492,7 @@ define pcodeop vscatter_QRMVwV; build EndPacket; } -# (hvx,2) "if (Qs4) vscatter(Rt,Mu,Vv.h).h=Vw32" +# (v60,2) "if (Qs4) vscatter(Rt,Mu,Vv.h).h=Vw32" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| # 0 0 1 0 1 1 1 1 1 0 0 t t t t t P P u v v v v v 1 s s w w w w w @@ -5250,7 +5505,7 @@ define pcodeop vscatter_QRMVhV; build EndPacket; } -# (hvx,1) vasr -- "Vd.b=vasr(Vu.h,Vv.h,Rt):sat" +# (v60,1) vasr -- "Vd.b=vasr(Vu.h,Vv.h,Rt):sat" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| # 0 0 0 1 1 0 0 0 v v v v v t t t P P 0 u u u u u 0 0 0 d d d d d @@ -5262,7 +5517,7 @@ define pcodeop Vb_vasr_VhVhR_sat; build EndPacket; } -# (hvx,1) vasr -- "Vd.uh=vasr(Vu.uw,Vv.uw,Rt):rnd:sat" +# (v60,1) vasr -- "Vd.uh=vasr(Vu.uw,Vv.uw,Rt):rnd:sat" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| # 0 0 0 1 1 0 0 0 v v v v v t t t P P 0 u u u u u 0 0 1 d d d d d @@ -5274,7 +5529,7 @@ define pcodeop vasr_VhVhR_rnd_sat; build EndPacket; } -# (hvx,1) vasr -- "Vd.uh=vasr(Vu.w,Vv.w,Rt):rnd:sat" +# (v60,1) vasr -- "Vd.uh=vasr(Vu.w,Vv.w,Rt):rnd:sat" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| # 0 0 0 1 1 0 0 0 v v v v v t t t P P 0 u u u u u 0 1 0 d d d d d @@ -5286,7 +5541,7 @@ define pcodeop Vuh_vasr_VwVwR_rnd_sat; build EndPacket; } -# (hvx,1) vasr -- "Vd.ub=vasr(Vu.uh,Vv.uh,Rt):rnd:sat" +# (v60,1) vasr -- "Vd.ub=vasr(Vu.uh,Vv.uh,Rt):rnd:sat" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| # 0 0 0 1 1 0 0 0 v v v v v t t t P P 0 u u u u u 1 1 1 d d d d d @@ -5298,7 +5553,7 @@ define pcodeop Vub_vasr_VuhVuhR_rnd_sat; build EndPacket; } -# (hvx,1) vasr -- "Vd.uh=vasr(Vu.uw,Vv.uw,Rt):sat" +# (v60,1) vasr -- "Vd.uh=vasr(Vu.uw,Vv.uw,Rt):sat" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| # 0 0 0 1 1 0 0 0 v v v v v t t t P P 1 u u u u u 1 0 0 d d d d d @@ -5310,7 +5565,7 @@ define pcodeop Vuh_vasr_VuwVuwR_sat; build EndPacket; } -# (hvx,1) vasr -- "Vd.ub=vasr(Vu.uh,Vv.uh,Rt):sat" +# (v60,1) vasr -- "Vd.ub=vasr(Vu.uh,Vv.uh,Rt):sat" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| # 0 0 0 1 1 0 0 0 v v v v v t t t P P 1 u u u u u 1 0 1 d d d d d @@ -5322,7 +5577,7 @@ define pcodeop Vub_vasr_VuhVuhR_sat; build EndPacket; } -# (hvx,1) vasr -- "Vd.h=vasr(Vu.w,Vv.w,Rt)" +# (v60,1) vasr -- "Vd.h=vasr(Vu.w,Vv.w,Rt)" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| # 0 0 0 1 1 0 1 1 v v v v v t t t P P 0 u u u u u 0 1 0 d d d d d @@ -5334,7 +5589,7 @@ define pcodeop Vh_vasr_VwVwR; build EndPacket; } -# (hvx,1) vasr -- "Vd.h=vasr(Vu.w,Vv.w,Rt):sat" +# (v60,1) vasr -- "Vd.h=vasr(Vu.w,Vv.w,Rt):sat" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| # 0 0 0 1 1 0 1 1 v v v v v t t t P P 0 u u u u u 0 1 1 d d d d d @@ -5346,7 +5601,7 @@ define pcodeop Vh_vasr_VwVwR_sat; build EndPacket; } -# (hvx,1) vasr -- "Vd.h=vasr(Vu.w,Vv.w,Rt):rnd:sat" +# (v60,1) vasr -- "Vd.h=vasr(Vu.w,Vv.w,Rt):rnd:sat" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| # 0 0 0 1 1 0 1 1 v v v v v t t t P P 0 u u u u u 1 0 0 d d d d d @@ -5358,7 +5613,7 @@ define pcodeop Vh_vasr_VwVwR_rnd_sat; build EndPacket; } -# (hvx,1) vasr -- "Vd.uh=vasr(Vu.w,Vv.w,Rt):sat" +# (v60,1) vasr -- "Vd.uh=vasr(Vu.w,Vv.w,Rt):sat" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| # 0 0 0 1 1 0 1 1 v v v v v t t t P P 0 u u u u u 1 0 1 d d d d d @@ -5370,7 +5625,7 @@ define pcodeop Vuh_vasr_VwVwR_sat; build EndPacket; } -# (hvx,1) vasr -- "Vd.ub=vasr(Vu.h,Vv.h,Rt):sat" +# (v60,1) vasr -- "Vd.ub=vasr(Vu.h,Vv.h,Rt):sat" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| # 0 0 0 1 1 0 1 1 v v v v v t t t P P 0 u u u u u 1 1 0 d d d d d @@ -5382,7 +5637,7 @@ define pcodeop Vub_vasr_VhVhR_sat; build EndPacket; } -# (hvx,1) vasr -- "Vd.ub=vasr(Vu.h,Vv.h,Rt):rnd:sat" +# (v60,1) vasr -- "Vd.ub=vasr(Vu.h,Vv.h,Rt):rnd:sat" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| # 0 0 0 1 1 0 1 1 v v v v v t t t P P 0 u u u u u 1 1 1 d d d d d @@ -5394,7 +5649,7 @@ define pcodeop Vub_vasr_VhVhR_rnd_sat; build EndPacket; } -# (hvx,1) vasr -- "Vd.b=vasr(Vu.h,Vv.h,Rt):rnd:sat" +# (v60,1) vasr -- "Vd.b=vasr(Vu.h,Vv.h,Rt):rnd:sat" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| # 0 0 0 1 1 0 1 1 v v v v v t t t P P 1 u u u u u 0 0 0 d d d d d @@ -5406,7 +5661,7 @@ define pcodeop Vb_vasr_VhVhR_rnd_sat; build EndPacket; } -# (hvx,1) prefixsum -- "Vd.b=prefixsum(Qv4)" +# (v60,1) prefixsum -- "Vd.b=prefixsum(Qv4)" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| # 0 0 0 1 1 1 1 0 v v 0 - - 0 1 1 P P 1 - - 0 0 0 0 1 0 d d d d d @@ -5418,7 +5673,7 @@ define pcodeop Vb_prefixsum_Q; build EndPacket; } -# (hvx,1) prefixsum -- "Vd.h=prefixsum(Qv4)" +# (v60,1) prefixsum -- "Vd.h=prefixsum(Qv4)" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| # 0 0 0 1 1 1 1 0 v v 0 - - 0 1 1 P P 1 - - 0 0 1 0 1 0 d d d d d @@ -5430,7 +5685,7 @@ define pcodeop Vh_prefixsum_Q; build EndPacket; } -# (hvx,1) prefixsum -- "Vd.w=prefixsum(Qv4)" +# (v60,1) prefixsum -- "Vd.w=prefixsum(Qv4)" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| # 0 0 0 1 1 1 1 0 v v 0 - - 0 1 1 P P 1 - - 0 1 0 0 1 0 d d d d d @@ -5442,7 +5697,7 @@ define pcodeop Vw_prefixsum_Q; build EndPacket; } -# (hvx,1) vadd -- "Vd.qf16=vadd(Vu.qf16,Vv.qf16)" +# (v60,1) vadd -- "Vd.qf16=vadd(Vu.qf16,Vv.qf16)" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| # 0 0 0 1 1 1 1 1 0 1 1 v v v v v P P 1 u u u u u 0 1 0 d d d d d @@ -5454,7 +5709,7 @@ define pcodeop Vqf16_vadd_Vqf16Vqf16; build EndPacket; } -# (hvx,1) vadd -- "Vd.qf16=vadd(Vu.hf,Vv.hf)" +# (v60,1) vadd -- "Vd.qf16=vadd(Vu.hf,Vv.hf)" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| # 0 0 0 1 1 1 1 1 0 1 1 v v v v v P P 1 u u u u u 0 1 1 d d d d d @@ -5466,7 +5721,7 @@ define pcodeop Vqf16_vadd_VhfVhf; build EndPacket; } -# (hvx,1) vadd -- "Vd.qf16=vadd(Vu.qf16,Vv.hf)" +# (v60,1) vadd -- "Vd.qf16=vadd(Vu.qf16,Vv.hf)" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| # 0 0 0 1 1 1 1 1 0 1 1 v v v v v P P 1 u u u u u 1 0 0 d d d d d @@ -5478,7 +5733,7 @@ define pcodeop Vqf16_vadd_Vqf16Vhf; build EndPacket; } -# (hvx,1) vadd -- "Vd.qf32=vadd(Vu.qf32,Vv.qf32)" +# (v60,1) vadd -- "Vd.qf32=vadd(Vu.qf32,Vv.qf32)" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| # 0 0 0 1 1 1 1 1 1 0 1 v v v v v P P 1 u u u u u 0 0 0 d d d d d @@ -5490,7 +5745,7 @@ define pcodeop Vqf32_vadd_Vqf32Vqf32; build EndPacket; } -# (hvx,1) vadd -- "Vd.qf32=vadd(Vu.sf,Vv.sf)" +# (v60,1) vadd -- "Vd.qf32=vadd(Vu.sf,Vv.sf)" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| # 0 0 0 1 1 1 1 1 1 0 1 v v v v v P P 1 u u u u u 0 0 1 d d d d d @@ -5502,7 +5757,7 @@ define pcodeop Vqf32_vadd_VsfVsf; build EndPacket; } -# (hvx,1) vadd -- "Vd.qf32=vadd(Vu.qf32,Vv.sf)" +# (v60,1) vadd -- "Vd.qf32=vadd(Vu.qf32,Vv.sf)" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| # 0 0 0 1 1 1 1 1 1 0 1 v v v v v P P 1 u u u u u 0 1 0 d d d d d @@ -5514,7 +5769,7 @@ define pcodeop Vqf32_vadd_Vqf32Vsf; build EndPacket; } -# (hvx,1) vasl -- "Vx.w+=vasl(Vu.w,Rt)" +# (v60,1) vasl -- "Vx.w+=vasl(Vu.w,Rt)" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| # 0 0 0 1 1 0 0 1 0 1 1 t t t t t P P 1 u u u u u 0 1 0 x x x x x @@ -5526,7 +5781,7 @@ define pcodeop vaslacc_VwVwR; build EndPacket; } -# (hvx,1) vasr -- "Vx.w+=vasr(Vu.w,Rt)" +# (v60,1) vasr -- "Vx.w+=vasr(Vu.w,Rt)" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| # 0 0 0 1 1 0 0 1 0 1 1 t t t t t P P 1 u u u u u 1 0 1 x x x x x @@ -5538,7 +5793,7 @@ define pcodeop vasracc_VwVwR; build EndPacket; } -# (hvx,1) vasr -- "Vx.h+=vasr(Vu.h,Rt)" +# (v60,1) vasr -- "Vx.h+=vasr(Vu.h,Rt)" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| # 0 0 0 1 1 0 0 1 1 0 0 t t t t t P P 1 u u u u u 1 1 1 x x x x x @@ -5550,7 +5805,7 @@ define pcodeop vasracc_VhVhR; build EndPacket; } -# (hvx,1) vasl -- "Vx.h+=vasl(Vu.h,Rt)" +# (v60,1) vasl -- "Vx.h+=vasl(Vu.h,Rt)" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| # 0 0 0 1 1 0 0 1 1 0 1 t t t t t P P 1 u u u u u 1 0 1 x x x x x @@ -5562,7 +5817,7 @@ define pcodeop vaslacc_VhVhR; build EndPacket; } -# (hvx,1) vasr -- "Vd.w=vasr(Vu.w,Rt)" +# (v60,1) vasr -- "Vd.w=vasr(Vu.w,Rt)" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| # 0 0 0 1 1 0 0 1 0 1 1 t t t t t P P 0 u u u u u 1 0 1 d d d d d @@ -5574,7 +5829,7 @@ define pcodeop vasr_VwR; build EndPacket; } -# (hvx,1) vasr -- "Vd.h=vasr(Vu.h,Rt)" +# (v60,1) vasr -- "Vd.h=vasr(Vu.h,Rt)" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| # 0 0 0 1 1 0 0 1 0 1 1 t t t t t P P 0 u u u u u 1 1 0 d d d d d @@ -5586,7 +5841,7 @@ define pcodeop vasr_VhR; build EndPacket; } -# (hvx,1) vasl -- "Vd.w=vasl(Vu.w,Rt)" +# (v60,1) vasl -- "Vd.w=vasl(Vu.w,Rt)" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| # 0 0 0 1 1 0 0 1 0 1 1 t t t t t P P 0 u u u u u 1 1 1 d d d d d @@ -5598,7 +5853,7 @@ define pcodeop vasl_VwR; build EndPacket; } -# (hvx,1) vasl -- "Vd.h=vasl(Vu.h,Rt)" +# (v60,1) vasl -- "Vd.h=vasl(Vu.h,Rt)" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| # 0 0 0 1 1 0 0 1 1 0 0 t t t t t P P 0 u u u u u 0 0 0 d d d d d @@ -5610,7 +5865,7 @@ define pcodeop vasl_VhR; build EndPacket; } -# (hvx,1) vlsr -- "Vd.uw=vlsr(Vu.uw,Rt)" +# (v60,1) vlsr -- "Vd.uw=vlsr(Vu.uw,Rt)" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| # 0 0 0 1 1 0 0 1 1 0 0 t t t t t P P 0 u u u u u 0 0 1 d d d d d @@ -5622,7 +5877,7 @@ define pcodeop vlsr_VuwR; build EndPacket; } -# (hvx,1) vlsr -- "Vd.uh=vlsr(Vu.uh,Rt)" +# (v60,1) vlsr -- "Vd.uh=vlsr(Vu.uh,Rt)" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| # 0 0 0 1 1 0 0 1 1 0 0 t t t t t P P 0 u u u u u 0 1 0 d d d d d @@ -5634,7 +5889,7 @@ define pcodeop vlsr_VuhR; build EndPacket; } -# (hvx,1) vlsr -- "Vd.ub=vlsr(Vu.ub,Rt)" +# (v60,1) vlsr -- "Vd.ub=vlsr(Vu.ub,Rt)" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| # 0 0 0 1 1 0 0 1 1 0 0 t t t t t P P 0 u u u u u 0 1 1 d d d d d @@ -5646,7 +5901,7 @@ define pcodeop vlsr_VubR; build EndPacket; } -# (hvx,1) vasr -- "Vd.w=vasr(Vu.w,Vv.w)" +# (v60,1) vasr -- "Vd.w=vasr(Vu.w,Vv.w)" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| # 0 0 0 1 1 1 1 1 1 0 1 v v v v v P P 0 u u u u u 0 0 0 d d d d d @@ -5658,7 +5913,7 @@ define pcodeop vasr_VwVw; build EndPacket; } -# (hvx,1) vlsr -- "Vd.w=vlsr(Vu.w,Vv.w)" +# (v60,1) vlsr -- "Vd.w=vlsr(Vu.w,Vv.w)" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| # 0 0 0 1 1 1 1 1 1 0 1 v v v v v P P 0 u u u u u 0 0 1 d d d d d @@ -5670,7 +5925,7 @@ define pcodeop vlsr_VwVw; build EndPacket; } -# (hvx,1) vlsr -- "Vd.h=vlsr(Vu.h,Vv.h)" +# (v60,1) vlsr -- "Vd.h=vlsr(Vu.h,Vv.h)" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| # 0 0 0 1 1 1 1 1 1 0 1 v v v v v P P 0 u u u u u 0 1 0 d d d d d @@ -5682,7 +5937,7 @@ define pcodeop vlsr_VhVh; build EndPacket; } -# (hvx,1) vasr -- "Vd.h=vasr(Vu.h,Vv.h)" +# (v60,1) vasr -- "Vd.h=vasr(Vu.h,Vv.h)" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| # 0 0 0 1 1 1 1 1 1 0 1 v v v v v P P 0 u u u u u 0 1 1 d d d d d @@ -5694,7 +5949,7 @@ define pcodeop vasr_VhVh; build EndPacket; } -# (hvx,1) vasl -- "Vd.w=vasl(Vu.w,Vv.w)" +# (v60,1) vasl -- "Vd.w=vasl(Vu.w,Vv.w)" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| # 0 0 0 1 1 1 1 1 1 0 1 v v v v v P P 0 u u u u u 1 0 0 d d d d d @@ -5706,7 +5961,7 @@ define pcodeop vasl_VwVw; build EndPacket; } -# (hvx,1) vasl -- "Vd.h=vasl(Vu.h,Vv.h)" +# (v60,1) vasl -- "Vd.h=vasl(Vu.h,Vv.h)" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| # 0 0 0 1 1 1 1 1 1 0 1 v v v v v P P 0 u u u u u 1 0 1 d d d d d @@ -5718,7 +5973,7 @@ define pcodeop vasl_VhVh; build EndPacket; } -# (hvx,1) vasr -- "Vd.uh=vasr(Vuu.w,Vv.uh):sat" +# (v60,1) vasr -- "Vd.uh=vasr(Vuu.w,Vv.uh):sat" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| # 0 0 0 1 1 1 0 1 0 0 0 v v v v v P P 0 u u u u u 0 0 0 d d d d d @@ -5730,7 +5985,7 @@ define pcodeop Vuh_vasr_WwVuh_sat; build EndPacket; } -# (hvx,1) vasr -- "Vd.uh=vasr(Vuu.w,Vv.uh):rnd:sat" +# (v60,1) vasr -- "Vd.uh=vasr(Vuu.w,Vv.uh):rnd:sat" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| # 0 0 0 1 1 1 0 1 0 0 0 v v v v v P P 0 u u u u u 0 0 1 d d d d d @@ -5742,7 +5997,7 @@ define pcodeop Vuh_vasr_WwVuh_rnd_sat; build EndPacket; } -# (hvx,1) vasr -- "Vd.ub=vasr(Vuu.uh,Vv.ub):sat" +# (v60,1) vasr -- "Vd.ub=vasr(Vuu.uh,Vv.ub):sat" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| # 0 0 0 1 1 1 0 1 0 0 0 v v v v v P P 0 u u u u u 0 1 0 d d d d d @@ -5754,7 +6009,7 @@ define pcodeop Vub_vasr_WuhVub_sat; build EndPacket; } -# (hvx,1) vasr -- "Vd.ub=vasr(Vuu.uh,Vv.ub):rnd:sat" +# (v60,1) vasr -- "Vd.ub=vasr(Vuu.uh,Vv.ub):rnd:sat" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| # 0 0 0 1 1 1 0 1 0 0 0 v v v v v P P 0 u u u u u 0 1 1 d d d d d @@ -5766,43 +6021,43 @@ define pcodeop Vub_vasr_WuhVub_rnd_sat; build EndPacket; } -# (hvx,1) "Vd.sf=Vu.qf32" +# (v60,1) "Vd.sf=Vu.qf32" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| # 0 0 0 1 1 1 1 0 - - 0 - - 1 0 0 P P 1 u u u u u 0 0 0 d d d d d define pcodeop Vsf_equals_Vqf32; -:assign VdSF_0004,VuQF32_0812 EndPacket is iclass=0x1 & op2427=0xe & op21=0x0 & op18=0x1 & op1617=0x0 & op13=0x1 & op0507=0x0 & VdSF_0004 & VuQF32_0812 & $(END_PACKET) { +:assign VdSF_0004,VuQF32_0812 EndPacket is iclass=0x1 & op2427=0xe & op2123=0x0 & op1620=0x4 & op13=0x1 & op0507=0x0 & VdSF_0004 & VuQF32_0812 & $(END_PACKET) { VdSF_0004 = Vsf_equals_Vqf32(VuQF32_0812); build EndPacket; } -# (hvx,1) "Vd.hf=Vu.qf16" +# (v60,1) "Vd.hf=Vu.qf16" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| # 0 0 0 1 1 1 1 0 - - 0 - - 1 0 0 P P 1 u u u u u 0 1 1 d d d d d define pcodeop Vhf_equals_Vqf16; -:assign VdHF_0004,VuQF16_0812 EndPacket is iclass=0x1 & op2427=0xe & op21=0x0 & op18=0x1 & op1617=0x0 & op13=0x1 & op0507=0x3 & VdHF_0004 & VuQF16_0812 & $(END_PACKET) { +:assign VdHF_0004,VuQF16_0812 EndPacket is iclass=0x1 & op2427=0xe & op2123=0x0 & op1620=0x4 & op13=0x1 & op0507=0x3 & VdHF_0004 & VuQF16_0812 & $(END_PACKET) { VdHF_0004 = Vhf_equals_Vqf16(VuQF16_0812); build EndPacket; } -# (hvx,1) "Vd.hf=Vuu.qf32" +# (v60,1) "Vd.hf=Vuu.qf32" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| # 0 0 0 1 1 1 1 0 - - 0 - - 1 0 0 P P 1 u u u u u 1 1 0 d d d d d define pcodeop Vhf_equals_Wqf32; -:assign VdHF_0004,VuuQF32_0812 EndPacket is iclass=0x1 & op2427=0xe & op21=0x0 & op18=0x1 & op1617=0x0 & op13=0x1 & op0507=0x6 & VdHF_0004 & VuuQF32_0812 & $(END_PACKET) { +:assign VdHF_0004,VuuQF32_0812 EndPacket is iclass=0x1 & op2427=0xe & op2123=0x0 & op1620=0x4 & op13=0x1 & op0507=0x6 & VdHF_0004 & VuuQF32_0812 & $(END_PACKET) { VdHF_0004 = Vhf_equals_Wqf32(VuuQF32_0812); build EndPacket; } -# (hvx,1) vround -- "Vd.h=vround(Vu.w,Vv.w):sat" +# (v60,1) vround -- "Vd.h=vround(Vu.w,Vv.w):sat" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| # 0 0 0 1 1 1 1 1 0 1 1 v v v v v P P 0 u u u u u 1 0 0 d d d d d @@ -5814,7 +6069,7 @@ define pcodeop Vh_vround_VwVw_sat; build EndPacket; } -# (hvx,1) vround -- "Vd.uh=vround(Vu.w,Vv.w):sat" +# (v60,1) vround -- "Vd.uh=vround(Vu.w,Vv.w):sat" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| # 0 0 0 1 1 1 1 1 0 1 1 v v v v v P P 0 u u u u u 1 0 1 d d d d d @@ -5826,7 +6081,7 @@ define pcodeop Vuh_vround_VwVw_sat; build EndPacket; } -# (hvx,1) vround -- "Vd.b=vround(Vu.h,Vv.h):sat" +# (v60,1) vround -- "Vd.b=vround(Vu.h,Vv.h):sat" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| # 0 0 0 1 1 1 1 1 0 1 1 v v v v v P P 0 u u u u u 1 1 0 d d d d d @@ -5838,7 +6093,7 @@ define pcodeop Vb_vround_VhVh_sat; build EndPacket; } -# (hvx,1) vround -- "Vd.ub=vround(Vu.h,Vv.h):sat" +# (v60,1) vround -- "Vd.ub=vround(Vu.h,Vv.h):sat" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| # 0 0 0 1 1 1 1 1 0 1 1 v v v v v P P 0 u u u u u 1 1 1 d d d d d @@ -5850,7 +6105,7 @@ define pcodeop Vub_vround_VhVh_sat; build EndPacket; } -# (hvx,1) vround -- "Vd.ub=vround(Vu.uh,Vv.uh):sat" +# (v60,1) vround -- "Vd.ub=vround(Vu.uh,Vv.uh):sat" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| # 0 0 0 1 1 1 1 1 1 1 1 v v v v v P P 0 u u u u u 0 1 1 d d d d d @@ -5862,7 +6117,7 @@ define pcodeop Vub_vround_VuhVuh_sat; build EndPacket; } -# (hvx,1) vround -- "Vd.uh=vround(Vu.uw,Vv.uw):sat" +# (v60,1) vround -- "Vd.uh=vround(Vu.uw,Vv.uw):sat" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| # 0 0 0 1 1 1 1 1 1 1 1 v v v v v P P 0 u u u u u 1 0 0 d d d d d @@ -5874,7 +6129,7 @@ define pcodeop Vuh_vround_VuwVuw_sat; build EndPacket; } -# (hvx,1) vrotr -- "Vd.uw=vrotr(Vu.uw,Vv.uw)" +# (v60,1) vrotr -- "Vd.uw=vrotr(Vu.uw,Vv.uw)" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| # 0 0 0 1 1 0 1 0 1 0 0 v v v v v P P 1 u u u u u 1 1 1 d d d d d @@ -5886,7 +6141,7 @@ define pcodeop Vuw_vrotr_VuwVuw; build EndPacket; } -# (hvx,1) vsub -- "Vd.qf16=vsub(Vu.qf16,Vv.qf16)" +# (v60,1) vsub -- "Vd.qf16=vsub(Vu.qf16,Vv.qf16)" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| # 0 0 0 1 1 1 1 1 0 1 1 v v v v v P P 1 u u u u u 1 0 1 d d d d d @@ -5898,7 +6153,7 @@ define pcodeop Vqf16_vsub_Vqf16Vqf16; build EndPacket; } -# (hvx,1) vsub -- "Vd.qf16=vsub(Vu.hf,Vv.hf)" +# (v60,1) vsub -- "Vd.qf16=vsub(Vu.hf,Vv.hf)" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| # 0 0 0 1 1 1 1 1 0 1 1 v v v v v P P 1 u u u u u 1 1 0 d d d d d @@ -5910,7 +6165,7 @@ define pcodeop Vqf16_vsub_VhfVhf; build EndPacket; } -# (hvx,1) vsub -- "Vd.qf16=vsub(Vu.qf16,Vv.hf)" +# (v60,1) vsub -- "Vd.qf16=vsub(Vu.qf16,Vv.hf)" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| # 0 0 0 1 1 1 1 1 0 1 1 v v v v v P P 1 u u u u u 1 1 1 d d d d d @@ -5922,7 +6177,7 @@ define pcodeop Vqf16_vsub_Vqf16Vhf; build EndPacket; } -# (hvx,1) vsub -- "Vd.qf32=vsub(Vu.qf32,Vv.qf32)" +# (v60,1) vsub -- "Vd.qf32=vsub(Vu.qf32,Vv.qf32)" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| # 0 0 0 1 1 1 1 1 1 0 1 v v v v v P P 1 u u u u u 0 1 1 d d d d d @@ -5934,7 +6189,7 @@ define pcodeop Vqf32_vsub_Vqf32Vqf32; build EndPacket; } -# (hvx,1) vsub -- "Vd.qf32=vsub(Vu.sf,Vv.sf)" +# (v60,1) vsub -- "Vd.qf32=vsub(Vu.sf,Vv.sf)" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| # 0 0 0 1 1 1 1 1 1 0 1 v v v v v P P 1 u u u u u 1 0 0 d d d d d @@ -5946,7 +6201,7 @@ define pcodeop Vqf32_vsub_VsfVsf; build EndPacket; } -# (hvx,1) vsub -- "Vd.qf32=vsub(Vu.qf32,Vv.sf)" +# (v60,1) vsub -- "Vd.qf32=vsub(Vu.qf32,Vv.sf)" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| # 0 0 0 1 1 1 1 1 1 0 1 v v v v v P P 1 u u u u u 1 0 1 d d d d d @@ -5958,7 +6213,7 @@ define pcodeop Vqf32_vsub_Vqf32Vsf; build EndPacket; } -# (hvx,1) vcl0 -- "Vd.uw=vcl0(Vu.uw)" +# (v60,1) vcl0 -- "Vd.uw=vcl0(Vu.uw)" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| # 0 0 0 1 1 1 1 0 - - 0 - - - 1 0 P P 0 u u u u u 1 0 1 d d d d d @@ -5970,7 +6225,7 @@ define pcodeop Vuw_vcl0_Vuw; build EndPacket; } -# (hvx,1) vpopcount -- "Vd.h=vpopcount(Vu.h)" +# (v60,1) vpopcount -- "Vd.h=vpopcount(Vu.h)" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| # 0 0 0 1 1 1 1 0 - - 0 - - - 1 0 P P 0 u u u u u 1 1 0 d d d d d @@ -5982,7 +6237,7 @@ define pcodeop Vh_vpopcount_Vh; build EndPacket; } -# (hvx,1) vcl0 -- "Vd.uh=vcl0(Vu.uh)" +# (v60,1) vcl0 -- "Vd.uh=vcl0(Vu.uh)" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| # 0 0 0 1 1 1 1 0 - - 0 - - - 1 0 P P 0 u u u u u 1 1 1 d d d d d @@ -5994,7 +6249,7 @@ define pcodeop Vuh_vcl0_Vuh; build EndPacket; } -# (hvx,1) vnormamt -- "Vd.w=vnormamt(Vu.w)" +# (v60,1) vnormamt -- "Vd.w=vnormamt(Vu.w)" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| # 0 0 0 1 1 1 1 0 - - 0 - - - 1 1 P P 0 u u u u u 1 0 0 d d d d d @@ -6006,7 +6261,7 @@ define pcodeop Vw_vnormamt_Vw; build EndPacket; } -# (hvx,1) vnormamt -- "Vd.h=vnormamt(Vu.h)" +# (v60,1) vnormamt -- "Vd.h=vnormamt(Vu.h)" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| # 0 0 0 1 1 1 1 0 - - 0 - - - 1 1 P P 0 u u u u u 1 0 1 d d d d d @@ -6018,7 +6273,7 @@ define pcodeop Vh_vnormamt_Vh; build EndPacket; } -# (hvx,1) vadd -- "Vd.h=vadd(vclb(Vu.h),Vv.h)" +# (v60,1) vadd -- "Vd.h=vadd(vclb(Vu.h),Vv.h)" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| # 0 0 0 1 1 1 1 1 0 0 0 v v v v v P P 1 u u u u u 0 0 0 d d d d d @@ -6026,12 +6281,11 @@ define pcodeop Vh_vnormamt_Vh; define pcodeop vadd_vclb_VhVh; :vadd VdH_0004,"vclb("^VuH_0812^")",VvH_1620 EndPacket is iclass=0x1 & op2127=0x78 & op13=0x1 & op0507=0x0 & VdH_0004 & VuH_0812 & VvH_1620 & $(END_PACKET) { + VdH_0004 = vadd_vclb_VhVh(VuH_0812,VvH_1620); # writes vd5_ at issue time; Vd5 commits vd5=vd5_ build EndPacket; - <> - VdH_0004 = vadd_vclb_VhVh(VuH_0812,VvH_1620); } -# (hvx,1) vadd -- "Vd.w=vadd(vclb(Vu.w),Vv.w)" +# (v60,1) vadd -- "Vd.w=vadd(vclb(Vu.w),Vv.w)" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| # 0 0 0 1 1 1 1 1 0 0 0 v v v v v P P 1 u u u u u 0 0 1 d d d d d @@ -6039,384 +6293,451 @@ define pcodeop vadd_vclb_VhVh; define pcodeop vadd_vclb_VwVw; :vadd VdW_0004,"vclb("^VuW_0812^")",VvW_1620 EndPacket is iclass=0x1 & op2127=0x78 & op13=0x1 & op0507=0x1 & VdW_0004 & VuW_0812 & VvW_1620 & $(END_PACKET) { + VdW_0004 = vadd_vclb_VwVw(VuW_0812,VvW_1620); # writes vd5_ at issue time; Vd5 commits vd5=vd5_ build EndPacket; - <> - VdW_0004 = vadd_vclb_VwVw(VuW_0812,VvW_1620); } -# (hvx,2) "if (Qv4) vmem(Rt+#s4)=Vs" +# (v60,2) "if (Qv4) vmem(Rt+#s4)=Vs" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 0 0 1 0 1 0 0 0 1 0 0 t t t t t P P i v v i i i 0 0 0 s s s s s +# 0 0 1 0 1 0 0 0 1 n 0 t t t t t P P i v v i i i 0 0 0 s s s s s # -# (hvx,2) "if (Qv4) vmem(Rt+#s4):nt=Vs" +# (v60,2) "if (Qv4) vmem(Rt+#s4):nt=Vs" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 0 0 1 0 1 0 0 0 1 1 0 t t t t t P P i v v i i i 0 0 0 s s s s s +# 0 0 1 0 1 0 0 0 1 n 0 t t t t t P P i v v i i i 0 0 0 s s s s s # -# (hvx,2) "if (!Qv4) vmem(Rt+#s4)=Vs" +# (v60,2) "if (!Qv4) vmem(Rt+#s4)=Vs" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 0 0 1 0 1 0 0 0 1 0 0 t t t t t P P i v v i i i 0 0 1 s s s s s +# 0 0 1 0 1 0 0 0 1 n 0 t t t t t P P i v v i i i 0 0 1 s s s s s # -# (hvx,2) "if (!Qv4) vmem(Rt+#s4):nt=Vs" +# (v60,2) "if (!Qv4) vmem(Rt+#s4):nt=Vs" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 0 0 1 0 1 0 0 0 1 1 0 t t t t t P P i v v i i i 0 0 1 s s s s s +# 0 0 1 0 1 0 0 0 1 n 0 t t t t t P P i v v i i i 0 0 1 s s s s s define pcodeop vmemStoreIf; # aligned store of vector bytes where corresponding predicate bit is set -:vmem^".if("^Qv_1112_S05^")"^ntHint22 VAlignMemAddrRxS4,Vs_0004 EndPacket is iclass=0x2 & op2127=0x44 & op0607=0x0 & ntHint22 & Qv_1112_S05 & VAlignMemAddrRxS4 & Vs_0004 & $(END_PACKET) { +:vmem^".if("^Qv_1112_S05^")"^ntHint22 VAlignMemAddrRxS4,Vs_0004 EndPacket is iclass=0x2 & op2327=0x11 & op21=0 & op0607=0x0 & ntHint22 & Qv_1112_S05 & VAlignMemAddrRxS4 & Vs_0004 & $(END_PACKET) { + build Qv_1112_S05; + build Vs_0004; + build VAlignMemAddrRxS4; build EndPacket; <> vmemStoreIf(Qv_1112_S05, VAlignMemAddrRxS4, Vs_0004); } -# (hvx,2) "if (Qv4) vmem(Rx++#s3)=Vs" +# (v60,2) "if (Qv4) vmem(Rx++#s3)=Vs" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 0 0 1 0 1 0 0 1 1 0 0 x x x x x P P - v v i i i 0 0 0 s s s s s +# 0 0 1 0 1 0 0 1 1 n 0 x x x x x P P - v v i i i 0 0 0 s s s s s # -# (hvx,2) "if (Qv4) vmem(Rx++#s3):nt=Vs" +# (v60,2) "if (Qv4) vmem(Rx++#s3):nt=Vs" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 0 0 1 0 1 0 0 1 1 1 0 x x x x x P P - v v i i i 0 0 0 s s s s s +# 0 0 1 0 1 0 0 1 1 n 0 x x x x x P P - v v i i i 0 0 0 s s s s s # -# (hvx,2) "if (!Qv4) vmem(Rx++#s3)=Vs" +# (v60,2) "if (!Qv4) vmem(Rx++#s3)=Vs" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 0 0 1 0 1 0 0 1 1 0 0 x x x x x P P - v v i i i 0 0 1 s s s s s +# 0 0 1 0 1 0 0 1 1 n 0 x x x x x P P - v v i i i 0 0 1 s s s s s # -# (hvx,2) "if (!Qv4) vmem(Rx++#s3):nt=Vs" +# (v60,2) "if (!Qv4) vmem(Rx++#s3):nt=Vs" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 0 0 1 0 1 0 0 1 1 1 0 x x x x x P P - v v i i i 0 0 1 s s s s s +# 0 0 1 0 1 0 0 1 1 n 0 x x x x x P P - v v i i i 0 0 1 s s s s s -:vmem^".if("^Qv_1112_S05^")"^ntHint22 VAlignMemAddrRxAIS3,Vs_0004 EndPacket is iclass=0x2 & op2127=0x4c & op0607=0x0 & ntHint22 & Qv_1112_S05 & VAlignMemAddrRxAIS3 & Vs_0004 & $(END_PACKET) { +:vmem^".if("^Qv_1112_S05^")"^ntHint22 VAlignMemAddrRxAIS3,Vs_0004 EndPacket is iclass=0x2 & op2327=0x13 & op21=0 & op0607=0x0 & ntHint22 & Qv_1112_S05 & VAlignMemAddrRxAIS3 & Vs_0004 & $(END_PACKET) { + build VAlignMemAddrRxAIS3; + build Qv_1112_S05; + build Vs_0004; build EndPacket; <> + build VAlignMemAddrRxAIS3; vmemStoreIf(Qv_1112_S05, VAlignMemAddrRxAIS3, Vs_0004); } -# (hvx,2) "if (Qv4) vmem(Rx++Mu)=Vs" +# (v60,2) "if (Qv4) vmem(Rx++Mu)=Vs" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 0 0 1 0 1 0 1 1 1 0 0 x x x x x P P u v v - - - 0 0 0 s s s s s +# 0 0 1 0 1 0 1 1 1 n 0 x x x x x P P u v v - - - 0 0 0 s s s s s # -# (hvx,2) "if (Qv4) vmem(Rx++Mu):nt=Vs" +# (v60,2) "if (Qv4) vmem(Rx++Mu):nt=Vs" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 0 0 1 0 1 0 1 1 1 1 0 x x x x x P P u v v - - - 0 0 0 s s s s s +# 0 0 1 0 1 0 1 1 1 n 0 x x x x x P P u v v - - - 0 0 0 s s s s s # -# (hvx,2) "if (!Qv4) vmem(Rx++Mu)=Vs" +# (v60,2) "if (!Qv4) vmem(Rx++Mu)=Vs" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 0 0 1 0 1 0 1 1 1 0 0 x x x x x P P u v v - - - 0 0 1 s s s s s +# 0 0 1 0 1 0 1 1 1 n 0 x x x x x P P u v v - - - 0 0 1 s s s s s # -# (hvx,2) "if (!Qv4) vmem(Rx++Mu):nt=Vs" +# (v60,2) "if (!Qv4) vmem(Rx++Mu):nt=Vs" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 0 0 1 0 1 0 1 1 1 1 0 x x x x x P P u v v - - - 0 0 1 s s s s s +# 0 0 1 0 1 0 1 1 1 n 0 x x x x x P P u v v - - - 0 0 1 s s s s s -:vmem^".if("^Qv_1112_S05^")"^ntHint22 VAlignMemAddrRxAIMu,Vs_0004 EndPacket is iclass=0x2 & op2127=0x5c & op0607=0x0 & ntHint22 & Qv_1112_S05 & VAlignMemAddrRxAIMu & Vs_0004 & $(END_PACKET) { +:vmem^".if("^Qv_1112_S05^")"^ntHint22 VAlignMemAddrRxAIMu,Vs_0004 EndPacket is iclass=0x2 & op2327=0x17 & op21=0 & op0607=0x0 & ntHint22 & Qv_1112_S05 & VAlignMemAddrRxAIMu & Vs_0004 & $(END_PACKET) { + build VAlignMemAddrRxAIMu; + build Qv_1112_S05; + build Vs_0004; build EndPacket; <> + build VAlignMemAddrRxAIMu; vmemStoreIf(Qv_1112_S05, VAlignMemAddrRxAIMu, Vs_0004); } -# (hvx,2) "vmem(Rt+#s4)=Os8.new" +# (v60,2) "vmem(Rt+#s4)=Os8.new" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 0 0 1 0 1 0 0 0 0 0 1 t t t t t P P i - - i i i 0 0 1 - 0 s s s -# -# (hvx,2) "vmem(Rt+#s4):nt=Os8.new" +# 0 0 1 0 1 0 0 0 0 n 1 t t t t t P P i - - i i i 0 0 1 - 0 s s s + +:vmem VAlignMemAddrRxS4,VNreg0002 EndPacket is iclass=0x2 & op2327=0x10 & op22=0 & op21=1 & op0507=0x1 & op3=0x0 & VAlignMemAddrRxS4 & VNreg0002 & $(END_PACKET) { + build VAlignMemAddrRxS4; + build EndPacket; + <> + VAlignMemAddrRxS4 = VNreg0002; +} + +# (v60,2) "vmem(Rt+#s4):nt=Os8.new" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 0 0 1 0 1 0 0 0 0 1 1 t t t t t P P i - - i i i 0 0 1 - - s s s +# 0 0 1 0 1 0 0 0 0 n 1 t t t t t P P i - - i i i 0 0 1 - - s s s -:vmem^ntHint22 VAlignMemAddrRxS4,VNreg0002 EndPacket is iclass=0x2 & op2127=0x41 & op0507=0x1 & op3=0x0 & ntHint22 & VAlignMemAddrRxS4 & VNreg0002 & $(END_PACKET) { +:vmem^":nt" VAlignMemAddrRxS4,VNreg0002 EndPacket is iclass=0x2 & op2327=0x10 & op22=1 & op21=1 & op0507=0x1 & VAlignMemAddrRxS4 & VNreg0002 & $(END_PACKET) { + build VAlignMemAddrRxS4; build EndPacket; <> VAlignMemAddrRxS4 = VNreg0002; } -# (hvx,2) "if (Pv) vmem(Rt+#s4)=Os8.new" +# (v60,2) "if (Pv) vmem(Rt+#s4)=Os8.new" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| # 0 0 1 0 1 0 0 0 1 0 1 t t t t t P P i v v i i i 0 1 0 0 0 s s s # -# (hvx,2) "if (!Pv) vmem(Rt+#s4)=Os8.new" +# (v60,2) "if (!Pv) vmem(Rt+#s4)=Os8.new" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| # 0 0 1 0 1 0 0 0 1 0 1 t t t t t P P i v v i i i 0 1 1 0 1 s s s # -# (hvx,2) "if (Pv) vmem(Rt+#s4):nt=Os8.new" +# (v60,2) "if (Pv) vmem(Rt+#s4):nt=Os8.new" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| # 0 0 1 0 1 0 0 0 1 1 1 t t t t t P P i v v i i i 0 1 0 1 0 s s s # -# (hvx,2) "if (!Pv) vmem(Rt+#s4):nt=Os8.new" +# (v60,2) "if (!Pv) vmem(Rt+#s4):nt=Os8.new" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| # 0 0 1 0 1 0 0 0 1 1 1 t t t t t P P i v v i i i 0 1 1 1 1 s s s # # NOTE: We tie op4=op22 & op3=op5 to reduce the number of constructors -:vmem^VPuCond1112_S05^ntHint22 VAlignMemAddrRxS4,VNreg0002 EndPacket is iclass=0x2 & op21=1 & op2327=0x11 & op0607=0x1 & op4=op22 & op3=op5 & VPuCond1112_S05 & ntHint22 & VAlignMemAddrRxS4 & VNreg0002 & $(END_PACKET) { +:vmem^VPuCond1112_S05^ntHint22 VAlignMemAddrRxS4,VNreg0002 EndPacket is iclass=0x2 & op2327=0x11 & op21=1 & op0607=0x1 & op4=op22 & op3=op5 & VPuCond1112_S05 & ntHint22 & VAlignMemAddrRxS4 & VNreg0002 & $(END_PACKET) { build VPuCond1112_S05; + build VAlignMemAddrRxS4; build EndPacket; <> + build VPuCond1112_S05; if (ConditionReg == 0) goto ; VAlignMemAddrRxS4 = VNreg0002; } -# (hvx,2) "vmem(Rx++#s3)=Os8.new" +# (v60,2) "vmem(Rx++#s3)=Os8.new" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| # 0 0 1 0 1 0 0 1 0 0 1 x x x x x P P - - - i i i 0 0 1 - 0 s s s -# -# (hvx,2) "vmem(Rx++#s3):nt=Os8.new" + +:vmem VAlignMemAddrRxAIS3,VNreg0002 EndPacket is iclass=0x2 & op2127=0x49 & op0507=0x1 & op3=0x0 & VAlignMemAddrRxAIS3 & VNreg0002 & $(END_PACKET) [ cond=0; ] { + build VAlignMemAddrRxAIS3; + build EndPacket; + <> + build VAlignMemAddrRxAIS3; + VAlignMemAddrRxAIS3 = VNreg0002; +} + +# (v60,2) "vmem(Rx++#s3):nt=Os8.new" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| # 0 0 1 0 1 0 0 1 0 1 1 x x x x x P P - - - i i i 0 0 1 - - s s s -:vmem^ntHint22 VAlignMemAddrRxAIS3,VNreg0002 EndPacket is iclass=0x2 & op2127=0x49 & op0507=0x1 & op3=0x0 & ntHint22 & VAlignMemAddrRxAIS3 & VNreg0002 & $(END_PACKET) [ cond=0; ] { +:vmem^":nt" VAlignMemAddrRxAIS3,VNreg0002 EndPacket is iclass=0x2 & op2127=0x4b & op0507=0x1 & VAlignMemAddrRxAIS3 & VNreg0002 & $(END_PACKET) [ cond=0; ] { + build VAlignMemAddrRxAIS3; build EndPacket; <> + build VAlignMemAddrRxAIS3; VAlignMemAddrRxAIS3 = VNreg0002; } -# (hvx,2) "if (Pv) vmem(Rx++#s3)=Os8.new" +# (v60,2) "if (Pv) vmem(Rx++#s3)=Os8.new" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| # 0 0 1 0 1 0 0 1 1 0 1 x x x x x P P - v v i i i 0 1 0 0 0 s s s # -# (hvx,2) "if (!Pv) vmem(Rx++#s3)=Os8.new" +# (v60,2) "if (!Pv) vmem(Rx++#s3)=Os8.new" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| # 0 0 1 0 1 0 0 1 1 0 1 x x x x x P P - v v i i i 0 1 1 0 1 s s s # -# (hvx,2) "if (Pv) vmem(Rx++#s3):nt=Os8.new" +# (v60,2) "if (Pv) vmem(Rx++#s3):nt=Os8.new" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| # 0 0 1 0 1 0 0 1 1 1 1 x x x x x P P - v v i i i 0 1 0 1 0 s s s # -# (hvx,2) "if (!Pv) vmem(Rx++#s3):nt=Os8.new" +# (v60,2) "if (!Pv) vmem(Rx++#s3):nt=Os8.new" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| # 0 0 1 0 1 0 0 1 1 1 1 x x x x x P P - v v i i i 0 1 1 1 1 s s s # # NOTE: We tie op4=op22 & op3=op5 to reduce the number of constructors -:vmem^VPuCond1112_S05^ntHint22 VAlignMemAddrRxAIS3,VNreg0002 EndPacket is iclass=0x2 & op21=1 & op2327=0x13 & op0607=0x1 & op4=op22 & op3=op5 & VPuCond1112_S05 & ntHint22 & VAlignMemAddrRxAIS3 & VNreg0002 & $(END_PACKET) [ cond=1; ] { +:vmem^VPuCond1112_S05^ntHint22 VAlignMemAddrRxAIS3,VNreg0002 EndPacket is iclass=0x2 & op2327=0x13 & op21=1 & op0607=0x1 & op4=op22 & op3=op5 & VPuCond1112_S05 & ntHint22 & VAlignMemAddrRxAIS3 & VNreg0002 & $(END_PACKET) [ cond=1; ] { build VPuCond1112_S05; + build VAlignMemAddrRxAIS3; build EndPacket; <> + build VPuCond1112_S05; # set ConditionReg before any conditional commit below + build VAlignMemAddrRxAIS3; # conditional Rx post-increment if (ConditionReg == 0) goto ; VAlignMemAddrRxAIS3 = VNreg0002; } -# (hvx,2) "vmem(Rx++Mu)=Os8.new" +# (v60,2) "vmem(Rx++Mu)=Os8.new" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| # 0 0 1 0 1 0 1 1 0 0 1 x x x x x P P u - - - - - 0 0 1 - 0 s s s -# -# (hvx,2) "vmem(Rx++Mu):nt=Os8.new" + +:vmem VAlignMemAddrRxAIMu,VNreg0002 EndPacket is iclass=0x2 & op2127=0x59 & op0507=0x1 & op3=0x0 & VAlignMemAddrRxAIMu & VNreg0002 & $(END_PACKET) [ cond=0; ] { + build VAlignMemAddrRxAIMu; + build EndPacket; + <> + build VAlignMemAddrRxAIMu; + VAlignMemAddrRxAIMu = VNreg0002; +} + +# (v60,2) "vmem(Rx++Mu):nt=Os8.new" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| # 0 0 1 0 1 0 1 1 0 1 1 x x x x x P P u - - - - - 0 0 1 - - s s s -:vmem^ntHint22 VAlignMemAddrRxAIMu,VNreg0002 EndPacket is iclass=0x2 & op2127=0x59 & op0507=0x1 & op3=0x0 & ntHint22 & VAlignMemAddrRxAIMu & VNreg0002 & $(END_PACKET) [ cond=0; ] { +:vmem^":nt" VAlignMemAddrRxAIMu,VNreg0002 EndPacket is iclass=0x2 & op2127=0x5b & op0507=0x1 & VAlignMemAddrRxAIMu & VNreg0002 & $(END_PACKET) [ cond=0; ] { + build VAlignMemAddrRxAIMu; build EndPacket; <> + build VAlignMemAddrRxAIMu; VAlignMemAddrRxAIMu = VNreg0002; } -# (hvx,2) "if (Pv) vmem(Rx++Mu)=Os8.new" +# (v60,2) "if (Pv) vmem(Rx++Mu)=Os8.new" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| # 0 0 1 0 1 0 1 1 1 0 1 x x x x x P P u v v - - - 0 1 0 0 0 s s s # -# (hvx,2) "if (!Pv) vmem(Rx++Mu)=Os8.new" +# (v60,2) "if (!Pv) vmem(Rx++Mu)=Os8.new" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| # 0 0 1 0 1 0 1 1 1 0 1 x x x x x P P u v v - - - 0 1 1 0 1 s s s # -# (hvx,2) "if (Pv) vmem(Rx++Mu):nt=Os8.new" +# (v60,2) "if (Pv) vmem(Rx++Mu):nt=Os8.new" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| # 0 0 1 0 1 0 1 1 1 1 1 x x x x x P P u v v - - - 0 1 0 1 0 s s s # -# (hvx,2) "if (!Pv) vmem(Rx++Mu):nt=Os8.new" +# (v60,2) "if (!Pv) vmem(Rx++Mu):nt=Os8.new" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| # 0 0 1 0 1 0 1 1 1 1 1 x x x x x P P u v v - - - 0 1 1 1 1 s s s # # NOTE: We tie op4=op22 & op3=op5 to reduce the number of constructors -:vmem^VPuCond1112_S05^ntHint22 VAlignMemAddrRxAIMu,VNreg0002 EndPacket is iclass=0x2 & op21=1 & op2327=0x17 & op0607=0x1 & op4=op22 & op3=op5 & VPuCond1112_S05 & ntHint22 & VAlignMemAddrRxAIMu & VNreg0002 & $(END_PACKET) [ cond=1; ] { +:vmem^VPuCond1112_S05^ntHint22 VAlignMemAddrRxAIMu,VNreg0002 EndPacket is iclass=0x2 & op2327=0x17 & op21=1 & op0607=0x1 & op4=op22 & op3=op5 & VPuCond1112_S05 & ntHint22 & VAlignMemAddrRxAIMu & VNreg0002 & $(END_PACKET) [ cond=1; ] { build VPuCond1112_S05; + build VAlignMemAddrRxAIMu; build EndPacket; <> + build VPuCond1112_S05; + build VAlignMemAddrRxAIMu; # conditionally commit Rx post-increment update if (ConditionReg == 0) goto ; VAlignMemAddrRxAIMu = VNreg0002; } -# (hvx,2) "vmem(Rt+#s4)=Vs" +# (v60,2) "vmem(Rt+#s4)=Vs" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| # 0 0 1 0 1 0 0 0 0 0 1 t t t t t P P i - - i i i 0 0 0 s s s s s # -# (hvx,2) "vmem(Rt+#s4):nt=Vs" +# (v60,2) "vmem(Rt+#s4):nt=Vs" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| # 0 0 1 0 1 0 0 0 0 1 1 t t t t t P P i - - i i i 0 0 0 s s s s s -:vmem^ntHint22 VAlignMemAddrRxS4,Vs_0004 EndPacket is iclass=0x2 & op21=1 & op2327=0x10 & op0507=0x0 & ntHint22 & VAlignMemAddrRxS4 & Vs_0004 & $(END_PACKET) { +:vmem^ntHint22 VAlignMemAddrRxS4,Vs_0004 EndPacket is iclass=0x2 & op2327=0x10 & op21=1 & op0507=0x0 & ntHint22 & VAlignMemAddrRxS4 & Vs_0004 & $(END_PACKET) { + build Vs_0004; + build VAlignMemAddrRxS4; build EndPacket; <> VAlignMemAddrRxS4 = Vs_0004; } -# (hvx,2) "if (Pv) vmem(Rt+#s4)=Vs" +# (v60,2) "if (Pv) vmem(Rt+#s4)=Vs" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| # 0 0 1 0 1 0 0 0 1 0 1 t t t t t P P i v v i i i 0 0 0 s s s s s # -# (hvx,2) "if (!Pv) vmem(Rt+#s4)=Vs" +# (v60,2) "if (!Pv) vmem(Rt+#s4)=Vs" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| # 0 0 1 0 1 0 0 0 1 0 1 t t t t t P P i v v i i i 0 0 1 s s s s s # -# (hvx,2) "if (Pv) vmem(Rt+#s4):nt=Vs" +# (v60,2) "if (Pv) vmem(Rt+#s4):nt=Vs" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| # 0 0 1 0 1 0 0 0 1 1 1 t t t t t P P i v v i i i 0 0 0 s s s s s # -# (hvx,2) "if (!Pv) vmem(Rt+#s4):nt=Vs" +# (v60,2) "if (!Pv) vmem(Rt+#s4):nt=Vs" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| # 0 0 1 0 1 0 0 0 1 1 1 t t t t t P P i v v i i i 0 0 1 s s s s s -:vmem^VPuCond1112_S05^ntHint22 VAlignMemAddrRxS4,Vs_0004 EndPacket is iclass=0x2 & op21=1 & op2327=0x11 & op0607=0x0 & VPuCond1112_S05 & ntHint22 & VAlignMemAddrRxS4 & Vs_0004 & $(END_PACKET) { +:vmem^VPuCond1112_S05^ntHint22 VAlignMemAddrRxS4,Vs_0004 EndPacket is iclass=0x2 & op2327=0x11 & op21=1 & op0607=0x0 & VPuCond1112_S05 & ntHint22 & VAlignMemAddrRxS4 & Vs_0004 & $(END_PACKET) { build VPuCond1112_S05; + build Vs_0004; + build VAlignMemAddrRxS4; build EndPacket; <> + build VPuCond1112_S05; if (ConditionReg == 0) goto ; VAlignMemAddrRxS4 = Vs_0004; } -# (hvx,2) "vmem(Rx++#s3)=Vs" +# (v60,2) "vmem(Rx++#s3)=Vs" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 0 0 1 0 1 0 0 1 0 0 1 x x x x x P P - - - i i i 0 0 0 s s s s s +# 0 0 1 0 1 0 0 1 0 n 1 x x x x x P P - - - i i i 0 0 0 s s s s s # -# (hvx,2) "vmem(Rx++#s3):nt=Vs" +# (v60,2) "vmem(Rx++#s3):nt=Vs" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 0 0 1 0 1 0 0 1 0 1 1 x x x x x P P - - - i i i 0 0 0 s s s s s +# 0 0 1 0 1 0 0 1 0 n 1 x x x x x P P - - - i i i 0 0 0 s s s s s -:vmem^ntHint22 VAlignMemAddrRxAIS3,Vs_0004 EndPacket is iclass=0x2 & op21=1 & op2327=0x12 & op0607=0x0 & ntHint22 & VAlignMemAddrRxAIS3 & Vs_0004 & $(END_PACKET) [ cond=0; ] { +:vmem^ntHint22 VAlignMemAddrRxAIS3,Vs_0004 EndPacket is iclass=0x2 & op2327=0x12 & op21=1 & op0507=0x0 & ntHint22 & VAlignMemAddrRxAIS3 & Vs_0004 & $(END_PACKET) [ cond=0; ] { + build VAlignMemAddrRxAIS3; + build Vs_0004; build EndPacket; <> + build VAlignMemAddrRxAIS3; VAlignMemAddrRxAIS3 = Vs_0004; } -# (hvx,2) "if (Pv) vmem(Rx++#s3)=Vs" +# (v60,2) "if (Pv) vmem(Rx++#s3)=Vs" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| # 0 0 1 0 1 0 0 1 1 0 1 x x x x x P P - v v i i i 0 0 0 s s s s s # -# (hvx,2) "if (!Pv) vmem(Rx++#s3)=Vs" +# (v60,2) "if (!Pv) vmem(Rx++#s3)=Vs" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| # 0 0 1 0 1 0 0 1 1 0 1 x x x x x P P - v v i i i 0 0 1 s s s s s # -# (hvx,2) "if (Pv) vmem(Rx++#s3):nt=Vs" +# (v60,2) "if (Pv) vmem(Rx++#s3):nt=Vs" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| # 0 0 1 0 1 0 0 1 1 1 1 x x x x x P P - v v i i i 0 0 0 s s s s s # -# (hvx,2) "if (!Pv) vmem(Rx++#s3):nt=Vs" +# (v60,2) "if (!Pv) vmem(Rx++#s3):nt=Vs" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| # 0 0 1 0 1 0 0 1 1 1 1 x x x x x P P - v v i i i 0 0 1 s s s s s -:vmem^VPuCond1112_S05^ntHint22 VAlignMemAddrRxAIS3,Vs_0004 EndPacket is iclass=0x2 & op21=1 & op2327=0x13 & op0607=0x0 & VPuCond1112_S05 & ntHint22 & VAlignMemAddrRxAIS3 & Vs_0004 & $(END_PACKET) [ cond=1; ] { +:vmem^VPuCond1112_S05^ntHint22 VAlignMemAddrRxAIS3,Vs_0004 EndPacket is iclass=0x2 & op2327=0x13 & op21=1 & op0607=0x0 & VPuCond1112_S05 & ntHint22 & VAlignMemAddrRxAIS3 & Vs_0004 & $(END_PACKET) [ cond=1; ] { build VPuCond1112_S05; + build VAlignMemAddrRxAIS3; + build Vs_0004; build EndPacket; <> + build VPuCond1112_S05; # set ConditionReg before any conditional commit below + build VAlignMemAddrRxAIS3; # conditional Rx post-increment if (ConditionReg == 0) goto ; VAlignMemAddrRxAIS3 = Vs_0004; } -# (hvx,2) "vmem(Rx++Mu)=Vs" +# (v60,2) "vmem(Rx++Mu)=Vs" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| # 0 0 1 0 1 0 1 1 0 0 1 x x x x x P P u - - - - - 0 0 0 s s s s s # -# (hvx,2) "vmem(Rx++Mu):nt=Vs" +# (v60,2) "vmem(Rx++Mu):nt=Vs" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| # 0 0 1 0 1 0 1 1 0 1 1 x x x x x P P u - - - - - 0 0 0 s s s s s -:vmem^ntHint22 VAlignMemAddrRxAIMu,Vs_0004 EndPacket is iclass=0x2 & op21=1 & op2327=0x16 & op0507=0x0 & ntHint22 & VAlignMemAddrRxAIMu & Vs_0004 & $(END_PACKET) [ cond=0; ] { +:vmem^ntHint22 VAlignMemAddrRxAIMu,Vs_0004 EndPacket is iclass=0x2 & op2327=0x16 & op21=1 & op0507=0x0 & ntHint22 & VAlignMemAddrRxAIMu & Vs_0004 & $(END_PACKET) [ cond=0; ] { + build VAlignMemAddrRxAIMu; + build Vs_0004; build EndPacket; <> + build VAlignMemAddrRxAIMu; VAlignMemAddrRxAIMu = Vs_0004; } -# (hvx,2) "if (Pv) vmem(Rx++Mu)=Vs" +# (v60,2) "if (Pv) vmem(Rx++Mu)=Vs" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| # 0 0 1 0 1 0 1 1 1 0 1 x x x x x P P u v v - - - 0 0 0 s s s s s # -# (hvx,2) "if (!Pv) vmem(Rx++Mu)=Vs" +# (v60,2) "if (!Pv) vmem(Rx++Mu)=Vs" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| # 0 0 1 0 1 0 1 1 1 0 1 x x x x x P P u v v - - - 0 0 1 s s s s s # -# (hvx,2) "if (Pv) vmem(Rx++Mu):nt=Vs" +# (v60,2) "if (Pv) vmem(Rx++Mu):nt=Vs" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| # 0 0 1 0 1 0 1 1 1 1 1 x x x x x P P u v v - - - 0 0 0 s s s s s # -# (hvx,2) "if (!Pv) vmem(Rx++Mu):nt=Vs" +# (v60,2) "if (!Pv) vmem(Rx++Mu):nt=Vs" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| # 0 0 1 0 1 0 1 1 1 1 1 x x x x x P P u v v - - - 0 0 1 s s s s s -:vmem^VPuCond1112_S05^ntHint22 VAlignMemAddrRxAIMu,Vs_0004 EndPacket is iclass=0x2 & op21=1 & op2327=0x17 & op0607=0x0 & VPuCond1112_S05 & ntHint22 & VAlignMemAddrRxAIMu & Vs_0004 & $(END_PACKET) [ cond=1; ] { +:vmem^VPuCond1112_S05^ntHint22 VAlignMemAddrRxAIMu,Vs_0004 EndPacket is iclass=0x2 & op2327=0x17 & op21=1 & op0607=0x0 & VPuCond1112_S05 & ntHint22 & VAlignMemAddrRxAIMu & Vs_0004 & $(END_PACKET) [ cond=1; ] { build VPuCond1112_S05; + build VAlignMemAddrRxAIMu; + build Vs_0004; build EndPacket; <> + build VPuCond1112_S05; + build VAlignMemAddrRxAIMu; # conditionally commit Rx post-increment update if (ConditionReg == 0) goto ; VAlignMemAddrRxAIMu = Vs_0004; } -# (hvx,2) "vmemu(Rt+#s4)=Vs" +# (v60,2) "vmemu(Rt+#s4)=Vs" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| # 0 0 1 0 1 0 0 0 0 0 1 t t t t t P P i - - i i i 1 1 1 s s s s s :vmemu VMemAddrRxS4,Vs_0004 EndPacket is iclass=0x2 & op2127=0x41 & op0507=0x7 & VMemAddrRxS4 & Vs_0004 & $(END_PACKET) { + build Vs_0004; + build VMemAddrRxS4; build EndPacket; <> VMemAddrRxS4 = Vs_0004; } -# (hvx,2) "if (Pv) vmemu(Rt+#s4)=Vs" +# (v60,2) "if (Pv) vmemu(Rt+#s4)=Vs" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| # 0 0 1 0 1 0 0 0 1 0 1 t t t t t P P i v v i i i 1 1 0 s s s s s # -# (hvx,2) "if (!Pv) vmemu(Rt+#s4)=Vs" +# (v60,2) "if (!Pv) vmemu(Rt+#s4)=Vs" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| # 0 0 1 0 1 0 0 0 1 0 1 t t t t t P P i v v i i i 1 1 1 s s s s s @@ -6424,69 +6745,86 @@ define pcodeop vmemStoreIf; # aligned store of vector bytes where corresponding :vmemu^VPuCond1112_S05 VMemAddrRxS4,Vs_0004 EndPacket is iclass=0x2 & op2127=0x45 & op0607=0x3 & VPuCond1112_S05 & VMemAddrRxS4 & Vs_0004 & $(END_PACKET) { build VPuCond1112_S05; + build Vs_0004; + build VMemAddrRxS4; build EndPacket; <> + build VPuCond1112_S05; if (ConditionReg == 0) goto ; VMemAddrRxS4 = Vs_0004; } -# (hvx,2) "vmemu(Rx++#s3)=Vs" +# (v60,2) "vmemu(Rx++#s3)=Vs" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| # 0 0 1 0 1 0 0 1 0 0 1 x x x x x P P - - - i i i 1 1 1 s s s s s :vmemu VMemAddrRxAIS3,Vs_0004 EndPacket is iclass=0x2 & op2127=0x49 & op0507=0x7 & VMemAddrRxAIS3 & Vs_0004 & $(END_PACKET) [ cond=0; ] { + build VMemAddrRxAIS3; + build Vs_0004; build EndPacket; <> + build VMemAddrRxAIS3; VMemAddrRxAIS3 = Vs_0004; } # -# (hvx,2) "if (Pv) vmemu(Rx++#s3)=Vs" +# (v60,2) "if (Pv) vmemu(Rx++#s3)=Vs" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| # 0 0 1 0 1 0 0 1 1 0 1 x x x x x P P - v v i i i 1 1 0 s s s s s # -# (hvx,2) "if (!Pv) vmemu(Rx++#s3)=Vs" +# (v60,2) "if (!Pv) vmemu(Rx++#s3)=Vs" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| # 0 0 1 0 1 0 0 1 1 0 1 x x x x x P P - v v i i i 1 1 1 s s s s s :vmemu^VPuCond1112_S05 VMemAddrRxAIS3,Vs_0004 EndPacket is iclass=0x2 & op2127=0x4d & op0607=0x3 & VPuCond1112_S05 & VMemAddrRxAIS3 & Vs_0004 & $(END_PACKET) [ cond=1; ] { build VPuCond1112_S05; + build VMemAddrRxAIS3; + build Vs_0004; build EndPacket; <> + build VPuCond1112_S05; # set ConditionReg before any conditional commit below + build VMemAddrRxAIS3; # conditional Rx post-increment if (ConditionReg == 0) goto ; VMemAddrRxAIS3 = Vs_0004; } -# (hvx,2) "vmemu(Rx++Mu)=Vs" +# (v60,2) "vmemu(Rx++Mu)=Vs" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| # 0 0 1 0 1 0 1 1 0 0 1 x x x x x P P u - - - - - 1 1 1 s s s s s :vmemu VMemAddrRxAIMu,Vs_0004 EndPacket is iclass=0x2 & op2127=0x59 & op0507=0x7 & VMemAddrRxAIMu & Vs_0004 & $(END_PACKET) [ cond=0; ] { + build VMemAddrRxAIMu; + build Vs_0004; build EndPacket; <> + build VMemAddrRxAIMu; VMemAddrRxAIMu = Vs_0004; } -# (hvx,2) "if (Pv) vmemu(Rx++Mu)=Vs" +# (v60,2) "if (Pv) vmemu(Rx++Mu)=Vs" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| # 0 0 1 0 1 0 1 1 1 0 1 x x x x x P P u v v - - - 1 1 0 s s s s s # -# (hvx,2) "if (!Pv) vmemu(Rx++Mu)=Vs" +# (v60,2) "if (!Pv) vmemu(Rx++Mu)=Vs" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| # 0 0 1 0 1 0 1 1 1 0 1 x x x x x P P u v v - - - 1 1 1 s s s s s :vmemu^VPuCond1112_S05 VMemAddrRxAIMu,Vs_0004 EndPacket is iclass=0x2 & op2127=0x5d & op0607=0x3 & VPuCond1112_S05 & VMemAddrRxAIMu & Vs_0004 & $(END_PACKET) [ cond=1; ] { build VPuCond1112_S05; + build VMemAddrRxAIMu; + build Vs_0004; build EndPacket; <> + build VPuCond1112_S05; # set ConditionReg before any conditional commit below + build VMemAddrRxAIMu; # conditional Rx post-increment if (ConditionReg == 0) goto ; VMemAddrRxAIMu = Vs_0004; @@ -6495,43 +6833,57 @@ define pcodeop vmemStoreIf; # aligned store of vector bytes where corresponding # # NOTE: vmem scatter_release is specific to the V66 to address a V60/V61 pipeline issue where an # explicit release was required to avoid a scatter storage hazard. These vmem instructions were -# a microarchitectural workaround that existed only for V60‑class cores and was never part of the -# stable, forward‑compatible HVX ISA. +# a microarchitectural workaround that existed only for V60-class cores and was never part of the +# stable, forward-compatible HVX ISA. # define pcodeop scatter_release; -# (hvx,2) vmem -- "vmem(Rt+#s4):scatter_release" +# (v60,2) vmem -- "vmem(Rt+#s4):scatter_release" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| # 0 0 1 0 1 0 0 0 0 0 1 t t t t t P P i - - i i i 0 0 1 - 1 - - - :vmem^":scatter_release" VAlignMemAddrRxS4 EndPacket is iclass=0x2 & op2127=0x41 & op0507=0x1 & op3=0x1 & VAlignMemAddrRxS4 & $(END_PACKET) { + build VAlignMemAddrRxS4; build EndPacket; <> scatter_release(VAlignMemAddrRxS4); } -# (hvx,2) vmem -- "vmem(Rx++#s3):scatter_release" +# (v60,2) vmem -- "vmem(Rx++#s3):scatter_release" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| # 0 0 1 0 1 0 0 1 0 0 1 x x x x x P P - - - i i i 0 0 1 - 1 - - - :vmem^":scatter_release" VAlignMemAddrRxAIS3 EndPacket is iclass=0x2 & op2127=0x49 & op0507=0x1 & op3=0x1 & VAlignMemAddrRxAIS3 & $(END_PACKET) { + build VAlignMemAddrRxAIS3; build EndPacket; <> + build VAlignMemAddrRxAIS3; scatter_release(VAlignMemAddrRxAIS3); } -# (hvx,2) vmem -- "vmem(Rx++Mu):scatter_release" +# (v60,2) vmem -- "vmem(Rx++Mu):scatter_release" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| # 0 0 1 0 1 0 1 1 0 0 1 x x x x x P P u - - - - - 0 0 1 - 1 - - - :vmem^":scatter_release" VAlignMemAddrRxAIMu EndPacket is iclass=0x2 & op2127=0x59 & op0507=0x1 & op3=0x1 & VAlignMemAddrRxAIMu & $(END_PACKET) { + build VAlignMemAddrRxAIMu; build EndPacket; <> + build VAlignMemAddrRxAIMu; scatter_release(VAlignMemAddrRxAIMu); } +# (hvx,1) valign4 -- "Vd = valign4(Vu, Vv, Rt8)" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 1 0 0 0 0 0 0 z z t t t P P 0 u u u u u 1 0 1 d d d d d + +define pcodeop valign4; +:valign4 Vd5,Vu_0812,Vz_1923,rt1618 EndPacket is iclass=0x1 & op2427=0x8 & op2123=0x0 & op13=0x0 & op0507=0x5 & Vd5 & Vu_0812 & Vz_1923 & rt1618 & $(END_PACKET) { + Vd5 = valign4(Vu_0812,Vz_1923,rt1618); +} diff --git a/pypcode/processors/Hexagon/data/languages/hexagon_hvx.txt b/pypcode/processors/Hexagon/data/languages/hexagon_hvx.txt deleted file mode 100644 index 6a8dc21..0000000 --- a/pypcode/processors/Hexagon/data/languages/hexagon_hvx.txt +++ /dev/null @@ -1,618 +0,0 @@ -Hexagon V69 HVX instruction patterns - -0 0 0 1 1 1 1 0 - - 0 - - 0 0 0 P P 1 - 0 0 1 0 1 0 0 - - - - - vwhist256 -0 0 0 1 1 1 1 0 - - 0 - - 0 0 0 P P 1 - 0 0 1 1 1 0 0 - - - - - vwhist256:sat -0 0 0 1 1 1 1 0 - - 0 - - 0 0 0 P P 1 - 0 1 0 - 1 0 0 - - - - - vwhist128 -0 0 0 1 1 1 1 0 - - 0 - - 0 0 0 P P 1 - 0 1 1 i 1 0 0 - - - - - vwhist128(#u1) -0 0 0 1 1 1 1 0 v v 0 - - 0 1 0 P P 1 - - 0 1 0 1 0 0 - - - - - vwhist256(Qv4) -0 0 0 1 1 1 1 0 v v 0 - - 0 1 0 P P 1 - - 0 1 1 1 0 0 - - - - - vwhist256(Qv4):sat -0 0 0 1 1 1 1 0 v v 0 - - 0 1 0 P P 1 - - 1 0 - 1 0 0 - - - - - vwhist128(Qv4) -0 0 0 1 1 1 1 0 v v 0 - - 0 1 0 P P 1 - - 1 1 i 1 0 0 - - - - - vwhist128(Qv4,#u1) -0 0 0 1 1 1 1 0 t t 0 - - - 1 1 P P 0 - - - s s 0 0 0 0 0 0 d d Qd4=and(Qs4,Qt4) -0 0 0 1 1 1 1 0 t t 0 - - - 1 1 P P 0 - - - s s 0 0 0 0 0 1 d d Qd4=or(Qs4,Qt4) -0 0 0 1 1 1 1 0 t t 0 - - - 1 1 P P 0 - - - s s 0 0 0 0 1 1 d d Qd4=xor(Qs4,Qt4) -0 0 0 1 1 1 1 0 t t 0 - - - 1 1 P P 0 - - - s s 0 0 0 1 0 0 d d Qd4=or(Qs4,!Qt4) -0 0 0 1 1 1 1 0 t t 0 - - - 1 1 P P 0 - - - s s 0 0 0 1 0 1 d d Qd4=and(Qs4,!Qt4) -0 0 0 1 1 1 1 0 t t 0 - - - 1 1 P P 0 - - - s s 0 0 0 1 1 0 d d Qd4.b=vshuffe(Qs4.h,Qt4.h) -0 0 0 1 1 1 1 0 t t 0 - - - 1 1 P P 0 - - - s s 0 0 0 1 1 1 d d Qd4.h=vshuffe(Qs4.w,Qt4. -0 0 0 1 1 0 1 0 0 1 0 v v v v v P P - u u u u u - s s d d d d d if (!Ps) Vdd=vcombine(Vu,Vv) -0 0 0 1 1 0 1 0 0 1 1 v v v v v P P - u u u u u - s s d d d d d if (Ps) Vdd=vcombine(Vu,Vv) -0 0 0 1 1 1 1 1 0 1 0 v v v v v P P 0 u u u u u 1 1 1 d d d d d Vdd=vcombine(Vu,Vv) -0 0 0 1 1 1 1 1 0 1 0 v v v v v P P 0 u u u u u 1 0 1 d d d d d Vdd.h=vshuffoe(Vu.h,Vv.h) -0 0 0 1 1 1 1 1 0 1 0 v v v v v P P 0 u u u u u 1 1 0 d d d d d Vdd.b=vshuffoe(Vu.b,Vv.b) -0 0 0 1 1 1 1 0 1 0 1 v v v v v P P 1 u u u u u - t t d d d d d Vdd=vswap(Qt4,Vu,Vv) -0 0 0 1 1 1 1 0 - - 0 - - - 1 0 P P 0 u u u u u 0 0 1 d d d d d Vdd.uh=vzxt(Vu.ub) -0 0 0 1 1 1 1 0 - - 0 - - - 1 0 P P 0 u u u u u 0 1 0 d d d d d Vdd.uw=vzxt(Vu.uh) -0 0 0 1 1 1 1 0 - - 0 - - - 1 0 P P 0 u u u u u 0 1 1 d d d d d Vdd.h=vsxt(Vu.b) -0 0 0 1 1 1 1 0 - - 0 - - - 1 0 P P 0 u u u u u 1 0 0 d d d d d Vdd.w=vsxt(Vu.h) -0 0 0 1 1 1 0 0 0 1 1 v v v v v P P 0 u u u u u 1 0 0 d d d d d Vdd.b=vadd(Vuu.b,Vvv.b) -0 0 0 1 1 1 0 0 0 1 1 v v v v v P P 0 u u u u u 1 0 1 d d d d d Vdd.h=vadd(Vuu.h,Vvv.h) -0 0 0 1 1 1 0 0 0 1 1 v v v v v P P 0 u u u u u 1 1 0 d d d d d Vdd.w=vadd(Vuu.w,Vvv.w) -0 0 0 1 1 1 0 0 0 1 1 v v v v v P P 0 u u u u u 1 1 1 d d d d d Vdd.ub=vadd(Vuu.ub,Vvv.ub):sat -0 0 0 1 1 1 0 0 1 0 0 v v v v v P P 0 u u u u u 0 0 0 d d d d d Vdd.uh=vadd(Vuu.uh,Vvv.uh):sat -0 0 0 1 1 1 0 0 1 0 0 v v v v v P P 0 u u u u u 0 0 1 d d d d d Vdd.h=vadd(Vuu.h,Vvv.h):sat -0 0 0 1 1 1 0 0 1 0 0 v v v v v P P 0 u u u u u 0 1 0 d d d d d Vdd.w=vadd(Vuu.w,Vvv.w):sat -0 0 0 1 1 1 0 0 1 0 0 v v v v v P P 0 u u u u u 0 1 1 d d d d d Vdd.b=vsub(Vuu.b,Vvv.b) -0 0 0 1 1 1 0 0 1 0 0 v v v v v P P 0 u u u u u 1 0 0 d d d d d Vdd.h=vsub(Vuu.h,Vvv.h) -0 0 0 1 1 1 0 0 1 0 0 v v v v v P P 0 u u u u u 1 0 1 d d d d d Vdd.w=vsub(Vuu.w,Vvv.w) -0 0 0 1 1 1 0 0 1 0 0 v v v v v P P 0 u u u u u 1 1 0 d d d d d Vdd.ub=vsub(Vuu.ub,Vvv.ub):sat -0 0 0 1 1 1 0 0 1 0 0 v v v v v P P 0 u u u u u 1 1 1 d d d d d Vdd.uh=vsub(Vuu.uh,Vvv.uh):sat -0 0 0 1 1 1 0 0 1 0 1 v v v v v P P 0 u u u u u 0 0 0 d d d d d Vdd.h=vsub(Vuu.h,Vvv.h):sat -0 0 0 1 1 1 0 0 1 0 1 v v v v v P P 0 u u u u u 0 0 1 d d d d d Vdd.w=vsub(Vuu.w,Vvv.w):sat -0 0 0 1 1 1 1 0 1 0 1 v v v v v P P 0 u u u u u 0 0 0 d d d d d Vdd.b=vadd(Vuu.b,Vvv.b):sat -0 0 0 1 1 1 1 0 1 0 1 v v v v v P P 0 u u u u u 0 0 1 d d d d d Vdd.b=vsub(Vuu.b,Vvv.b):sat -0 0 0 1 1 1 1 0 1 0 1 v v v v v P P 0 u u u u u 0 1 0 d d d d d Vdd.uw=vadd(Vuu.uw,Vvv.uw):sat -0 0 0 1 1 1 1 0 1 0 1 v v v v v P P 0 u u u u u 0 1 1 d d d d d Vdd.uw=vsub(Vuu.uw,Vvv.uw):sat -0 0 0 1 1 1 1 0 - - 0 - - - 1 1 P P 0 - - - s s 0 0 0 0 1 0 d d Qd4=not(Qs4) -0 0 0 1 1 1 1 0 v v 0 - - 0 1 1 P P 1 u u u u u 0 0 0 d d d d d Vd=vand(Qv4,Vu) -0 0 0 1 1 1 1 0 v v 0 - - 0 1 1 P P 1 u u u u u 0 0 1 d d d d d Vd=vand(!Qv4,Vu) -0 0 0 1 1 1 1 1 0 0 0 v v v v v P P 0 u u u u u 0 0 1 d d d d d Vd.ub=vmin(Vu.ub,Vv.ub) -0 0 0 1 1 1 1 1 0 0 0 v v v v v P P 0 u u u u u 0 1 0 d d d d d Vd.uh=vmin(Vu.uh,Vv.uh) -0 0 0 1 1 1 1 1 0 0 0 v v v v v P P 0 u u u u u 0 1 1 d d d d d Vd.h=vmin(Vu.h,Vv.h) -0 0 0 1 1 1 1 1 0 0 0 v v v v v P P 0 u u u u u 1 0 0 d d d d d Vd.w=vmin(Vu.w,Vv.w) -0 0 0 1 1 1 1 1 0 0 0 v v v v v P P 0 u u u u u 1 0 1 d d d d d Vd.ub=vmax(Vu.ub,Vv.ub) -0 0 0 1 1 1 1 1 0 0 0 v v v v v P P 0 u u u u u 1 1 0 d d d d d Vd.uh=vmax(Vu.uh,Vv.uh) -0 0 0 1 1 1 1 1 0 0 0 v v v v v P P 0 u u u u u 1 1 1 d d d d d Vd.h=vmax(Vu.h,Vv.h) -0 0 0 1 1 1 1 1 0 0 1 v v v v v P P 0 u u u u u 0 0 0 d d d d d Vd.w=vmax(Vu.w,Vv.w) -0 0 0 1 1 1 1 1 0 0 1 v v v v v P P 0 u u u u u 1 0 0 d d d d d Vd.b=vmin(Vu.b,Vv.b) -0 0 0 1 1 1 1 1 0 0 1 v v v v v P P 0 u u u u u 1 0 1 d d d d d Vd.b=vmax(Vu.b,Vv.b) -0 0 0 1 1 1 1 1 1 1 0 v v v v v P P 1 u u u u u 0 0 1 d d d d d Vd.sf=vmax(Vu.sf,Vv.sf) -0 0 0 1 1 1 1 1 1 1 0 v v v v v P P 1 u u u u u 0 1 0 d d d d d Vd.sf=vmin(Vu.sf,Vv.sf) -0 0 0 1 1 1 1 1 1 1 0 v v v v v P P 1 u u u u u 0 1 1 d d d d d Vd.hf=vmax(Vu.hf,Vv.hf) -0 0 0 1 1 1 1 1 1 1 0 v v v v v P P 1 u u u u u 1 0 0 d d d d d Vd.hf=vmin(Vu.hf,Vv.hf) -0 0 0 1 1 1 1 0 - - 0 - - - 0 0 P P 0 u u u u u 0 0 0 d d d d d Vd.h=vabs(Vu.h) -0 0 0 1 1 1 1 0 - - 0 - - - 0 0 P P 0 u u u u u 0 0 1 d d d d d Vd.h=vabs(Vu.h):sat -0 0 0 1 1 1 1 0 - - 0 - - - 0 0 P P 0 u u u u u 0 1 0 d d d d d Vd.w=vabs(Vu.w) -0 0 0 1 1 1 1 0 - - 0 - - - 0 0 P P 0 u u u u u 0 1 1 d d d d d Vd.w=vabs(Vu.w):sat -0 0 0 1 1 1 1 0 - - 0 - - - 0 1 P P 0 u u u u u 1 0 0 d d d d d Vd.b=vabs(Vu.b) -0 0 0 1 1 1 1 0 - - 0 - - - 0 1 P P 0 u u u u u 1 0 1 d d d d d Vd.b=vabs(Vu.b):sat -0 0 0 1 1 1 0 0 0 1 0 v v v v v P P 0 u u u u u 0 0 0 d d d d d Vd.w=vadd(Vu.w,Vv.w) -0 0 0 1 1 1 0 0 0 1 0 v v v v v P P 0 u u u u u 0 0 1 d d d d d Vd.ub=vadd(Vu.ub,Vv.ub):sat -0 0 0 1 1 1 0 0 0 1 0 v v v v v P P 0 u u u u u 0 1 0 d d d d d Vd.uh=vadd(Vu.uh,Vv.uh):sat -0 0 0 1 1 1 0 0 0 1 0 v v v v v P P 0 u u u u u 0 1 1 d d d d d Vd.h=vadd(Vu.h,Vv.h):sat -0 0 0 1 1 1 0 0 0 1 0 v v v v v P P 0 u u u u u 1 0 0 d d d d d Vd.w=vadd(Vu.w,Vv.w):sat -0 0 0 1 1 1 0 0 0 1 0 v v v v v P P 0 u u u u u 1 0 1 d d d d d Vd.b=vsub(Vu.b,Vv.b) -0 0 0 1 1 1 0 0 0 1 0 v v v v v P P 0 u u u u u 1 1 0 d d d d d Vd.h=vsub(Vu.h,Vv.h) -0 0 0 1 1 1 0 0 0 1 0 v v v v v P P 0 u u u u u 1 1 1 d d d d d Vd.w=vsub(Vu.w,Vv.w) -0 0 0 1 1 1 0 0 0 1 1 v v v v v P P 0 u u u u u 0 0 0 d d d d d Vd.ub=vsub(Vu.ub,Vv.ub):sat -0 0 0 1 1 1 0 0 0 1 1 v v v v v P P 0 u u u u u 0 0 1 d d d d d Vd.uh=vsub(Vu.uh,Vv.uh):sat -0 0 0 1 1 1 0 0 0 1 1 v v v v v P P 0 u u u u u 0 1 0 d d d d d Vd.h=vsub(Vu.h,Vv.h):sat -0 0 0 1 1 1 0 0 0 1 1 v v v v v P P 0 u u u u u 0 1 1 d d d d d Vd.w=vsub(Vu.w,Vv.w):sat -0 0 0 1 1 1 1 0 1 0 1 v v v v v P P 0 u u u u u 1 0 0 d d d d d Vd.ub=vadd(Vu.ub,Vv.b):sat -0 0 0 1 1 1 1 0 1 0 1 v v v v v P P 0 u u u u u 1 0 1 d d d d d Vd.ub=vsub(Vu.ub,Vv.b):sat -0 0 0 1 1 1 1 1 0 0 0 v v v v v P P 0 u u u u u 0 0 0 d d d d d Vd.b=vadd(Vu.b,Vv.b):sat -0 0 0 1 1 1 1 1 0 0 1 v v v v v P P 0 u u u u u 0 1 0 d d d d d Vd.b=vsub(Vu.b,Vv.b):sat -0 0 0 1 1 1 1 1 0 1 1 v v v v v P P 0 u u u u u 0 0 1 d d d d d Vd.uw=vadd(Vu.uw,Vv.uw):sat -0 0 0 1 1 1 1 1 1 0 1 v v v v v P P 0 u u u u u 1 1 0 d d d d d Vd.b=vadd(Vu.b,Vv.b) -0 0 0 1 1 1 1 1 1 0 1 v v v v v P P 0 u u u u u 1 1 1 d d d d d Vd.h=vadd(Vu.h,Vv.h) -0 0 0 1 1 1 1 1 1 1 0 v v v v v P P 0 u u u u u 1 0 0 d d d d d Vd.uw=vsub(Vu.uw,Vv.uw):sat -0 0 0 1 1 1 0 0 1 0 1 v v v v v P P 1 u u u u u 0 x x d d d d d Vd.w=vadd(Vu.w,Vv.w,Qx4):carry -0 0 0 1 1 1 0 0 1 0 1 v v v v v P P 1 u u u u u 1 x x d d d d d Vd.w=vsub(Vu.w,Vv.w,Qx4):carry -0 0 0 1 1 1 0 1 1 0 0 v v v v v P P 1 u u u u u 0 s s d d d d d Vd.w=vadd(Vu.w,Vv.w,Qs4):carry:sat -0 0 0 1 1 1 0 1 1 0 1 v v v v v P P 1 u u u u u 0 e e d d d d d Vd.w,Qe4=vadd(Vu.w,Vv.w):carry -0 0 0 1 1 1 0 1 1 0 1 v v v v v P P 1 u u u u u 1 e e d d d d d Vd.w,Qe4=vsub(Vu.w,Vv.w):carry -1 1 0 0 0 0 1 0 1 1 0 s s s s s P P - t t t t t - x x d d d d d Rdd=add(Rss,Rtt,Px):carry -1 1 0 0 0 0 1 0 1 1 1 s s s s s P P - t t t t t - x x d d d d d Rdd=sub(Rss,Rtt,Px):carry -0 0 0 1 1 1 0 0 0 0 1 v v v v v P P 0 u u u u u 1 0 1 d d d d d Vd=vand(Vu,Vv) -0 0 0 1 1 1 0 0 0 0 1 v v v v v P P 0 u u u u u 1 1 0 d d d d d Vd=vor(Vu,Vv) -0 0 0 1 1 1 0 0 0 0 1 v v v v v P P 0 u u u u u 1 1 1 d d d d d Vd=vxor(Vu,Vv) -0 0 0 1 1 1 1 0 - - 0 - - - 0 0 P P 0 u u u u u 1 0 0 d d d d d Vd=vnot(Vu) -0 0 0 1 1 0 1 0 0 0 0 - - - - - P P - u u u u u - s s d d d d d if (Ps) Vd=Vu -0 0 0 1 1 0 1 0 0 0 1 - - - - - P P - u u u u u - s s d d d d d if (!Ps) Vd=Vu -0 0 0 1 1 1 1 0 - - 0 - - 0 1 1 P P 1 u u u u u 1 1 1 d d d d d Vd=Vu -0 0 0 1 1 1 1 0 - - 0 - - - 0 1 P P 0 u u u u u 1 1 0 d d d d d Vd.tmp=Vu -0 0 0 1 1 1 1 0 1 0 1 v v v v v P P 0 u u u u u 1 1 1 d d d d d Vdd.tmp=vcombine(Vu,Vv) -0 0 0 1 1 1 0 0 1 1 0 v v v v v P P 0 u u u u u 1 0 0 d d d d d Vd.ub=vavg(Vu.ub,Vv.ub) -0 0 0 1 1 1 0 0 1 1 0 v v v v v P P 0 u u u u u 1 0 1 d d d d d Vd.uh=vavg(Vu.uh,Vv.uh) -0 0 0 1 1 1 0 0 1 1 0 v v v v v P P 0 u u u u u 1 1 0 d d d d d Vd.h=vavg(Vu.h,Vv.h) -0 0 0 1 1 1 0 0 1 1 0 v v v v v P P 0 u u u u u 1 1 1 d d d d d Vd.w=vavg(Vu.w,Vv.w) -0 0 0 1 1 1 0 0 1 1 1 v v v v v P P 0 u u u u u 0 0 0 d d d d d Vd.b=vnavg(Vu.ub,Vv.ub) -0 0 0 1 1 1 0 0 1 1 1 v v v v v P P 0 u u u u u 0 0 1 d d d d d Vd.h=vnavg(Vu.h,Vv.h) -0 0 0 1 1 1 0 0 1 1 1 v v v v v P P 0 u u u u u 0 1 0 d d d d d Vd.w=vnavg(Vu.w,Vv.w) -0 0 0 1 1 1 0 0 1 1 1 v v v v v P P 0 u u u u u 0 1 1 d d d d d Vd.ub=vavg(Vu.ub,Vv.ub):rnd -0 0 0 1 1 1 0 0 1 1 1 v v v v v P P 0 u u u u u 1 0 0 d d d d d Vd.uh=vavg(Vu.uh,Vv.uh):rnd -0 0 0 1 1 1 0 0 1 1 1 v v v v v P P 0 u u u u u 1 0 1 d d d d d Vd.h=vavg(Vu.h,Vv.h):rnd -0 0 0 1 1 1 0 0 1 1 1 v v v v v P P 0 u u u u u 1 1 0 d d d d d Vd.w=vavg(Vu.w,Vv.w):rnd -0 0 0 1 1 1 1 1 0 0 0 v v v v v P P 1 u u u u u 0 1 0 d d d d d Vd.uw=vavg(Vu.uw,Vv.uw) -0 0 0 1 1 1 1 1 0 0 0 v v v v v P P 1 u u u u u 0 1 1 d d d d d Vd.uw=vavg(Vu.uw,Vv.uw):rnd -0 0 0 1 1 1 1 1 0 0 0 v v v v v P P 1 u u u u u 1 0 0 d d d d d Vd.b=vavg(Vu.b,Vv.b) -0 0 0 1 1 1 1 1 0 0 0 v v v v v P P 1 u u u u u 1 0 1 d d d d d Vd.b=vavg(Vu.b,Vv.b):rnd -0 0 0 1 1 1 1 1 0 0 0 v v v v v P P 1 u u u u u 1 1 0 d d d d d Vd.b=vnavg(Vu.b,Vv.b) -0 0 0 1 1 1 0 0 1 0 0 v v v v v P P 1 u u u u u 0 0 0 0 0 0 x x Qx4&=vcmp.eq(Vu.b,Vv.b) -0 0 0 1 1 1 0 0 1 0 0 v v v v v P P 1 u u u u u 0 0 0 0 0 1 x x Qx4&=vcmp.eq(Vu.h,Vv.h) -0 0 0 1 1 1 0 0 1 0 0 v v v v v P P 1 u u u u u 0 0 0 0 1 0 x x Qx4&=vcmp.eq(Vu.w,Vv.w) -0 0 0 1 1 1 0 0 1 0 0 v v v v v P P 1 u u u u u 0 0 0 1 0 0 x x Qx4&=vcmp.gt(Vu.b,Vv.b) -0 0 0 1 1 1 0 0 1 0 0 v v v v v P P 1 u u u u u 0 0 0 1 0 1 x x Qx4&=vcmp.gt(Vu.h,Vv.h) -0 0 0 1 1 1 0 0 1 0 0 v v v v v P P 1 u u u u u 0 0 0 1 1 0 x x Qx4&=vcmp.gt(Vu.w,Vv.w) -0 0 0 1 1 1 0 0 1 0 0 v v v v v P P 1 u u u u u 0 0 1 0 0 0 x x Qx4&=vcmp.gt(Vu.ub,Vv.ub) -0 0 0 1 1 1 0 0 1 0 0 v v v v v P P 1 u u u u u 0 0 1 0 0 1 x x Qx4&=vcmp.gt(Vu.uh,Vv.uh) -0 0 0 1 1 1 0 0 1 0 0 v v v v v P P 1 u u u u u 0 0 1 0 1 0 x x Qx4&=vcmp.gt(Vu.uw,Vv.uw) -0 0 0 1 1 1 0 0 1 0 0 v v v v v P P 1 u u u u u 0 0 1 1 0 0 x x Qx4|=vcmp.gt(Vu.sf,Vv.sf) -0 0 0 1 1 1 0 0 1 0 0 v v v v v P P 1 u u u u u 0 0 1 1 0 1 x x Qx4|=vcmp.gt(Vu.hf,Vv.hf) -0 0 0 1 1 1 0 0 1 0 0 v v v v v P P 1 u u u u u 0 1 0 0 0 0 x x Qx4|=vcmp.eq(Vu.b,Vv.b) -0 0 0 1 1 1 0 0 1 0 0 v v v v v P P 1 u u u u u 0 1 0 0 0 1 x x Qx4|=vcmp.eq(Vu.h,Vv.h) -0 0 0 1 1 1 0 0 1 0 0 v v v v v P P 1 u u u u u 0 1 0 0 1 0 x x Qx4|=vcmp.eq(Vu.w,Vv.w) -0 0 0 1 1 1 0 0 1 0 0 v v v v v P P 1 u u u u u 0 1 0 1 0 0 x x Qx4|=vcmp.gt(Vu.b,Vv.b) -0 0 0 1 1 1 0 0 1 0 0 v v v v v P P 1 u u u u u 0 1 0 1 0 1 x x Qx4|=vcmp.gt(Vu.h,Vv.h) -0 0 0 1 1 1 0 0 1 0 0 v v v v v P P 1 u u u u u 0 1 0 1 1 0 x x Qx4|=vcmp.gt(Vu.w,Vv.w) -0 0 0 1 1 1 0 0 1 0 0 v v v v v P P 1 u u u u u 0 1 1 0 0 0 x x Qx4|=vcmp.gt(Vu.ub,Vv.ub) -0 0 0 1 1 1 0 0 1 0 0 v v v v v P P 1 u u u u u 0 1 1 0 0 1 x x Qx4|=vcmp.gt(Vu.uh,Vv.uh) -0 0 0 1 1 1 0 0 1 0 0 v v v v v P P 1 u u u u u 0 1 1 0 1 0 x x Qx4|=vcmp.gt(Vu.uw,Vv.uw) -0 0 0 1 1 1 0 0 1 0 0 v v v v v P P 1 u u u u u 0 1 1 1 0 0 d d Qd4=vcmp.gt(Vu.sf,Vv.sf) -0 0 0 1 1 1 0 0 1 0 0 v v v v v P P 1 u u u u u 0 1 1 1 0 1 d d Qd4=vcmp.gt(Vu.hf,Vv.hf) -0 0 0 1 1 1 0 0 1 0 0 v v v v v P P 1 u u u u u 1 0 0 0 0 0 x x Qx4^=vcmp.eq(Vu.b,Vv.b) -0 0 0 1 1 1 0 0 1 0 0 v v v v v P P 1 u u u u u 1 0 0 0 0 1 x x Qx4^=vcmp.eq(Vu.h,Vv.h) -0 0 0 1 1 1 0 0 1 0 0 v v v v v P P 1 u u u u u 1 0 0 0 1 0 x x Qx4^=vcmp.eq(Vu.w,Vv.w) -0 0 0 1 1 1 0 0 1 0 0 v v v v v P P 1 u u u u u 1 0 0 1 0 0 x x Qx4^=vcmp.gt(Vu.b,Vv.b) -0 0 0 1 1 1 0 0 1 0 0 v v v v v P P 1 u u u u u 1 0 0 1 0 1 x x Qx4^=vcmp.gt(Vu.h,Vv.h) -0 0 0 1 1 1 0 0 1 0 0 v v v v v P P 1 u u u u u 1 0 0 1 1 0 x x Qx4^=vcmp.gt(Vu.w,Vv.w) -0 0 0 1 1 1 0 0 1 0 0 v v v v v P P 1 u u u u u 1 0 1 0 0 0 x x Qx4^=vcmp.gt(Vu.ub,Vv.ub) -0 0 0 1 1 1 0 0 1 0 0 v v v v v P P 1 u u u u u 1 0 1 0 0 1 x x Qx4^=vcmp.gt(Vu.uh,Vv.uh) -0 0 0 1 1 1 0 0 1 0 0 v v v v v P P 1 u u u u u 1 0 1 0 1 0 x x Qx4^=vcmp.gt(Vu.uw,Vv.uw) -0 0 0 1 1 1 0 0 1 0 0 v v v v v P P 1 u u u u u 1 1 0 0 1 0 x x Qx4&=vcmp.gt(Vu.sf,Vv.sf) -0 0 0 1 1 1 0 0 1 0 0 v v v v v P P 1 u u u u u 1 1 0 0 1 1 x x Qx4&=vcmp.gt(Vu.hf,Vv.hf) -0 0 0 1 1 1 0 0 1 0 0 v v v v v P P 1 u u u u u 1 1 1 0 1 0 x x Qx4^=vcmp.gt(Vu.sf,Vv.sf) -0 0 0 1 1 1 0 0 1 0 0 v v v v v P P 1 u u u u u 1 1 1 0 1 1 x x Qx4^=vcmp.gt(Vu.hf,Vv.hf) -0 0 0 1 1 1 1 1 1 0 0 v v v v v P P 0 u u u u u 0 0 0 0 0 0 d d Qd4=vcmp.eq(Vu.b,Vv.b) -0 0 0 1 1 1 1 1 1 0 0 v v v v v P P 0 u u u u u 0 0 0 0 0 1 d d Qd4=vcmp.eq(Vu.h,Vv.h) -0 0 0 1 1 1 1 1 1 0 0 v v v v v P P 0 u u u u u 0 0 0 0 1 0 d d Qd4=vcmp.eq(Vu.w,Vv.w) -0 0 0 1 1 1 1 1 1 0 0 v v v v v P P 0 u u u u u 0 0 0 1 0 0 d d Qd4=vcmp.gt(Vu.b,Vv.b) -0 0 0 1 1 1 1 1 1 0 0 v v v v v P P 0 u u u u u 0 0 0 1 0 1 d d Qd4=vcmp.gt(Vu.h,Vv.h) -0 0 0 1 1 1 1 1 1 0 0 v v v v v P P 0 u u u u u 0 0 0 1 1 0 d d Qd4=vcmp.gt(Vu.w,Vv.w) -0 0 0 1 1 1 1 1 1 0 0 v v v v v P P 0 u u u u u 0 0 1 0 0 0 d d Qd4=vcmp.gt(Vu.ub,Vv.ub) -0 0 0 1 1 1 1 1 1 0 0 v v v v v P P 0 u u u u u 0 0 1 0 0 1 d d Qd4=vcmp.gt(Vu.uh,Vv.uh) -0 0 0 1 1 1 1 1 1 0 0 v v v v v P P 0 u u u u u 0 0 1 0 1 0 d d Qd4=vcmp.gt(Vu.uw,Vv.uw) -0 0 0 1 1 1 1 0 v v 0 - - 0 0 1 P P 1 u u u u u 0 0 0 x x x x x if (Qv4) Vx.b+=Vu.b -0 0 0 1 1 1 1 0 v v 0 - - 0 0 1 P P 1 u u u u u 0 0 1 x x x x x if (Qv4) Vx.h+=Vu.h -0 0 0 1 1 1 1 0 v v 0 - - 0 0 1 P P 1 u u u u u 0 1 0 x x x x x if (Qv4) Vx.w+=Vu.w -0 0 0 1 1 1 1 0 v v 0 - - 0 0 1 P P 1 u u u u u 0 1 1 x x x x x if (!Qv4) Vx.b+=Vu.b -0 0 0 1 1 1 1 0 v v 0 - - 0 0 1 P P 1 u u u u u 1 0 0 x x x x x if (!Qv4) Vx.h+=Vu.h -0 0 0 1 1 1 1 0 v v 0 - - 0 0 1 P P 1 u u u u u 1 0 1 x x x x x if (!Qv4) Vx.w+=Vu.w -0 0 0 1 1 1 1 0 v v 0 - - 0 0 1 P P 1 u u u u u 1 1 0 x x x x x if (Qv4) Vx.b-=Vu.b -0 0 0 1 1 1 1 0 v v 0 - - 0 0 1 P P 1 u u u u u 1 1 1 x x x x x if (Qv4) Vx.h-=Vu.h -0 0 0 1 1 1 1 0 v v 0 - - 0 1 0 P P 1 u u u u u 0 0 0 x x x x x if (Qv4) Vx.w-=Vu.w -0 0 0 1 1 1 1 0 v v 0 - - 0 1 0 P P 1 u u u u u 0 0 1 x x x x x if (!Qv4) Vx.b-=Vu.b -0 0 0 1 1 1 1 0 v v 0 - - 0 1 0 P P 1 u u u u u 0 1 0 x x x x x if (!Qv4) Vx.h-=Vu.h -0 0 0 1 1 1 1 0 v v 0 - - 0 1 0 P P 1 u u u u u 0 1 1 x x x x x if (!Qv4) Vx.w-=Vu.w -0 0 0 1 1 1 1 0 1 1 1 v v v v v P P 1 u u u u u - t t d d d d d Vd=vmux(Qt4,Vu,Vv) -0 0 0 1 1 1 0 1 1 0 0 v v v v v P P 1 u u u u u 1 1 1 d d d d d Vd.w=vsatdw(Vu.w,Vv.w) -0 0 0 1 1 1 1 1 0 0 1 v v v v v P P 0 u u u u u 1 1 0 d d d d d Vd.uh=vsat(Vu.uw,Vv.uw) -0 0 0 1 1 1 1 1 0 1 1 v v v v v P P 0 u u u u u 0 1 0 d d d d d Vd.ub=vsat(Vu.h,Vv.h) -0 0 0 1 1 1 1 1 0 1 1 v v v v v P P 0 u u u u u 0 1 1 d d d d d Vd.h=vsat(Vu.w,Vv.w) -0 0 0 1 1 1 1 1 0 1 0 v v v v v P P 0 u u u u u 0 0 1 d d d d d Vd.b=vshuffe(Vu.b,Vv.b) -0 0 0 1 1 1 1 1 0 1 0 v v v v v P P 0 u u u u u 0 1 0 d d d d d Vd.b=vshuffo(Vu.b,Vv.b) -0 0 0 1 1 1 1 1 0 1 0 v v v v v P P 0 u u u u u 0 1 1 d d d d d Vd.h=vshuffe(Vu.h,Vv.h) -0 0 0 1 1 1 1 1 0 1 0 v v v v v P P 0 u u u u u 1 0 0 d d d d d Vd.h=vshuffo(Vu.h,Vv.h) -1 0 0 1 0 0 1 0 0 0 0 s s s s s P P 0 u u u u u 0 0 1 d d d d d Rd=vextract(Vu,Rs) -0 0 1 0 1 1 1 1 0 0 0 t t t t t P P u - - 0 1 0 - - - v v v v v vtmp.h=vgather(Rt,Mu,Vvv.w).h -0 0 1 0 1 1 1 1 0 0 0 t t t t t P P u - - 1 1 0 - s s v v v v v if (Qs4) vtmp.h=vgather(Rt,Mu,Vvv.w).h -0 0 1 0 1 1 1 1 0 0 0 t t t t t P P u - - 0 0 0 - - - v v v v v vtmp.w=vgather(Rt,Mu,Vv.w).w -0 0 1 0 1 1 1 1 0 0 0 t t t t t P P u - - 0 0 1 - - - v v v v v vtmp.h=vgather(Rt,Mu,Vv.h).h -0 0 1 0 1 1 1 1 0 0 0 t t t t t P P u - - 1 0 0 - s s v v v v v if (Qs4) vtmp.w=vgather(Rt,Mu,Vv.w).w -0 0 1 0 1 1 1 1 0 0 0 t t t t t P P u - - 1 0 1 - s s v v v v v if (Qs4) vtmp.h=vgather(Rt,Mu,Vv.h).h -0 0 1 0 1 0 0 0 0 0 0 t t t t t P P i 0 0 i i i 0 0 0 d d d d d Vd=vmem(Rt+#s4) -0 0 1 0 1 0 0 0 0 1 0 t t t t t P P i 0 0 i i i 0 0 0 d d d d d Vd=vmem(Rt+#s4):nt -0 0 1 0 1 0 0 0 1 0 0 t t t t t P P i v v i i i 0 1 0 d d d d d if (Pv) Vd=vmem(Rt+#s4) -0 0 1 0 1 0 0 0 1 0 0 t t t t t P P i v v i i i 0 1 1 d d d d d if (!Pv) Vd=vmem(Rt+#s4) -0 0 1 0 1 0 0 0 1 1 0 t t t t t P P i v v i i i 0 1 0 d d d d d if (Pv) Vd=vmem(Rt+#s4):nt -0 0 1 0 1 0 0 0 1 1 0 t t t t t P P i v v i i i 0 1 1 d d d d d if (!Pv) Vd=vmem(Rt+#s4):nt -0 0 1 0 1 0 0 1 0 0 0 x x x x x P P - 0 0 i i i 0 0 0 d d d d d Vd=vmem(Rx++#s3) -0 0 1 0 1 0 0 1 0 1 0 x x x x x P P - 0 0 i i i 0 0 0 d d d d d Vd=vmem(Rx++#s3):nt -0 0 1 0 1 0 0 1 1 0 0 x x x x x P P - v v i i i 0 1 0 d d d d d if (Pv) Vd=vmem(Rx++#s3) -0 0 1 0 1 0 0 1 1 0 0 x x x x x P P - v v i i i 0 1 1 d d d d d if (!Pv) Vd=vmem(Rx++#s3) -0 0 1 0 1 0 0 1 1 1 0 x x x x x P P - v v i i i 0 1 0 d d d d d if (Pv) Vd=vmem(Rx++#s3):nt -0 0 1 0 1 0 0 1 1 1 0 x x x x x P P - v v i i i 0 1 1 d d d d d if (!Pv) Vd=vmem(Rx++#s3):nt -0 0 1 0 1 0 1 1 0 0 0 x x x x x P P u 0 0 - - - 0 0 0 d d d d d Vd=vmem(Rx++Mu) -0 0 1 0 1 0 1 1 0 1 0 x x x x x P P u 0 0 - - - 0 0 0 d d d d d Vd=vmem(Rx++Mu):nt -0 0 1 0 1 0 1 1 1 0 0 x x x x x P P u v v - - - 0 1 0 d d d d d if (Pv) Vd=vmem(Rx++Mu) -0 0 1 0 1 0 1 1 1 0 0 x x x x x P P u v v - - - 0 1 1 d d d d d if (!Pv) Vd=vmem(Rx++Mu) -0 0 1 0 1 0 1 1 1 1 0 x x x x x P P u v v - - - 0 1 0 d d d d d if (Pv) Vd=vmem(Rx++Mu):nt -0 0 1 0 1 0 1 1 1 1 0 x x x x x P P u v v - - - 0 1 1 d d d d d if (!Pv) Vd=vmem(Rx++Mu):nt -0 0 1 0 1 0 0 0 0 0 0 t t t t t P P i 0 0 i i i 0 0 1 d d d d d Vd.cur=vmem(Rt+#s4) -0 0 1 0 1 0 0 0 0 1 0 t t t t t P P i 0 0 i i i 0 0 1 d d d d d Vd.cur=vmem(Rt+#s4):nt -0 0 1 0 1 0 0 0 1 0 0 t t t t t P P i v v i i i 1 0 0 d d d d d if (Pv) Vd.cur=vmem(Rt+#s4) -0 0 1 0 1 0 0 0 1 0 0 t t t t t P P i v v i i i 1 0 1 d d d d d if (!Pv) Vd.cur=vmem(Rt+#s4) -0 0 1 0 1 0 0 0 1 1 0 t t t t t P P i v v i i i 1 0 0 d d d d d if (Pv) Vd.cur=vmem(Rt+#s4):nt -0 0 1 0 1 0 0 0 1 1 0 t t t t t P P i v v i i i 1 0 1 d d d d d if (!Pv) Vd.cur=vmem(Rt+#s4):nt -0 0 1 0 1 0 0 1 0 0 0 x x x x x P P - 0 0 i i i 0 0 1 d d d d d Vd.cur=vmem(Rx++#s3) -0 0 1 0 1 0 0 1 0 1 0 x x x x x P P - 0 0 i i i 0 0 1 d d d d d Vd.cur=vmem(Rx++#s3):nt -0 0 1 0 1 0 0 1 1 0 0 x x x x x P P - v v i i i 1 0 0 d d d d d if (Pv) Vd.cur=vmem(Rx++#s3) -0 0 1 0 1 0 0 1 1 0 0 x x x x x P P - v v i i i 1 0 1 d d d d d if (!Pv) Vd.cur=vmem(Rx++#s3) -0 0 1 0 1 0 0 1 1 1 0 x x x x x P P - v v i i i 1 0 0 d d d d d if (Pv) Vd.cur=vmem(Rx++#s3):nt -0 0 1 0 1 0 0 1 1 1 0 x x x x x P P - v v i i i 1 0 1 d d d d d if (!Pv) Vd.cur=vmem(Rx++#s3):nt -0 0 1 0 1 0 1 1 0 0 0 x x x x x P P u 0 0 - - - 0 0 1 d d d d d Vd.cur=vmem(Rx++Mu) -0 0 1 0 1 0 1 1 0 1 0 x x x x x P P u 0 0 - - - 0 0 1 d d d d d Vd.cur=vmem(Rx++Mu):nt -0 0 1 0 1 0 1 1 1 0 0 x x x x x P P u v v - - - 1 0 0 d d d d d if (Pv) Vd.cur=vmem(Rx++Mu) -0 0 1 0 1 0 1 1 1 0 0 x x x x x P P u v v - - - 1 0 1 d d d d d if (!Pv) Vd.cur=vmem(Rx++Mu) -0 0 1 0 1 0 1 1 1 1 0 x x x x x P P u v v - - - 1 0 0 d d d d d if (Pv) Vd.cur=vmem(Rx++Mu):nt -0 0 1 0 1 0 1 1 1 1 0 x x x x x P P u v v - - - 1 0 1 d d d d d if (!Pv) Vd.cur=vmem(Rx++Mu):nt -0 0 1 0 1 0 0 0 0 0 0 t t t t t P P i 0 0 i i i 0 1 0 d d d d d Vd.tmp=vmem(Rt+#s4) -0 0 1 0 1 0 0 0 0 1 0 t t t t t P P i 0 0 i i i 0 1 0 d d d d d Vd.tmp=vmem(Rt+#s4):nt -0 0 1 0 1 0 0 0 1 0 0 t t t t t P P i v v i i i 1 1 0 d d d d d if (Pv) Vd.tmp=vmem(Rt+#s4) -0 0 1 0 1 0 0 0 1 0 0 t t t t t P P i v v i i i 1 1 1 d d d d d if (!Pv) Vd.tmp=vmem(Rt+#s4) -0 0 1 0 1 0 0 0 1 1 0 t t t t t P P i v v i i i 1 1 0 d d d d d if (Pv) Vd.tmp=vmem(Rt+#s4):nt -0 0 1 0 1 0 0 0 1 1 0 t t t t t P P i v v i i i 1 1 1 d d d d d if (!Pv) Vd.tmp=vmem(Rt+#s4):nt -0 0 1 0 1 0 0 1 0 0 0 x x x x x P P - 0 0 i i i 0 1 0 d d d d d Vd.tmp=vmem(Rx++#s3) -0 0 1 0 1 0 0 1 0 1 0 x x x x x P P - 0 0 i i i 0 1 0 d d d d d Vd.tmp=vmem(Rx++#s3):nt -0 0 1 0 1 0 0 1 1 0 0 x x x x x P P - v v i i i 1 1 0 d d d d d if (Pv) Vd.tmp=vmem(Rx++#s3) -0 0 1 0 1 0 0 1 1 0 0 x x x x x P P - v v i i i 1 1 1 d d d d d if (!Pv) Vd.tmp=vmem(Rx++#s3) -0 0 1 0 1 0 0 1 1 1 0 x x x x x P P - v v i i i 1 1 0 d d d d d if (Pv) Vd.tmp=vmem(Rx++#s3):nt -0 0 1 0 1 0 0 1 1 1 0 x x x x x P P - v v i i i 1 1 1 d d d d d if (!Pv) Vd.tmp=vmem(Rx++#s3):nt -0 0 1 0 1 0 1 1 0 0 0 x x x x x P P u 0 0 - - - 0 1 0 d d d d d Vd.tmp=vmem(Rx++Mu) -0 0 1 0 1 0 1 1 0 1 0 x x x x x P P u 0 0 - - - 0 1 0 d d d d d Vd.tmp=vmem(Rx++Mu):nt -0 0 1 0 1 0 1 1 1 0 0 x x x x x P P u v v - - - 1 1 0 d d d d d if (Pv) Vd.tmp=vmem(Rx++Mu) -0 0 1 0 1 0 1 1 1 0 0 x x x x x P P u v v - - - 1 1 1 d d d d d if (!Pv) Vd.tmp=vmem(Rx++Mu) -0 0 1 0 1 0 1 1 1 1 0 x x x x x P P u v v - - - 1 1 0 d d d d d if (Pv) Vd.tmp=vmem(Rx++Mu):nt -0 0 1 0 1 0 1 1 1 1 0 x x x x x P P u v v - - - 1 1 1 d d d d d if (!Pv) Vd.tmp=vmem(Rx++Mu):nt -0 0 1 0 1 0 0 0 0 0 0 t t t t t P P i 0 0 i i i 1 1 1 d d d d d Vd=vmemu(Rt+#s4) -0 0 1 0 1 0 0 1 0 0 0 x x x x x P P - 0 0 i i i 1 1 1 d d d d d Vd=vmemu(Rx++#s3) -0 0 1 0 1 0 1 1 0 0 0 x x x x x P P u 0 0 - - - 1 1 1 d d d d d Vd=vmemu(Rx++Mu) -0 0 0 1 1 1 1 1 0 0 1 v v v v v P P 1 u u u u u 0 i i x x x x x Vxx.w+=v6mpy(Vuu.ub,Vvv.b,#u2):v -0 0 0 1 1 1 1 1 0 0 1 v v v v v P P 1 u u u u u 1 i i x x x x x Vxx.w+=v6mpy(Vuu.ub,Vvv.b,#u2):h -0 0 0 1 1 1 1 1 0 1 0 v v v v v P P 1 u u u u u 0 i i d d d d d Vdd.w=v6mpy(Vuu.ub,Vvv.b,#u2):v -0 0 0 1 1 1 1 1 0 1 0 v v v v v P P 1 u u u u u 1 i i d d d d d Vdd.w=v6mpy(Vuu.ub,Vvv.b,#u2):h -0 0 0 1 1 1 0 0 0 0 1 v v v v v P P 1 u u u u u 0 1 0 x x x x x Vxx.w+=vadd(Vu.h,Vv.h) -0 0 0 1 1 1 0 0 0 1 0 v v v v v P P 1 u u u u u 1 0 0 x x x x x Vxx.w+=vadd(Vu.uh,Vv.uh) -0 0 0 1 1 1 0 0 0 1 0 v v v v v P P 1 u u u u u 1 0 1 x x x x x Vxx.h+=vadd(Vu.ub,Vv.ub) -0 0 0 1 1 1 0 0 1 0 1 v v v v v P P 0 u u u u u 0 1 0 d d d d d Vdd.h=vadd(Vu.ub,Vv.ub) -0 0 0 1 1 1 0 0 1 0 1 v v v v v P P 0 u u u u u 0 1 1 d d d d d Vdd.w=vadd(Vu.uh,Vv.uh) -0 0 0 1 1 1 0 0 1 0 1 v v v v v P P 0 u u u u u 1 0 0 d d d d d Vdd.w=vadd(Vu.h,Vv.h) -0 0 0 1 1 1 0 0 1 0 1 v v v v v P P 0 u u u u u 1 0 1 d d d d d Vdd.h=vsub(Vu.ub,Vv.ub) -0 0 0 1 1 1 0 0 1 0 1 v v v v v P P 0 u u u u u 1 1 0 d d d d d Vdd.w=vsub(Vu.uh,Vv.uh) -0 0 0 1 1 1 0 0 1 0 1 v v v v v P P 0 u u u u u 1 1 1 d d d d d Vdd.w=vsub(Vu.h,Vv.h) -0 0 0 1 1 0 0 1 0 0 0 t t t t t P P 0 u u u u u 1 1 1 d d d d d Vdd.h=vdmpy(Vuu.ub,Rt.b) -0 0 0 1 1 0 0 1 0 0 0 t t t t t P P 1 u u u u u 1 1 1 x x x x x Vxx.h+=vdmpy(Vuu.ub,Rt.b) -0 0 0 1 1 0 0 1 0 0 1 t t t t t P P 0 u u u u u 0 0 1 d d d d d Vd.w=vdmpy(Vuu.h,Rt.uh,#1):sat -0 0 0 1 1 0 0 1 0 0 1 t t t t t P P 0 u u u u u 0 1 1 d d d d d Vd.w=vdmpy(Vuu.h,Rt.h):sat -0 0 0 1 1 0 0 1 0 0 1 t t t t t P P 0 u u u u u 1 0 0 d d d d d Vdd.w=vdmpy(Vuu.h,Rt.b) -0 0 0 1 1 0 0 1 0 0 1 t t t t t P P 1 u u u u u 0 0 1 x x x x x Vx.w+=vdmpy(Vuu.h,Rt.uh,#1):sat -0 0 0 1 1 0 0 1 0 0 1 t t t t t P P 1 u u u u u 0 1 0 x x x x x Vx.w+=vdmpy(Vuu.h,Rt.h):sat -0 0 0 1 1 0 0 1 0 0 1 t t t t t P P 1 u u u u u 1 0 0 x x x x x Vxx.w+=vdmpy(Vuu.h,Rt.b) -0 0 0 1 1 1 0 0 0 0 0 v v v v v P P 1 u u u u u 0 1 1 x x x x x Vx.w+=vdmpy(Vu.h,Vv.h):sat -0 0 0 1 1 0 0 1 0 1 1 t t t t t P P 0 u u u u u 1 0 0 d d d d d Vd.h=vlut4(Vu.uh,Rtt.h) -0 0 0 1 1 0 0 1 1 0 0 t t t t t P P 1 u u u u u 1 0 0 x x x x x Vx.h=vmpa(Vx.h,Vu.h,Rtt.h):sat -0 0 0 1 1 0 0 1 1 0 0 t t t t t P P 1 u u u u u 1 0 1 x x x x x Vx.h=vmpa(Vx.h,Vu.uh,Rtt.uh):sat -0 0 0 1 1 0 0 1 1 0 0 t t t t t P P 1 u u u u u 1 1 0 x x x x x Vx.h=vmps(Vx.h,Vu.uh,Rtt.uh):sat -0 0 0 1 1 0 0 1 0 0 1 t t t t t P P 0 u u u u u 1 1 0 d d d d d Vdd.h=vmpa(Vuu.ub,Rt.b) -0 0 0 1 1 0 0 1 0 0 1 t t t t t P P 0 u u u u u 1 1 1 d d d d d Vdd.w=vmpa(Vuu.h,Rt.b) -0 0 0 1 1 0 0 1 0 0 1 t t t t t P P 1 u u u u u 1 1 0 x x x x x Vxx.h+=vmpa(Vuu.ub,Rt.b) -0 0 0 1 1 0 0 1 0 0 1 t t t t t P P 1 u u u u u 1 1 1 x x x x x Vxx.w+=vmpa(Vuu.h,Rt.b) -0 0 0 1 1 0 0 1 0 1 1 t t t t t P P 0 u u u u u 0 1 1 d d d d d Vdd.h=vmpa(Vuu.ub,Rt.ub) -0 0 0 1 1 0 0 1 1 0 0 t t t t t P P 0 u u u u u 1 0 1 d d d d d Vdd.w=vmpa(Vuu.uh,Rt.b) -0 0 0 1 1 0 0 1 1 0 0 t t t t t P P 1 u u u u u 0 1 0 x x x x x Vxx.w+=vmpa(Vuu.uh,Rt.b) -0 0 0 1 1 0 0 1 1 0 1 t t t t t P P 1 u u u u u 1 0 0 x x x x x Vxx.h+=vmpa(Vuu.ub,Rt.ub) -0 0 0 1 1 1 0 0 0 0 1 v v v v v P P 0 u u u u u 0 1 1 d d d d d Vdd.h=vmpa(Vuu.ub,Vvv.b) -0 0 0 1 1 1 0 0 1 1 1 v v v v v P P 0 u u u u u 1 1 1 d d d d d Vdd.h=vmpa(Vuu.ub,Vvv.ub) -0 0 0 1 1 0 0 1 0 0 1 t t t t t P P 0 u u u u u 1 0 1 d d d d d Vdd.h=vmpy(Vu.ub,Rt.b) -0 0 0 1 1 0 0 1 0 0 1 t t t t t P P 1 u u u u u 1 0 1 x x x x x Vxx.h+=vmpy(Vu.ub,Rt.b) -0 0 0 1 1 0 0 1 0 1 0 t t t t t P P 0 u u u u u 0 0 0 d d d d d Vdd.w=vmpy(Vu.h,Rt.h) -0 0 0 1 1 0 0 1 0 1 0 t t t t t P P 0 u u u u u 0 1 1 d d d d d Vdd.uw=vmpy(Vu.uh,Rt.uh) -0 0 0 1 1 0 0 1 0 1 0 t t t t t P P 1 u u u u u 0 0 0 x x x x x Vxx.w+=vmpy(Vu.h,Rt.h):sat -0 0 0 1 1 0 0 1 0 1 0 t t t t t P P 1 u u u u u 0 0 1 x x x x x Vxx.uw+=vmpy(Vu.uh,Rt.uh) -0 0 0 1 1 0 0 1 1 0 0 t t t t t P P 1 u u u u u 0 0 0 x x x x x Vxx.uh+=vmpy(Vu.ub,Rt.ub) -0 0 0 1 1 0 0 1 1 0 1 t t t t t P P 1 u u u u u 1 1 0 x x x x x Vxx.w+=vmpy(Vu.h,Rt.h) -0 0 0 1 1 0 0 1 1 1 0 t t t t t P P 0 u u u u u 0 0 0 d d d d d Vdd.uh=vmpy(Vu.ub,Rt.ub) -0 0 0 1 1 1 0 0 0 0 0 v v v v v P P 0 u u u u u 1 0 0 d d d d d Vdd.h=vmpy(Vu.b,Vv.b) -0 0 0 1 1 1 0 0 0 0 0 v v v v v P P 0 u u u u u 1 0 1 d d d d d Vdd.uh=vmpy(Vu.ub,Vv.ub) -0 0 0 1 1 1 0 0 0 0 0 v v v v v P P 0 u u u u u 1 1 0 d d d d d Vdd.h=vmpy(Vu.ub,Vv.b) -0 0 0 1 1 1 0 0 0 0 0 v v v v v P P 1 u u u u u 1 0 0 x x x x x Vxx.h+=vmpy(Vu.b,Vv.b) -0 0 0 1 1 1 0 0 0 0 0 v v v v v P P 1 u u u u u 1 0 1 x x x x x Vxx.uh+=vmpy(Vu.ub,Vv.ub) -0 0 0 1 1 1 0 0 0 0 0 v v v v v P P 1 u u u u u 1 1 0 x x x x x Vxx.h+=vmpy(Vu.ub,Vv.b) -0 0 0 1 1 1 0 0 0 0 1 v v v v v P P 0 u u u u u 0 0 0 d d d d d Vdd.uw=vmpy(Vu.uh,Vv.uh) -0 0 0 1 1 1 0 0 0 0 1 v v v v v P P 1 u u u u u 0 0 0 x x x x x Vxx.uw+=vmpy(Vu.uh,Vv.uh) -0 0 0 1 1 1 1 1 1 0 0 v v v v v P P 1 u u u u u 0 0 0 d d d d d Vdd.qf32=vmpy(Vu.qf16,Vv.hf) -0 0 0 1 1 1 1 1 1 1 1 v v v v v P P 1 u u u u u 0 1 1 d d d d d Vd.qf16=vmpy(Vu.qf16,Vv.qf16) -0 0 0 1 1 1 1 1 1 1 1 v v v v v P P 1 u u u u u 1 0 0 d d d d d Vd.qf16=vmpy(Vu.hf,Vv.hf) -0 0 0 1 1 1 1 1 1 1 1 v v v v v P P 1 u u u u u 1 0 1 d d d d d Vd.qf16=vmpy(Vu.qf16,Vv.hf) -0 0 0 1 1 1 1 1 1 1 1 v v v v v P P 1 u u u u u 1 1 0 d d d d d Vdd.qf32=vmpy(Vu.qf16,Vv.qf16) -0 0 0 1 1 1 1 1 1 1 1 v v v v v P P 1 u u u u u 1 1 1 d d d d d Vdd.qf32=vmpy(Vu.hf,Vv.hf) -0 0 0 1 1 1 0 0 0 0 1 v v v v v P P 0 u u u u u 1 0 0 d d d d d Vd.h=vmpyi(Vu.h,Vv.h) -0 0 0 1 1 1 0 0 0 0 1 v v v v v P P 1 u u u u u 1 0 0 x x x x x Vx.h+=vmpyi(Vu.h,Vv.h) -0 0 0 1 1 1 0 0 0 0 1 v v v v v P P 1 u u u u u 1 0 1 x x x x x Vx.w+=vmpyie(Vu.w,Vv.uh) -0 0 0 1 1 1 0 0 0 1 0 v v v v v P P 1 u u u u u 0 0 0 x x x x x Vx.w+=vmpyie(Vu.w,Vv.h) -0 0 0 1 1 1 1 1 1 1 0 v v v v v P P 0 u u u u u 0 0 0 d d d d d Vd.w=vmpyie(Vu.w,Vv.uh) -0 0 0 1 1 1 1 1 1 1 0 v v v v v P P 0 u u u u u 0 0 1 d d d d d Vd.w=vmpyio(Vu.w,Vv.h) -0 0 0 1 1 0 0 1 0 1 0 t t t t t P P 1 u u u u u 0 1 1 x x x x x Vx.w+=vmpyi(Vu.w,Rt.h) -0 0 0 1 1 0 0 1 1 0 0 t t t t t P P 0 u u u u u 1 1 1 d d d d d Vd.w=vmpyi(Vu.w,Rt.h) -0 0 0 1 1 1 1 1 1 1 1 v v v v v P P 1 u u u u u 0 0 0 d d d d d Vd.qf32=vmpy(Vu.qf32,Vv.qf32) -0 0 0 1 1 1 1 1 1 1 1 v v v v v P P 1 u u u u u 0 0 1 d d d d d Vd.qf32=vmpy(Vu.sf,Vv.sf) -0 0 0 1 1 1 0 0 0 0 1 v v v v v P P 1 u u u u u 0 1 1 x x x x x Vxx+=vmpyo(Vu.w,Vv.h) -0 0 0 1 1 1 0 0 0 0 1 v v v v v P P 1 u u u u u 1 1 0 x x x x x Vx.w+=vmpyo(Vu.w,Vv.h):<<1:sat:shift -0 0 0 1 1 1 0 0 0 0 1 v v v v v P P 1 u u u u u 1 1 1 x x x x x Vx.w+=vmpyo(Vu.w,Vv.h):<<1:rnd:sat:shift -0 0 0 1 1 1 1 0 1 0 1 v v v v v P P 0 u u u u u 1 1 0 d d d d d Vdd=vmpye(Vu.w,Vv.uh) -0 0 0 1 1 1 1 1 0 1 0 v v v v v P P 0 u u u u u 0 0 0 d d d d d Vd.w=vmpyo(Vu.w,Vv.h):<<1:rnd:sat -0 0 0 1 1 1 1 1 1 1 1 v v v v v P P 0 u u u u u 1 0 1 d d d d d Vd.w=vmpye(Vu.w,Vv.uh) -0 0 0 1 1 1 1 1 1 1 1 v v v v v P P 0 u u u u u 1 1 1 d d d d d Vd.w=vmpyo(Vu.w,Vv.h):<<1:sat -0 0 0 1 1 0 0 1 0 1 0 t t t t t P P 0 u u u u u 1 0 i d d d d d Vdd.w=vrmpy(Vuu.ub,Rt.b,#u1) -0 0 0 1 1 0 0 1 0 1 0 t t t t t P P 1 u u u u u 1 0 i x x x x x Vxx.w+=vrmpy(Vuu.ub,Rt.b,#u1) -0 0 0 1 1 0 0 1 0 1 1 t t t t t P P 1 u u u u u 1 1 i x x x x x Vxx.uw+=vrmpy(Vuu.ub,Rt.ub,#u1) -0 0 0 1 1 0 0 1 1 0 1 t t t t t P P 0 u u u u u 1 1 i d d d d d Vdd.uw=vrmpy(Vuu.ub,Rt.ub,#u1) -0 0 0 1 1 1 0 0 0 0 0 v v v v v P P 1 u u u u u 0 0 0 x x x x x Vx.uw+=vrmpy(Vu.ub,Vv.ub) -0 0 0 1 1 1 0 0 0 0 0 v v v v v P P 1 u u u u u 0 0 1 x x x x x Vx.w+=vrmpy(Vu.b,Vv.b) -0 0 0 1 1 1 0 0 0 0 0 v v v v v P P 1 u u u u u 0 1 0 x x x x x Vx.w+=vrmpy(Vu.ub,Vv.b) -0 0 0 1 1 0 0 1 0 0 0 t t t t t P P 0 u u u u u 0 0 0 d d d d d Vdd.h=vtmpy(Vuu.b,Rt.b) -0 0 0 1 1 0 0 1 0 0 0 t t t t t P P 0 u u u u u 0 0 1 d d d d d Vdd.h=vtmpy(Vuu.ub,Rt.b) -0 0 0 1 1 0 0 1 0 0 0 t t t t t P P 1 u u u u u 0 0 0 x x x x x Vxx.h+=vtmpy(Vuu.b,Rt.b) -0 0 0 1 1 0 0 1 0 0 0 t t t t t P P 1 u u u u u 0 0 1 x x x x x Vxx.h+=vtmpy(Vuu.ub,Rt.b) -0 0 0 1 1 0 0 1 0 0 0 t t t t t P P 1 u u u u u 0 1 0 x x x x x Vxx.w+=vtmpy(Vuu.h,Rt.b) -0 0 0 1 1 0 0 1 1 0 1 t t t t t P P 0 u u u u u 1 0 0 d d d d d Vdd.w=vtmpy(Vuu.h,Rt.b) -0 0 0 1 1 0 0 1 0 0 0 t t t t t P P 0 u u u u u 1 0 1 d d d d d Vdd.uw=vdsad(Vuu.uh,Rt.uh) -0 0 0 1 1 0 0 1 0 1 1 t t t t t P P 1 u u u u u 0 0 0 x x x x x Vxx.uw+=vdsad(Vuu.uh,Rt.uh) -0 0 0 1 1 0 0 1 0 1 0 t t t t t P P 0 u u u u u 1 1 i d d d d d Vdd.uw=vrsad(Vuu.ub,Rt.ub,#u1) -0 0 0 1 1 0 0 1 0 1 0 t t t t t P P 1 u u u u u 1 1 i x x x x x Vxx.uw+=vrsad(Vuu.ub,Rt.ub,#u1) -0 0 0 1 1 0 0 1 0 0 0 t t t t t P P 0 u u u u u 0 1 0 d d d d d Vd.w=vdmpy(Vu.h,Rt.b) -0 0 0 1 1 0 0 1 0 0 0 t t t t t P P 0 u u u u u 1 1 0 d d d d d Vd.h=vdmpy(Vu.ub,Rt.b) -0 0 0 1 1 0 0 1 0 0 0 t t t t t P P 1 u u u u u 0 1 1 x x x x x Vx.w+=vdmpy(Vu.h,Rt.b) -0 0 0 1 1 0 0 1 0 0 0 t t t t t P P 1 u u u u u 1 1 0 x x x x x Vx.h+=vdmpy(Vu.ub,Rt.b) -0 0 0 1 1 0 0 1 0 0 1 t t t t t P P 0 u u u u u 0 0 0 d d d d d Vd.w=vdmpy(Vu.h,Rt.uh):sat -0 0 0 1 1 0 0 1 0 0 1 t t t t t P P 0 u u u u u 0 1 0 d d d d d Vd.w=vdmpy(Vu.h,Rt.h):sat -0 0 0 1 1 0 0 1 0 0 1 t t t t t P P 1 u u u u u 0 0 0 x x x x x Vx.w+=vdmpy(Vu.h,Rt.uh):sat -0 0 0 1 1 0 0 1 0 0 1 t t t t t P P 1 u u u u u 0 1 1 x x x x x Vx.w+=vdmpy(Vu.h,Rt.h):sat -0 0 0 1 1 1 0 0 0 0 0 v v v v v P P 0 u u u u u 0 1 1 d d d d d Vd.w=vdmpy(Vu.h,Vv.h):sat -0 0 0 1 1 0 0 1 0 1 0 t t t t t P P 0 u u u u u 0 0 1 d d d d d Vd.h=vmpy(Vu.h,Rt.h):<<1:sat -0 0 0 1 1 0 0 1 0 1 0 t t t t t P P 0 u u u u u 0 1 0 d d d d d Vd.h=vmpy(Vu.h,Rt.h):<<1:md:sat -0 0 0 1 1 1 1 1 1 1 0 v v v v v P P 1 u u u u u 1 1 1 d d d d d Vd.uh=vmpy(Vu.uh,Vv.uh):>>16 -0 0 0 1 1 1 1 1 0 1 1 v v v v v P P 0 u u u u u 0 0 0 d d d d d Vd.w=vmpyieo(Vu.h,Vv.h) -0 0 0 1 1 0 0 1 0 1 0 t t t t t P P 1 u u u u u 0 1 0 x x x x x Vx.w+=vmpyi(Vu.w,Rt.b) -0 0 0 1 1 0 0 1 0 1 1 t t t t t P P 0 u u u u u 0 0 0 d d d d d Vd.h=vmpyi(Vu.h,Rt.b) -0 0 0 1 1 0 0 1 0 1 1 t t t t t P P 1 u u u u u 0 0 1 x x x x x Vx.h+=vmpyi(Vu.h,Rt.b) -0 0 0 1 1 0 0 1 1 0 0 t t t t t P P 0 u u u u u 1 1 0 d d d d d Vd.w=vmpyi(Vu.w,Rt.ub) -0 0 0 1 1 0 0 1 1 0 0 t t t t t P P 1 u u u u u 0 0 1 x x x x x Vx.w+=vmpyi(Vu.w,Rt.ub) -0 0 0 1 1 0 0 1 1 0 1 t t t t t P P 0 u u u u u 0 0 0 d d d d d Vd.w=vmpyi(Vu.w,Rt.b) -0 0 0 1 1 0 0 1 0 1 1 t t t t t P P 0 u u u u u 0 1 0 d d d d d Vd.uw=vmpye(Vu.uh,Rt.uh) -0 0 0 1 1 0 0 1 1 0 0 t t t t t P P 1 u u u u u 0 1 1 x x x x x Vx.uw+=vmpye(Vu.uh,Rt.uh) -0 0 0 1 1 0 0 1 0 0 0 t t t t t P P 0 u u u u u 0 1 1 d d d d d Vd.uw=vrmpy(Vu.ub,Rt.ub) -0 0 0 1 1 0 0 1 0 0 0 t t t t t P P 0 u u u u u 1 0 0 d d d d d Vd.w=vrmpy(Vu.ub,Rt.b) -0 0 0 1 1 0 0 1 0 0 0 t t t t t P P 1 u u u u u 1 0 0 x x x x x Vx.uw+=vrmpy(Vu.ub,Rt.ub) -0 0 0 1 1 0 0 1 0 0 0 t t t t t P P 1 u u u u u 1 0 1 x x x x x Vx.w+=vrmpy(Vu.ub,Rt.b) -0 0 0 1 1 1 0 0 0 0 0 v v v v v P P 0 u u u u u 0 0 0 d d d d d Vd.uw=vrmpy(Vu.ub,Vv.ub) -0 0 0 1 1 1 0 0 0 0 0 v v v v v P P 0 u u u u u 0 0 1 d d d d d Vd.w=vrmpy(Vu.b,Vv.b) -0 0 0 1 1 1 0 0 0 0 0 v v v v v P P 0 u u u u u 0 1 0 d d d d d Vd.w=vrmpy(Vu.ub,Vv.b) -0 0 0 1 1 0 0 1 1 0 1 t t t t t P P 0 - - - - 0 0 0 1 d d d d d Vd=vsplat(Rt) -0 0 0 1 1 0 0 1 1 1 0 t t t t t P P 0 - - - - - 0 0 1 d d d d d Vd.h=vsplat(Rt) -0 0 0 1 1 0 0 1 1 1 0 t t t t t P P 0 - - - - - 0 1 0 d d d d d Vd.b=vsplat(Rt) -0 0 0 1 1 0 0 1 0 1 1 t t t t t P P 1 u u u u u 1 0 0 - - - x x Qx4|=vand(Vu,Rt) -0 0 0 1 1 0 0 1 1 0 1 t t t t t P P 0 u u u u u 0 1 0 - 1 0 d d Qd4=vand(Vu,Rt) -0 0 0 1 1 0 0 1 0 1 1 t t t t t P P 1 - - 0 u u 0 1 1 x x x x x Vx|=vand(Qu4,Rt) -0 0 0 1 1 0 0 1 0 1 1 t t t t t P P 1 - - 1 u u 0 1 1 x x x x x Vx|=vand(!Qu4,Rt) -0 0 0 1 1 0 0 1 1 0 1 t t t t t P P 0 - - 0 u u 1 0 1 d d d d d Vd=vand(Qu4,Rt) -0 0 0 1 1 0 0 1 1 0 1 t t t t t P P 0 - - 1 u u 1 0 1 d d d d d Vd=vand(!Qu4,Rt) -0 0 0 1 1 1 0 0 1 1 0 v v v v v P P 0 u u u u u 0 0 0 d d d d d Vd.ub=vabsdiff(Vu.ub,Vv.ub) -0 0 0 1 1 1 0 0 1 1 0 v v v v v P P 0 u u u u u 0 0 1 d d d d d Vd.uh=vabsdiff(Vu.h,Vv.h) -0 0 0 1 1 1 0 0 1 1 0 v v v v v P P 0 u u u u u 0 1 0 d d d d d Vd.uh=vabsdiff(Vu.uh,Vv.uh) -0 0 0 1 1 1 0 0 1 1 0 v v v v v P P 0 u u u u u 0 1 1 d d d d d Vd.uw=vabsdiff(Vu.w,Vv.w) -0 0 0 1 1 0 0 1 1 0 1 t t t t t P P 1 - - - - - 0 0 1 x x x x x Vx.w=vinsert(Rt) -0 0 0 1 1 0 0 1 0 1 1 t t t t t P P 0 u u u u u 0 0 1 d d d d d Vd=vror(Vu,Rt) -0 0 0 1 1 0 1 1 v v v v v t t t P P 0 u u u u u 0 0 0 d d d d d Vd=valign(Vu,Vv,Rt) -0 0 0 1 1 0 1 1 v v v v v t t t P P 0 u u u u u 0 0 1 d d d d d Vd=vlalign(Vu,Vv,Rt) -0 0 0 1 1 1 1 0 0 0 1 v v v v v P P 1 u u u u u i i i d d d d d Vd=valign(Vu,Vv,#u3) -0 0 0 1 1 1 1 0 0 1 1 v v v v v P P 1 u u u u u i i i d d d d d Vd=vlalign(Vu,Vv,#u3) -0 0 0 1 1 1 1 1 0 0 1 v v v v v P P 0 u u u u u 0 0 1 d d d d d Vd=vdelta(Vu,Vv) -0 0 0 1 1 1 1 1 0 0 1 v v v v v P P 0 u u u u u 0 1 1 d d d d d Vd=vrdelta(Vu,Vv) -0 0 0 1 1 1 1 0 - - 0 - - - 0 0 P P 0 u u u u u 1 1 0 d d d d d Vd.h=vdeal(Vu.h) -0 0 0 1 1 1 1 0 - - 0 - - - 0 0 P P 0 u u u u u 1 1 1 d d d d d Vd.b=vdeal(Vu.b) -0 0 0 1 1 1 1 0 - - 0 - - - 0 1 P P 0 u u u u u 1 1 1 d d d d d Vd.h=vshuff(Vu.h) -0 0 0 1 1 1 1 0 - - 0 - - - 1 0 P P 0 u u u u u 0 0 0 d d d d d Vd.b=vshuff(Vu.b) -0 0 0 1 1 1 1 1 0 0 1 v v v v v P P 0 u u u u u 1 1 1 d d d d d Vd.b=vdeale(Vu.b,Vv.b) -0 0 0 1 1 1 1 1 1 1 0 v v v v v P P 0 u u u u u 0 1 0 d d d d d Vd.b=vpacke(Vu.h,Vv.h) -0 0 0 1 1 1 1 1 1 1 0 v v v v v P P 0 u u u u u 0 1 1 d d d d d Vd.h=vpacke(Vu.w,Vv.w) -0 0 0 1 1 1 1 1 1 1 0 v v v v v P P 0 u u u u u 1 0 1 d d d d d Vd.ub=vpack(Vu.h,Vv.h):sat -0 0 0 1 1 1 1 1 1 1 0 v v v v v P P 0 u u u u u 1 1 0 d d d d d Vd.b=vpack(Vu.h,Vv.h):sat -0 0 0 1 1 1 1 1 1 1 0 v v v v v P P 0 u u u u u 1 1 1 d d d d d Vd.uh=vpack(Vu.w,Vv.w):sat -0 0 0 1 1 1 1 1 1 1 1 v v v v v P P 0 u u u u u 0 0 0 d d d d d Vd.h=vpack(Vu.w,Vv.w):sat -0 0 0 1 1 1 1 1 1 1 1 v v v v v P P 0 u u u u u 0 0 1 d d d d d Vd.b=vpacko(Vu.h,Vv.h) -0 0 0 1 1 1 1 1 1 1 1 v v v v v P P 0 u u u u u 0 1 0 d d d d d Vd.h=vpacko(Vu.w,Vv.w) -0 0 0 1 1 0 0 1 1 0 1 t t t t t P P 0 - - - - - 0 1 0 - 0 1 d d Qd4=vsetq(Rt) -0 0 0 1 1 0 0 1 1 0 1 t t t t t P P 0 - - - - - 0 1 0 - 1 1 d d Qd4=vsetq2(Rt) -0 0 0 1 1 0 0 0 v v v v v t t t P P 0 u u u u u 0 1 1 d d d d d Vd.b=vlut32(Vu.b,Vv.b,Rt):nomatch -0 0 0 1 1 0 1 1 v v v v v t t t P P 1 u u u u u 0 0 1 d d d d d Vd.b=vlut32(Vu.b,Vv.b,Rt) -0 0 0 1 1 1 1 0 0 0 1 v v v v v P P 0 u u u u u i i i d d d d d Vd.b=vlut32(Vu.b,Vv.b,#u3) -0 0 0 1 1 0 1 0 1 0 1 v v v v v P P 1 u u u u u 1 1 1 x x x x x Vxx.w=vasrinto(Vu.w,Vv.w) -0 0 0 1 1 0 0 1 1 1 1 t t t t t P P 1 y y y y y 0 0 1 x x x x x vshuff(Vy,Vx,Rt) -0 0 0 1 1 0 0 1 1 1 1 t t t t t P P 1 y y y y y 0 1 0 x x x x x vdeal(Vy,Vx,Rt) -0 0 0 1 1 0 1 1 v v v v v t t t P P 1 u u u u u 0 1 1 d d d d d Vdd=vshuff(Vu,Vv,Rt) -0 0 0 1 1 0 1 1 v v v v v t t t P P 1 u u u u u 1 0 0 d d d d d Vdd=vdeal(Vu,Vv,Rt) -0 0 0 1 1 0 0 0 v v v v v t t t P P 0 u u u u u 1 0 0 d d d d d Vdd.h=vlut16(Vu.b,Vv.h,Rt):nomatch -0 0 0 1 1 0 1 1 v v v v v t t t P P 1 u u u u u 1 0 1 x x x x x Vx.b|=vlut32(Vu.b,Vv.b,Rt) -0 0 0 1 1 0 1 1 v v v v v t t t P P 1 u u u u u 1 1 0 d d d d d Vdd.h=vlut16(Vu.b,Vv.h,Rt) -0 0 0 1 1 0 1 1 v v v v v t t t P P 1 u u u u u 1 1 1 x x x x x Vxx.h|=vlut16(Vu.b,Vv.h,Rt) -0 0 0 1 1 1 0 0 1 1 0 v v v v v P P 1 u u u u u i i i x x x x x Vx.b|=vlut32(Vu.b,Vv.b,#u3) -0 0 0 1 1 1 0 0 1 1 1 v v v v v P P 1 u u u u u i i i x x x x x Vxx.h|=vlut16(Vu.b,Vv.h,#u3) -0 0 0 1 1 1 1 0 0 1 1 v v v v v P P 0 u u u u u i i i d d d d d Vdd.h=vlut16(Vu.b,Vv.h,#u3) -0 0 0 1 1 1 1 0 - - 0 - - - 0 1 P P 0 u u u u u 0 0 0 d d d d d Vdd.uh=vunpack(Vu.ub) -0 0 0 1 1 1 1 0 - - 0 - - - 0 1 P P 0 u u u u u 0 0 1 d d d d d Vdd.uw=vunpack(Vu.uh) -0 0 0 1 1 1 1 0 - - 0 - - - 0 1 P P 0 u u u u u 0 1 0 d d d d d Vdd.h=vunpack(Vu.b) -0 0 0 1 1 1 1 0 - - 0 - - - 0 1 P P 0 u u u u u 0 1 1 d d d d d Vdd.w=vunpack(Vu.h) -0 0 0 1 1 1 1 0 - - 0 - - 0 0 0 P P 1 u u u u u 0 0 0 x x x x x Vxx.h|=vunpacko(Vu.b) -0 0 0 1 1 1 1 0 - - 0 - - 0 0 0 P P 1 u u u u u 0 0 1 x x x x x Vxx.w|=vunpacko(Vu.h) -0 0 1 0 1 1 1 1 0 0 1 t t t t t P P u v v v v v 0 1 0 w w w w w vscatter(Rt,Mu,Vvv.w).h=Vw32 -0 0 1 0 1 1 1 1 0 0 1 t t t t t P P u v v v v v 1 1 0 w w w w w vscatter(Rt,Mu,Vvv.w).h+=Vw32 -0 0 1 0 1 1 1 1 1 0 1 t t t t t P P u v v v v v 0 s s w w w w w if (Qs4) vscatter(Rt,Mu,Vvv.w).h=Vw32 -0 0 1 0 1 1 1 1 0 0 1 t t t t t P P u v v v v v 0 0 0 w w w w w vscatter(Rt,Mu,Vv.w).w=Vw32 -0 0 1 0 1 1 1 1 0 0 1 t t t t t P P u v v v v v 0 0 1 w w w w w vscatter(Rt,Mu,Vv.h).h=Vw32 -0 0 1 0 1 1 1 1 0 0 1 t t t t t P P u v v v v v 1 0 0 w w w w w vscatter(Rt,Mu,Vv.w).w+=Vw32 -0 0 1 0 1 1 1 1 0 0 1 t t t t t P P u v v v v v 1 0 1 w w w w w vscatter(Rt,Mu,Vv.h).h+=Vw32 -0 0 1 0 1 1 1 1 1 0 0 t t t t t P P u v v v v v 0 s s w w w w w if (Qs4) vscatter(Rt,Mu,Vv.w).w=Vw32 -0 0 1 0 1 1 1 1 1 0 0 t t t t t P P u v v v v v 1 s s w w w w w if (Qs4) vscatter(Rt,Mu,Vv.h).h=Vw32 - -0 0 0 1 1 0 0 0 v v v v v t t t P P 0 u u u u u 0 0 0 d d d d d Vd.b=vasr(Vu.h,Vv.h,Rt):sat -0 0 0 1 1 0 0 0 v v v v v t t t P P 0 u u u u u 0 0 1 d d d d d Vd.uh=vasr(Vu.uw,Vv.uw,Rt):rnd:sat -0 0 0 1 1 0 0 0 v v v v v t t t P P 0 u u u u u 0 1 0 d d d d d Vd.uh=vasr(Vu.w,Vv.w,Rt):rnd:sat -0 0 0 1 1 0 0 0 v v v v v t t t P P 0 u u u u u 1 1 1 d d d d d Vd.ub=vasr(Vu.uh,Vv.uh,Rt):rnd:sat -0 0 0 1 1 0 0 0 v v v v v t t t P P 1 u u u u u 1 0 0 d d d d d Vd.uh=vasr(Vu.uw,Vv.uw,Rt):sat -0 0 0 1 1 0 0 0 v v v v v t t t P P 1 u u u u u 1 0 1 d d d d d Vd.ub=vasr(Vu.uh,Vv.uh,Rt):sat - -0 0 0 1 1 0 1 1 v v v v v t t t P P 0 u u u u u 0 1 0 d d d d d Vd.h=vasr(Vu.w,Vv.w,Rt) -0 0 0 1 1 0 1 1 v v v v v t t t P P 0 u u u u u 0 1 1 d d d d d Vd.h=vasr(Vu.w,Vv.w,Rt):sat -0 0 0 1 1 0 1 1 v v v v v t t t P P 0 u u u u u 1 0 0 d d d d d Vd.h=vasr(Vu.w,Vv.w,Rt):rnd:sat -0 0 0 1 1 0 1 1 v v v v v t t t P P 0 u u u u u 1 0 1 d d d d d Vd.uh=vasr(Vu.w,Vv.w,Rt):sat -0 0 0 1 1 0 1 1 v v v v v t t t P P 0 u u u u u 1 1 0 d d d d d Vd.ub=vasr(Vu.h,Vv.h,Rt):sat -0 0 0 1 1 0 1 1 v v v v v t t t P P 0 u u u u u 1 1 1 d d d d d Vd.ub=vasr(Vu.h,Vv.h,Rt):rnd:sat -0 0 0 1 1 0 1 1 v v v v v t t t P P 1 u u u u u 0 0 0 d d d d d Vd.b=vasr(Vu.h,Vv.h,Rt):rnd:sat -0 0 0 1 1 1 1 0 v v 0 - - 0 1 1 P P 1 - - 0 0 0 0 1 0 d d d d d Vd.b=prefixsum(Qv4) -0 0 0 1 1 1 1 0 v v 0 - - 0 1 1 P P 1 - - 0 0 1 0 1 0 d d d d d Vd.h=prefixsum(Qv4) -0 0 0 1 1 1 1 0 v v 0 - - 0 1 1 P P 1 - - 0 1 0 0 1 0 d d d d d Vd.w=prefixsum(Qv4) -0 0 0 1 1 1 1 1 0 1 1 v v v v v P P 1 u u u u u 0 1 0 d d d d d Vd.qf16=vadd(Vu.qf16,Vv.qf16) -0 0 0 1 1 1 1 1 0 1 1 v v v v v P P 1 u u u u u 0 1 1 d d d d d Vd.qf16=vadd(Vu.hf,Vv.hf) -0 0 0 1 1 1 1 1 0 1 1 v v v v v P P 1 u u u u u 1 0 0 d d d d d Vd.qf16=vadd(Vu.qf16,Vv.hf) -0 0 0 1 1 1 1 1 1 0 1 v v v v v P P 1 u u u u u 0 0 0 d d d d d Vd.qf32=vadd(Vu.qf32,Vv.qf32) -0 0 0 1 1 1 1 1 1 0 1 v v v v v P P 1 u u u u u 0 0 1 d d d d d Vd.qf32=vadd(Vu.sf,Vv.sf) -0 0 0 1 1 1 1 1 1 0 1 v v v v v P P 1 u u u u u 0 1 0 d d d d d Vd.qf32=vadd(Vu.qf32,Vv.sf) -0 0 0 1 1 0 0 1 0 1 1 t t t t t P P 1 u u u u u 0 1 0 x x x x x Vx.w+=vasl(Vu.w,Rt) -0 0 0 1 1 0 0 1 0 1 1 t t t t t P P 1 u u u u u 1 0 1 x x x x x Vx.w+=vasr(Vu.w,Rt) -0 0 0 1 1 0 0 1 1 0 0 t t t t t P P 1 u u u u u 1 1 1 x x x x x Vx.h+=vasr(Vu.h,Rt) -0 0 0 1 1 0 0 1 1 0 1 t t t t t P P 1 u u u u u 1 0 1 x x x x x Vx.h+=vasl(Vu.h,Rt) - -# 0 0 0 1 1 0 0 0 v v v v v t t t P P 0 u u u u u 0 0 0 d d d d d Vd.b=vasr(Vu.h,Vv.h,Rt):sat -# 0 0 0 1 1 0 0 0 v v v v v t t t P P 0 u u u u u 0 0 1 d d d d d Vd.uh=vasr(Vu.uw,Vv.uw,Rt):rnd:sat -# 0 0 0 1 1 0 0 0 v v v v v t t t P P 0 u u u u u 0 1 0 d d d d d Vd.uh=vasr(Vu.w,Vv.w,Rt):rnd:sat -# 0 0 0 1 1 0 0 0 v v v v v t t t P P 0 u u u u u 1 1 1 d d d d d Vd.ub=vasr(Vu.uh,Vv.uh,Rt):rnd:sat -# 0 0 0 1 1 0 0 0 v v v v v t t t P P 1 u u u u u 1 0 0 d d d d d Vd.uh=vasr(Vu.uw,Vv.uw,Rt):sat -# 0 0 0 1 1 0 0 0 v v v v v t t t P P 1 u u u u u 1 0 1 d d d d d Vd.ub=vasr(Vu.uh,Vv.uh,Rt):sat - -0 0 0 1 1 0 0 1 0 1 1 t t t t t P P 0 u u u u u 1 0 1 d d d d d Vd.w=vasr(Vu.w,Rt) -0 0 0 1 1 0 0 1 0 1 1 t t t t t P P 0 u u u u u 1 1 0 d d d d d Vd.h=vasr(Vu.h,Rt) -0 0 0 1 1 0 0 1 0 1 1 t t t t t P P 0 u u u u u 1 1 1 d d d d d Vd.w=vasl(Vu.w,Rt) -0 0 0 1 1 0 0 1 1 0 0 t t t t t P P 0 u u u u u 0 0 0 d d d d d Vd.h=vasl(Vu.h,Rt) -0 0 0 1 1 0 0 1 1 0 0 t t t t t P P 0 u u u u u 0 0 1 d d d d d Vd.uw=vlsr(Vu.uw,Rt) -0 0 0 1 1 0 0 1 1 0 0 t t t t t P P 0 u u u u u 0 1 0 d d d d d Vd.uh=vlsr(Vu.uh,Rt) -0 0 0 1 1 0 0 1 1 0 0 t t t t t P P 0 u u u u u 0 1 1 d d d d d Vd.ub=vlsr(Vu.ub,Rt) - -# 0 0 0 1 1 0 1 1 v v v v v t t t P P 0 u u u u u 0 1 0 d d d d d Vd.h=vasr(Vu.w,Vv.w,Rt) -# 0 0 0 1 1 0 1 1 v v v v v t t t P P 0 u u u u u 0 1 1 d d d d d Vd.h=vasr(Vu.w,Vv.w,Rt):sat -# 0 0 0 1 1 0 1 1 v v v v v t t t P P 0 u u u u u 1 0 0 d d d d d Vd.h=vasr(Vu.w,Vv.w,Rt):rnd:sat -# 0 0 0 1 1 0 1 1 v v v v v t t t P P 0 u u u u u 1 0 1 d d d d d Vd.uh=vasr(Vu.w,Vv.w,Rt):sat -# 0 0 0 1 1 0 1 1 v v v v v t t t P P 0 u u u u u 1 1 0 d d d d d Vd.ub=vasr(Vu.h,Vv.h,Rt):sat -# 0 0 0 1 1 0 1 1 v v v v v t t t P P 0 u u u u u 1 1 1 d d d d d Vd.ub=vasr(Vu.h,Vv.h,Rt):rnd:sat -# 0 0 0 1 1 0 1 1 v v v v v t t t P P 1 u u u u u 0 0 0 d d d d d Vd.b=vasr(Vu.h,Vv.h,Rt):rnd:sat - -0 0 0 1 1 1 1 1 1 0 1 v v v v v P P 0 u u u u u 0 0 0 d d d d d Vd.w=vasr(Vu.w,Vv.w) -0 0 0 1 1 1 1 1 1 0 1 v v v v v P P 0 u u u u u 0 0 1 d d d d d Vd.w=vlsr(Vu.w,Vv.w) -0 0 0 1 1 1 1 1 1 0 1 v v v v v P P 0 u u u u u 0 1 0 d d d d d Vd.h=vlsr(Vu.h,Vv.h) -0 0 0 1 1 1 1 1 1 0 1 v v v v v P P 0 u u u u u 0 1 1 d d d d d Vd.h=vasr(Vu.h,Vv.h) -0 0 0 1 1 1 1 1 1 0 1 v v v v v P P 0 u u u u u 1 0 0 d d d d d Vd.w=vasl(Vu.w,Vv.w) -0 0 0 1 1 1 1 1 1 0 1 v v v v v P P 0 u u u u u 1 0 1 d d d d d Vd.h=vasl(Vu.h,Vv.h) -0 0 0 1 1 1 0 1 0 0 0 v v v v v P P 0 u u u u u 0 0 0 d d d d d Vd.uh=vasr(Vuu.w,Vv.uh):sat -0 0 0 1 1 1 0 1 0 0 0 v v v v v P P 0 u u u u u 0 0 1 d d d d d Vd.uh=vasr(Vuu.w,Vv.uh):rnd:sat -0 0 0 1 1 1 0 1 0 0 0 v v v v v P P 0 u u u u u 0 1 0 d d d d d Vd.ub=vasr(Vuu.uh,Vv.ub):sat -0 0 0 1 1 1 0 1 0 0 0 v v v v v P P 0 u u u u u 0 1 1 d d d d d Vd.ub=vasr(Vuu.uh,Vv.ub):rnd:sat -0 0 0 1 1 1 1 0 - - 0 - - 1 0 0 P P 1 u u u u u 0 0 0 d d d d d Vd.sf=Vu.qf32 -0 0 0 1 1 1 1 0 - - 0 - - 1 0 0 P P 1 u u u u u 0 1 1 d d d d d Vd.hf=Vu.qf16 -0 0 0 1 1 1 1 0 - - 0 - - 1 0 0 P P 1 u u u u u 1 1 0 d d d d d Vd.hf=Vuu.qf32 -0 0 0 1 1 1 1 1 0 1 1 v v v v v P P 0 u u u u u 1 0 0 d d d d d Vd.h=vround(Vu.w,Vv.w):sat -0 0 0 1 1 1 1 1 0 1 1 v v v v v P P 0 u u u u u 1 0 1 d d d d d Vd.uh=vround(Vu.w,Vv.w):sat -0 0 0 1 1 1 1 1 0 1 1 v v v v v P P 0 u u u u u 1 1 0 d d d d d Vd.b=vround(Vu.h,Vv.h):sat -0 0 0 1 1 1 1 1 0 1 1 v v v v v P P 0 u u u u u 1 1 1 d d d d d Vd.ub=vround(Vu.h,Vv.h):sat -0 0 0 1 1 1 1 1 1 1 1 v v v v v P P 0 u u u u u 0 1 1 d d d d d Vd.ub=vround(Vu.uh,Vv.uh):sat -0 0 0 1 1 1 1 1 1 1 1 v v v v v P P 0 u u u u u 1 0 0 d d d d d Vd.uh=vround(Vu.uw,Vv.uw):sat -0 0 0 1 1 0 1 0 1 0 0 v v v v v P P 1 u u u u u 1 1 1 d d d d d Vd.uw=vrotr(Vu.uw,Vv.uw) -0 0 0 1 1 1 1 1 0 1 1 v v v v v P P 1 u u u u u 1 0 1 d d d d d Vd.qf16=vsub(Vu.qf16,Vv.qf16) -0 0 0 1 1 1 1 1 0 1 1 v v v v v P P 1 u u u u u 1 1 0 d d d d d Vd.qf16=vsub(Vu.hf,Vv.hf) -0 0 0 1 1 1 1 1 0 1 1 v v v v v P P 1 u u u u u 1 1 1 d d d d d Vd.qf16=vsub(Vu.qf16,Vv.hf) -0 0 0 1 1 1 1 1 1 0 1 v v v v v P P 1 u u u u u 0 1 1 d d d d d Vd.qf32=vsub(Vu.qf32,Vv.qf32) -0 0 0 1 1 1 1 1 1 0 1 v v v v v P P 1 u u u u u 1 0 0 d d d d d Vd.qf32=vsub(Vu.sf,Vv.sf) -0 0 0 1 1 1 1 1 1 0 1 v v v v v P P 1 u u u u u 1 0 1 d d d d d Vd.qf32=vsub(Vu.qf32,Vv.sf) -0 0 0 1 1 1 1 0 - - 0 - - - 1 0 P P 0 u u u u u 1 0 1 d d d d d Vd.uw=vcl0(Vu.uw) -0 0 0 1 1 1 1 0 - - 0 - - - 1 0 P P 0 u u u u u 1 1 0 d d d d d Vd.h=vpopcount(Vu.h) -0 0 0 1 1 1 1 0 - - 0 - - - 1 0 P P 0 u u u u u 1 1 1 d d d d d Vd.uh=vcl0(Vu.uh) -0 0 0 1 1 1 1 0 - - 0 - - - 1 1 P P 0 u u u u u 1 0 0 d d d d d Vd.w=vnormamt(Vu.w) -0 0 0 1 1 1 1 0 - - 0 - - - 1 1 P P 0 u u u u u 1 0 1 d d d d d Vd.h=vnormamt(Vu.h) -0 0 0 1 1 1 1 1 0 0 0 v v v v v P P 1 u u u u u 0 0 0 d d d d d Vd.h=vadd(vclb(Vu.h),Vv.h) -0 0 0 1 1 1 1 1 0 0 0 v v v v v P P 1 u u u u u 0 0 1 d d d d d Vd.w=vadd(vclb(Vu.w),Vv.w) -0 0 1 0 1 0 0 0 1 0 0 t t t t t P P i v v i i i 0 0 0 s s s s s if (Qv4) vmem(Rt+#s4)=Vs -0 0 1 0 1 0 0 0 1 0 0 t t t t t P P i v v i i i 0 0 1 s s s s s if (!Qv4) vmem(Rt+#s4)=Vs -0 0 1 0 1 0 0 0 1 1 0 t t t t t P P i v v i i i 0 0 0 s s s s s if (Qv4) vmem(Rt+#s4):nt=Vs -0 0 1 0 1 0 0 0 1 1 0 t t t t t P P i v v i i i 0 0 1 s s s s s if (!Qv4) vmem(Rt+#s4):nt=Vs -0 0 1 0 1 0 0 1 1 0 0 x x x x x P P - v v i i i 0 0 0 s s s s s if (Qv4) vmem(Rx++#s3)=Vs -0 0 1 0 1 0 0 1 1 0 0 x x x x x P P - v v i i i 0 0 1 s s s s s if (!Qv4) vmem(Rx++#s3)=Vs -0 0 1 0 1 0 0 1 1 1 0 x x x x x P P - v v i i i 0 0 0 s s s s s if (Qv4) vmem(Rx++#s3):nt=Vs -0 0 1 0 1 0 0 1 1 1 0 x x x x x P P - v v i i i 0 0 1 s s s s s if (!Qv4) vmem(Rx++#s3):nt=Vs -0 0 1 0 1 0 1 1 1 0 0 x x x x x P P u v v - - - 0 0 0 s s s s s if (Qv4) vmem(Rx++Mu)=Vs -0 0 1 0 1 0 1 1 1 0 0 x x x x x P P u v v - - - 0 0 1 s s s s s if (!Qv4) vmem(Rx++Mu)=Vs -0 0 1 0 1 0 1 1 1 1 0 x x x x x P P u v v - - - 0 0 0 s s s s s if (Qv4) vmem(Rx++Mu):nt=Vs -0 0 1 0 1 0 1 1 1 1 0 x x x x x P P u v v - - - 0 0 1 s s s s s if (!Qv4) vmem(Rx++Mu):nt=Vs -0 0 1 0 1 0 0 0 0 0 1 t t t t t P P i - - i i i 0 0 1 - 0 s s s vmem(Rt+#s4)=Os8.new -0 0 1 0 1 0 0 0 0 1 1 t t t t t P P i - - i i i 0 0 1 - - s s s vmem(Rt+#s4):nt=Os8.new -0 0 1 0 1 0 0 0 1 0 1 t t t t t P P i v v i i i 0 1 0 0 0 s s s if (Pv) vmem(Rt+#s4)=Os8.new -0 0 1 0 1 0 0 0 1 0 1 t t t t t P P i v v i i i 0 1 1 0 1 s s s if (!Pv) vmem(Rt+#s4)=Os8.new -0 0 1 0 1 0 0 0 1 1 1 t t t t t P P i v v i i i 0 1 0 1 0 s s s if (Pv) vmem(Rt+#s4):nt=Os8.new -0 0 1 0 1 0 0 0 1 1 1 t t t t t P P i v v i i i 0 1 1 1 1 s s s if (!Pv) vmem(Rt+#s4):nt=Os8.new -0 0 1 0 1 0 0 1 0 0 1 x x x x x P P - - - i i i 0 0 1 - 0 s s s vmem(Rx++#s3)=Os8.new -0 0 1 0 1 0 0 1 0 1 1 x x x x x P P - - - i i i 0 0 1 - - s s s vmem(Rx++#s3):nt=Os8.new -0 0 1 0 1 0 0 1 1 0 1 x x x x x P P - v v i i i 0 1 0 0 0 s s s if (Pv) vmem(Rx++#s3)=Os8.new -0 0 1 0 1 0 0 1 1 0 1 x x x x x P P - v v i i i 0 1 1 0 1 s s s if (!Pv) vmem(Rx++#s3)=Os8.new -0 0 1 0 1 0 0 1 1 1 1 x x x x x P P - v v i i i 0 1 0 1 0 s s s if (Pv) vmem(Rx++#s3):nt=Os8.new -0 0 1 0 1 0 0 1 1 1 1 x x x x x P P - v v i i i 0 1 1 1 1 s s s if (!Pv) vmem(Rx++#s3):nt=Os8.new -0 0 1 0 1 0 1 1 0 0 1 x x x x x P P u - - - - - 0 0 1 - 0 s s s vmem(Rx++Mu)=Os8.new -0 0 1 0 1 0 1 1 0 1 1 x x x x x P P u - - - - - 0 0 1 - - s s s vmem(Rx++Mu):nt=Os8.new -0 0 1 0 1 0 1 1 1 0 1 x x x x x P P u v v - - - 0 1 0 0 0 s s s if (Pv) vmem(Rx++Mu)=Os8.new -0 0 1 0 1 0 1 1 1 0 1 x x x x x P P u v v - - - 0 1 1 0 1 s s s if (!Pv) vmem(Rx++Mu)=Os8.new -0 0 1 0 1 0 1 1 1 1 1 x x x x x P P u v v - - - 0 1 0 1 0 s s s if (Pv) vmem(Rx++Mu):nt=Os8.new -0 0 1 0 1 0 1 1 1 1 1 x x x x x P P u v v - - - 0 1 1 1 1 s s s if (!Pv) vmem(Rx++Mu):nt=Os8.ne -0 0 1 0 1 0 0 0 0 0 1 t t t t t P P i - - i i i 0 0 0 s s s s s vmem(Rt+#s4)=Vs -0 0 1 0 1 0 0 0 0 1 1 t t t t t P P i - - i i i 0 0 0 s s s s s vmem(Rt+#s4):nt=Vs -0 0 1 0 1 0 0 0 1 0 1 t t t t t P P i v v i i i 0 0 0 s s s s s if (Pv) vmem(Rt+#s4)=Vs -0 0 1 0 1 0 0 0 1 0 1 t t t t t P P i v v i i i 0 0 1 s s s s s if (!Pv) vmem(Rt+#s4)=Vs -0 0 1 0 1 0 0 0 1 1 1 t t t t t P P i v v i i i 0 0 0 s s s s s if (Pv) vmem(Rt+#s4):nt=Vs -0 0 1 0 1 0 0 0 1 1 1 t t t t t P P i v v i i i 0 0 1 s s s s s if (!Pv) vmem(Rt+#s4):nt=Vs -0 0 1 0 1 0 0 1 0 0 1 x x x x x P P - - - i i i 0 0 0 s s s s s vmem(Rx++#s3)=Vs -0 0 1 0 1 0 0 1 0 1 1 x x x x x P P - - - i i i 0 0 0 s s s s s vmem(Rx++#s3):nt=Vs -0 0 1 0 1 0 0 1 1 0 1 x x x x x P P - v v i i i 0 0 0 s s s s s if (Pv) vmem(Rx++#s3)=Vs -0 0 1 0 1 0 0 1 1 0 1 x x x x x P P - v v i i i 0 0 1 s s s s s if (!Pv) vmem(Rx++#s3)=Vs -0 0 1 0 1 0 0 1 1 1 1 x x x x x P P - v v i i i 0 0 0 s s s s s if (Pv) vmem(Rx++#s3):nt=Vs -0 0 1 0 1 0 0 1 1 1 1 x x x x x P P - v v i i i 0 0 1 s s s s s if (!Pv) vmem(Rx++#s3):nt=Vs -0 0 1 0 1 0 1 1 0 0 1 x x x x x P P u - - - - - 0 0 0 s s s s s vmem(Rx++Mu)=Vs -0 0 1 0 1 0 1 1 0 1 1 x x x x x P P u - - - - - 0 0 0 s s s s s vmem(Rx++Mu):nt=Vs -0 0 1 0 1 0 1 1 1 0 1 x x x x x P P u v v - - - 0 0 0 s s s s s if (Pv) vmem(Rx++Mu)=Vs -0 0 1 0 1 0 1 1 1 0 1 x x x x x P P u v v - - - 0 0 1 s s s s s if (!Pv) vmem(Rx++Mu)=Vs -0 0 1 0 1 0 1 1 1 1 1 x x x x x P P u v v - - - 0 0 0 s s s s s if (Pv) vmem(Rx++Mu):nt=Vs -0 0 1 0 1 0 1 1 1 1 1 x x x x x P P u v v - - - 0 0 1 s s s s s if (!Pv) vmem(Rx++Mu):nt=Vs -0 0 1 0 1 0 0 0 0 0 1 t t t t t P P i - - i i i 1 1 1 s s s s s vmemu(Rt+#s4)=Vs -0 0 1 0 1 0 0 0 1 0 1 t t t t t P P i v v i i i 1 1 0 s s s s s if (Pv) vmemu(Rt+#s4)=Vs -0 0 1 0 1 0 0 0 1 0 1 t t t t t P P i v v i i i 1 1 1 s s s s s if (!Pv) vmemu(Rt+#s4)=Vs -0 0 1 0 1 0 0 1 0 0 1 x x x x x P P - - - i i i 1 1 1 s s s s s vmemu(Rx++#s3)=Vs -0 0 1 0 1 0 0 1 1 0 1 x x x x x P P - v v i i i 1 1 0 s s s s s if (Pv) vmemu(Rx++#s3)=Vs -0 0 1 0 1 0 0 1 1 0 1 x x x x x P P - v v i i i 1 1 1 s s s s s if (!Pv) vmemu(Rx++#s3)=Vs -0 0 1 0 1 0 1 1 0 0 1 x x x x x P P u - - - - - 1 1 1 s s s s s vmemu(Rx++Mu)=Vs -0 0 1 0 1 0 1 1 1 0 1 x x x x x P P u v v - - - 1 1 0 s s s s s if (Pv) vmemu(Rx++Mu)=Vs -0 0 1 0 1 0 1 1 1 0 1 x x x x x P P u v v - - - 1 1 1 s s s s s if (!Pv) vmemu(Rx++Mu)=Vs -0 0 1 0 1 0 0 0 0 0 1 t t t t t P P i - - i i i 0 0 1 - 1 - - - vmem(Rt+#s4):scatter_release -0 0 1 0 1 0 0 1 0 0 1 x x x x x P P - - - i i i 0 0 1 - 1 - - - vmem(Rx++#s3):scatter_release -0 0 1 0 1 0 1 1 0 0 1 x x x x x P P u - - - - - 0 0 1 - 1 - - - vmem(Rx++Mu):scatter_release - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - diff --git a/pypcode/processors/Hexagon/data/languages/hexagon_hvx2.sinc b/pypcode/processors/Hexagon/data/languages/hexagon_hvx2.sinc new file mode 100644 index 0000000..b88e006 --- /dev/null +++ b/pypcode/processors/Hexagon/data/languages/hexagon_hvx2.sinc @@ -0,0 +1,1065 @@ +# Qualcomm Hexagon HVX-v2 Instruction Set (V73 additions) +# +# V73 HVX "version 2" additions layered on the V69 HVX base in hexagon_hvx.sinc: +# IEEE/Qualcomm floating-point element ops (hf/sf/bf/f8), qf16/qf32 fixed-format +# conversions, and vrmpy(Rtt) reductions. Conventions follow hexagon_hvx.sinc +# (typed Vd/Vu/Vv lane wrappers, vs5/vss5 accumulate shadows, pcodeop stubs). +# +# NOTE: Quad-Vector support has been omitted +# +# Reuses hexagon.sinc / hexagon_hvx.sinc definitions; @include'd from hexagon.slaspec. + +# +# Quad-Vector Operands (e.g., V0V3 ) +# TODO: Addition of HVX-v2 quad-vector support has been deferred + +# Quad-Vector destination unconditional write (2,4) +#Vdddd3: vdddd3 is cond=0 & vdddd3 & vdddd3_ { +# export vdddd3_; # must be updated unconditionally +# <> +# vdddd3 = vdddd3_; +#} + +# source quad-vector (2,4) - read-only use +#Vssss_0004:vssss3 is vssss3 { +# tmp:$(HVX_VECTOR_QUAD_SIZE) = vssss3; +# export tmp; +#} + +# Auto-generated HVX-v2 subtables +RtHF_1620: rx5^".hf" is rx5 { tmp:4 = rx5; export tmp; } +RtSF_1620: rx5^".sf" is rx5 { tmp:4 = rx5; export tmp; } +RttUB_1620: rxx5^".ub" is rxx5 { tmp:8 = rxx5; export tmp; } +VdBF_0004: Vd5^".bf" is Vd5 { export Vd5; } +VdF8_0004: Vd5^".f8" is Vd5 { export Vd5; } +VdX_0004: Vd5^".x" is Vd5 { export Vd5; } +VddHF_0004: Vdd5^".hf" is Vdd5 { export Vdd5; } +VddQF16_0004: Vdd5^".qf16" is Vdd5 { export Vdd5; } +VddSF_0004: Vdd5^".sf" is Vdd5 { export Vdd5; } +VuBF_0812: Vu_0812^".bf" is Vu_0812 { export Vu_0812; } +VuF8_0812: Vu_0812^".f8" is Vu_0812 { export Vu_0812; } +VuX_0812: Vu_0812^".x" is Vu_0812 { export Vu_0812; } +VvBF_1620: Vv_1620^".bf" is Vv_1620 { export Vv_1620; } +VvF8_1620: Vv_1620^".f8" is Vv_1620 { export Vv_1620; } + +define pcodeop v_vgetqfext_Vux_Rt; +define pcodeop v_vgetqfext_Vux_Rt_acc; +define pcodeop v_vsetqfext_Vu_Rt; +define pcodeop v_vabs_Vuf8; +define pcodeop v_vabs_Vuhf; +define pcodeop v_vabs_Vuqf16; +define pcodeop v_vabs_Vuqf32; +define pcodeop v_vabs_Vusf; +define pcodeop v_vadd_Vuf8_Vvf8; +define pcodeop v_vadd_Vuhf_Vvhf; +define pcodeop v_vadd_Vubf_Vvbf; +define pcodeop v_vadd_Vusf_Vvsf; +define pcodeop v_vfmv_Vuw; +define pcodeop Vbf_equals_Vqf32; +define pcodeop Vf8_equals_Vqf16; +define pcodeop Vh_equals_Vhf; +define pcodeop Vhf_equals_Vh; +define pcodeop Vqf16_equals_Vf8; +define pcodeop Vqf16_equals_Vhf; +define pcodeop Vqf16_equals_Vqf16; +define pcodeop Vqf32_equals_Vqf32; +define pcodeop Vqf32_equals_Vsf; +define pcodeop Vsf_equals_Vw; +define pcodeop Vw_equals_Vsf; +define pcodeop v_vcvt2_Vuhf_Vvhf; +define pcodeop v_vcvt2_Vub; +define pcodeop v_vcvt2_Vuub; +define pcodeop v_vcvt_Vuhf_Vvhf; +define pcodeop v_vcvt_Vusf_Vvsf; +define pcodeop v_vcvt_Vuhf; +define pcodeop v_vcvt_Vub; +define pcodeop v_vcvt_Vuf8; +define pcodeop v_vcvt_Vuh; +define pcodeop v_vcvt_Vuub; +define pcodeop v_vcvt_Vuuh; +define pcodeop v_vdmpy_Vuhf_Vvhf; +define pcodeop v_vdmpy_Vuhf_Vvhf_acc; +define pcodeop v_vfmax_Vuf8_Vvf8; +define pcodeop v_vfmax_Vuhf_Vvhf; +define pcodeop v_vfmax_Vusf_Vvsf; +define pcodeop v_vfmin_Vuf8_Vvf8; +define pcodeop v_vfmin_Vuhf_Vvhf; +define pcodeop v_vfmin_Vusf_Vvsf; +define pcodeop v_vfneg_Vuf8; +define pcodeop v_vfneg_Vuhf; +define pcodeop v_vfneg_Vusf; +define pcodeop v_vilog2_Vuhf; +define pcodeop v_vilog2_Vuqf16; +define pcodeop v_vilog2_Vuqf32; +define pcodeop v_vilog2_Vusf; +define pcodeop v_vmax_Vubf_Vvbf; +define pcodeop v_vmerge_Vux_Vvw; +define pcodeop v_vmin_Vubf_Vvbf; +define pcodeop v_vmpy_Vuf8_Vvf8; +define pcodeop v_vmpy_Vuf8_Vvf8_acc; +define pcodeop v_vmpy_Vuhf_Vvhf; +define pcodeop v_vmpy_Vuhf_Vvhf_acc; +define pcodeop v_vmpy_Vuhf_Rthf; +define pcodeop v_vmpy_Vuqf16_Rthf; +define pcodeop v_vmpy_Vusf_Rtsf; +define pcodeop v_vmpy_Vubf_Vvbf; +define pcodeop v_vmpy_Vubf_Vvbf_acc; +define pcodeop v_vmpy_Vusf_Vvsf; +define pcodeop v_vneg_Vuhf; +define pcodeop v_vneg_Vuqf16; +define pcodeop v_vneg_Vuqf32; +define pcodeop v_vneg_Vusf; +define pcodeop v_vrmpy_Vub_Rttub; +define pcodeop v_vrmpy_Vub_Rttub_acc; +define pcodeop v_vrmpy_Vuub_Rttub; +define pcodeop v_vrmpy_Vuub_Rttub_acc; +define pcodeop v_vsub_Vuf8_Vvf8; +define pcodeop v_vsub_Vuhf_Vvhf; +define pcodeop v_vsub_Vuhf_Vvqf16; +define pcodeop v_vsub_Vubf_Vvbf; +define pcodeop v_vsub_Vusf_Vvqf32; +define pcodeop v_vsub_Vusf_Vvsf; +define pcodeop v_zextract_Rt; + +# (v73,1) V6_get_qfext -- "Vd32 = vgetqfext(Vu32.x,Rt32)" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 1 0 0 1 1 1 0 t t t t t P P 0 u u u u u 1 1 1 d d d d d +:vgetqfext Vd5,VuX_0812,rx5 EndPacket is iclass=1 & op2127=0x4e & op13=0 & op0507=0x7 & Vd5 & VuX_0812 & rx5 & $(END_PACKET) { + Vd5 = v_vgetqfext_Vux_Rt(VuX_0812,rx5); + build EndPacket; +} + +# (v73,1) V6_get_qfext_oracc -- "Vx32 |= vgetqfext(Vu32.x,Rt32)" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 1 0 0 1 1 1 0 t t t t t P P 0 u u u u u 1 1 0 x x x x x +:vgetqfext|= Vd5,VuX_0812,rx5 EndPacket is iclass=1 & op2127=0x4e & op13=0 & op0507=0x6 & vs5 & Vd5 & VuX_0812 & rx5 & $(END_PACKET) { + Vd5 = v_vgetqfext_Vux_Rt_acc(vs5,VuX_0812,rx5); + build EndPacket; +} + +# (v73,1) V6_set_qfext -- "Vd32.x = vsetqfext(Vu32,Rt32)" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 1 0 0 1 1 1 0 t t t t t P P 0 u u u u u 0 1 1 d d d d d +:vsetqfext VdX_0004,Vu_0812,rx5 EndPacket is iclass=1 & op2127=0x4e & op13=0 & op0507=0x3 & VdX_0004 & Vu_0812 & rx5 & $(END_PACKET) { + VdX_0004 = v_vsetqfext_Vu_Rt(Vu_0812,rx5); + build EndPacket; +} + +# (v73,1) V6_vabs_f8 -- "Vd32.f8 = vabs(Vu32.f8)" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 1 1 0 0 0 1 1 0 0 1 1 0 P P 1 u u u u u 1 1 0 d d d d d +:vabs VdF8_0004,VuF8_0812 EndPacket is iclass=1 & op2127=0x63 & op1620=0x6 & op13=1 & op0507=0x6 & VdF8_0004 & VuF8_0812 & $(END_PACKET) { + VdF8_0004 = v_vabs_Vuf8(VuF8_0812); + build EndPacket; +} + +# (v73,1) V6_vabs_hf -- "Vd32.hf = vabs(Vu32.hf)" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 1 1 1 0 0 0 0 0 0 1 1 0 P P 1 u u u u u 1 0 0 d d d d d +:vabs VdHF_0004,VuHF_0812 EndPacket is iclass=1 & op2127=0x70 & op1620=0x6 & op13=1 & op0507=0x4 & VdHF_0004 & VuHF_0812 & $(END_PACKET) { + VdHF_0004 = v_vabs_Vuhf(VuHF_0812); + build EndPacket; +} + +# (v73,1) V6_vabs_qf16_hf -- "Vd32.qf16 = vabs(Vu32.hf)" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 1 1 1 0 0 0 0 0 1 1 1 0 P P 1 u u u u u 1 1 0 d d d d d +:vabs VdQF16_0004,VuHF_0812 EndPacket is iclass=1 & op2127=0x70 & op1620=0xe & op13=1 & op0507=0x6 & VdQF16_0004 & VuHF_0812 & $(END_PACKET) { + VdQF16_0004 = v_vabs_Vuhf(VuHF_0812); + build EndPacket; +} + +# (v73,1) V6_vabs_qf16_qf16 -- "Vd32.qf16 = vabs(Vu32.qf16)" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 1 1 1 0 0 0 0 0 1 1 1 0 P P 1 u u u u u 1 1 1 d d d d d +:vabs VdQF16_0004,VuQF16_0812 EndPacket is iclass=1 & op2127=0x70 & op1620=0xe & op13=1 & op0507=0x7 & VdQF16_0004 & VuQF16_0812 & $(END_PACKET) { + VdQF16_0004 = v_vabs_Vuqf16(VuQF16_0812); + build EndPacket; +} + +# (v73,1) V6_vabs_qf32_qf32 -- "Vd32.qf32 = vabs(Vu32.qf32)" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 1 1 1 0 0 0 0 0 1 1 1 0 P P 1 u u u u u 1 0 1 d d d d d +:vabs VdQF32_0004,VuQF32_0812 EndPacket is iclass=1 & op2127=0x70 & op1620=0xe & op13=1 & op0507=0x5 & VdQF32_0004 & VuQF32_0812 & $(END_PACKET) { + VdQF32_0004 = v_vabs_Vuqf32(VuQF32_0812); + build EndPacket; +} + +# (v73,1) V6_vabs_qf32_sf -- "Vd32.qf32 = vabs(Vu32.sf)" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 1 1 1 0 0 0 0 0 1 1 1 0 P P 1 u u u u u 1 0 0 d d d d d +:vabs VdQF32_0004,VuSF_0812 EndPacket is iclass=1 & op2127=0x70 & op1620=0xe & op13=1 & op0507=0x4 & VdQF32_0004 & VuSF_0812 & $(END_PACKET) { + VdQF32_0004 = v_vabs_Vusf(VuSF_0812); + build EndPacket; +} + +# (v73,1) V6_vabs_sf -- "Vd32.sf = vabs(Vu32.sf)" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 1 1 1 0 0 0 0 0 0 1 1 0 P P 1 u u u u u 1 0 1 d d d d d +:vabs VdSF_0004,VuSF_0812 EndPacket is iclass=1 & op2127=0x70 & op1620=0x6 & op13=1 & op0507=0x5 & VdSF_0004 & VuSF_0812 & $(END_PACKET) { + VdSF_0004 = v_vabs_Vusf(VuSF_0812); + build EndPacket; +} + +# (v73,1) V6_vadd_hf_f8 -- "Vdd32.hf = vadd(Vu32.f8,Vv32.f8)" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 1 1 1 1 1 0 0 v v v v v P P 0 u u u u u 1 0 0 d d d d d +:vadd VddHF_0004,VuF8_0812,VvF8_1620 EndPacket is iclass=1 & op2127=0x7c & op13=0 & op0507=0x4 & VddHF_0004 & VuF8_0812 & VvF8_1620 & $(END_PACKET) { + VddHF_0004 = v_vadd_Vuf8_Vvf8(VuF8_0812,VvF8_1620); + build EndPacket; +} + +# (v73,1) V6_vadd_hf_hf -- "Vd32.hf = vadd(Vu32.hf,Vv32.hf)" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 1 1 1 1 1 0 1 v v v v v P P 1 u u u u u 1 1 1 d d d d d +:vadd VdHF_0004,VuHF_0812,VvHF_1620 EndPacket is iclass=1 & op2127=0x7d & op13=1 & op0507=0x7 & VdHF_0004 & VuHF_0812 & VvHF_1620 & $(END_PACKET) { + VdHF_0004 = v_vadd_Vuhf_Vvhf(VuHF_0812,VvHF_1620); + build EndPacket; +} + +# (v73,1) V6_vadd_sf_bf -- "Vdd32.sf = vadd(Vu32.bf,Vv32.bf)" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 1 1 0 1 0 1 0 v v v v v P P 1 u u u u u 1 1 0 d d d d d +:vadd VddSF_0004,VuBF_0812,VvBF_1620 EndPacket is iclass=1 & op2127=0x6a & op13=1 & op0507=0x6 & VddSF_0004 & VuBF_0812 & VvBF_1620 & $(END_PACKET) { + VddSF_0004 = v_vadd_Vubf_Vvbf(VuBF_0812,VvBF_1620); + build EndPacket; +} + +# (v73,1) V6_vadd_sf_hf -- "Vdd32.sf = vadd(Vu32.hf,Vv32.hf)" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 1 1 1 1 1 0 0 v v v v v P P 1 u u u u u 1 0 0 d d d d d +:vadd VddSF_0004,VuHF_0812,VvHF_1620 EndPacket is iclass=1 & op2127=0x7c & op13=1 & op0507=0x4 & VddSF_0004 & VuHF_0812 & VvHF_1620 & $(END_PACKET) { + VddSF_0004 = v_vadd_Vuhf_Vvhf(VuHF_0812,VvHF_1620); + build EndPacket; +} + +# (v73,1) V6_vadd_sf_sf -- "Vd32.sf = vadd(Vu32.sf,Vv32.sf)" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 1 1 1 1 1 0 0 v v v v v P P 1 u u u u u 1 1 0 d d d d d +:vadd VdSF_0004,VuSF_0812,VvSF_1620 EndPacket is iclass=1 & op2127=0x7c & op13=1 & op0507=0x6 & VdSF_0004 & VuSF_0812 & VvSF_1620 & $(END_PACKET) { + VdSF_0004 = v_vadd_Vusf_Vvsf(VuSF_0812,VvSF_1620); + build EndPacket; +} + +# (v73,1) V6_vassign_fp -- "Vd32.w = vfmv(Vu32.w)" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 1 1 1 0 0 0 0 0 0 1 1 0 P P 1 u u u u u 0 0 1 d d d d d +:vfmv VdW_0004,VuW_0812 EndPacket is iclass=1 & op2127=0x70 & op1620=0x6 & op13=1 & op0507=0x1 & VdW_0004 & VuW_0812 & $(END_PACKET) { + VdW_0004 = v_vfmv_Vuw(VuW_0812); + build EndPacket; +} + +# (v73,1) V6_vconv_bf_qf32 -- "Vd32.bf = Vuu32.qf32" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 1 1 1 0 0 0 0 0 0 1 1 0 P P 1 u u u u u 1 1 1 d d d d d +:assign VdBF_0004,VuuQF32_0812 EndPacket is iclass=1 & op2127=0x70 & op1620=0x6 & op13=1 & op0507=0x7 & VdBF_0004 & VuuQF32_0812 & $(END_PACKET) { + VdBF_0004 = Vbf_equals_Vqf32(VuuQF32_0812); + build EndPacket; +} + +# (v73,1) V6_vconv_f8_qf16 -- "Vd32.f8 = Vu32.qf16" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 1 1 1 0 0 0 0 0 1 1 0 0 P P 1 u u u u u 1 1 1 d d d d d +:assign VdF8_0004,VuQF16_0812 EndPacket is iclass=1 & op2127=0x70 & op1620=0xc & op13=1 & op0507=0x7 & VdF8_0004 & VuQF16_0812 & $(END_PACKET) { + VdF8_0004 = Vf8_equals_Vqf16(VuQF16_0812); + build EndPacket; +} + +# (v73,1) V6_vconv_h_hf -- "Vd32.h = Vu32.hf" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 1 1 1 0 - - 0 - - 1 0 1 P P 1 u u u u u 0 1 0 d d d d d +:assign VdH_0004,VuHF_0812 EndPacket is iclass=1 & op2427=0xe & op21=0 & op1618=0x5 & op13=1 & op0507=0x2 & VdH_0004 & VuHF_0812 & $(END_PACKET) { + VdH_0004 = Vh_equals_Vhf(VuHF_0812); + build EndPacket; +} + +# (v73,1) V6_vconv_h_hf_rnd -- "Vd32.h = Vu32.hf:rnd" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 1 1 1 0 0 0 0 0 0 1 1 0 P P 1 u u u u u 1 1 0 d d d d d +:assign^":rnd" VdH_0004,VuHF_0812 EndPacket is iclass=1 & op2127=0x70 & op1620=0x6 & op13=1 & op0507=0x6 & VdH_0004 & VuHF_0812 & $(END_PACKET) { + VdH_0004 = Vh_equals_Vhf(VuHF_0812); + build EndPacket; +} + +# (v73,1) V6_vconv_hf_h -- "Vd32.hf = Vu32.h" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 1 1 1 0 - - 0 - - 1 0 1 P P 1 u u u u u 1 0 0 d d d d d +:assign VdHF_0004,VuH_0812 EndPacket is iclass=1 & op2427=0xe & op21=0 & op1618=0x5 & op13=1 & op0507=0x4 & VdHF_0004 & VuH_0812 & $(END_PACKET) { + VdHF_0004 = Vhf_equals_Vh(VuH_0812); + build EndPacket; +} + +# (v73,1) V6_vconv_qf16_f8 -- "Vdd32.qf16 = Vu32.f8" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 1 1 1 0 0 0 0 0 1 1 0 0 P P 1 u u u u u 1 0 1 d d d d d +:assign VddQF16_0004,VuF8_0812 EndPacket is iclass=1 & op2127=0x70 & op1620=0xc & op13=1 & op0507=0x5 & VddQF16_0004 & VuF8_0812 & $(END_PACKET) { + VddQF16_0004 = Vqf16_equals_Vf8(VuF8_0812); + build EndPacket; +} + +# (v73,1) V6_vconv_qf16_hf -- "Vd32.qf16 = Vu32.hf" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 1 1 1 0 0 0 0 0 1 1 0 0 P P 1 u u u u u 1 0 0 d d d d d +:assign VdQF16_0004,VuHF_0812 EndPacket is iclass=1 & op2127=0x70 & op1620=0xc & op13=1 & op0507=0x4 & VdQF16_0004 & VuHF_0812 & $(END_PACKET) { + VdQF16_0004 = Vqf16_equals_Vhf(VuHF_0812); + build EndPacket; +} + +# (v73,1) V6_vconv_qf16_qf16 -- "Vd32.qf16 = Vu32.qf16" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 1 1 1 0 0 0 0 0 1 1 0 0 P P 1 u u u u u 1 1 0 d d d d d +:assign VdQF16_0004,VuQF16_0812 EndPacket is iclass=1 & op2127=0x70 & op1620=0xc & op13=1 & op0507=0x6 & VdQF16_0004 & VuQF16_0812 & $(END_PACKET) { + VdQF16_0004 = Vqf16_equals_Vqf16(VuQF16_0812); + build EndPacket; +} + +# (v73,1) V6_vconv_qf32_qf32 -- "Vd32.qf32 = Vu32.qf32" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 1 1 1 0 0 0 0 0 1 1 0 1 P P 1 u u u u u 1 1 1 d d d d d +:assign VdQF32_0004,VuQF32_0812 EndPacket is iclass=1 & op2127=0x70 & op1620=0xd & op13=1 & op0507=0x7 & VdQF32_0004 & VuQF32_0812 & $(END_PACKET) { + VdQF32_0004 = Vqf32_equals_Vqf32(VuQF32_0812); + build EndPacket; +} + +# (v73,1) V6_vconv_qf32_sf -- "Vd32.qf32 = Vu32.sf" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 1 1 1 0 0 0 0 0 1 1 0 1 P P 1 u u u u u 1 1 0 d d d d d +:assign VdQF32_0004,VuSF_0812 EndPacket is iclass=1 & op2127=0x70 & op1620=0xd & op13=1 & op0507=0x6 & VdQF32_0004 & VuSF_0812 & $(END_PACKET) { + VdQF32_0004 = Vqf32_equals_Vsf(VuSF_0812); + build EndPacket; +} + +# (v73,1) V6_vconv_sf_w -- "Vd32.sf = Vu32.w" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 1 1 1 0 - - 0 - - 1 0 1 P P 1 u u u u u 0 1 1 d d d d d +:assign VdSF_0004,VuW_0812 EndPacket is iclass=1 & op2427=0xe & op21=0 & op1618=0x5 & op13=1 & op0507=0x3 & VdSF_0004 & VuW_0812 & $(END_PACKET) { + VdSF_0004 = Vsf_equals_Vw(VuW_0812); + build EndPacket; +} + +# (v73,1) V6_vconv_w_sf -- "Vd32.w = Vu32.sf" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 1 1 1 0 - - 0 - - 1 0 1 P P 1 u u u u u 0 0 1 d d d d d +:assign VdW_0004,VuSF_0812 EndPacket is iclass=1 & op2427=0xe & op21=0 & op1618=0x5 & op13=1 & op0507=0x1 & VdW_0004 & VuSF_0812 & $(END_PACKET) { + VdW_0004 = Vw_equals_Vsf(VuSF_0812); + build EndPacket; +} + +# (v73,1) V6_vcvt2_b_hf -- "Vd32.b = vcvt2(Vu32.hf,Vv32.hf)" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 1 0 1 0 1 1 0 v v v v v P P 1 u u u u u 1 1 0 d d d d d +:vcvt2 VdB_0004,VuHF_0812,VvHF_1620 EndPacket is iclass=1 & op2127=0x56 & op13=1 & op0507=0x6 & VdB_0004 & VuHF_0812 & VvHF_1620 & $(END_PACKET) { + VdB_0004 = v_vcvt2_Vuhf_Vvhf(VuHF_0812,VvHF_1620); + build EndPacket; +} + +# (v73,1) V6_vcvt2_hf_b -- "Vdd32.hf = vcvt2(Vu32.b)" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 1 1 1 0 1 1 0 1 0 1 0 1 P P 1 u u u u u 1 1 0 d d d d d +:vcvt2 VddHF_0004,VuB_0812 EndPacket is iclass=1 & op2127=0x76 & op1620=0x15 & op13=1 & op0507=0x6 & VddHF_0004 & VuB_0812 & $(END_PACKET) { + VddHF_0004 = v_vcvt2_Vub(VuB_0812); + build EndPacket; +} + +# (v73,1) V6_vcvt2_hf_ub -- "Vdd32.hf = vcvt2(Vu32.ub)" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 1 1 1 0 1 1 0 1 0 1 0 1 P P 1 u u u u u 1 1 1 d d d d d +:vcvt2 VddHF_0004,VuUB_0812 EndPacket is iclass=1 & op2127=0x76 & op1620=0x15 & op13=1 & op0507=0x7 & VddHF_0004 & VuUB_0812 & $(END_PACKET) { + VddHF_0004 = v_vcvt2_Vuub(VuUB_0812); + build EndPacket; +} + +# (v73,1) V6_vcvt2_ub_hf -- "Vd32.ub = vcvt2(Vu32.hf,Vv32.hf)" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 1 0 1 0 1 1 0 v v v v v P P 1 u u u u u 1 1 1 d d d d d +:vcvt2 VdUB_0004,VuHF_0812,VvHF_1620 EndPacket is iclass=1 & op2127=0x56 & op13=1 & op0507=0x7 & VdUB_0004 & VuHF_0812 & VvHF_1620 & $(END_PACKET) { + VdUB_0004 = v_vcvt2_Vuhf_Vvhf(VuHF_0812,VvHF_1620); + build EndPacket; +} + +# (v73,1) V6_vcvt_b_hf -- "Vd32.b = vcvt(Vu32.hf,Vv32.hf)" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 1 1 1 1 1 1 0 v v v v v P P 1 u u u u u 1 1 0 d d d d d +:vcvt VdB_0004,VuHF_0812,VvHF_1620 EndPacket is iclass=1 & op2127=0x7e & op13=1 & op0507=0x6 & VdB_0004 & VuHF_0812 & VvHF_1620 & $(END_PACKET) { + VdB_0004 = v_vcvt_Vuhf_Vvhf(VuHF_0812,VvHF_1620); + build EndPacket; +} + +# (v73,1) V6_vcvt_bf_sf -- "Vd32.bf = vcvt(Vu32.sf,Vv32.sf)" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 1 1 0 1 0 1 0 v v v v v P P 1 u u u u u 0 1 1 d d d d d +:vcvt VdBF_0004,VuSF_0812,VvSF_1620 EndPacket is iclass=1 & op2127=0x6a & op13=1 & op0507=0x3 & VdBF_0004 & VuSF_0812 & VvSF_1620 & $(END_PACKET) { + VdBF_0004 = v_vcvt_Vusf_Vvsf(VuSF_0812,VvSF_1620); + build EndPacket; +} + +# (v73,1) V6_vcvt_f8_hf -- "Vd32.f8 = vcvt(Vu32.hf,Vv32.hf)" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 1 1 1 1 1 1 1 v v v v v P P 1 u u u u u 0 1 0 d d d d d +:vcvt VdF8_0004,VuHF_0812,VvHF_1620 EndPacket is iclass=1 & op2127=0x7f & op13=1 & op0507=0x2 & VdF8_0004 & VuHF_0812 & VvHF_1620 & $(END_PACKET) { + VdF8_0004 = v_vcvt_Vuhf_Vvhf(VuHF_0812,VvHF_1620); + build EndPacket; +} + +# (v73,1) V6_vcvt_h_hf -- "Vd32.h = vcvt(Vu32.hf)" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 1 1 1 0 0 0 0 0 0 1 1 0 P P 1 u u u u u 0 0 0 d d d d d +:vcvt VdH_0004,VuHF_0812 EndPacket is iclass=1 & op2127=0x70 & op1620=0x6 & op13=1 & op0507=0x0 & VdH_0004 & VuHF_0812 & $(END_PACKET) { + VdH_0004 = v_vcvt_Vuhf(VuHF_0812); + build EndPacket; +} + +# (v73,1) V6_vcvt_hf_b -- "Vdd32.hf = vcvt(Vu32.b)" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 1 1 1 0 0 0 0 0 0 1 0 0 P P 1 u u u u u 0 1 0 d d d d d +:vcvt VddHF_0004,VuB_0812 EndPacket is iclass=1 & op2127=0x70 & op1620=0x4 & op13=1 & op0507=0x2 & VddHF_0004 & VuB_0812 & $(END_PACKET) { + VddHF_0004 = v_vcvt_Vub(VuB_0812); + build EndPacket; +} + +# (v73,1) V6_vcvt_hf_f8 -- "Vdd32.hf = vcvt(Vu32.f8)" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 1 1 1 0 0 0 0 0 0 1 0 1 P P 1 u u u u u 1 0 1 d d d d d +:vcvt VddHF_0004,VuF8_0812 EndPacket is iclass=1 & op2127=0x70 & op1620=0x5 & op13=1 & op0507=0x5 & VddHF_0004 & VuF8_0812 & $(END_PACKET) { + VddHF_0004 = v_vcvt_Vuf8(VuF8_0812); + build EndPacket; +} + +# (v73,1) V6_vcvt_hf_h -- "Vd32.hf = vcvt(Vu32.h)" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 1 1 1 0 0 0 0 0 0 1 0 0 P P 1 u u u u u 1 1 1 d d d d d +:vcvt VdHF_0004,VuH_0812 EndPacket is iclass=1 & op2127=0x70 & op1620=0x4 & op13=1 & op0507=0x7 & VdHF_0004 & VuH_0812 & $(END_PACKET) { + VdHF_0004 = v_vcvt_Vuh(VuH_0812); + build EndPacket; +} + +# (v73,1) V6_vcvt_hf_sf -- "Vd32.hf = vcvt(Vu32.sf,Vv32.sf)" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 1 1 1 1 0 1 1 v v v v v P P 1 u u u u u 0 0 1 d d d d d +:vcvt VdHF_0004,VuSF_0812,VvSF_1620 EndPacket is iclass=1 & op2127=0x7b & op13=1 & op0507=0x1 & VdHF_0004 & VuSF_0812 & VvSF_1620 & $(END_PACKET) { + VdHF_0004 = v_vcvt_Vusf_Vvsf(VuSF_0812,VvSF_1620); + build EndPacket; +} + +# (v73,1) V6_vcvt_hf_ub -- "Vdd32.hf = vcvt(Vu32.ub)" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 1 1 1 0 0 0 0 0 0 1 0 0 P P 1 u u u u u 0 0 1 d d d d d +:vcvt VddHF_0004,VuUB_0812 EndPacket is iclass=1 & op2127=0x70 & op1620=0x4 & op13=1 & op0507=0x1 & VddHF_0004 & VuUB_0812 & $(END_PACKET) { + VddHF_0004 = v_vcvt_Vuub(VuUB_0812); + build EndPacket; +} + +# (v73,1) V6_vcvt_hf_uh -- "Vd32.hf = vcvt(Vu32.uh)" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 1 1 1 0 0 0 0 0 0 1 0 0 P P 1 u u u u u 1 0 1 d d d d d +:vcvt VdHF_0004,VuUH_0812 EndPacket is iclass=1 & op2127=0x70 & op1620=0x4 & op13=1 & op0507=0x5 & VdHF_0004 & VuUH_0812 & $(END_PACKET) { + VdHF_0004 = v_vcvt_Vuuh(VuUH_0812); + build EndPacket; +} + +# (v73,1) V6_vcvt_sf_hf -- "Vdd32.sf = vcvt(Vu32.hf)" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 1 1 1 0 0 0 0 0 0 1 0 0 P P 1 u u u u u 1 0 0 d d d d d +:vcvt VddSF_0004,VuHF_0812 EndPacket is iclass=1 & op2127=0x70 & op1620=0x4 & op13=1 & op0507=0x4 & VddSF_0004 & VuHF_0812 & $(END_PACKET) { + VddSF_0004 = v_vcvt_Vuhf(VuHF_0812); + build EndPacket; +} + +# (v73,1) V6_vcvt_ub_hf -- "Vd32.ub = vcvt(Vu32.hf,Vv32.hf)" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 1 1 1 1 1 1 0 v v v v v P P 1 u u u u u 1 0 1 d d d d d +:vcvt VdUB_0004,VuHF_0812,VvHF_1620 EndPacket is iclass=1 & op2127=0x7e & op13=1 & op0507=0x5 & VdUB_0004 & VuHF_0812 & VvHF_1620 & $(END_PACKET) { + VdUB_0004 = v_vcvt_Vuhf_Vvhf(VuHF_0812,VvHF_1620); + build EndPacket; +} + +# (v73,1) V6_vcvt_uh_hf -- "Vd32.uh = vcvt(Vu32.hf)" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 1 1 1 0 0 0 0 0 0 1 0 1 P P 1 u u u u u 0 0 0 d d d d d +:vcvt VdUH_0004,VuHF_0812 EndPacket is iclass=1 & op2127=0x70 & op1620=0x5 & op13=1 & op0507=0x0 & VdUH_0004 & VuHF_0812 & $(END_PACKET) { + VdUH_0004 = v_vcvt_Vuhf(VuHF_0812); + build EndPacket; +} + +# (v73,1) V6_vdmpy_sf_hf -- "Vd32.sf = vdmpy(Vu32.hf,Vv32.hf)" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 1 1 1 1 1 0 1 v v v v v P P 1 u u u u u 1 1 0 d d d d d +:vdmpy VdSF_0004,VuHF_0812,VvHF_1620 EndPacket is iclass=1 & op2127=0x7d & op13=1 & op0507=0x6 & VdSF_0004 & VuHF_0812 & VvHF_1620 & $(END_PACKET) { + VdSF_0004 = v_vdmpy_Vuhf_Vvhf(VuHF_0812,VvHF_1620); + build EndPacket; +} + +# (v73,1) V6_vdmpy_sf_hf_acc -- "Vx32.sf += vdmpy(Vu32.hf,Vv32.hf)" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 1 1 0 0 0 1 0 v v v v v P P 1 u u u u u 0 1 1 x x x x x +:vdmpy+= VdSF_0004,VuHF_0812,VvHF_1620 EndPacket is iclass=1 & op2127=0x62 & op13=1 & op0507=0x3 & vs5 & VdSF_0004 & VuHF_0812 & VvHF_1620 & $(END_PACKET) { + VdSF_0004 = v_vdmpy_Vuhf_Vvhf_acc(vs5,VuHF_0812,VvHF_1620); + build EndPacket; +} + +# (v73,1) V6_vfmax_f8 -- "Vd32.f8 = vfmax(Vu32.f8,Vv32.f8)" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 1 1 0 0 0 1 1 v v v v v P P 1 u u u u u 1 0 1 d d d d d +:vfmax VdF8_0004,VuF8_0812,VvF8_1620 EndPacket is iclass=1 & op2127=0x63 & op13=1 & op0507=0x5 & VdF8_0004 & VuF8_0812 & VvF8_1620 & $(END_PACKET) { + VdF8_0004 = v_vfmax_Vuf8_Vvf8(VuF8_0812,VvF8_1620); + build EndPacket; +} + +# (v73,1) V6_vfmax_hf -- "Vd32.hf = vfmax(Vu32.hf,Vv32.hf)" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 1 1 0 0 0 1 1 v v v v v P P 1 u u u u u 0 1 0 d d d d d +:vfmax VdHF_0004,VuHF_0812,VvHF_1620 EndPacket is iclass=1 & op2127=0x63 & op13=1 & op0507=0x2 & VdHF_0004 & VuHF_0812 & VvHF_1620 & $(END_PACKET) { + VdHF_0004 = v_vfmax_Vuhf_Vvhf(VuHF_0812,VvHF_1620); + build EndPacket; +} + +# (v73,1) V6_vfmax_sf -- "Vd32.sf = vfmax(Vu32.sf,Vv32.sf)" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 1 1 0 0 0 1 1 v v v v v P P 1 u u u u u 0 1 1 d d d d d +:vfmax VdSF_0004,VuSF_0812,VvSF_1620 EndPacket is iclass=1 & op2127=0x63 & op13=1 & op0507=0x3 & VdSF_0004 & VuSF_0812 & VvSF_1620 & $(END_PACKET) { + VdSF_0004 = v_vfmax_Vusf_Vvsf(VuSF_0812,VvSF_1620); + build EndPacket; +} + +# (v73,1) V6_vfmin_f8 -- "Vd32.f8 = vfmin(Vu32.f8,Vv32.f8)" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 1 1 0 0 0 1 1 v v v v v P P 1 u u u u u 1 0 0 d d d d d +:vfmin VdF8_0004,VuF8_0812,VvF8_1620 EndPacket is iclass=1 & op2127=0x63 & op13=1 & op0507=0x4 & VdF8_0004 & VuF8_0812 & VvF8_1620 & $(END_PACKET) { + VdF8_0004 = v_vfmin_Vuf8_Vvf8(VuF8_0812,VvF8_1620); + build EndPacket; +} + +# (v73,1) V6_vfmin_hf -- "Vd32.hf = vfmin(Vu32.hf,Vv32.hf)" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 1 1 0 0 0 1 1 v v v v v P P 1 u u u u u 0 0 0 d d d d d +:vfmin VdHF_0004,VuHF_0812,VvHF_1620 EndPacket is iclass=1 & op2127=0x63 & op13=1 & op0507=0x0 & VdHF_0004 & VuHF_0812 & VvHF_1620 & $(END_PACKET) { + VdHF_0004 = v_vfmin_Vuhf_Vvhf(VuHF_0812,VvHF_1620); + build EndPacket; +} + +# (v73,1) V6_vfmin_sf -- "Vd32.sf = vfmin(Vu32.sf,Vv32.sf)" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 1 1 0 0 0 1 1 v v v v v P P 1 u u u u u 0 0 1 d d d d d +:vfmin VdSF_0004,VuSF_0812,VvSF_1620 EndPacket is iclass=1 & op2127=0x63 & op13=1 & op0507=0x1 & VdSF_0004 & VuSF_0812 & VvSF_1620 & $(END_PACKET) { + VdSF_0004 = v_vfmin_Vusf_Vvsf(VuSF_0812,VvSF_1620); + build EndPacket; +} + +# (v73,1) V6_vfneg_f8 -- "Vd32.f8 = vfneg(Vu32.f8)" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 1 1 0 0 0 1 1 0 0 1 1 0 P P 1 u u u u u 1 1 1 d d d d d +:vfneg VdF8_0004,VuF8_0812 EndPacket is iclass=1 & op2127=0x63 & op1620=0x6 & op13=1 & op0507=0x7 & VdF8_0004 & VuF8_0812 & $(END_PACKET) { + VdF8_0004 = v_vfneg_Vuf8(VuF8_0812); + build EndPacket; +} + +# (v73,1) V6_vfneg_hf -- "Vd32.hf = vfneg(Vu32.hf)" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 1 1 1 0 0 0 0 0 0 1 1 0 P P 1 u u u u u 0 1 0 d d d d d +:vfneg VdHF_0004,VuHF_0812 EndPacket is iclass=1 & op2127=0x70 & op1620=0x6 & op13=1 & op0507=0x2 & VdHF_0004 & VuHF_0812 & $(END_PACKET) { + VdHF_0004 = v_vfneg_Vuhf(VuHF_0812); + build EndPacket; +} + +# (v73,1) V6_vfneg_sf -- "Vd32.sf = vfneg(Vu32.sf)" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 1 1 1 0 0 0 0 0 0 1 1 0 P P 1 u u u u u 0 1 1 d d d d d +:vfneg VdSF_0004,VuSF_0812 EndPacket is iclass=1 & op2127=0x70 & op1620=0x6 & op13=1 & op0507=0x3 & VdSF_0004 & VuSF_0812 & $(END_PACKET) { + VdSF_0004 = v_vfneg_Vusf(VuSF_0812); + build EndPacket; +} + +# (v73,1) V6_vilog2_hf -- "Vd32.w = vilog2(Vu32.hf)" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 1 1 1 0 0 0 0 0 1 1 0 0 P P 1 u u u u u 0 1 1 d d d d d +:vilog2 VdW_0004,VuHF_0812 EndPacket is iclass=1 & op2127=0x70 & op1620=0xc & op13=1 & op0507=0x3 & VdW_0004 & VuHF_0812 & $(END_PACKET) { + VdW_0004 = v_vilog2_Vuhf(VuHF_0812); + build EndPacket; +} + +# (v73,1) V6_vilog2_qf16 -- "Vd32.w = vilog2(Vu32.qf16)" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 1 1 1 0 0 0 0 0 1 1 0 0 P P 1 u u u u u 0 0 1 d d d d d +:vilog2 VdW_0004,VuQF16_0812 EndPacket is iclass=1 & op2127=0x70 & op1620=0xc & op13=1 & op0507=0x1 & VdW_0004 & VuQF16_0812 & $(END_PACKET) { + VdW_0004 = v_vilog2_Vuqf16(VuQF16_0812); + build EndPacket; +} + +# (v73,1) V6_vilog2_qf32 -- "Vd32.w = vilog2(Vu32.qf32)" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 1 1 1 0 0 0 0 0 1 1 0 0 P P 1 u u u u u 0 0 0 d d d d d +:vilog2 VdW_0004,VuQF32_0812 EndPacket is iclass=1 & op2127=0x70 & op1620=0xc & op13=1 & op0507=0x0 & VdW_0004 & VuQF32_0812 & $(END_PACKET) { + VdW_0004 = v_vilog2_Vuqf32(VuQF32_0812); + build EndPacket; +} + +# (v73,1) V6_vilog2_sf -- "Vd32.w = vilog2(Vu32.sf)" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 1 1 1 0 0 0 0 0 1 1 0 0 P P 1 u u u u u 0 1 0 d d d d d +:vilog2 VdW_0004,VuSF_0812 EndPacket is iclass=1 & op2127=0x70 & op1620=0xc & op13=1 & op0507=0x2 & VdW_0004 & VuSF_0812 & $(END_PACKET) { + VdW_0004 = v_vilog2_Vusf(VuSF_0812); + build EndPacket; +} + +# (v73,1) V6_vmax_bf -- "Vd32.bf = vmax(Vu32.bf,Vv32.bf)" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 1 1 0 1 0 1 0 v v v v v P P 1 u u u u u 1 1 1 d d d d d +:vmax VdBF_0004,VuBF_0812,VvBF_1620 EndPacket is iclass=1 & op2127=0x6a & op13=1 & op0507=0x7 & VdBF_0004 & VuBF_0812 & VvBF_1620 & $(END_PACKET) { + VdBF_0004 = v_vmax_Vubf_Vvbf(VuBF_0812,VvBF_1620); + build EndPacket; +} + +# (v73,1) V6_vmerge_qf -- "Vd32 = vmerge(Vu32.x,Vv32.w)" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 1 1 1 1 0 0 0 v v v v v P P 1 u u u u u 1 1 1 d d d d d +:vmerge Vd5,VuX_0812,VvW_1620 EndPacket is iclass=1 & op2127=0x78 & op13=1 & op0507=0x7 & Vd5 & VuX_0812 & VvW_1620 & $(END_PACKET) { + Vd5 = v_vmerge_Vux_Vvw(VuX_0812,VvW_1620); + build EndPacket; +} + +# (v73,1) V6_vmin_bf -- "Vd32.bf = vmin(Vu32.bf,Vv32.bf)" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 1 1 0 1 0 1 0 v v v v v P P 1 u u u u u 0 0 0 d d d d d +:vmin VdBF_0004,VuBF_0812,VvBF_1620 EndPacket is iclass=1 & op2127=0x6a & op13=1 & op0507=0x0 & VdBF_0004 & VuBF_0812 & VvBF_1620 & $(END_PACKET) { + VdBF_0004 = v_vmin_Vubf_Vvbf(VuBF_0812,VvBF_1620); + build EndPacket; +} + +# (v73,1) V6_vmpy_hf_f8 -- "Vdd32.hf = vmpy(Vu32.f8,Vv32.f8)" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 1 1 1 1 1 0 0 v v v v v P P 0 u u u u u 1 1 0 d d d d d +:vmpy VddHF_0004,VuF8_0812,VvF8_1620 EndPacket is iclass=1 & op2127=0x7c & op13=0 & op0507=0x6 & VddHF_0004 & VuF8_0812 & VvF8_1620 & $(END_PACKET) { + VddHF_0004 = v_vmpy_Vuf8_Vvf8(VuF8_0812,VvF8_1620); + build EndPacket; +} + +# (v73,1) V6_vmpy_hf_f8_acc -- "Vxx32.hf += vmpy(Vu32.f8,Vv32.f8)" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 1 1 1 1 1 0 0 v v v v v P P 0 u u u u u 1 1 1 x x x x x +:vmpy+= VddHF_0004,VuF8_0812,VvF8_1620 EndPacket is iclass=1 & op2127=0x7c & op13=0 & op0507=0x7 & Vss_0004 & VddHF_0004 & VuF8_0812 & VvF8_1620 & $(END_PACKET) { + VddHF_0004 = v_vmpy_Vuf8_Vvf8_acc(Vss_0004,VuF8_0812,VvF8_1620); + build EndPacket; +} + +# (v73,1) V6_vmpy_hf_hf -- "Vd32.hf = vmpy(Vu32.hf,Vv32.hf)" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 1 1 1 1 1 0 0 v v v v v P P 1 u u u u u 0 1 1 d d d d d +:vmpy VdHF_0004,VuHF_0812,VvHF_1620 EndPacket is iclass=1 & op2127=0x7c & op13=1 & op0507=0x3 & VdHF_0004 & VuHF_0812 & VvHF_1620 & $(END_PACKET) { + VdHF_0004 = v_vmpy_Vuhf_Vvhf(VuHF_0812,VvHF_1620); + build EndPacket; +} + +# (v73,1) V6_vmpy_hf_hf_acc -- "Vx32.hf += vmpy(Vu32.hf,Vv32.hf)" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 1 1 0 0 0 1 0 v v v v v P P 1 u u u u u 0 1 0 x x x x x +:vmpy+= VdHF_0004,VuHF_0812,VvHF_1620 EndPacket is iclass=1 & op2127=0x62 & op13=1 & op0507=0x2 & vs5 & VdHF_0004 & VuHF_0812 & VvHF_1620 & $(END_PACKET) { + VdHF_0004 = v_vmpy_Vuhf_Vvhf_acc(vs5,VuHF_0812,VvHF_1620); + build EndPacket; +} + +# (v73,1) V6_vmpy_rt_hf -- "Vd32.qf16 = vmpy(Vu32.hf,Rt32.hf)" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 1 0 1 0 0 0 0 t t t t t P P 1 u u u u u 0 1 1 d d d d d +:vmpy VdQF16_0004,VuHF_0812,RtHF_1620 EndPacket is iclass=1 & op2127=0x50 & op13=1 & op0507=0x3 & VdQF16_0004 & VuHF_0812 & RtHF_1620 & $(END_PACKET) { + VdQF16_0004 = v_vmpy_Vuhf_Rthf(VuHF_0812,RtHF_1620); + build EndPacket; +} + +# (v73,1) V6_vmpy_rt_qf16 -- "Vd32.qf16 = vmpy(Vu32.qf16,Rt32.hf)" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 1 0 1 0 0 0 0 t t t t t P P 1 u u u u u 0 1 0 d d d d d +:vmpy VdQF16_0004,VuQF16_0812,RtHF_1620 EndPacket is iclass=1 & op2127=0x50 & op13=1 & op0507=0x2 & VdQF16_0004 & VuQF16_0812 & RtHF_1620 & $(END_PACKET) { + VdQF16_0004 = v_vmpy_Vuqf16_Rthf(VuQF16_0812,RtHF_1620); + build EndPacket; +} + +# (v73,1) V6_vmpy_rt_sf -- "Vd32.qf32 = vmpy(Vu32.sf,Rt32.sf)" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 1 0 1 0 0 0 0 t t t t t P P 1 u u u u u 0 0 1 d d d d d +:vmpy VdQF32_0004,VuSF_0812,RtSF_1620 EndPacket is iclass=1 & op2127=0x50 & op13=1 & op0507=0x1 & VdQF32_0004 & VuSF_0812 & RtSF_1620 & $(END_PACKET) { + VdQF32_0004 = v_vmpy_Vusf_Rtsf(VuSF_0812,RtSF_1620); + build EndPacket; +} + +# (v73,1) V6_vmpy_sf_bf -- "Vdd32.sf = vmpy(Vu32.bf,Vv32.bf)" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 1 1 0 1 0 1 0 v v v v v P P 1 u u u u u 1 0 0 d d d d d +:vmpy VddSF_0004,VuBF_0812,VvBF_1620 EndPacket is iclass=1 & op2127=0x6a & op13=1 & op0507=0x4 & VddSF_0004 & VuBF_0812 & VvBF_1620 & $(END_PACKET) { + VddSF_0004 = v_vmpy_Vubf_Vvbf(VuBF_0812,VvBF_1620); + build EndPacket; +} + +# (v73,1) V6_vmpy_sf_bf_acc -- "Vxx32.sf += vmpy(Vu32.bf,Vv32.bf)" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 1 1 0 1 0 0 0 v v v v v P P 1 u u u u u 0 0 0 x x x x x +:vmpy+= VddSF_0004,VuBF_0812,VvBF_1620 EndPacket is iclass=1 & op2127=0x68 & op13=1 & op0507=0x0 & Vss_0004 & VddSF_0004 & VuBF_0812 & VvBF_1620 & $(END_PACKET) { + VddSF_0004 = v_vmpy_Vubf_Vvbf_acc(Vss_0004,VuBF_0812,VvBF_1620); + build EndPacket; +} + +# (v73,1) V6_vmpy_sf_hf -- "Vdd32.sf = vmpy(Vu32.hf,Vv32.hf)" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 1 1 1 1 1 0 0 v v v v v P P 1 u u u u u 0 1 0 d d d d d +:vmpy VddSF_0004,VuHF_0812,VvHF_1620 EndPacket is iclass=1 & op2127=0x7c & op13=1 & op0507=0x2 & VddSF_0004 & VuHF_0812 & VvHF_1620 & $(END_PACKET) { + VddSF_0004 = v_vmpy_Vuhf_Vvhf(VuHF_0812,VvHF_1620); + build EndPacket; +} + +# (v73,1) V6_vmpy_sf_hf_acc -- "Vxx32.sf += vmpy(Vu32.hf,Vv32.hf)" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 1 1 0 0 0 1 0 v v v v v P P 1 u u u u u 0 0 1 x x x x x +:vmpy+= VddSF_0004,VuHF_0812,VvHF_1620 EndPacket is iclass=1 & op2127=0x62 & op13=1 & op0507=0x1 & Vss_0004 & VddSF_0004 & VuHF_0812 & VvHF_1620 & $(END_PACKET) { + VddSF_0004 = v_vmpy_Vuhf_Vvhf_acc(Vss_0004,VuHF_0812,VvHF_1620); + build EndPacket; +} + +# (v73,1) V6_vmpy_sf_sf -- "Vd32.sf = vmpy(Vu32.sf,Vv32.sf)" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 1 1 1 1 1 0 0 v v v v v P P 1 u u u u u 0 0 1 d d d d d +:vmpy VdSF_0004,VuSF_0812,VvSF_1620 EndPacket is iclass=1 & op2127=0x7c & op13=1 & op0507=0x1 & VdSF_0004 & VuSF_0812 & VvSF_1620 & $(END_PACKET) { + VdSF_0004 = v_vmpy_Vusf_Vvsf(VuSF_0812,VvSF_1620); + build EndPacket; +} + +# (v73,1) V6_vneg_qf16_hf -- "Vd32.qf16 = vneg(Vu32.hf)" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 1 1 1 0 0 0 0 0 1 1 1 0 P P 1 u u u u u 0 1 0 d d d d d +:vneg VdQF16_0004,VuHF_0812 EndPacket is iclass=1 & op2127=0x70 & op1620=0xe & op13=1 & op0507=0x2 & VdQF16_0004 & VuHF_0812 & $(END_PACKET) { + VdQF16_0004 = v_vneg_Vuhf(VuHF_0812); + build EndPacket; +} + +# (v73,1) V6_vneg_qf16_qf16 -- "Vd32.qf16 = vneg(Vu32.qf16)" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 1 1 1 0 0 0 0 0 1 1 1 0 P P 1 u u u u u 0 1 1 d d d d d +:vneg VdQF16_0004,VuQF16_0812 EndPacket is iclass=1 & op2127=0x70 & op1620=0xe & op13=1 & op0507=0x3 & VdQF16_0004 & VuQF16_0812 & $(END_PACKET) { + VdQF16_0004 = v_vneg_Vuqf16(VuQF16_0812); + build EndPacket; +} + +# (v73,1) V6_vneg_qf32_qf32 -- "Vd32.qf32 = vneg(Vu32.qf32)" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 1 1 1 0 0 0 0 0 1 1 1 0 P P 1 u u u u u 0 0 1 d d d d d +:vneg VdQF32_0004,VuQF32_0812 EndPacket is iclass=1 & op2127=0x70 & op1620=0xe & op13=1 & op0507=0x1 & VdQF32_0004 & VuQF32_0812 & $(END_PACKET) { + VdQF32_0004 = v_vneg_Vuqf32(VuQF32_0812); + build EndPacket; +} + +# (v73,1) V6_vneg_qf32_sf -- "Vd32.qf32 = vneg(Vu32.sf)" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 1 1 1 0 0 0 0 0 1 1 1 0 P P 1 u u u u u 0 0 0 d d d d d +:vneg VdQF32_0004,VuSF_0812 EndPacket is iclass=1 & op2127=0x70 & op1620=0xe & op13=1 & op0507=0x0 & VdQF32_0004 & VuSF_0812 & $(END_PACKET) { + VdQF32_0004 = v_vneg_Vusf(VuSF_0812); + build EndPacket; +} + +# (v73,1) V6_vrmpybub_rtt -- "Vdd32.w = vrmpy(Vu32.b,Rtt32.ub)" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 1 0 0 1 1 1 0 t t t t t P P 0 u u u u u 1 0 1 d d d d d +:vrmpy VddW_0004,VuB_0812,RttUB_1620 EndPacket is iclass=1 & op2127=0x4e & op13=0 & op0507=0x5 & VddW_0004 & VuB_0812 & RttUB_1620 & $(END_PACKET) { + VddW_0004 = v_vrmpy_Vub_Rttub(VuB_0812,RttUB_1620); + build EndPacket; +} + +# (v73,1) V6_vrmpybub_rtt_acc -- "Vxx32.w += vrmpy(Vu32.b,Rtt32.ub)" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 1 0 0 1 1 0 1 t t t t t P P 1 u u u u u 0 0 0 x x x x x +:vrmpy+= VddW_0004,VuB_0812,RttUB_1620 EndPacket is iclass=1 & op2127=0x4d & op13=1 & op0507=0x0 & Vss_0004 & VddW_0004 & VuB_0812 & RttUB_1620 & $(END_PACKET) { + VddW_0004 = v_vrmpy_Vub_Rttub_acc(Vss_0004,VuB_0812,RttUB_1620); + build EndPacket; +} + +# (v73,1) V6_vrmpyub_rtt -- "Vdd32.uw = vrmpy(Vu32.ub,Rtt32.ub)" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 1 0 0 1 1 1 0 t t t t t P P 0 u u u u u 1 0 0 d d d d d +:vrmpy VddUW_0004,VuUB_0812,RttUB_1620 EndPacket is iclass=1 & op2127=0x4e & op13=0 & op0507=0x4 & VddUW_0004 & VuUB_0812 & RttUB_1620 & $(END_PACKET) { + VddUW_0004 = v_vrmpy_Vuub_Rttub(VuUB_0812,RttUB_1620); + build EndPacket; +} + +# (v73,1) V6_vrmpyub_rtt_acc -- "Vxx32.uw += vrmpy(Vu32.ub,Rtt32.ub)" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 1 0 0 1 1 0 1 t t t t t P P 1 u u u u u 1 1 1 x x x x x +:vrmpy+= VddUW_0004,VuUB_0812,RttUB_1620 EndPacket is iclass=1 & op2127=0x4d & op13=1 & op0507=0x7 & Vss_0004 & VddUW_0004 & VuUB_0812 & RttUB_1620 & $(END_PACKET) { + VddUW_0004 = v_vrmpy_Vuub_Rttub_acc(Vss_0004,VuUB_0812,RttUB_1620); + build EndPacket; +} + +# (v73,1) V6_vsub_hf_f8 -- "Vdd32.hf = vsub(Vu32.f8,Vv32.f8)" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 1 1 1 1 1 0 0 v v v v v P P 0 u u u u u 1 0 1 d d d d d +:vsub VddHF_0004,VuF8_0812,VvF8_1620 EndPacket is iclass=1 & op2127=0x7c & op13=0 & op0507=0x5 & VddHF_0004 & VuF8_0812 & VvF8_1620 & $(END_PACKET) { + VddHF_0004 = v_vsub_Vuf8_Vvf8(VuF8_0812,VvF8_1620); + build EndPacket; +} + +# (v73,1) V6_vsub_hf_hf -- "Vd32.hf = vsub(Vu32.hf,Vv32.hf)" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 1 1 1 1 0 1 1 v v v v v P P 1 u u u u u 0 0 0 d d d d d +:vsub VdHF_0004,VuHF_0812,VvHF_1620 EndPacket is iclass=1 & op2127=0x7b & op13=1 & op0507=0x0 & VdHF_0004 & VuHF_0812 & VvHF_1620 & $(END_PACKET) { + VdHF_0004 = v_vsub_Vuhf_Vvhf(VuHF_0812,VvHF_1620); + build EndPacket; +} + +# (v73,1) V6_vsub_hf_mix -- "Vd32.qf16 = vsub(Vu32.hf,Vv32.qf16)" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 1 0 1 0 0 0 0 v v v v v P P 1 u u u u u 1 0 0 d d d d d +:vsub VdQF16_0004,VuHF_0812,VvQF16_1620 EndPacket is iclass=1 & op2127=0x50 & op13=1 & op0507=0x4 & VdQF16_0004 & VuHF_0812 & VvQF16_1620 & $(END_PACKET) { + VdQF16_0004 = v_vsub_Vuhf_Vvqf16(VuHF_0812,VvQF16_1620); + build EndPacket; +} + +# (v73,1) V6_vsub_sf_bf -- "Vdd32.sf = vsub(Vu32.bf,Vv32.bf)" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 1 1 0 1 0 1 0 v v v v v P P 1 u u u u u 1 0 1 d d d d d +:vsub VddSF_0004,VuBF_0812,VvBF_1620 EndPacket is iclass=1 & op2127=0x6a & op13=1 & op0507=0x5 & VddSF_0004 & VuBF_0812 & VvBF_1620 & $(END_PACKET) { + VddSF_0004 = v_vsub_Vubf_Vvbf(VuBF_0812,VvBF_1620); + build EndPacket; +} + +# (v73,1) V6_vsub_sf_hf -- "Vdd32.sf = vsub(Vu32.hf,Vv32.hf)" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 1 1 1 1 1 0 0 v v v v v P P 1 u u u u u 1 0 1 d d d d d +:vsub VddSF_0004,VuHF_0812,VvHF_1620 EndPacket is iclass=1 & op2127=0x7c & op13=1 & op0507=0x5 & VddSF_0004 & VuHF_0812 & VvHF_1620 & $(END_PACKET) { + VddSF_0004 = v_vsub_Vuhf_Vvhf(VuHF_0812,VvHF_1620); + build EndPacket; +} + +# (v73,1) V6_vsub_sf_mix -- "Vd32.qf32 = vsub(Vu32.sf,Vv32.qf32)" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 1 0 1 0 0 0 0 v v v v v P P 1 u u u u u 0 0 0 d d d d d +:vsub VdQF32_0004,VuSF_0812,VvQF32_1620 EndPacket is iclass=1 & op2127=0x50 & op13=1 & op0507=0x0 & VdQF32_0004 & VuSF_0812 & VvQF32_1620 & $(END_PACKET) { + VdQF32_0004 = v_vsub_Vusf_Vvqf32(VuSF_0812,VvQF32_1620); + build EndPacket; +} + +# (v73,1) V6_vsub_sf_sf -- "Vd32.sf = vsub(Vu32.sf,Vv32.sf)" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 1 1 1 1 1 0 0 v v v v v P P 1 u u u u u 1 1 1 d d d d d +:vsub VdSF_0004,VuSF_0812,VvSF_1620 EndPacket is iclass=1 & op2127=0x7c & op13=1 & op0507=0x7 & VdSF_0004 & VuSF_0812 & VvSF_1620 & $(END_PACKET) { + VdSF_0004 = v_vsub_Vusf_Vvsf(VuSF_0812,VvSF_1620); + build EndPacket; +} + +# (v73,1) V6_zextract -- "Vd32 = zextract(Rt32)" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 1 0 0 1 1 0 1 t t t t t P P 0 0 0 0 0 1 0 0 1 d d d d d +:zextract Vd5,rx5 EndPacket is iclass=1 & op2127=0x4d & op13=0 & op0812=0x1 & op0507=0x1 & Vd5 & rx5 & $(END_PACKET) { + Vd5 = v_zextract_Rt(rx5); + build EndPacket; +} + + +# --- HVX-v2 floating-point vector predicate compares (vcmp.eq/vcmp.gt) --- +define pcodeop vcmp_eq_QVhfVhf; +define pcodeop vcmp_eqand_QVhfVhf; +define pcodeop vcmp_eqor_QVhfVhf; +define pcodeop vcmp_eqxacc_QVhfVhf; +define pcodeop vcmp_eq_QVsfVsf; +define pcodeop vcmp_eqand_QVsfVsf; +define pcodeop vcmp_eqor_QVsfVsf; +define pcodeop vcmp_eqxacc_QVsfVsf; +define pcodeop vcmp_gt_QVbfVbf; +define pcodeop vcmp_gtand_QVbfVbf; +define pcodeop vcmp_gtor_QVbfVbf; +define pcodeop vcmp_gtxacc_QVbfVbf; + +# (v73,1) V6_veqhf -- "Qd4 = vcmp.eq(Vu32.hf,Vv32.hf)" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 1 1 1 1 1 0 0 v v v v v P P 0 u u u u u 0 0 0 1 1 1 d d +:vcmp.eq Qd2,VuHF_0812,VvHF_1620 EndPacket is iclass=0x1 & op2127=0x7c & op13=0x0 & op0207=0x7 & Qd2 & VuHF_0812 & VvHF_1620 & $(END_PACKET) { + Qd2 = vcmp_eq_QVhfVhf(VuHF_0812,VvHF_1620); + build EndPacket; +} + +# (v73,1) V6_veqhf_and -- "Qx4 &= vcmp.eq(Vu32.hf,Vv32.hf)" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 1 1 0 0 1 0 0 v v v v v P P 1 u u u u u 0 0 0 1 1 1 d d +:vcmp.eq&= Qd2,VuHF_0812,VvHF_1620 EndPacket is iclass=0x1 & op2127=0x64 & op13=0x1 & op0207=0x7 & Qd2 & VuHF_0812 & VvHF_1620 & $(END_PACKET) { + Qd2 = vcmp_eqand_QVhfVhf(Qd2,VuHF_0812,VvHF_1620); + build EndPacket; +} + +# (v73,1) V6_veqhf_or -- "Qx4 |= vcmp.eq(Vu32.hf,Vv32.hf)" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 1 1 0 0 1 0 0 v v v v v P P 1 u u u u u 0 1 0 1 1 1 d d +:vcmp.eq|= Qd2,VuHF_0812,VvHF_1620 EndPacket is iclass=0x1 & op2127=0x64 & op13=0x1 & op0207=0x17 & Qd2 & VuHF_0812 & VvHF_1620 & $(END_PACKET) { + Qd2 = vcmp_eqor_QVhfVhf(Qd2,VuHF_0812,VvHF_1620); + build EndPacket; +} + +# (v73,1) V6_veqhf_xor -- "Qx4 ^= vcmp.eq(Vu32.hf,Vv32.hf)" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 1 1 0 0 1 0 0 v v v v v P P 1 u u u u u 1 0 0 1 1 1 d d +:vcmp.eq^"^=" Qd2,VuHF_0812,VvHF_1620 EndPacket is iclass=0x1 & op2127=0x64 & op13=0x1 & op0207=0x27 & Qd2 & VuHF_0812 & VvHF_1620 & $(END_PACKET) { + Qd2 = vcmp_eqxacc_QVhfVhf(Qd2,VuHF_0812,VvHF_1620); + build EndPacket; +} + +# (v73,1) V6_veqsf -- "Qd4 = vcmp.eq(Vu32.sf,Vv32.sf)" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 1 1 1 1 1 0 0 v v v v v P P 0 u u u u u 0 0 0 0 1 1 d d +:vcmp.eq Qd2,VuSF_0812,VvSF_1620 EndPacket is iclass=0x1 & op2127=0x7c & op13=0x0 & op0207=0x3 & Qd2 & VuSF_0812 & VvSF_1620 & $(END_PACKET) { + Qd2 = vcmp_eq_QVsfVsf(VuSF_0812,VvSF_1620); + build EndPacket; +} + +# (v73,1) V6_veqsf_and -- "Qx4 &= vcmp.eq(Vu32.sf,Vv32.sf)" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 1 1 0 0 1 0 0 v v v v v P P 1 u u u u u 0 0 0 0 1 1 d d +:vcmp.eq&= Qd2,VuSF_0812,VvSF_1620 EndPacket is iclass=0x1 & op2127=0x64 & op13=0x1 & op0207=0x3 & Qd2 & VuSF_0812 & VvSF_1620 & $(END_PACKET) { + Qd2 = vcmp_eqand_QVsfVsf(Qd2,VuSF_0812,VvSF_1620); + build EndPacket; +} + +# (v73,1) V6_veqsf_or -- "Qx4 |= vcmp.eq(Vu32.sf,Vv32.sf)" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 1 1 0 0 1 0 0 v v v v v P P 1 u u u u u 0 1 0 0 1 1 d d +:vcmp.eq|= Qd2,VuSF_0812,VvSF_1620 EndPacket is iclass=0x1 & op2127=0x64 & op13=0x1 & op0207=0x13 & Qd2 & VuSF_0812 & VvSF_1620 & $(END_PACKET) { + Qd2 = vcmp_eqor_QVsfVsf(Qd2,VuSF_0812,VvSF_1620); + build EndPacket; +} + +# (v73,1) V6_veqsf_xor -- "Qx4 ^= vcmp.eq(Vu32.sf,Vv32.sf)" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 1 1 0 0 1 0 0 v v v v v P P 1 u u u u u 1 0 0 0 1 1 d d +:vcmp.eq^"^=" Qd2,VuSF_0812,VvSF_1620 EndPacket is iclass=0x1 & op2127=0x64 & op13=0x1 & op0207=0x23 & Qd2 & VuSF_0812 & VvSF_1620 & $(END_PACKET) { + Qd2 = vcmp_eqxacc_QVsfVsf(Qd2,VuSF_0812,VvSF_1620); + build EndPacket; +} + +# (v73,1) V6_vgtbf -- "Qd4 = vcmp.gt(Vu32.bf,Vv32.bf)" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 1 1 0 0 1 0 0 v v v v v P P 1 u u u u u 0 1 1 1 1 0 d d +:vcmp.gt Qd2,VuBF_0812,VvBF_1620 EndPacket is iclass=0x1 & op2127=0x64 & op13=0x1 & op0207=0x1e & Qd2 & VuBF_0812 & VvBF_1620 & $(END_PACKET) { + Qd2 = vcmp_gt_QVbfVbf(VuBF_0812,VvBF_1620); + build EndPacket; +} + +# (v73,1) V6_vgtbf_and -- "Qx4 &= vcmp.gt(Vu32.bf,Vv32.bf)" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 1 1 0 0 1 0 0 v v v v v P P 1 u u u u u 1 1 0 1 0 0 d d +:vcmp.gt&= Qd2,VuBF_0812,VvBF_1620 EndPacket is iclass=0x1 & op2127=0x64 & op13=0x1 & op0207=0x34 & Qd2 & VuBF_0812 & VvBF_1620 & $(END_PACKET) { + Qd2 = vcmp_gtand_QVbfVbf(Qd2,VuBF_0812,VvBF_1620); + build EndPacket; +} + +# (v73,1) V6_vgtbf_or -- "Qx4 |= vcmp.gt(Vu32.bf,Vv32.bf)" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 1 1 0 0 1 0 0 v v v v v P P 1 u u u u u 0 0 1 1 1 0 d d +:vcmp.gt|= Qd2,VuBF_0812,VvBF_1620 EndPacket is iclass=0x1 & op2127=0x64 & op13=0x1 & op0207=0xe & Qd2 & VuBF_0812 & VvBF_1620 & $(END_PACKET) { + Qd2 = vcmp_gtor_QVbfVbf(Qd2,VuBF_0812,VvBF_1620); + build EndPacket; +} + +# (v73,1) V6_vgtbf_xor -- "Qx4 ^= vcmp.gt(Vu32.bf,Vv32.bf)" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 1 1 0 0 1 0 0 v v v v v P P 1 u u u u u 1 1 1 1 0 0 d d +:vcmp.gt^"^=" Qd2,VuBF_0812,VvBF_1620 EndPacket is iclass=0x1 & op2127=0x64 & op13=0x1 & op0207=0x3c & Qd2 & VuBF_0812 & VvBF_1620 & $(END_PACKET) { + Qd2 = vcmp_gtxacc_QVbfVbf(Qd2,VuBF_0812,VvBF_1620); + build EndPacket; +} + diff --git a/pypcode/processors/Hexagon/data/languages/hexagon_left.sinc b/pypcode/processors/Hexagon/data/languages/hexagon_left.sinc index e7dcf8d..0bea5ec 100644 --- a/pypcode/processors/Hexagon/data/languages/hexagon_left.sinc +++ b/pypcode/processors/Hexagon/data/languages/hexagon_left.sinc @@ -103,6 +103,16 @@ build EndPackedLeft; } +# (v4,left,15) allocframe -- "allocframe ( #u5:3 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 1 1 1 1 0 i i i i i 0 0 0 0 - - 0 - - - - - - - - - - - - - + +:allocframe Uimm8_2024_shift3 EndPackedLeft is iclass=15 & op2527=6 & op1619=0 & op13=0 & Uimm8_2024_shift3 & AllocFrameSPU5x8Left & $(END_PACKED_LEFT) { + build AllocFrameSPU5x8Left; # allocframe(SP, Uimm8_2024_shift3); + build EndPackedLeft; +} + # (v4,left,5,7) and -- "Rd16 = and ( Rs16 , #1 )" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| @@ -146,7 +156,7 @@ # (v4,left,5,7) assign -- "Rd16 = #-1" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 0 1 - 1 1 0 1 + + 0 + + d d d d - - - - - - - - - - - - - - - - +# 0 1 - 1 1 0 1 0 0 0 0 0 d d d d - - - - - - - - - - - - - - - - :assign Rd4l,MinusOne EndPackedLeft is iclass3031=1 & iclass28=1 & op2127=0x50 & op20=0 & Rd4l & MinusOne & $(END_PACKED_LEFT) { Rd4l = -1; @@ -196,7 +206,7 @@ # (v4,left,3) assign -- "Re16 = #-1" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 0 0 1 1 1 0 1 + + 0 + + e e e e - - 1 - - - - - - - - - - - - - +# 0 0 1 1 1 0 1 0 0 0 0 0 e e e e - - 1 - - - - - - - - - - - - - :assign Rd4l,MinusOne EndPackedLeft is iclass=3 & op2127=0x50 & op20=0 & op13=1 & Rd4l & MinusOne & $(END_PACKED_LEFT) { Rd4l = -1; @@ -206,27 +216,28 @@ # (v4,left,5,7) assign -- "if ( ! p0 ) Rd16 = #0" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 0 1 - 1 1 0 1 + + 1 1 1 d d d d - - - - - - - - - - - - - - - - +# 0 1 - 1 1 0 1 0 0 1 1 1 d d d d - - - - - - - - - - - - - - - - # # (v4,left,5,7) assign -- "if ( ! p0 .new ) Rd16 = #0" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 0 1 - 1 1 0 1 + + 1 0 1 d d d d - - - - - - - - - - - - - - - - +# 0 1 - 1 1 0 1 0 0 1 0 1 d d d d - - - - - - - - - - - - - - - - # # (v4,left,5,7) assign -- "if ( p0 ) Rd16 = #0" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 0 1 - 1 1 0 1 + + 1 1 0 d d d d - - - - - - - - - - - - - - - - +# 0 1 - 1 1 0 1 0 0 1 1 0 d d d d - - - - - - - - - - - - - - - - # # (v4,left,5,7) assign -- "if ( p0 .new ) Rd16 = #0" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 0 1 - 1 1 0 1 + + 1 0 0 d d d d - - - - - - - - - - - - - - - - +# 0 1 - 1 1 0 1 0 0 1 0 0 d d d d - - - - - - - - - - - - - - - - :assign^P0Cond_N21_S20 rd4l,Zero EndPackedLeft is iclass3031=1 & iclass28=1 & op2227=0x29 & rd4l & P0Cond_N21_S20 & Zero & $(END_PACKED_LEFT) { build P0Cond_N21_S20; build EndPackedLeft; <> + build P0Cond_N21_S20; if (ConditionReg == 0) goto ; rd4l = 0; @@ -235,27 +246,28 @@ # (v4,left,3) assign -- "if ( ! p0 ) Re16 = #0" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 0 0 1 1 1 0 1 + + 1 1 1 e e e e - - 1 - - - - - - - - - - - - - +# 0 0 1 1 1 0 1 0 0 1 1 1 e e e e - - 1 - - - - - - - - - - - - - # # (v4,left,3) assign -- "if ( ! p0 .new ) Re16 = #0" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 0 0 1 1 1 0 1 + + 1 0 1 e e e e - - 1 - - - - - - - - - - - - - +# 0 0 1 1 1 0 1 0 0 1 0 1 e e e e - - 1 - - - - - - - - - - - - - # # (v4,left,3) assign -- "if ( p0 ) Re16 = #0" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 0 0 1 1 1 0 1 + + 1 1 0 e e e e - - 1 - - - - - - - - - - - - - +# 0 0 1 1 1 0 1 0 0 1 1 0 e e e e - - 1 - - - - - - - - - - - - - # # (v4,left,3) assign -- "if ( p0 .new ) Re16 = #0" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 0 0 1 1 1 0 1 + + 1 0 0 e e e e - - 1 - - - - - - - - - - - - - +# 0 0 1 1 1 0 1 0 0 1 0 0 e e e e - - 1 - - - - - - - - - - - - - :assign^P0Cond_N21_S20 rd4l,Zero EndPackedLeft is iclass=3 & op2227=0x29 & op13=1 & rd4l & P0Cond_N21_S20 & Zero & $(END_PACKED_LEFT) { build P0Cond_N21_S20; build EndPackedLeft; <> + build P0Cond_N21_S20; if (ConditionReg == 0) goto ; rd4l = 0; @@ -286,39 +298,27 @@ # (v4,left,5,7) combine -- "Rdd8 = combine ( #n2 , #u2 )" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 0 1 - 1 1 1 + 0 + i i n n d d d - - - - - - - - - - - - - - - - +# 0 1 - 1 1 1 0 0 0 i i n n d d d - - - - - - - - - - - - - - - - :combine Rdd3l,Uimm2_1920,Uimm2_2122 EndPackedLeft is iclass3031=1 & iclass28=1 & op2327=0x18 & Uimm2_1920 & Uimm2_2122 & Rdd3l & $(END_PACKED_LEFT) { Rdd3l = (zext(Uimm2_1920) << 32) + zext(Uimm2_2122); build EndPackedLeft; } -# Simplification: "Rdd8 = #u2" -:assign Rdd3l,Uimm2_2122 EndPackedLeft is iclass3031=1 & iclass28=1 & op2327=0x18 & op1920=0 & Uimm2_2122 & Rdd3l & $(END_PACKED_LEFT) { - Rdd3l = zext(Uimm2_2122); - build EndPackedLeft; -} - # (v4,left,3) combine -- "Rdd8 = combine ( #n2 , #u2 )" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 0 0 1 1 1 1 + 0 + i i n n d d d - - 1 - - - - - - - - - - - - - +# 0 0 1 1 1 1 0 0 0 i i n n d d d - - 1 - - - - - - - - - - - - - :combine Rdd3l,Uimm2_1920,Uimm2_2122 EndPackedLeft is iclass=3 & op2327=0x18 & op13=1 & Uimm2_1920 & Uimm2_2122 & Rdd3l & $(END_PACKED_LEFT) { Rdd3l = (zext(Uimm2_1920) << 32) + zext(Uimm2_2122); build EndPackedLeft; } -# Simplification: "Rdd8 = #u2" -:assign Rdd3l,Uimm2_2122 EndPackedLeft is iclass=3 & op2327=0x18 & op1920=0 & op13=1 & Uimm2_2122 & Rdd3l & $(END_PACKED_LEFT) { - Rdd3l = zext(Uimm2_2122); - build EndPackedLeft; -} - # (v4,left,5,7) combine -- "Rdd8 = combine ( #0 , Rs16 )" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 0 1 - 1 1 1 + 1 s s s s 0 d d d - - - - - - - - - - - - - - - - +# 0 1 - 1 1 1 0 1 s s s s 0 d d d - - - - - - - - - - - - - - - - :combine Rdd3l,Zero,rs4l EndPackedLeft is iclass3031=1 & iclass28=1 & op2427=13 & op19=0 & rs4l & Zero & Rdd3l & $(END_PACKED_LEFT) { Rdd3l = zext(rs4l); @@ -328,7 +328,7 @@ # (v4,left,3) combine -- "Ree8 = combine ( #0 , Ru16 )" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 0 0 1 1 1 1 + 1 u u u u 0 e e e - - 1 - - - - - - - - - - - - - +# 0 0 1 1 1 1 0 1 u u u u 0 e e e - - 1 - - - - - - - - - - - - - :combine Rdd3l,Zero,rs4l EndPackedLeft is iclass=3 & op2427=13 & op19=0 & op13=1 & rs4l & Zero & Rdd3l & $(END_PACKED_LEFT) { Rdd3l = zext(rs4l); @@ -338,7 +338,7 @@ # (v4,left,5,7) combine -- "Rdd8 = combine ( Rs16 , #0 )" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 0 1 - 1 1 1 + 1 s s s s 1 d d d - - - - - - - - - - - - - - - - +# 0 1 - 1 1 1 0 1 s s s s 1 d d d - - - - - - - - - - - - - - - - :combine Rdd3l,rs4l,Zero EndPackedLeft is iclass3031=1 & iclass28=1 & op2427=13 & op19=1 & rs4l & Zero & Rdd3l & $(END_PACKED_LEFT) { Rdd3l = zext(rs4l) << 32; @@ -348,33 +348,117 @@ # (v4,left,3) combine -- "Ree8 = combine ( Ru16 , #0 )" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 0 0 1 1 1 1 + 1 u u u u 1 e e e - - 1 - - - - - - - - - - - - - +# 0 0 1 1 1 1 0 1 u u u u 1 e e e - - 1 - - - - - - - - - - - - - :combine Rdd3l,rs4l,Zero EndPackedLeft is iclass=3 & op2427=13 & op19=1 & op13=1 & rs4l & Zero & Rdd3l & $(END_PACKED_LEFT) { Rdd3l = zext(rs4l) << 32; build EndPackedLeft; } +# (v4,left,3) dealloc_return -- "dealloc_return" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 1 1 1 1 1 1 0 1 0 0 0 0 0 0 - - 0 - - - - - - - - - - - - - + +:dealloc_return EndPackedLeft is iclass2931=1 & op1628=0x1F40 & op13=0 & DeallocFrameRaw & $(END_PACKED_LEFT) { + build DeallocFrameRaw; + build EndPackedLeft; + <> + return [LR]; +} + +# (v4,left,9,13) dealloc_return -- "dealloc_return" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 - 0 1 1 1 1 1 0 1 0 0 0 0 0 0 - - 1 - - - - - - - - - - - - - + +:dealloc_return EndPackedLeft is iclass31=1 & iclass29=0 & op1628=0x1F40 & op13=1 & DeallocFrameRaw & $(END_PACKED_LEFT) { + build DeallocFrameRaw; + build EndPackedLeft; + <> + return [LR]; +} + +# (v4,left,3) dealloc_return -- "if ( p0 ) dealloc_return" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 1 1 1 1 1 1 0 1 0 0 0 1 0 0 - - 0 - - - - - - - - - - - - - +# +# (v4,left,3) dealloc_return -- "if ( ! p0 ) dealloc_return" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 1 1 1 1 1 1 0 1 0 0 0 1 0 1 - - 0 - - - - - - - - - - - - - +# +# (v4,left,3) dealloc_return -- "if ( p0 .new ) dealloc_return:nt" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 1 1 1 1 1 1 0 1 0 0 0 1 1 0 - - 0 - - - - - - - - - - - - - +# +# (v4,left,3) dealloc_return -- "if ( ! p0 .new ) dealloc_return:nt" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 1 1 1 1 1 1 0 1 0 0 0 1 1 1 - - 0 - - - - - - - - - - - - - + +:dealloc_return^FlowP0Cond_N17_S16 EndPackedLeft is iclass=3 & op1827=0x3D1 & op13=0 & FlowP0Cond_N17_S16 & DeallocFrameRawCond & $(END_PACKED_LEFT) { + build FlowP0Cond_N17_S16; + build DeallocFrameRawCond; + build EndPackedLeft; + <> + build FlowP0Cond_N17_S16; + if (ConditionReg == 0) goto ; + return [LR]; + +} + +# (v4,left,9,13) dealloc_return -- "if ( p0 ) dealloc_return" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 - 0 1 1 1 1 1 0 1 0 0 0 1 0 0 - - 1 - - - - - - - - - - - - - +# +# (v4,left,9,13) dealloc_return -- "if ( ! p0 ) dealloc_return" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 - 0 1 1 1 1 1 0 1 0 0 0 1 0 1 - - 1 - - - - - - - - - - - - - +# +# (v4,left,9,13) dealloc_return -- "if ( p0 .new ) dealloc_return:nt" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 - 0 1 1 1 1 1 0 1 0 0 0 1 1 0 - - 1 - - - - - - - - - - - - - +# +# (v4,left,9,13) dealloc_return -- "if ( ! p0 .new ) dealloc_return:nt" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 - 0 1 1 1 1 1 0 1 0 0 0 1 1 1 - - 1 - - - - - - - - - - - - - + +:dealloc_return^FlowP0Cond_N17_S16 EndPackedLeft is iclass31=1 & iclass2829=1 & op1827=0x3D1 & op13=1 & FlowP0Cond_N17_S16 & DeallocFrameRawCond & $(END_PACKED_LEFT) { + build FlowP0Cond_N17_S16; + build DeallocFrameRawCond; + build EndPackedLeft; + <> + build FlowP0Cond_N17_S16; + if (ConditionReg == 0) goto ; + return [LR]; + +} + # (v4,left,3) deallocframe -- "deallocframe" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 0 0 1 1 1 1 1 1 0 0 - - - 0 - - - - 0 - - - - - - - - - - - - - +# 0 0 1 1 1 1 1 1 0 0 0 0 0 0 0 0 - - 0 - - - - - - - - - - - - - -:deallocframe EndPackedLeft is iclass=3 & op2227=0x3c & op18=0 & op13=0 & $(END_PACKED_LEFT) { +:deallocframe EndPackedLeft is iclass2931=1 & op1628=0x1F00 & op13=0 & DeallocFrameRaw & $(END_PACKED_LEFT) { + build DeallocFrameRaw; build EndPackedLeft; - <> - deallocframe(FP); } # (v4,left,9,13) deallocframe -- "deallocframe" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 1 - 0 1 1 1 1 1 0 0 - - - 0 - - - - 1 - - - - - - - - - - - - - +# 1 - 0 1 1 1 1 1 0 0 0 0 0 0 0 0 - - 1 - - - - - - - - - - - - - -:deallocframe EndPackedLeft is iclass31=1 & iclass2829=1 & op2227=0x3c & op18=0 & op13=1 & $(END_PACKED_LEFT) { +:deallocframe EndPackedLeft is iclass31=1 & iclass29=0 & op1628=0x1F00 & op13=1 & DeallocFrameRaw & $(END_PACKED_LEFT) { + build DeallocFrameRaw; build EndPackedLeft; - <> - deallocframe(FP); } # (v4,left,9,13) memb -- "Rd16 = memb ( Ru16 + #U3:0 )" diff --git a/pypcode/processors/Hexagon/data/languages/hexagon_right.sinc b/pypcode/processors/Hexagon/data/languages/hexagon_right.sinc index ed7f7c5..7acb794 100644 --- a/pypcode/processors/Hexagon/data/languages/hexagon_right.sinc +++ b/pypcode/processors/Hexagon/data/languages/hexagon_right.sinc @@ -23,12 +23,12 @@ build EndPackedRight; } -# (v4,right,2) add -- "Rd16 = add ( Sp , #u6:2 )" +# (v4,right,2,3) add -- "Rd16 = add ( Sp , #u6:2 )" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 0 0 1 0 - - - - - - - - - - - - - - 1 0 1 1 i i i i i i d d d d +# 0 0 1 - - - - - - - - - - - - - - - 1 0 1 1 i i i i i i d d d d -:add Rd4r,SP,Uimm8_0409_shift2 EndPackedRight is iclass=2 & op1013=11 & Rd4r & SP & Uimm8_0409_shift2 & $(END_PACKED_RIGHT) { +:add Rd4r,SP,Uimm8_0409_shift2 EndPackedRight is iclass2931=1 & op1013=11 & Rd4r & SP & Uimm8_0409_shift2 & $(END_PACKED_RIGHT) { Rd4r = SP + zext(Uimm8_0409_shift2); build EndPackedRight; } @@ -43,12 +43,12 @@ build EndPackedRight; } -# (v4,right,2) add -- "Rx16 = add ( Rx16 , #s7 )" +# (v4,right,2,3) add -- "Rx16 = add ( Rx16 , #s7 )" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 0 0 1 0 - - - - - - - - - - - - - - 1 0 0 i i i i i i i x x x x +# 0 0 1 - - - - - - - - - - - - - - - 1 0 0 i i i i i i i x x x x -:add Rd4r,rd4r,Simm8_0410 EndPackedRight is iclass=2 & op1113=4 & Rd4r & rd4r & Simm8_0410 & $(END_PACKED_RIGHT) { +:add Rd4r,rd4r,Simm8_0410 EndPackedRight is iclass2931=1 & op1113=4 & Rd4r & rd4r & Simm8_0410 & $(END_PACKED_RIGHT) { Rd4r = rd4r + sext(Simm8_0410); build EndPackedRight; } @@ -56,35 +56,35 @@ # (v4,right,6,7) allocframe -- "allocframe ( #u5:3 )" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 0 1 1 - - - - - - - - - - - - - - - 1 1 1 1 0 i i i i i - - - - +# 0 1 1 - - - - - - - - - - - - - - - 1 1 1 1 0 i i i i i 0 0 0 0 # # (v4,right,10,11) allocframe -- "allocframe ( #u5:3 )" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 1 0 1 - - - - - - - - - - - - - - - 1 1 1 1 0 i i i i i - - - - +# 1 0 1 - - - - - - - - - - - - - - - 1 1 1 1 0 i i i i i 0 0 0 0 -:allocframe Uimm8_0408_shift3 EndPackedRight is (iclass2931=3 | iclass2931=5) & op0913=0x1e & Uimm8_0408_shift3 & $(END_PACKED_RIGHT) { - allocframe(SP, Uimm8_0408_shift3); +:allocframe Uimm8_0408_shift3 EndPackedRight is op0913=0x1e & op3=0 & op0002=0 & (iclass2931=3 | iclass2931=5) & Uimm8_0408_shift3 & AllocFrameSPU5x8Right & $(END_PACKED_RIGHT) { + build AllocFrameSPU5x8Right; # allocframe(SP, Uimm8_0408_shift3) build EndPackedRight; } # (v4,right,12,13) allocframe -- "allocframe ( #u5:3 )" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 1 1 0 - - - - - - - - - - - - - - - - 1 1 1 0 i i i i i - - - - +# 1 1 0 - - - - - - - - - - - - - - - - 1 1 1 0 i i i i i 0 0 0 0 -:allocframe Uimm8_0408_shift3 EndPackedRight is iclass2931=6 & op0912=14 & Uimm8_0408_shift3 & $(END_PACKED_RIGHT) { - allocframe(SP, Uimm8_0408_shift3); +:allocframe Uimm8_0408_shift3 EndPackedRight is iclass2931=6 & op0912=14 & op3=0 & op0002=0 & Uimm8_0408_shift3 & AllocFrameSPU5x8Right & $(END_PACKED_RIGHT) { + build AllocFrameSPU5x8Right; # allocframe(SP, Uimm8_0408_shift3) build EndPackedRight; } # (v4,right,14,15) allocframe -- "allocframe ( #u5:3 )" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 1 1 1 - - - - - - - - - - - - - - - 0 1 1 1 0 i i i i i - - - - +# 1 1 1 - - - - - - - - - - - - - - - 0 1 1 1 0 i i i i i 0 0 0 0 -:allocframe Uimm8_0408_shift3 EndPackedRight is iclass2931=7 & op0913=0x0e & Uimm8_0408_shift3 & $(END_PACKED_RIGHT) { - allocframe(SP, Uimm8_0408_shift3); +:allocframe Uimm8_0408_shift3 EndPackedRight is iclass2931=7 & op0913=0x0e & op3=0 & op0002=0 & Uimm8_0408_shift3 & AllocFrameSPU5x8Right & $(END_PACKED_RIGHT) { + build AllocFrameSPU5x8Right; # allocframe(SP, Uimm8_0408_shift3); build EndPackedRight; } @@ -111,19 +111,19 @@ # (v4,right,2,3) assign -- "Rd16 = #-1" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 0 0 1 - - - - - - - - - - - - - - - 1 1 1 0 1 + + 0 + + d d d d +# 0 0 1 - - - - - - - - - - - - - - - 1 1 1 0 1 0 0 0 0 0 d d d d :assign Rd4r,MinusOne EndPackedRight is iclass2931=1 & op13=1 & op0412=0x1a0 & Rd4r & MinusOne & $(END_PACKED_RIGHT) { Rd4r = -1; build EndPackedRight; } -# (v4,right,2) assign -- "Rd16 = #u6" +# (v4,right,2,3) assign -- "Rd16 = #u6" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 0 0 1 0 - - - - - - - - - - - - - - 1 0 1 0 i i i i i i d d d d +# 0 0 1 - - - - - - - - - - - - - - - 1 0 1 0 i i i i i i d d d d -:assign Rd4r,Uimm8_0409 EndPackedRight is iclass=2 & op1013=10 & Rd4r & Uimm8_0409 & $(END_PACKED_RIGHT) { +:assign Rd4r,Uimm8_0409 EndPackedRight is iclass2931=1 & op1013=10 & Rd4r & Uimm8_0409 & $(END_PACKED_RIGHT) { Rd4r = zext(Uimm8_0409); build EndPackedRight; } @@ -141,27 +141,28 @@ # (v4,right,2,3) assign -- "if ( ! p0 ) Rd16 = #0" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 0 0 1 - - - - - - - - - - - - - - - 1 1 1 0 1 + + 1 1 1 d d d d +# 0 0 1 - - - - - - - - - - - - - - - 1 1 1 0 1 0 0 1 1 1 d d d d # # (v4,right,2,3) assign -- "if ( ! p0 .new ) Rd16 = #0" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 0 0 1 - - - - - - - - - - - - - - - 1 1 1 0 1 + + 1 0 1 d d d d +# 0 0 1 - - - - - - - - - - - - - - - 1 1 1 0 1 0 0 1 0 1 d d d d # # (v4,right,2,3) assign -- "if ( p0 ) Rd16 = #0" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 0 0 1 - - - - - - - - - - - - - - - 1 1 1 0 1 + + 1 1 0 d d d d +# 0 0 1 - - - - - - - - - - - - - - - 1 1 1 0 1 0 0 1 1 0 d d d d # # (v4,right,2,3) assign -- "if ( p0 .new ) Rd16 = #0" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 0 0 1 - - - - - - - - - - - - - - - 1 1 1 0 1 + + 1 0 0 d d d d +# 0 0 1 - - - - - - - - - - - - - - - 1 1 1 0 1 0 0 1 0 0 d d d d :assign^P0Cond_N05_S04 rd4r,Zero EndPackedRight is iclass2931=1 & op13=1 & op0612=0x69 & rd4r & Zero & P0Cond_N05_S04 & $(END_PACKED_RIGHT) { build P0Cond_N05_S04; build EndPackedRight; <> + build P0Cond_N05_S04; if (ConditionReg == 0) goto ; rd4r = 0; @@ -183,9 +184,9 @@ # (v4,right,2,3) combine -- "Rdd8 = combine ( #n2 , #u2 )" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 0 0 1 - - - - - - - - - - - - - - - 1 1 1 1 + 0 - i i n n d d d +# 0 0 1 - - - - - - - - - - - - - - - 1 1 1 1 0 0 - i i n n d d d -:combine Rdd3r,Uimm2_0304,Uimm2_0506 EndPackedRight is iclass2931=1 & op0813=0x3c & Uimm2_0304 & Uimm2_0506 & Rdd3r & Zero & $(END_PACKED_RIGHT) { +:combine Rdd3r,Uimm2_0304,Uimm2_0506 EndPackedRight is iclass2931=1 & op0813=0x3c & Uimm2_0304 & Uimm2_0506 & Rdd3r & $(END_PACKED_RIGHT) { Rdd3r = (zext(Uimm2_0304) << 32) + zext(Uimm2_0506); build EndPackedRight; } @@ -193,7 +194,7 @@ # (v4,right,2,3) combine -- "Rdd8 = combine ( #0 , Rs16 )" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 0 0 1 - - - - - - - - - - - - - - - 1 1 1 1 + 1 s s s s 0 d d d +# 0 0 1 - - - - - - - - - - - - - - - 1 1 1 1 0 1 s s s s 0 d d d :combine Rdd3r,Zero,rs4r EndPackedRight is iclass2931=1 & op0813=0x3d & op3=0 & rs4r & Rdd3r & Zero & $(END_PACKED_RIGHT) { Rdd3r = zext(rs4r); @@ -203,7 +204,7 @@ # (v4,right,2,3) combine -- "Rdd8 = combine ( Rs16 , #0 )" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 0 0 1 - - - - - - - - - - - - - - - 1 1 1 1 + 1 s s s s 1 d d d +# 0 0 1 - - - - - - - - - - - - - - - 1 1 1 1 0 1 s s s s 1 d d d :combine Rdd3r,rs4r,Zero EndPackedRight is iclass2931=1 & op0813=0x3d & op3=1 & rs4r & Rdd3r & Zero & $(END_PACKED_RIGHT) { Rdd3r = zext(rs4r) << 32; @@ -213,53 +214,54 @@ # (v4,right,0,1,4,5) dealloc_return -- "dealloc_return" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 0 - 0 - - - - - - - - - - - - - - - 1 1 1 1 1 1 0 1 - - - 0 - - +# 0 - 0 - - - - - - - - - - - - - - - 1 1 1 1 1 1 0 1 0 0 0 0 0 0 -:dealloc_return EndPackedRight is iclass31=0 & iclass29=0 & op13=1 & op0612=0x7d & op2=0 & $(END_PACKED_RIGHT) { +:dealloc_return EndPackedRight is iclass31=0 & iclass29=0 & op0013=0x3F40 & DeallocFrameRaw & $(END_PACKED_RIGHT) { + build DeallocFrameRaw; build EndPackedRight; <> - deallocframe(FP); return [LR]; } # (v4,right,2,3) dealloc_return -- "dealloc_return" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 0 0 1 - - - - - - - - - - - - - - - 0 1 1 1 1 1 0 1 - - - 0 - - +# 0 0 1 - - - - - - - - - - - - - - - 0 1 1 1 1 1 0 1 0 0 0 0 0 0 -:dealloc_return EndPackedRight is iclass2931=1 & op13=0 & op0612=0x7d & op2=0 & $(END_PACKED_RIGHT) { +:dealloc_return EndPackedRight is iclass2931=1 & op0013=0x1F40 & DeallocFrameRaw & $(END_PACKED_RIGHT) { + build DeallocFrameRaw; build EndPackedRight; <> - deallocframe(FP); return [LR]; } # (v4,right,0,1,4,5) dealloc_return -- "if ( ! p0 ) dealloc_return" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 0 - 0 - - - - - - - - - - - - - - - 1 1 1 1 1 1 0 1 - - - 1 0 1 +# 0 - 0 - - - - - - - - - - - - - - - 1 1 1 1 1 1 0 1 0 0 0 1 0 1 # # (v4,right,0,1,4,5) dealloc_return:nt -- "if ( ! p0 .new ) dealloc_return:nt" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 0 - 0 - - - - - - - - - - - - - - - 1 1 1 1 1 1 0 1 - - - 1 1 1 +# 0 - 0 - - - - - - - - - - - - - - - 1 1 1 1 1 1 0 1 0 0 0 1 1 1 # # (v4,right,0,1,4,5) dealloc_return -- "if ( p0 ) dealloc_return" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 0 - 0 - - - - - - - - - - - - - - - 1 1 1 1 1 1 0 1 - - - 1 0 0 +# 0 - 0 - - - - - - - - - - - - - - - 1 1 1 1 1 1 0 1 0 0 0 1 0 0 # # (v4,right,0,1,4,5) dealloc_return:nt -- "if ( p0 .new ) dealloc_return:nt" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 0 - 0 - - - - - - - - - - - - - - - 1 1 1 1 1 1 0 1 - - - 1 1 0 +# 0 - 0 - - - - - - - - - - - - - - - 1 1 1 1 1 1 0 1 0 0 0 1 1 0 -:dealloc_return^FlowP0Cond_N01_S00^NotTaken01 EndPackedRight is iclass31=0 & iclass29=0 & op13=1 & op0612=0x7d & op2=1 & FlowP0Cond_N01_S00 & NotTaken01 & $(END_PACKED_RIGHT) { +:dealloc_return^FlowP0Cond_N01_S00^NotTaken01 EndPackedRight is iclass31=0 & iclass29=0 & op0213=0xFD1 & FlowP0Cond_N01_S00 & NotTaken01 & DeallocFrameRawCond & $(END_PACKED_RIGHT) { build FlowP0Cond_N01_S00; + build DeallocFrameRawCond; build EndPackedRight; <> + build FlowP0Cond_N01_S00; if (ConditionReg == 0) goto ; - deallocframe(FP); return [LR]; } @@ -267,29 +269,30 @@ # (v4,right,2,3) dealloc_return -- "if ( ! p0 ) dealloc_return" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 0 0 1 - - - - - - - - - - - - - - - 0 1 1 1 1 1 0 1 - - - 1 0 1 +# 0 0 1 - - - - - - - - - - - - - - - 0 1 1 1 1 1 0 1 0 0 0 1 0 1 # # (v4,right,2,3) dealloc_return:nt -- "if ( ! p0 .new ) dealloc_return:nt" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 0 0 1 - - - - - - - - - - - - - - - 0 1 1 1 1 1 0 1 - - - 1 1 1 +# 0 0 1 - - - - - - - - - - - - - - - 0 1 1 1 1 1 0 1 0 0 0 1 1 1 # # (v4,right,2,3) dealloc_return -- "if ( p0 ) dealloc_return" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 0 0 1 - - - - - - - - - - - - - - - 0 1 1 1 1 1 0 1 - - - 1 0 0 +# 0 0 1 - - - - - - - - - - - - - - - 0 1 1 1 1 1 0 1 0 0 0 1 0 0 # # (v4,right,2,3) dealloc_return:nt -- "if ( p0 .new ) dealloc_return:nt" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 0 0 1 - - - - - - - - - - - - - - - 0 1 1 1 1 1 0 1 - - - 1 1 0 +# 0 0 1 - - - - - - - - - - - - - - - 0 1 1 1 1 1 0 1 0 0 0 1 1 0 -:dealloc_return^FlowP0Cond_N01_S00^NotTaken01 EndPackedRight is iclass2931=1 & op13=0 & op0612=0x7d & op2=1 & FlowP0Cond_N01_S00 & NotTaken01 & $(END_PACKED_RIGHT) { +:dealloc_return^FlowP0Cond_N01_S00^NotTaken01 EndPackedRight is iclass2931=1 & op0213=0x7D1 & FlowP0Cond_N01_S00 & NotTaken01 & DeallocFrameRawCond & $(END_PACKED_RIGHT) { build FlowP0Cond_N01_S00; + build DeallocFrameRawCond; build EndPackedRight; <> + build FlowP0Cond_N01_S00; if (ConditionReg == 0) goto ; - deallocframe(FP); return [LR]; } @@ -297,31 +300,29 @@ # (v4,right,0,1,4,5) deallocframe -- "deallocframe" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 0 - 0 - - - - - - - - - - - - - - - 1 1 1 1 1 1 0 0 - - - 0 - - +# 0 - 0 - - - - - - - - - - - - - - - 1 1 1 1 1 1 0 0 0 0 0 0 0 0 -:deallocframe EndPackedRight is iclass31=0 & iclass29=0 & op13=1 & op0612=0x7c & op2=0 & $(END_PACKED_RIGHT) { +:deallocframe EndPackedRight is iclass31=0 & iclass29=0 & op0013=0x3F00 & DeallocFrameRaw & $(END_PACKED_RIGHT) { + build DeallocFrameRaw; build EndPackedRight; - <> - deallocframe(FP); } # (v4,right,2,3) deallocframe -- "deallocframe" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 0 0 1 - - - - - - - - - - - - - - - 0 1 1 1 1 1 0 0 - - - 0 - - +# 0 0 1 - - - - - - - - - - - - - - - 0 1 1 1 1 1 0 0 0 0 0 0 0 0 -:deallocframe EndPackedRight is iclass2931=1 & op13=0 & op0612=0x7c & op2=0 & $(END_PACKED_RIGHT) { +:deallocframe EndPackedRight is iclass2931=1 & op0013=0x1F00 & DeallocFrameRaw & $(END_PACKED_RIGHT) { + build DeallocFrameRaw; build EndPackedRight; - <> - deallocframe(FP); } # (v4,right,0,1,4,5) jumpr -- "jumpr Lr" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 0 - 0 - - - - - - - - - - - - - - - 1 1 1 1 1 1 1 1 - - - 0 - - +# 0 - 0 - - - - - - - - - - - - - - - 1 1 1 1 1 1 1 1 0 0 0 0 0 0 -:jumpr LR EndPackedRight is iclass31=0 & iclass29=0 & op13=1 & op0612=0x7f & op2=0 & LR & $(END_PACKED_RIGHT) { +:jumpr LR EndPackedRight is iclass31=0 & iclass29=0 & op0013=0x3FC0 & LR & $(END_PACKED_RIGHT) { dest:4 = LR; build EndPackedRight; <> @@ -331,9 +332,9 @@ # (v4,right,2,3) jumpr -- "jumpr Lr" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 0 0 1 - - - - - - - - - - - - - - - 0 1 1 1 1 1 1 1 - - - 0 - - +# 0 0 1 - - - - - - - - - - - - - - - 0 1 1 1 1 1 1 1 0 0 0 0 0 0 -:jumpr LR EndPackedRight is iclass2931=1 & op13=0 & op0612=0x7f & op2=0 & LR & $(END_PACKED_RIGHT) { +:jumpr LR EndPackedRight is iclass2931=1 & op0013=0x1FC0 & LR & $(END_PACKED_RIGHT) { dest:4 = LR; build EndPackedRight; <> @@ -343,29 +344,30 @@ # (v4,right,0,1,4,5) jumpr -- "if ( ! p0 ) jumpr Lr" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 0 - 0 - - - - - - - - - - - - - - - 1 1 1 1 1 1 1 1 - - - 1 0 1 +# 0 - 0 - - - - - - - - - - - - - - - 1 1 1 1 1 1 1 1 0 0 0 1 0 1 # # (v4,right,0,1,4,5) jumpr:nt -- "if ( ! p0 .new ) jumpr:nt Lr" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 0 - 0 - - - - - - - - - - - - - - - 1 1 1 1 1 1 1 1 - - - 1 1 1 +# 0 - 0 - - - - - - - - - - - - - - - 1 1 1 1 1 1 1 1 0 0 0 1 1 1 # # (v4,right,0,1,4,5) jumpr -- "if ( p0 ) jumpr Lr" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 0 - 0 - - - - - - - - - - - - - - - 1 1 1 1 1 1 1 1 - - - 1 0 0 +# 0 - 0 - - - - - - - - - - - - - - - 1 1 1 1 1 1 1 1 0 0 0 1 0 0 # # (v4,right,0,1,4,5) jumpr:nt -- "if ( p0 .new ) jumpr:nt Lr" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 0 - 0 - - - - - - - - - - - - - - - 1 1 1 1 1 1 1 1 - - - 1 1 0 +# 0 - 0 - - - - - - - - - - - - - - - 1 1 1 1 1 1 1 1 0 0 0 1 1 0 # Conditional Return -:jumpr^FlowP0Cond_N01_S00^NotTaken01 LR EndPackedRight is iclass31=0 & iclass29=0 & op13=1 & op0612=0x7f & op2=1 & FlowP0Cond_N01_S00 & NotTaken01 & LR & $(END_PACKED_RIGHT) { +:jumpr^FlowP0Cond_N01_S00^NotTaken01 LR EndPackedRight is iclass31=0 & iclass29=0 & op0213=0xFF1 & FlowP0Cond_N01_S00 & NotTaken01 & LR & $(END_PACKED_RIGHT) { dest:4 = LR; build FlowP0Cond_N01_S00; build EndPackedRight; <> + build FlowP0Cond_N01_S00; if (ConditionReg == 0) goto ; return [dest]; @@ -374,28 +376,29 @@ # (v4,right,2,3) jumpr -- "if ( ! p0 ) jumpr Lr" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 0 0 1 - - - - - - - - - - - - - - - 0 1 1 1 1 1 1 1 - - - 1 0 1 +# 0 0 1 - - - - - - - - - - - - - - - 0 1 1 1 1 1 1 1 0 0 0 1 0 1 # # (v4,right,2,3) jumpr:nt -- "if ( ! p0 .new ) jumpr:nt Lr" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 0 0 1 - - - - - - - - - - - - - - - 0 1 1 1 1 1 1 1 - - - 1 1 1 +# 0 0 1 - - - - - - - - - - - - - - - 0 1 1 1 1 1 1 1 0 0 0 1 1 1 # # (v4,right,2,3) jumpr -- "if ( p0 ) jumpr Lr" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 0 0 1 - - - - - - - - - - - - - - - 0 1 1 1 1 1 1 1 - - - 1 0 0 +# 0 0 1 - - - - - - - - - - - - - - - 0 1 1 1 1 1 1 1 0 0 0 1 0 0 # # (v4,right,2,3) jumpr:nt -- "if ( p0 .new ) jumpr:nt Lr" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 0 0 1 - - - - - - - - - - - - - - - 0 1 1 1 1 1 1 1 - - - 1 1 0 +# 0 0 1 - - - - - - - - - - - - - - - 0 1 1 1 1 1 1 1 0 0 0 1 1 0 -:jumpr^FlowP0Cond_N01_S00^NotTaken01 LR EndPackedRight is iclass2931=1 & op13=0 & op0612=0x7f & op2=1 & FlowP0Cond_N01_S00 & NotTaken01 & LR & $(END_PACKED_RIGHT) { +:jumpr^FlowP0Cond_N01_S00^NotTaken01 LR EndPackedRight is iclass2931=1 & op0213=0x7F1 & FlowP0Cond_N01_S00 & NotTaken01 & LR & $(END_PACKED_RIGHT) { dest:4 = LR; build FlowP0Cond_N01_S00; build EndPackedRight; <> + build FlowP0Cond_N01_S00; if (ConditionReg == 0) goto ; return [dest]; @@ -431,7 +434,7 @@ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| # 1 0 1 - - - - - - - - - - - - - - - 1 1 0 0 1 n s s s s i i i i -:memb MemRsRelU4Rnb,Uimm1_08 EndPackedRight is (iclass2931=3 | iclass2931=5) & op0913=0x19 & MemRsRelU4Rnb & Uimm1_08 & $(END_PACKED_RIGHT) { +:memb MemRsRelU4Rnb,Uimm1_08 EndPackedRight is op0913=0x19 & (iclass2931=3 | iclass2931=5) & MemRsRelU4Rnb & Uimm1_08 & $(END_PACKED_RIGHT) { MemRsRelU4Rnb = Uimm1_08; build EndPackedRight; } @@ -466,7 +469,7 @@ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| # 1 0 1 - - - - - - - - - - - - - - - 0 1 i i i i s s s s t t t t -:memb MemRsRelU4Rb,rt4r EndPackedRight is (iclass2931=3 | iclass2931=5) & op1213=1 & MemRsRelU4Rb & rt4r & $(END_PACKED_RIGHT) { +:memb MemRsRelU4Rb,rt4r EndPackedRight is op1213=1 & (iclass2931=3 | iclass2931=5) & MemRsRelU4Rb & rt4r & $(END_PACKED_RIGHT) { MemRsRelU4Rb = rt4r:1; build EndPackedRight; } @@ -510,7 +513,7 @@ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| # 1 0 1 - - - - - - - - - - - - - - - 1 0 1 0 1 i i i i i i t t t -:memd MemSpRelS6Rd,rtt3r EndPackedRight is (iclass2931=3 | iclass2931=5) & op0913=0x15 & MemSpRelS6Rd & rtt3r & $(END_PACKED_RIGHT) { +:memd MemSpRelS6Rd,rtt3r EndPackedRight is op0913=0x15 & (iclass2931=3 | iclass2931=5) & MemSpRelS6Rd & rtt3r & $(END_PACKED_RIGHT) { MemSpRelS6Rd = rtt3r; build EndPackedRight; } @@ -545,12 +548,12 @@ build EndPackedRight; } -# (v4,right,2) memh -- "Rd16 = memh ( Rs16 + #u3:1 )" +# (v4,right,2,3) memh -- "Rd16 = memh ( Rs16 + #u3:1 )" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 0 0 1 0 - - - - - - - - - - - - - - 0 0 0 i i i s s s s d d d d +# 0 0 1 - - - - - - - - - - - - - - - 0 0 0 i i i s s s s d d d d -:memh Rd4r,MemRsRelU3Rh EndPackedRight is iclass=2 & op1113=0 & MemRsRelU3Rh & Rd4r & $(END_PACKED_RIGHT) { +:memh Rd4r,MemRsRelU3Rh EndPackedRight is iclass2931=1 & op1113=0 & MemRsRelU3Rh & Rd4r & $(END_PACKED_RIGHT) { Rd4r = sext(MemRsRelU3Rh); build EndPackedRight; } @@ -565,7 +568,7 @@ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| # 1 0 1 - - - - - - - - - - - - - - - 1 0 0 i i i s s s s t t t t -:memh MemRsRelU3Rh,rt4r EndPackedRight is (iclass2931=3 | iclass2931=5) & op1113=4 & MemRsRelU3Rh & rt4r & $(END_PACKED_RIGHT) { +:memh MemRsRelU3Rh,rt4r EndPackedRight is op1113=4 & (iclass2931=3 | iclass2931=5) & MemRsRelU3Rh & rt4r & $(END_PACKED_RIGHT) { MemRsRelU3Rh = rt4r:2; build EndPackedRight; } @@ -610,12 +613,12 @@ build EndPackedRight; } -# (v4,right,2) memuh -- "Rd16 = memuh ( Rs16 + #u3:1 )" +# (v4,right,2,3) memuh -- "Rd16 = memuh ( Rs16 + #u3:1 )" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -# 0 0 1 0 - - - - - - - - - - - - - - 0 0 1 i i i s s s s d d d d +# 0 0 1 - - - - - - - - - - - - - - - 0 0 1 i i i s s s s d d d d -:memuh Rd4r,MemRsRelU3Rh EndPackedRight is iclass=2 & op1113=1 & MemRsRelU3Rh & Rd4r & $(END_PACKED_RIGHT) { +:memuh Rd4r,MemRsRelU3Rh EndPackedRight is iclass2931=1 & op1113=1 & MemRsRelU3Rh & Rd4r & $(END_PACKED_RIGHT) { Rd4r = zext(MemRsRelU3Rh); build EndPackedRight; } @@ -640,7 +643,7 @@ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| # 1 0 1 - - - - - - - - - - - - - - - 1 1 0 0 0 n s s s s i i i i -:memw StMemRsRelC15Rw,Uimm1_08 EndPackedRight is (iclass2931=3 | iclass2931=5) & op13=1 & op0912=8 & StMemRsRelC15Rw & Uimm1_08 & $(END_PACKED_RIGHT) { +:memw StMemRsRelC15Rw,Uimm1_08 EndPackedRight is op13=1 & op0912=8 & (iclass2931=3 | iclass2931=5) & StMemRsRelC15Rw & Uimm1_08 & $(END_PACKED_RIGHT) { StMemRsRelC15Rw = zext(Uimm1_08); build EndPackedRight; } @@ -685,7 +688,7 @@ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| # 1 0 1 - - - - - - - - - - - - - - - 0 0 i i i i s s s s t t t t -:memw MemRsRelU4Rw,rt4r EndPackedRight is (iclass2931=5 | iclass2931=3) & op1213=0 & MemRsRelU4Rw & rt4r & $(END_PACKED_RIGHT) { +:memw MemRsRelU4Rw,rt4r EndPackedRight is op1213=0 & (iclass2931=5 | iclass2931=3) & MemRsRelU4Rw & rt4r & $(END_PACKED_RIGHT) { MemRsRelU4Rw = rt4r; build EndPackedRight; } @@ -720,7 +723,7 @@ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| # 1 0 1 - - - - - - - - - - - - - - - 1 0 1 0 0 i i i i i t t t t -:memw MemSpRelU5Rw,rt4r EndPackedRight is (iclass2931=3 | iclass2931=5) & op0913=0x14 & MemSpRelU5Rw & rt4r & $(END_PACKED_RIGHT) { +:memw MemSpRelU5Rw,rt4r EndPackedRight is op0913=0x14 & (iclass2931=3 | iclass2931=5) & MemSpRelU5Rw & rt4r & $(END_PACKED_RIGHT) { MemSpRelU5Rw = rt4r; build EndPackedRight; } @@ -773,4 +776,4 @@ :zxth Rd4r,rs4r EndPackedRight is iclass2931=1 & op0813=0x36 & rs4r & Rd4r & $(END_PACKED_RIGHT) { Rd4r = rs4r & 0xffff; build EndPackedRight; -} \ No newline at end of file +} diff --git a/pypcode/processors/MCS96/data/languages/MCS96.sinc b/pypcode/processors/MCS96/data/languages/MCS96.sinc index b75988f..2ac6ab0 100644 --- a/pypcode/processors/MCS96/data/languages/MCS96.sinc +++ b/pypcode/processors/MCS96/data/languages/MCS96.sinc @@ -617,11 +617,7 @@ macro setSignedShiftRightCarryFlag(shiftee,amount) { :CMPL dlreg, lreg is op8=0xc5; lreg; dlreg { op1:4 = lreg; tmp:4 = dlreg - op1; - $(N) = (tmp s< 0); - $(Z) = (tmp == 0); - $(C) = scarry(dlreg, op1); - $(V) = (((dlreg & ~op1 & ~tmp) | (~dlreg & op1 & tmp)) & 0x80000000 ) != 0; - $(VT) = $(VT) | $(V); + subtractFlags(dlreg, op1, tmp); } @endif diff --git a/pypcode/processors/MIPS/data/languages/mips.ldefs b/pypcode/processors/MIPS/data/languages/mips.ldefs index 6b19a2f..59dc5bb 100644 --- a/pypcode/processors/MIPS/data/languages/mips.ldefs +++ b/pypcode/processors/MIPS/data/languages/mips.ldefs @@ -20,6 +20,26 @@ + + MIPS32 32-bit addresses, big endian, in mips16e mode + + + + + + + + + + + + MIPS32 32-bit addresses, little endian, in mips16e mode + + + + + + + + + + + MIPS64 64-bit addresses, big endian, in mips16e mode + + + + + + + + - MIPS64 64-bit addreses, little endian, with mips16e + MIPS64 64-bit addresses, little endian, with mips16e + + + + + + + + + + + MIPS64 64-bit addresses, little endian, in mips16e mode diff --git a/pypcode/processors/MIPS/data/languages/mips.sinc b/pypcode/processors/MIPS/data/languages/mips.sinc index 18c8652..261a92b 100644 --- a/pypcode/processors/MIPS/data/languages/mips.sinc +++ b/pypcode/processors/MIPS/data/languages/mips.sinc @@ -539,8 +539,9 @@ define token instr(32) pcrel = (19,20) pcrel2 = (18,20) cc = (18,20) - immed1625 = (16,25) signed - immed1623 = (16,23) signed + immed1625 = (16,25) + simmed1625 = (16,25) signed + simmed1623 = (16,23) signed rt32 = (16,20) rt = (16,20) rtmtdsp = (16,20) @@ -617,7 +618,7 @@ define token instr(32) spec2 = (9,10) svrs_s1 = (10,10) spec3 = (8,10) - simmed9 = (7,15) + simmed9 = (7,15) signed zero2 = (7,10) code = (6,15) fdD = (6,10) @@ -650,7 +651,7 @@ define token instr(32) immed = (0,15) simmed = (0,15) signed simmseq = (6,15) signed - simmed11 = (0,10) + simmed11 = (0,10) signed ; attach variables [ rs rt rd base index baser6 ] [ diff --git a/pypcode/processors/MIPS/data/languages/mips32_16e.pspec b/pypcode/processors/MIPS/data/languages/mips32_16e.pspec new file mode 100644 index 0000000..836c4da --- /dev/null +++ b/pypcode/processors/MIPS/data/languages/mips32_16e.pspec @@ -0,0 +1,79 @@ + + + + + + + + + + + + + + + + + + + diff --git a/pypcode/processors/MIPS/data/languages/mips64_16e.pspec b/pypcode/processors/MIPS/data/languages/mips64_16e.pspec new file mode 100644 index 0000000..a24d9df --- /dev/null +++ b/pypcode/processors/MIPS/data/languages/mips64_16e.pspec @@ -0,0 +1,81 @@ + + + + + + + + + + + + + + + + + + + + + diff --git a/pypcode/processors/MIPS/data/languages/mips_dsp.sinc b/pypcode/processors/MIPS/data/languages/mips_dsp.sinc index e4c1835..86218e8 100644 --- a/pypcode/processors/MIPS/data/languages/mips_dsp.sinc +++ b/pypcode/processors/MIPS/data/languages/mips_dsp.sinc @@ -989,22 +989,22 @@ define pcodeop SUBUH.QB; RD = DSPControl & immed1625:$(REGSIZE); } -:rddsp RD is $(AMODE) & prime=0x1f & immed1625=0x1f & RD & fct2=0x12 & fct=0x38 { +:rddsp RD is $(AMODE) & prime=0x1f & simmed1625=0x1f & RD & fct2=0x12 & fct=0x38 { RD = DSPControl; } # REPL.PH Purpose: Replicate Immediate Integer into all Vector Element Positions -:repl.ph RD, immed1625 is $(AMODE) & prime=0x1f & immed1625 & RD & fct2=0xa & fct=0x12 { - val:2 = immed1625; +:repl.ph RD, simmed1625 is $(AMODE) & prime=0x1f & simmed1625 & RD & fct2=0xa & fct=0x12 { + val:2 = simmed1625; repl:$(REGSIZE) = sext(val) << 16 | zext(val); RD = repl; } # REPL.QB Purpose: Replicate Immediate Integer into all Vector Element Positions -:repl.qb RD, immed1623 is $(AMODE) & prime=0x1f & zero2425=0x0 & immed1623 & RD & fct2=0x2 & fct=0x12 { - byte:1 = immed1623; +:repl.qb RD, simmed1623 is $(AMODE) & prime=0x1f & zero2425=0x0 & simmed1623 & RD & fct2=0x2 & fct=0x12 { + byte:1 = simmed1623; RD = sext((byte << 24) | (byte << 16) | (byte << 8) | (byte)); } diff --git a/pypcode/processors/NDS32/data/languages/nds32.sinc b/pypcode/processors/NDS32/data/languages/nds32.sinc index 141183a..eb6f8c8 100644 --- a/pypcode/processors/NDS32/data/languages/nds32.sinc +++ b/pypcode/processors/NDS32/data/languages/nds32.sinc @@ -1317,12 +1317,12 @@ define pcodeop fnmsubs; } define pcodeop fmuls; -:fmuls Fst, Fsa, Fsb is $(I32) & $(COP) & fop4=0xa & Fst & Fsa & Fsb & cop4=0x0 { +:fmuls Fst, Fsa, Fsb is $(I32) & $(COP) & fop4=0xc & Fst & Fsa & Fsb & cop4=0x0 { Fst = fmuls(Fsa, Fsb); } define pcodeop fdivs; -:fdivs Fst, Fsa, Fsb is $(I32) & $(COP) & fop4=0xb & Fst & Fsa & Fsb & cop4=0x0 { +:fdivs Fst, Fsa, Fsb is $(I32) & $(COP) & fop4=0xd & Fst & Fsa & Fsb & cop4=0x0 { Fst = fdivs(Fsa, Fsb); } @@ -1439,12 +1439,12 @@ define pcodeop fnmsubd; } define pcodeop fmuld; -:fmuld Fdt, Fda, Fdb is $(I32) & $(COP) & fop4=0xa & Fdt & Fda & Fdb & cop4=0x8 { +:fmuld Fdt, Fda, Fdb is $(I32) & $(COP) & fop4=0xc & Fdt & Fda & Fdb & cop4=0x8 { Fdt = fmuld(Fda, Fdb); } define pcodeop fdivd; -:fdivd Fdt, Fda, Fdb is $(I32) & $(COP) & fop4=0xb & Fdt & Fda & Fdb & cop4=0x8 { +:fdivd Fdt, Fda, Fdb is $(I32) & $(COP) & fop4=0xd & Fdt & Fda & Fdb & cop4=0x8 { Fdt = fdivd(Fda, Fdb); } diff --git a/pypcode/processors/PowerPC/data/languages/altivec.sinc b/pypcode/processors/PowerPC/data/languages/altivec.sinc index 2acecf5..1e5a190 100644 --- a/pypcode/processors/PowerPC/data/languages/altivec.sinc +++ b/pypcode/processors/PowerPC/data/languages/altivec.sinc @@ -1850,3 +1850,12 @@ define pcodeop altv300_71; :vsrv vrD,vrA,vrB is OP=4 & vrD & vrA & vrB & XOP_0_10=1796 { vrD = altv300_71(vrA,vrB); } + +# vmsumudm 000100 ..... ..... ..... ..... 100011 +# Vector Multiply Sum Unsigned Doubleword Modulo +:vmsumudm vrD,vrA,vrB,vrC is OP=4 & vrD & vrA & vrB & vrC & XOP_0_5=35 { + local temp:16 = zext(vrC); + temp = temp + zext(vrA[ 0,32])*zext(vrB[ 0,32]); + temp = temp + zext(vrA[32,32])*zext(vrB[32,32]); + vrD = temp; +} diff --git a/pypcode/processors/PowerPC/data/languages/ppc_32_e500mc_be.cspec b/pypcode/processors/PowerPC/data/languages/ppc_32_e500mc_be.cspec index c5b9eef..4fc00a8 100644 --- a/pypcode/processors/PowerPC/data/languages/ppc_32_e500mc_be.cspec +++ b/pypcode/processors/PowerPC/data/languages/ppc_32_e500mc_be.cspec @@ -33,7 +33,7 @@ - + diff --git a/pypcode/processors/PowerPC/data/languages/ppc_32_e500mc_le.cspec b/pypcode/processors/PowerPC/data/languages/ppc_32_e500mc_le.cspec index f5fbbb7..7988e6b 100644 --- a/pypcode/processors/PowerPC/data/languages/ppc_32_e500mc_le.cspec +++ b/pypcode/processors/PowerPC/data/languages/ppc_32_e500mc_le.cspec @@ -33,7 +33,7 @@ - + diff --git a/pypcode/processors/PowerPC/data/languages/ppc_common.sinc b/pypcode/processors/PowerPC/data/languages/ppc_common.sinc index e7f9580..cbcfd2b 100644 --- a/pypcode/processors/PowerPC/data/languages/ppc_common.sinc +++ b/pypcode/processors/PowerPC/data/languages/ppc_common.sinc @@ -47,7 +47,7 @@ define register offset=0x500 size=1 [ fp_fx fp_fex fp_vx fp_ox fp_cc0 fp_cc1 fp_cc2 fp_cc3 fp_reserve1 fp_vxsoft fp_vxsqrt fp_vxcvi fp_ve fp_oe fp_ue fp_ze - fp_xe fp_ni fp_rn0 fp_rn1 ]; + fp_xe fp_ni fp_rn0 fp_rn1 fp_drn ]; define register offset = 0x700 size =$(REGISTER_SIZE) [MSR]; define register offset = 0x720 size=$(REGISTER_SIZE) [RESERVE_ADDRESS]; @@ -676,6 +676,7 @@ define token instr(32) CT=(21,25) CT2=(21,24) CX=(3,3) + CYex=(9,10) D0=(6,15) signed D1=(16,20) D2=(0,0) @@ -690,6 +691,7 @@ define token instr(32) DM2=(2,2) DQ=(4,15) DQs=(4,15) signed + DRM=(11,13) DS=(2,15) DSs=(2,15) signed DX=(16,20) @@ -713,6 +715,7 @@ define token instr(32) fS=(21,25) fT=(21,25) IMM=(11,15) + IMM4=(11,14) EVUIMM=(11,15) BU_UIMM=(16,20) @@ -724,6 +727,7 @@ define token instr(32) L= (21,22) L2=(21,21) L16=(16,17) + LBIT=(16,16) LEV=(5,11) LI=(2,25) signed LK=(0,0) @@ -743,6 +747,7 @@ define token instr(32) RA=(16,20) RB=(11,15) + RM=(11,12) RS=(21,25) RT=(21,25) R0=(0,0) @@ -1780,8 +1785,7 @@ macro storeRegisterPartial(reg, ea, sa) { ea = ea + 4; } - -macro packbits( D,a0,a1,a2,a3,a4,a5,a6,a7,a8,a9,a10,a11,a12,a13,a14,a15, + macro packbits( D,a0,a1,a2,a3,a4,a5,a6,a7,a8,a9,a10,a11,a12,a13,a14,a15, a16,a17,a18,a19,a20,a21,a22,a23,a24,a25,a26,a27,a28,a29,a30,a31) { D = zext(a31) & 1; D=D|(zext(a0)&1)<<31; D=D|(zext(a1)&1)<<30; D=D|(zext(a2)&1)<<29; D=D|(zext(a3)&1)<<28; @@ -1793,6 +1797,7 @@ macro packbits( D,a0,a1,a2,a3,a4,a5,a6,a7,a8,a9,a10,a11,a12,a13,a14,a15, D=D|(zext(a24)&1)<<7; D=D|(zext(a25)&1)<<6; D=D|(zext(a26)&1)<<5; D=D|(zext(a27)&1)<<4; D=D|(zext(a28)&1)<<3; D=D|(zext(a29)&1)<<2; D=D|(zext(a30)&1)<<1; } + macro unpackbits(D,a0,a1,a2,a3,a4,a5,a6,a7,a8,a9,a10,a11,a12,a13,a14,a15, a16,a17,a18,a19,a20,a21,a22,a23,a24,a25,a26,a27,a28,a29,a30,a31) { @@ -1803,13 +1808,15 @@ macro unpackbits(D,a0,a1,a2,a3,a4,a5,a6,a7,a8,a9,a10,a11,a12,a13,a14,a15, a16=(D&0x8000)!=0; a17=(D&0x4000)!=0; a18=(D&0x2000)!=0; a19=(D&0x1000)!=0; a20=(D&0x800)!=0; a21=(D&0x400)!=0; a22=(D&0x200)!=0; a23=(D&0x100)!=0; a24=(D&0x80)!=0; a25=(D&0x40)!=0; a26=(D&0x20)!=0; a27=(D&0x10)!=0; - a28=(D&0x8)!=0; a29=(D&0x4)!=0; a30=(D&0x2)!=0; a31=(D&0x1)!=0; } + a28=(D&0x8)!=0; a29=(D&0x4)!=0; a30=(D&0x2)!=0; a31=(D&0x1)!=0; + } macro packFPSCR(tmp) { packbits(tmp, fp_fx, fp_fex, fp_vx, fp_ox, fp_ux, fp_zx, fp_xx, fp_vxsnan, fp_vxisi, fp_vxidi, fp_vxzdz, fp_vximz, fp_vxvc, fp_fr, fp_fi, fp_c, fp_cc0, fp_cc1, fp_cc2, fp_cc3, fp_reserve1, fp_vxsoft, fp_vxsqrt, fp_vxcvi, fp_ve, fp_oe, fp_ue, fp_ze, fp_xe, fp_ni, fp_rn0, fp_rn1); + tmp[32,3] = fp_drn; } macro unpackFPSCR(tmp) { unpackbits(tmp, fp_fx, fp_fex, fp_vx, fp_ox, @@ -1819,7 +1826,8 @@ macro unpackFPSCR(tmp) { fp_cc0, fp_cc1, fp_cc2, fp_cc3, fp_reserve1, fp_vxsoft, fp_vxsqrt, fp_vxcvi, fp_ve, fp_oe, fp_ue, fp_ze, - fp_xe, fp_ni, fp_rn0, fp_rn1); + fp_xe, fp_ni, fp_rn0, fp_rn1); + fp_drn = tmp[32,3]; } diff --git a/pypcode/processors/PowerPC/data/languages/ppc_instructions.sinc b/pypcode/processors/PowerPC/data/languages/ppc_instructions.sinc index fd17f4f..736c7cc 100644 --- a/pypcode/processors/PowerPC/data/languages/ppc_instructions.sinc +++ b/pypcode/processors/PowerPC/data/languages/ppc_instructions.sinc @@ -2401,17 +2401,17 @@ define pcodeop lswxOp; #mffs fD 0xfc 00 04 8e :mffs fD is $(NOTVLE) & OP=63 & fD & BITS_11_20=0 & XOP_1_10=583 & Rc=0 { - tmp:4 = 0; + tmp:8 = 0; packFPSCR(tmp); - fD = zext(tmp); + fD = tmp; } #mffs. fD 0xfc 00 04 8f :mffs. fD is $(NOTVLE) & OP=63 & fD & BITS_11_20=0 & XOP_1_10=583 & Rc=1 { - tmp:4 = 0; + tmp:8 = 0; packFPSCR(tmp); - fD = zext(tmp); + fD = tmp; cr1flags(); } @@ -2489,69 +2489,113 @@ define pcodeop lswxOp; #mtfsf 10,fr0 0xfc 00 05 8e :mtfsf FM,fB is $(NOTVLE) & OP=63 & BIT_25=0 & FM & FM0 & FM1 & FM2 & FM3 & FM4 & FM5 & FM6 & FM7 & BIT_16=0 & fB & XOP_1_10=711 & Rc=0 { - tmp:4 = 0; + tmp:8 = 0; packFPSCR(tmp); - mask0:4 = zext((FM0:1 == 1)* 0xf) << 28; - mask1:4 = zext((FM1:1 == 1)* 0xf) << 24; - mask2:4 = zext((FM2:1 == 1)* 0xf) << 20; - mask3:4 = zext((FM3:1 == 1)* 0xf) << 16; - mask4:4 = zext((FM4:1 == 1)* 0xf) << 12; - mask5:4 = zext((FM5:1 == 1)* 0xf) << 8; - mask6:4 = zext((FM6:1 == 1)* 0xf) << 4; - mask7:4 = zext((FM7:1 == 1)* 0xf); + mask0:8 = zext((FM0:1 == 1)* 0xf) << 28; + mask1:8 = zext((FM1:1 == 1)* 0xf) << 24; + mask2:8 = zext((FM2:1 == 1)* 0xf) << 20; + mask3:8 = zext((FM3:1 == 1)* 0xf) << 16; + mask4:8 = zext((FM4:1 == 1)* 0xf) << 12; + mask5:8 = zext((FM5:1 == 1)* 0xf) << 8; + mask6:8 = zext((FM6:1 == 1)* 0xf) << 4; + mask7:8 = zext((FM7:1 == 1)* 0xf); - mask:4 = mask0 | mask1 | mask2 | mask3 | mask4 | mask5 | mask6 | mask7; + mask:8 = mask0 | mask1 | mask2 | mask3 | mask4 | mask5 | mask6 | mask7; - tmp1:4 = fB:4; - tmp2:4 = (tmp & ~mask) | (tmp1 & mask); + tmp1:8 = fB; + tmp2:8 = (tmp & ~mask) | (tmp1 & mask); + unpackFPSCR(tmp2); +} + +:mtfsf FM,fB,1 is $(NOTVLE) & OP=63 & BIT_25=0 & FM & FM0 & FM1 & FM2 & FM3 & FM4 & FM5 & FM6 & FM7 & BIT_16=1 & fB & XOP_1_10=711 & Rc=0 +{ + tmp:8 = 0; + packFPSCR(tmp); + + mask0:8 = zext((FM0:1 == 1)* 0xf) << 60; + mask1:8 = zext((FM1:1 == 1)* 0xf) << 56; + mask2:8 = zext((FM2:1 == 1)* 0xf) << 52; + mask3:8 = zext((FM3:1 == 1)* 0xf) << 48; + mask4:8 = zext((FM4:1 == 1)* 0xf) << 44; + mask5:8 = zext((FM5:1 == 1)* 0xf) << 40; + mask6:8 = zext((FM6:1 == 1)* 0xf) << 36; + mask7:8 = zext((FM7:1 == 1)* 0xf) << 32; + + mask:8 = mask0 | mask1 | mask2 | mask3 | mask4 | mask5 | mask6 | mask7; + + tmp1:8 = fB:8; + tmp2:8 = (tmp & ~mask) | (tmp1 & mask); unpackFPSCR(tmp2); } #mtfsf. 10,fr0 0xfc 00 05 8f :mtfsf. FM,fB is $(NOTVLE) & OP=63 & BIT_25=0 & FM & FM0 & FM1 & FM2 & FM3 & FM4 & FM5 & FM6 & FM7 & BIT_16=0 & fB & XOP_1_10=711 & Rc=1 { - tmp:4 = 0; + tmp:8 = 0; packFPSCR(tmp); - mask0:4 = zext((FM0:1 == 1)* 0xf) << 28; - mask1:4 = zext((FM1:1 == 1)* 0xf) << 24; - mask2:4 = zext((FM2:1 == 1)* 0xf) << 20; - mask3:4 = zext((FM3:1 == 1)* 0xf) << 16; - mask4:4 = zext((FM4:1 == 1)* 0xf) << 12; - mask5:4 = zext((FM5:1 == 1)* 0xf) << 8; - mask6:4 = zext((FM6:1 == 1)* 0xf) << 4; - mask7:4 = zext((FM7:1 == 1)* 0xf); + mask0:8 = zext((FM0:1 == 1)* 0xf) << 28; + mask1:8 = zext((FM1:1 == 1)* 0xf) << 24; + mask2:8 = zext((FM2:1 == 1)* 0xf) << 20; + mask3:8 = zext((FM3:1 == 1)* 0xf) << 16; + mask4:8 = zext((FM4:1 == 1)* 0xf) << 12; + mask5:8 = zext((FM5:1 == 1)* 0xf) << 8; + mask6:8 = zext((FM6:1 == 1)* 0xf) << 4; + mask7:8 = zext((FM7:1 == 1)* 0xf); - mask:4 = mask0 | mask1 | mask2 | mask3 | mask4 | mask5 | mask6 | mask7; + mask:8 = mask0 | mask1 | mask2 | mask3 | mask4 | mask5 | mask6 | mask7; - tmp1:4 = fB:4; - tmp2:4 = (tmp & ~mask) | (tmp1 & mask); + tmp1:8 = fB:8; + tmp2:8 = (tmp & ~mask) | (tmp1 & mask); unpackFPSCR(tmp2); cr1flags(); } #mtfsfi 10,3 0xfc 00 01 0c -:mtfsfi crfD,IMM is $(NOTVLE) & OP=63 & crfD & BITS_16_22=0 & IMM & BIT_11=0 & XOP_1_10=134 & Rc=0 +:mtfsfi crfD,IMM4 is $(NOTVLE) & OP=63 & crfD & BITS_16_22=0 & IMM4 & BIT_11=0 & XOP_1_10=134 & Rc=0 { - tmp:4 = 0; + tmp:8 = 0; packFPSCR(tmp); shift:1 = 28-(crfD*4); - mask:4 = 0xf << shift; - tmp1:4 = IMM << shift; - tmp2:4 = (tmp & ~mask) | tmp1; + mask:8 = 0xf << shift; + tmp1:8 = IMM4 << shift; + tmp2:8 = (tmp & ~mask) | tmp1; + unpackFPSCR(tmp2); +} + +:mtfsfi crfD,IMM4,1 is $(NOTVLE) & OP=63 & crfD & BITS_16_22=0 & IMM4 & BIT_11=1 & XOP_1_10=134 & Rc=0 +{ + tmp:8 = 0; + packFPSCR(tmp); + shift:1 = 60-(crfD*4); + mask:8 = 0xf << shift; + tmp1:8 = IMM4 << shift; + tmp2:8 = (tmp & ~mask) | tmp1; unpackFPSCR(tmp2); } #mtfsfi. 10,3 0xfc 00 01 0d -:mtfsfi. crfD,IMM is $(NOTVLE) & OP=63 & crfD & BITS_16_22=0 & IMM & BIT_11=0 & XOP_1_10=134 & Rc=1 +:mtfsfi. crfD,IMM4 is $(NOTVLE) & OP=63 & crfD & BITS_16_22=0 & IMM4 & BIT_11=0 & XOP_1_10=134 & Rc=1 { - tmp:4 = 0; + tmp:8 = 0; packFPSCR(tmp); shift:1 = 28-(crfD*4); - mask:4 = 0xf << shift; - tmp1:4 = IMM << shift; - tmp2:4 = (tmp & ~mask) | tmp1; + mask:8 = 0xf << shift; + tmp1:8 = IMM4 << shift; + tmp2:8 = (tmp & ~mask) | tmp1; + unpackFPSCR(tmp2); + cr1flags(); +} + +:mtfsfi. crfD,IMM4,1 is $(NOTVLE) & OP=63 & crfD & BITS_16_22=0 & IMM4 & BIT_11=1 & XOP_1_10=134 & Rc=1 +{ + tmp:8 = 0; + packFPSCR(tmp); + shift:1 = 60-(crfD*4); + mask:8 = 0xf << shift; + tmp1:8 = IMM4 << shift; + tmp2:8 = (tmp & ~mask) | tmp1; unpackFPSCR(tmp2); cr1flags(); } @@ -3116,7 +3160,10 @@ CRM_val: crmval is CRM [crmval = CRM+0;] {export *[const]:1 crmval;} #sc 0x44 00 00 02 :sc LEV is $(NOTVLE) & OP=17 & BITS_12_25=0 & LEV & BITS_2_4=0 & BIT_1=1 & BIT_0=0 { - syscall(); + local lev:1 = LEV; + SRR0 = inst_next; + SRR1 = MSR; + syscall(lev); } #slbia 0x7C 00 03 E4 diff --git a/pypcode/processors/PowerPC/data/languages/ppc_isa.sinc b/pypcode/processors/PowerPC/data/languages/ppc_isa.sinc index bfce773..3fb587c 100644 --- a/pypcode/processors/PowerPC/data/languages/ppc_isa.sinc +++ b/pypcode/processors/PowerPC/data/languages/ppc_isa.sinc @@ -1131,7 +1131,7 @@ define pcodeop MessageClear; # binutils: a2.d: 548: 7c 00 51 9c msgsnd r10 # binutils: e500mc.d: 18: 7c 00 71 9c msgsnd r14 define pcodeop MessageSend; -:msgsnd B is OP=31 & BITS_21_25=0 & BITS_16_20=0 & B & XOP_1_10=206 & BIT_0=0 { MessageSend(); } +:msgsnd B is OP=31 & BITS_21_25=0 & BITS_16_20=0 & B & XOP_1_10=206 & BIT_0=0 { MessageSend(B); } # ======================================================================= @@ -2441,21 +2441,21 @@ define pcodeop InstructionCacheBlockLockSetX; } :cnttzw A,S is OP=31 & S & A & BITS_11_15=0 & XOP_1_10=538 & Rc=0 { - A = countTrailingZeros(S); + A = countTrailingZeros(S); } :cnttzw. A,S is OP=31 & S & A & BITS_11_15=0 & XOP_1_10=538 & Rc=1 { - A = countTrailingZeros(S); - cr0flags(A); + A = countTrailingZeros(S); + cr0flags(A); } :cnttzd A,S is OP=31 & S & A & BITS_11_15=0 & XOP_1_10=570 & Rc=0 { - A = countTrailingZeros(S); + A = countTrailingZeros(S); } :cnttzd. A,S is OP=31 & S & A & BITS_11_15=0 & XOP_1_10=570 & Rc=1 { - A = countTrailingZeros(S); - cr0flags(A); + A = countTrailingZeros(S); + cr0flags(A); } :copy RA_OR_ZERO,B,L2 is $(NOTVLE) & OP=31 & BITS_22_25=0 & BIT_0=0 & XOP_1_10=774 & RA_OR_ZERO & B & L2 { @@ -2580,6 +2580,23 @@ define pcodeop InstructionCacheBlockLockSetX; setCrBit(cr0, 2, 1); } +define pcodeop returnFromSyscallVectored; +:rfscv is $(NOTVLE) & OP=19 & BITS_11_25=0 & XOP_1_10=82 & BIT_0=0 +{ + MSR = returnFromSyscallVectored(MSR, CTR); + local ra = LR; + return[ra]; +} + +define pcodeop syscallVectored; +:scv LEV is $(NOTVLE) & OP=17 & BITS_12_25=0 & LEV & BITS_2_4=0 & BIT_1=0 & BIT_0=1 +{ + local lev:1 = LEV; + LR = inst_next; + CTR = MSR; + syscallVectored(lev); +} + :setb D,BFA is $(NOTVLE) & OP=31 & BITS_11_17=0 & BIT_0=0 & XOP_1_10=128 & D & BFA { tmpcr:8 = 1 << (8 * BFA:1); tmpr0:1 = (BFA & 0x8) != 0; @@ -2614,3 +2631,104 @@ define pcodeop InstructionCacheBlockLockSetX; :wait WC is $(NOTVLE) & OP=31 & BITS_23_25=0 & BITS_11_20=0 & BIT_0=0 & XOP_1_10=30 & WC { waitT(WC:1); } + +##### +# v3.0B/C instructions added + +# note: CY=0 is the only one currently defined. 1-3 are reserved +# addex 011111 ..... ..... ..... ..101 01010/ +:addex D, A, B, CYex is $(NOTVLE) & OP=31 & D & A & B & CYex & BIT_9=0 & BIT_10=0 & XOP_1_8=170 & BIT_0=0 { + local sum:$(REGISTER_SIZE) = A + B; + local carryOut = carry(A,B) | carry(sum, zext(xer_ov)); + D = sum + zext(xer_ov); + xer_ov = carryOut; +} + +@ifdef BIT_64 +# mffscdrn 111111 ..... 10100 ..... 10010 00111/ +define pcodeop mffscdrn; +:mffscdrn fT, fB is $(NOTVLE) & OP=63 & fT & BITS_16_20=20 & fB & XOP_1_10=583 & BIT_0=0 { + local tmp:8 = 0; + local _tmpDRM:1 = fB[29,3]; + packFPSCR(tmp); + fT = tmp & 0x7000000ff; + fp_drn = _tmpDRM; +} + +# mffscdrni 111111 ..... 10101 //... 10010 00111/ +:mffscdrni fT, DRM is $(NOTVLE) & OP=63 & fT & BITS_16_20=20 & BITS_13_15=0 & DRM & XOP_1_10=583 & BIT_0=0 { + local tmp:8 = 0; + local _tmpDRM:1 = DRM; + packFPSCR(tmp); + fT = tmp & 0x7000000ff; + fp_drn = _tmpDRM; +} + +# mffsce 111111 ..... 00001 ///// 10010 00111/ +:mffsce fT is $(NOTVLE) & OP=63 & fT & BITS_16_20=1 & BITS_11_15=0 & XOP_1_10=583 & BIT_0=0 { + tmp:8 = 0; + packFPSCR(tmp); + fT = tmp; + fp_ve=0; + fp_oe=0; + fp_ue=0; + fp_ze=0; + fp_xe=0; +} + +# mffscrn 111111 ..... 10110 ..... 10010 00111/ +:mffscrn fT, fB is $(NOTVLE) & OP=63 & fT & BITS_16_20=22 & fB & XOP_1_10=583 & BIT_0=0 { + tmp:8 = 0; + packFPSCR(tmp); + fT = tmp & 0x7000000ff; + fp_rn0=fB[1,1]; + fp_rn1=fB[0,1]; +} + +# mffscrni 111111 ..... 10111 ///.. 10010 00111/ +:mffscrni fT, RM is $(NOTVLE) & OP=63 & fT & BITS_16_20=23 & BITS_13_15=0 & RM & XOP_1_10=583 & BIT_0=0 { + tmp:8 = 0; + _tmpRM:1 = RM; + packFPSCR(tmp); + fT = tmp & 0x7000000ff; + fp_rn0=_tmpRM[0,1]; + fp_rn1=_tmpRM[1,1]; +} + + +:mffsl fT is $(NOTVLE) & OP=63 & fT & BITS_11_20=24 & XOP_1_10=583 & BIT_0=0 { + tmp:8 = 0; + packFPSCR(tmp); + fT = tmp & 0x7000000ff; +} +@endif + +# msgclru 011111 ///// ///// ..... 00011 01110/ +# Message Clear Ultravisor +:msgclru B is $(NOTVLE) & OP=31 & BITS_21_25=0 & BITS_16_20=0 & B & XOP_1_10=10 & BIT_0=0 { + MessageClear(B); +} + +# msgsndu 011111 ///// ///// ..... 00010 01110/ +# Message Send Ultravisor +:msgsndu B is $(NOTVLE) & OP=31 & BITS_21_25=0 & BITS_16_20=0 & B & XOP_1_10=78 & BIT_0=0 { + MessageSend(B); +} + +# urfid 000100 ..... ..... ..... ..... 100011 +# Ultravisor Return from Interrupt Doubleword +:rfid is $(NOTVLE) & OP=19 & BITS_11_25=0 & XOP_1_10=306 & BIT_0=0 +{ + MSR = returnFromInterrupt(MSR, SRR1); + local ra = SRR0; + return[ra]; +} + +# slbiag 011111 ..... ///// ..... 11010 10010/ +# SLB Invalidate All Global +define pcodeop SLBInvalidateAllGlobal; +:slbiag S, LBIT is $(NOTVLE) & OP=31 & S & BITS_17_20=0 & LBIT & BITS_11_15=0 & XOP_1_10=850 & BIT_0=0 { + SLBInvalidateAllGlobal(S, LBIT:1); +} + + diff --git a/pypcode/processors/RISCV/data/languages/riscv.csr.sinc b/pypcode/processors/RISCV/data/languages/riscv.csr.sinc index a38313f..827eddb 100644 --- a/pypcode/processors/RISCV/data/languages/riscv.csr.sinc +++ b/pypcode/processors/RISCV/data/languages/riscv.csr.sinc @@ -11,13 +11,13 @@ } # csrrc d,E,s 00003073 0000707f SIMPLE (0, 0) -:csrrc rdDst,csr,rs1 is rs1 & csr & rdDst & op0001=0x3 & op0204=0x4 & op0506=0x3 & funct3=0x3 & op0711 +:csrrc rd,csr,rs1 is rs1 & csr & rd & op0001=0x3 & op0204=0x4 & op0506=0x3 & funct3=0x3 & op0711 { local tmprs1:$(XLEN) = rs1; local oldcsr:$(XLEN) = csr:$(XLEN); local newcsr:$(XLEN) = oldcsr & ~tmprs1; csr = newcsr; - rdDst = oldcsr; + rd = oldcsr; } # csrrci d,E,Z 00007073 0000707f SIMPLE (0, 0) @@ -30,19 +30,19 @@ # csrrci d,E,Z 00007073 0000707f SIMPLE (0, 0) -:csrrci rdDst,csr,op1519 is op1519 & csr & rdDst & op0001=0x3 & op0204=0x4 & op0506=0x3 & funct3=0x7 +:csrrci rd,csr,op1519 is op1519 & csr & rd & op0001=0x3 & op0204=0x4 & op0506=0x3 & funct3=0x7 { local oldcsr:$(XLEN) = csr:$(XLEN); local tmp:$(XLEN) = op1519; csr = oldcsr & ~tmp; - rdDst = oldcsr; + rd = oldcsr; } # csrrs d,E,s 00002073 0000707f SIMPLE (0, 0) -:csrr rdDst,csr is csr & rdDst & op0001=0x3 & op0204=0x4 & op0506=0x3 & funct3=0x2 & op1519=0 & op0711 +:csrr rd,csr is csr & rd & op0001=0x3 & op0204=0x4 & op0506=0x3 & funct3=0x2 & op1519=0 & op0711 { - rdDst = csr:$(XLEN); + rd = csr:$(XLEN); } # csrrs d,E,s 00002073 0000707f SIMPLE (0, 0) @@ -53,11 +53,11 @@ } # csrrs d,E,s 00002073 0000707f SIMPLE (0, 0) -:csrrs rdDst,csr,rs1 is rs1 & csr & rdDst & op0001=0x3 & op0204=0x4 & op0506=0x3 & funct3=0x2 & op1519 & op0711 +:csrrs rd,csr,rs1 is rs1 & csr & rd & op0001=0x3 & op0204=0x4 & op0506=0x3 & funct3=0x2 & op1519 & op0711 { local oldcsr:$(XLEN) = csr:$(XLEN); csr = oldcsr | rs1; - rdDst = oldcsr; + rd = oldcsr; } # csrrsi d,E,Z 00006073 0000707f SIMPLE (0, 0) @@ -69,12 +69,12 @@ } # csrrsi d,E,Z 00006073 0000707f SIMPLE (0, 0) -:csrrsi rdDst,csr,op1519 is op1519 & csr & rdDst & op0001=0x3 & op0204=0x4 & op0506=0x3 & funct3=0x6 & op0711 +:csrrsi rd,csr,op1519 is op1519 & csr & rd & op0001=0x3 & op0204=0x4 & op0506=0x3 & funct3=0x6 & op0711 { local oldcsr:$(XLEN) = csr:$(XLEN); local tmp:$(XLEN) = op1519; csr = oldcsr | tmp; - rdDst = oldcsr; + rd = oldcsr; } # csrw d,E,s 00001073 0000707f SIMPLE (0, 0) @@ -84,12 +84,12 @@ } # csrrw d,E,s 00001073 0000707f SIMPLE (0, 0) -:csrrw rdDst,csr,rs1 is rs1 & csr & rdDst & r0711 & op0001=0x3 & op0204=0x4 & op0506=0x3 & funct3=0x1 +:csrrw rd,csr,rs1 is rs1 & csr & rd & r0711 & op0001=0x3 & op0204=0x4 & op0506=0x3 & funct3=0x1 { local tmprs1:$(XLEN) = rs1; local oldcsr:$(XLEN) = csr:$(XLEN); csr = tmprs1; - rdDst = oldcsr; + rd = oldcsr; } # csrrwi d,E,Z 00005073 0000707f SIMPLE (0, 0) @@ -100,31 +100,31 @@ } # csrrwi d,E,Z 00005073 0000707f SIMPLE (0, 0) -:csrrwi rdDst,csr,op1519 is op1519 & csr & rdDst & op0001=0x3 & op0204=0x4 & op0506=0x3 & funct3=0x5 & r0711 +:csrrwi rd,csr,op1519 is op1519 & csr & rd & op0001=0x3 & op0204=0x4 & op0506=0x3 & funct3=0x5 & r0711 { local oldcsr:$(XLEN) = csr:$(XLEN); local val:$(XLEN) = op1519; csr = val; - rdDst = oldcsr; + rd = oldcsr; } # frcsr d 00302073 fffff07f SIMPLE (0, 0) -:frcsr rdDst is rdDst & op0001=0x3 & op0204=0x4 & op0506=0x3 & funct3=0x2 & op1531=0x60 +:frcsr rd is rd & op0001=0x3 & op0204=0x4 & op0506=0x3 & funct3=0x2 & op1531=0x60 { - rdDst = fcsr; + rd = fcsr; } # frflags d 00102073 fffff07f SIMPLE (0, 0) -:frflags rdDst is rdDst & op0001=0x3 & op0204=0x4 & op0506=0x3 & funct3=0x2 & op1531=0x20 +:frflags rd is rd & op0001=0x3 & op0204=0x4 & op0506=0x3 & funct3=0x2 & op1531=0x20 { - rdDst = zext(fflags[0,5]); + rd = zext(fflags[0,5]); } # frrm d 00202073 fffff07f SIMPLE (0, 0) -:frrm rdDst is rdDst & op0001=0x3 & op0204=0x4 & op0506=0x3 & funct3=0x2 & op1531=0x40 +:frrm rd is rd & op0001=0x3 & op0204=0x4 & op0506=0x3 & funct3=0x2 & op1531=0x40 { - rdDst = frm; + rd = frm; } # fscsr s 00301073 fff07fff SIMPLE (0, 0) @@ -135,9 +135,9 @@ } # fscsr d,s 00301073 fff0707f SIMPLE (0, 0) -:fscsr rdDst,rs1 is rs1 & rdDst & op0001=0x3 & op0204=0x4 & op0506=0x3 & funct3=0x1 & op2031=0x3 +:fscsr rd,rs1 is rs1 & rd & op0001=0x3 & op0204=0x4 & op0506=0x3 & funct3=0x1 & op2031=0x3 { - rdDst = fcsr; + rd = fcsr; fcsr = rs1; } @@ -150,16 +150,16 @@ } # fsflags d,s 00101073 fff0707f SIMPLE (0, 0) -:fsflags rdDst,rs1 is rs1 & rdDst & op0001=0x3 & op0204=0x4 & op0506=0x3 & funct3=0x1 & op2031=0x1 +:fsflags rd,rs1 is rs1 & rd & op0001=0x3 & op0204=0x4 & op0506=0x3 & funct3=0x1 & op2031=0x1 { - rdDst = zext(fflags[0,5]); + rd = zext(fflags[0,5]); fflags[0,5] = rs1[0,5]; } # fsflagsi d,Z 00105073 fff0707f SIMPLE (0, 0) -:fsflagsi rdDst,op1519 is op1519 & rdDst & op0001=0x3 & op0204=0x4 & op0506=0x3 & funct3=0x5 & op2031=0x1 +:fsflagsi rd,op1519 is op1519 & rd & op0001=0x3 & op0204=0x4 & op0506=0x3 & funct3=0x5 & op2031=0x1 { - rdDst = zext(fflags[0,5]); + rd = zext(fflags[0,5]); local tmp:1 = op1519:1; fflags[0,5] = tmp[0,5]; } @@ -180,16 +180,16 @@ } # fsrm d,s 00201073 fff0707f SIMPLE (0, 0) -:fsrm rdDst,rs1 is rs1 & rdDst & op0001=0x3 & op0204=0x4 & op0506=0x3 & funct3=0x1 & op2031=0x2 +:fsrm rd,rs1 is rs1 & rd & op0001=0x3 & op0204=0x4 & op0506=0x3 & funct3=0x1 & op2031=0x2 { - rdDst = zext(frm[0,3]); + rd = zext(frm[0,3]); frm[0,3] = rs1[0,3]; } # fsrmi d,Z 00205073 fff0707f SIMPLE (0, 0) -:fsrmi rdDst,op1519 is op1519 & rdDst & op0001=0x3 & op0204=0x4 & op0506=0x3 & funct3=0x5 & op2031=0x2 +:fsrmi rd,op1519 is op1519 & rd & op0001=0x3 & op0204=0x4 & op0506=0x3 & funct3=0x5 & op2031=0x2 { - rdDst = zext(frm[0,3]); + rd = zext(frm[0,3]); local tmp:1 = op1519:1; frm[0,3] = tmp[0,3]; } diff --git a/pypcode/processors/RISCV/data/languages/riscv.rv32a.sinc b/pypcode/processors/RISCV/data/languages/riscv.rv32a.sinc index 5196042..35194bb 100644 --- a/pypcode/processors/RISCV/data/languages/riscv.rv32a.sinc +++ b/pypcode/processors/RISCV/data/languages/riscv.rv32a.sinc @@ -1,10 +1,10 @@ # RV32A Standard Extension # amoadd.w d,t,0(s) 0000202f fe00707f DWORD|DREF (0, 4) -:amoadd.w^aqrl rd,rs2W,(rs1) is rs1 & rs2W & rd & op0001=0x3 & op0204=0x3 & op0506=0x1 & funct3=0x2 & op2731=0 & aqrl +:amoadd.w^aqrl rd,rs2,(rs1) is rs1 & rs2 & rd & op0001=0x3 & op0204=0x3 & op0506=0x1 & funct3=0x2 & op2731=0 & aqrl { local tmprs1 = rs1; - local tmprs2 = rs2W; + local tmprs2:$(WXLEN) = rs2:$(WXLEN); local tmp:4 = *[ram]:4 tmprs1; assignW(rd, tmp); tmp = tmp + tmprs2; @@ -13,10 +13,10 @@ # amoand.w d,t,0(s) 6000202f fe00707f DWORD|DREF (0, 4) -:amoand.w^aqrl rd,rs2W,(rs1) is rs1 & rs2W & rd & op0001=0x3 & op0204=0x3 & op0506=0x1 & funct3=0x2 & op2731=0xc & aqrl +:amoand.w^aqrl rd,rs2,(rs1) is rs1 & rs2 & rd & op0001=0x3 & op0204=0x3 & op0506=0x1 & funct3=0x2 & op2731=0xc & aqrl { local tmprs1 = rs1; - local tmprs2 = rs2W; + local tmprs2:$(WXLEN) = rs2:$(WXLEN); local tmp:4 = *[ram]:4 tmprs1; assignW(rd, tmp); tmp = tmp & tmprs2; @@ -25,10 +25,10 @@ # amomax.w d,t,0(s) a000202f fe00707f DWORD|DREF (0, 4) -:amomax.w^aqrl rd,rs2W,(rs1) is rs1 & rs2W & rd & op0001=0x3 & op0204=0x3 & op0506=0x1 & funct3=0x2 & op2731=0x14 & aqrl +:amomax.w^aqrl rd,rs2,(rs1) is rs1 & rs2 & rd & op0001=0x3 & op0204=0x3 & op0506=0x1 & funct3=0x2 & op2731=0x14 & aqrl { local tmprs1 = rs1; - local tmprs2 = rs2W; + local tmprs2:$(WXLEN) = rs2:$(WXLEN); local tmp:4 = *[ram]:4 tmprs1; assignW(rd, tmp); if (tmprs2 s<= tmp) goto inst_next; @@ -37,10 +37,10 @@ # amomaxu.w d,t,0(s) e000202f fe00707f DWORD|DREF (0, 4) -:amomaxu.w^aqrl rd,rs2W,(rs1) is rs1 & rs2W & rd & op0001=0x3 & op0204=0x3 & op0506=0x1 & funct3=0x2 & op2731=0x1c & aqrl +:amomaxu.w^aqrl rd,rs2,(rs1) is rs1 & rs2 & rd & op0001=0x3 & op0204=0x3 & op0506=0x1 & funct3=0x2 & op2731=0x1c & aqrl { local tmprs1 = rs1; - local tmprs2 = rs2W; + local tmprs2:$(WXLEN) = rs2:$(WXLEN); local tmp:4 = *[ram]:4 tmprs1; assignW(rd, tmp); if (tmprs2 <= tmp) goto inst_next; @@ -49,10 +49,10 @@ # amomin.w d,t,0(s) 8000202f fe00707f DWORD|DREF (0, 4) -:amomin.w^aqrl rd,rs2W,(rs1) is rs1 & rs2W & rd & op0001=0x3 & op0204=0x3 & op0506=0x1 & funct3=0x2 & op2731=0x10 & aqrl +:amomin.w^aqrl rd,rs2,(rs1) is rs1 & rs2 & rd & op0001=0x3 & op0204=0x3 & op0506=0x1 & funct3=0x2 & op2731=0x10 & aqrl { local tmprs1 = rs1; - local tmprs2 = rs2W; + local tmprs2:$(WXLEN) = rs2:$(WXLEN); local tmp:4 = *[ram]:4 tmprs1; assignW(rd, tmp); if (tmprs2 s>= tmp) goto inst_next; @@ -61,10 +61,10 @@ # amominu.w d,t,0(s) c000202f fe00707f DWORD|DREF (0, 4) -:amominu.w^aqrl rd,rs2W,(rs1) is rs1 & rs2W & rd & op0001=0x3 & op0204=0x3 & op0506=0x1 & funct3=0x2 & op2731=0x18 & aqrl +:amominu.w^aqrl rd,rs2,(rs1) is rs1 & rs2 & rd & op0001=0x3 & op0204=0x3 & op0506=0x1 & funct3=0x2 & op2731=0x18 & aqrl { local tmprs1 = rs1; - local tmprs2 = rs2W; + local tmprs2:$(WXLEN) = rs2:$(WXLEN); local tmp:4 = *[ram]:4 tmprs1; assignW(rd, tmp); if (tmprs2 >= tmp) goto inst_next; @@ -73,10 +73,10 @@ # amoor.w d,t,0(s) 4000202f fe00707f DWORD|DREF (0, 4) -:amoor.w^aqrl rd,rs2W,(rs1) is rs1 & rs2W & rd & op0001=0x3 & op0204=0x3 & op0506=0x1 & funct3=0x2 & op2731=0x8 & aqrl +:amoor.w^aqrl rd,rs2,(rs1) is rs1 & rs2 & rd & op0001=0x3 & op0204=0x3 & op0506=0x1 & funct3=0x2 & op2731=0x8 & aqrl { local tmprs1 = rs1; - local tmprs2 = rs2W; + local tmprs2:$(WXLEN) = rs2:$(WXLEN); local tmp:4 = *[ram]:4 tmprs1; assignW(rd, tmp); tmp = tmp | tmprs2; @@ -85,10 +85,10 @@ # amoswap.w d,t,0(s) 0800202f fe00707f DWORD|DREF (0, 4) -:amoswap.w^aqrl rd,rs2W,(rs1) is rs1 & rs2W & rd & op0001=0x3 & op0204=0x3 & op0506=0x1 & funct3=0x2 & op2731=0x1 & aqrl +:amoswap.w^aqrl rd,rs2,(rs1) is rs1 & rs2 & rd & op0001=0x3 & op0204=0x3 & op0506=0x1 & funct3=0x2 & op2731=0x1 & aqrl { local tmprs1 = rs1; - local tmprs2 = rs2W; + local tmprs2:$(WXLEN) = rs2:$(WXLEN); local tmp:4 = *[ram]:4 tmprs1; assignW(rd, tmp); *[ram]:4 tmprs1 = tmprs2; @@ -96,10 +96,10 @@ # amoxor.w d,t,0(s) 2000202f fe00707f DWORD|DREF (0, 4) -:amoxor.w^aqrl rd,rs2W,(rs1) is rs1 & rs2W & rd & op0001=0x3 & op0204=0x3 & op0506=0x1 & funct3=0x2 & op2731=0x4 & aqrl +:amoxor.w^aqrl rd,rs2,(rs1) is rs1 & rs2 & rd & op0001=0x3 & op0204=0x3 & op0506=0x1 & funct3=0x2 & op2731=0x4 & aqrl { local tmprs1 = rs1; - local tmprs2 = rs2W; + local tmprs2:$(WXLEN) = rs2:$(WXLEN); local tmp:4 = *[ram]:4 tmprs1; assignW(rd, tmp); tmp = tmp ^ tmprs2; @@ -118,9 +118,9 @@ # sc.w d,t,0(s) 1800202f fe00707f DWORD|DREF (0, 4) -:sc.w^aqrl rd,rs2W,(rs1) is rs1 & rs2W & rd & op0001=0x3 & op0204=0x3 & op0506=0x1 & funct3=0x2 & op2731=0x3 & aqrl +:sc.w^aqrl rd,rs2,(rs1) is rs1 & rs2 & rd & op0001=0x3 & op0204=0x3 & op0506=0x1 & funct3=0x2 & op2731=0x3 & aqrl { - local tmprs2 = rs2W; + local tmprs2:$(WXLEN) = rs2:$(WXLEN); local tmprs1 = rs1; rd = 1; if ((RESERVE == 0)||(RESERVE_ADDRESS != tmprs1)||(RESERVE_LENGTH != 4)) goto inst_next; diff --git a/pypcode/processors/RISCV/data/languages/riscv.rv32d.sinc b/pypcode/processors/RISCV/data/languages/riscv.rv32d.sinc index e8d298b..aa2e72e 100644 --- a/pypcode/processors/RISCV/data/languages/riscv.rv32d.sinc +++ b/pypcode/processors/RISCV/data/languages/riscv.rv32d.sinc @@ -35,18 +35,18 @@ # fcvt.d.w D,s d2000053 fff0707f SIMPLE (0, 0) -:fcvt.d.w frd,rs1W is frd & rs1W & op0001=0x3 & op0204=0x4 & op0506=0x2 & funct3=0x0 & funct7=0x69 & op2024=0x0 +:fcvt.d.w frd,rs1 is frd & rs1 & op0001=0x3 & op0204=0x4 & op0506=0x2 & funct3=0x0 & funct7=0x69 & op2024=0x0 { - local tmp:8 = int2float(rs1W); + local tmp:8 = int2float(rs1:$(WXLEN)); frd = tmp; } # fcvt.d.wu D,s d2100053 fff0707f SIMPLE (0, 0) -:fcvt.d.wu frd,rs1W is frd & rs1W & op0001=0x3 & op0204=0x4 & op0506=0x2 & funct3=0x0 & funct7=0x69 & op2024=0x1 +:fcvt.d.wu frd,rs1 is frd & rs1 & op0001=0x3 & op0204=0x4 & op0506=0x2 & funct3=0x0 & funct7=0x69 & op2024=0x1 { #ATTN unsigned can be an issue here - local u32:$(XLEN2) = zext(rs1W); + local u32:8 = zext(rs1:$(WXLEN)); local tmp:8 = int2float(u32); frd = tmp; } @@ -61,17 +61,19 @@ # fcvt.w.d d,S,m c2000053 fff0007f SIMPLE (0, 0) -:fcvt.w.d rdW,frs1D,FRM is frs1D & FRM & rdW & op0001=0x3 & op0204=0x4 & op0506=0x2 & funct7=0x61 & op2024=0x0 +:fcvt.w.d rd,frs1D,FRM is frs1D & FRM & rd & op0001=0x3 & op0204=0x4 & op0506=0x2 & funct7=0x61 & op2024=0x0 { - rdW = trunc(frs1D); + local tmp:4 = trunc(frs1D); + rd = sext(tmp); } # fcvt.wu.d d,S,m c2100053 fff0007f SIMPLE (0, 0) -:fcvt.wu.d rdW,frs1D,FRM is frs1D & FRM & rdW & op0001=0x3 & op0204=0x4 & op0506=0x2 & funct7=0x61 & op2024=0x1 +:fcvt.wu.d rd,frs1D,FRM is frs1D & FRM & rd & op0001=0x3 & op0204=0x4 & op0506=0x2 & funct7=0x61 & op2024=0x1 { - #TODO unsigned - rdW = trunc(frs1D); + local cond = (frs1D s<0); + local tmp:4 = (zext(cond) * 0) + (zext(!cond) * trunc(frs1D)); + rd = sext(tmp); # x[rd] = sext(f32->u32(f[rs1])) } diff --git a/pypcode/processors/RISCV/data/languages/riscv.rv32f.sinc b/pypcode/processors/RISCV/data/languages/riscv.rv32f.sinc index e830008..8061d87 100644 --- a/pypcode/processors/RISCV/data/languages/riscv.rv32f.sinc +++ b/pypcode/processors/RISCV/data/languages/riscv.rv32f.sinc @@ -27,35 +27,37 @@ # fcvt.s.w D,s,m d0000053 fff0007f SIMPLE (0, 0) -:fcvt.s.w frd,rs1W,FRM is frd & FRM & rs1W & op0001=0x3 & op0204=0x4 & op0506=0x2 & funct7=0x68 & op2024=0x0 +:fcvt.s.w frd,rs1,FRM is frd & FRM & rs1 & op0001=0x3 & op0204=0x4 & op0506=0x2 & funct7=0x68 & op2024=0x0 { - local tmp:4 = int2float(rs1W); + local tmp:4 = int2float(rs1:$(WXLEN)); fassignS(frd, tmp); } # fcvt.s.wu D,s,m d0100053 fff0007f SIMPLE (0, 0) -:fcvt.s.wu frd,rs1W,FRM is frd & FRM & rs1W & op0001=0x3 & op0204=0x4 & op0506=0x2 & funct7=0x68 & op2024=0x1 +:fcvt.s.wu frd,rs1,FRM is frd & FRM & rs1 & op0001=0x3 & op0204=0x4 & op0506=0x2 & funct7=0x68 & op2024=0x1 { #ATTN unsigned can be an issue here - local u32:$(XLEN2) = zext(rs1W); + local u32:8 = zext(rs1:$(WXLEN)); local tmp:4 = int2float(u32); fassignS(frd, tmp); } # fcvt.w.s d,S,m c0000053 fff0007f SIMPLE (0, 0) -:fcvt.w.s rdW,frs1S,FRM is frs1S & FRM & rdW & op0001=0x3 & op0204=0x4 & op0506=0x2 & funct7=0x60 & op2024=0x0 +:fcvt.w.s rd,frs1S,FRM is frs1S & FRM & rd & op0001=0x3 & op0204=0x4 & op0506=0x2 & funct7=0x60 & op2024=0x0 { - rdW = trunc(frs1S); + local tmp:4 = trunc(frs1S); + rd = sext(tmp); } # fcvt.wu.s d,S,m c0100053 fff0007f SIMPLE (0, 0) -:fcvt.wu.s rdW,frs1S,FRM is frs1S & FRM & rdW & op0001=0x3 & op0204=0x4 & op0506=0x2 & funct7=0x60 & op2024=0x1 +:fcvt.wu.s rd,frs1S,FRM is frs1S & FRM & rd & op0001=0x3 & op0204=0x4 & op0506=0x2 & funct7=0x60 & op2024=0x1 { - #TODO unsigned - rdW = trunc(frs1S); + local cond = (frs1S s<0); + local tmp:4 = (zext(cond) * 0:4) + (zext(!cond) * trunc(frs1S)); + rd = sext(tmp); # x[rd] = sext(f32->u32(f[rs1])) } @@ -153,17 +155,17 @@ # fmv.w.x D,s f0000053 fff0707f SIMPLE (0, 0) -:fmv.w.x frd,rs1W is frd & rs1W & op0001=0x3 & op0204=0x4 & op0506=0x2 & funct3=0x0 & funct7=0x78 & op2024=0x0 +:fmv.w.x frd,rs1 is frd & rs1 & op0001=0x3 & op0204=0x4 & op0506=0x2 & funct3=0x0 & funct7=0x78 & op2024=0x0 { - fassignS(frd, rs1W); + fassignS(frd, rs1:$(WXLEN)); } # fmv.x.w d,S e0000053 fff0707f SIMPLE (0, 0) -:fmv.x.w rdW,frs1S is frs1S & rdW & op0001=0x3 & op0204=0x4 & op0506=0x2 & funct3=0x0 & funct7=0x70 & op2024=0x0 +:fmv.x.w rd,frs1S is frs1S & rd & op0001=0x3 & op0204=0x4 & op0506=0x2 & funct3=0x0 & funct7=0x70 & op2024=0x0 { local tmpreg:4 = &frs1S; local tmp:4 = *[register]:4 tmpreg; - rdW = tmp; + rd = zext(tmp); } diff --git a/pypcode/processors/RISCV/data/languages/riscv.rv32m.sinc b/pypcode/processors/RISCV/data/languages/riscv.rv32m.sinc index f7202a3..07bb6e8 100644 --- a/pypcode/processors/RISCV/data/languages/riscv.rv32m.sinc +++ b/pypcode/processors/RISCV/data/languages/riscv.rv32m.sinc @@ -1,8 +1,15 @@ # RV32M Standard Extension +macro checkDivByZero(reg, rd, adjustment) { + if (reg != 0) goto ; + rd = adjustment; + goto inst_next; + +} # div d,s,t 02004033 fe00707f SIMPLE (0, 0) :div rd,rs1,rs2 is rs1 & rs2 & rd & op0001=0x3 & op0204=0x4 & op0506=0x1 & funct3=0x4 & funct7=0x1 { + checkDivByZero(rs2, rd, ~0); rd = rs1 s/ rs2; } @@ -10,6 +17,7 @@ # divu d,s,t 02005033 fe00707f SIMPLE (0, 0) :divu rd,rs1,rs2 is rs1 & rs2 & rd & op0001=0x3 & op0204=0x4 & op0506=0x1 & funct3=0x5 & funct7=0x1 { + checkDivByZero(rs2, rd, ~0); rd = rs1 / rs2; } @@ -54,6 +62,7 @@ # rem d,s,t 02006033 fe00707f SIMPLE (0, 0) :rem rd,rs1,rs2 is rs1 & rs2 & rd & op0001=0x3 & op0204=0x4 & op0506=0x1 & funct3=0x6 & funct7=0x1 { + checkDivByZero(rs2, rd, rs1); rd = rs1 s% rs2; } @@ -61,5 +70,6 @@ # remu d,s,t 02007033 fe00707f SIMPLE (0, 0) :remu rd,rs1,rs2 is rs1 & rs2 & rd & op0001=0x3 & op0204=0x4 & op0506=0x1 & funct3=0x7 & funct7=0x1 { + checkDivByZero(rs2, rd, rs1); rd = rs1 % rs2; } diff --git a/pypcode/processors/RISCV/data/languages/riscv.rv32q.sinc b/pypcode/processors/RISCV/data/languages/riscv.rv32q.sinc index b033986..5d42914 100644 --- a/pypcode/processors/RISCV/data/languages/riscv.rv32q.sinc +++ b/pypcode/processors/RISCV/data/languages/riscv.rv32q.sinc @@ -64,13 +64,16 @@ # fcvt.w.q d,S,m c6000053 fff0007f SIMPLE (0, 0) :fcvt.w.q rd,frs1,FRM is frs1 & FRM & rd & op0001=0x3 & op0204=0x4 & op0506=0x2 & funct7=0x63 & op2024=0x0 { - rd = trunc(frs1); + local tmp:4 = trunc(frs1S); + rd = sext(tmp); } # fcvt.wu.q d,S,m c6100053 fff0007f SIMPLE (0, 0) :fcvt.wu.q rd,frs1,FRM is frs1 & FRM & rd & op0001=0x3 & op0204=0x4 & op0506=0x2 & funct7=0x63 & op2024=0x1 { - rd = trunc(frs1); + local cond = (frs1S s<0); + local tmp:4 = (zext(cond) * 0) + (zext(!cond) * trunc(frs1S)); + rdL = sext(tmp); } diff --git a/pypcode/processors/RISCV/data/languages/riscv.rv64d.sinc b/pypcode/processors/RISCV/data/languages/riscv.rv64d.sinc index 0436594..7029ee6 100644 --- a/pypcode/processors/RISCV/data/languages/riscv.rv64d.sinc +++ b/pypcode/processors/RISCV/data/languages/riscv.rv64d.sinc @@ -28,8 +28,9 @@ # fcvt.lu.d d,S,m c2300053 fff0007f SIMPLE (64, 0) :fcvt.lu.d rdL,frs1D,FRM is frs1D & FRM & rdL & op0001=0x3 & op0204=0x4 & op0506=0x2 & funct7=0x61 & op2024=0x3 { - #TODO unsigned - rdL = trunc(frs1D); + local cond = (frs1D s<0); + local tmp:8 = (zext(cond) * 0:8) + (zext(!cond) * trunc(frs1D)); + rdL = tmp; } diff --git a/pypcode/processors/RISCV/data/languages/riscv.rv64f.sinc b/pypcode/processors/RISCV/data/languages/riscv.rv64f.sinc index 9a88490..55c28ca 100644 --- a/pypcode/processors/RISCV/data/languages/riscv.rv64f.sinc +++ b/pypcode/processors/RISCV/data/languages/riscv.rv64f.sinc @@ -10,8 +10,9 @@ # fcvt.lu.s d,S,m c0300053 fff0007f SIMPLE (64, 0) :fcvt.lu.s rdL,frs1S,FRM is frs1S & FRM & rdL & op0001=0x3 & op0204=0x4 & op0506=0x2 & funct7=0x60 & op2024=0x3 { - #TODO unsigned - rdL = trunc(frs1S); + local cond = (frs1S s<0); + local tmp:8 = (zext(cond) * 0) + (zext(!cond) * trunc(frs1S)); + rdL = tmp; } diff --git a/pypcode/processors/RISCV/data/languages/riscv.rv64i.sinc b/pypcode/processors/RISCV/data/languages/riscv.rv64i.sinc index c0ad6f0..a7d2106 100644 --- a/pypcode/processors/RISCV/data/languages/riscv.rv64i.sinc +++ b/pypcode/processors/RISCV/data/languages/riscv.rv64i.sinc @@ -107,15 +107,15 @@ # subw d,s,t 4000003b fe00707f SIMPLE (64, 0) -:subw rd,rs1W,rs2W is rs1W & rs2W & rd & op0001=0x3 & op0204=0x6 & op0506=0x1 & funct3=0x0 & funct7=0x20 +:subw rd,rs1,rs2 is rs1 & rs2 & rd & op0001=0x3 & op0204=0x6 & op0506=0x1 & funct3=0x0 & funct7=0x20 { - local result = rs1W - rs2W; + local result = rs1:$(WXLEN)- rs2:$(WXLEN); rd = sext(result); } # negw d,t 4000003b fe0ff07f ALIAS (64, 0) -:negw rd,rs2W is rs2W & rd & op0001=0x3 & op0204=0x6 & op0506=0x1 & funct3=0x0 & funct7=0x20 & op1519=0x0 +:negw rd,rs2 is rs2 & rd & op0001=0x3 & op0204=0x6 & op0506=0x1 & funct3=0x0 & funct7=0x20 & op1519=0x0 { - local tmp = -rs2W; + local tmp = -rs2:$(WXLEN); rd = sext(tmp); } diff --git a/pypcode/processors/RISCV/data/languages/riscv.rv64m.sinc b/pypcode/processors/RISCV/data/languages/riscv.rv64m.sinc index 8da116d..50fc2cd 100644 --- a/pypcode/processors/RISCV/data/languages/riscv.rv64m.sinc +++ b/pypcode/processors/RISCV/data/languages/riscv.rv64m.sinc @@ -5,6 +5,7 @@ { local tmpr1:4 = rs1:4; local tmpr2:4 = rs2:4; + checkDivByZero(tmpr2, rd, ~0); rd = sext(tmpr1 / tmpr2); } @@ -14,6 +15,7 @@ { local tmpr1:4 = rs1:4; local tmpr2:4 = rs2:4; + checkDivByZero(tmpr2, rd, ~0); rd = sext(tmpr1 s/ tmpr2); } @@ -31,6 +33,7 @@ { local tmpr1:4 = rs1:4; local tmpr2:4 = rs2:4; + checkDivByZero(tmpr2, rd, sext(tmpr1)); rd = sext(tmpr1 % tmpr2); } @@ -40,5 +43,6 @@ { local tmpr1:4 = rs1:4; local tmpr2:4 = rs2:4; + checkDivByZero(tmpr2, rd, sext(tmpr1)); rd = sext(tmpr1 s% tmpr2); } diff --git a/pypcode/processors/RISCV/data/languages/riscv.table.sinc b/pypcode/processors/RISCV/data/languages/riscv.table.sinc index 2cd1ab0..5e7a356 100644 --- a/pypcode/processors/RISCV/data/languages/riscv.table.sinc +++ b/pypcode/processors/RISCV/data/languages/riscv.table.sinc @@ -615,33 +615,21 @@ rs3: r2731 is r2731 { export r2731; } rs3: zero is zero & op2731=0 { export 0:$(XLEN); } rd: r0711 is r0711 { export r0711; } -rd: zero is r0711 & zero & op0711=0 { local tempZero:$(XLEN) = 0; export tempZero; } -rdDst: r0711 is r0711 { export r0711; } - - -rs1W: r1519 is r1519 { local tmp:$(WXLEN) = r1519:$(WXLEN); export tmp; } -rs1W: zero is r1519 & zero & op1519=0 { export 0:$(WXLEN); } - -rs2W: r2024 is r2024 { local tmp:$(WXLEN) = r2024:$(WXLEN); export tmp; } -rs2W: zero is r2024 & zero & op2024=0 { export 0:$(WXLEN); } - -#TODO dest may be bad, might need an assign macro -rdW: r0711 is r0711 { local tmp:$(WXLEN) = r0711:$(WXLEN); export tmp; } -rdW: zero is r0711 & zero & op0711=0 { export 0:$(WXLEN); } - +rd: zero is r0711=0 & zero { local tmp:$(XLEN) = 0; export tmp; } #TODO does this need to be in an if/endif @if ADDRSIZE == "64" -rs1L: r1519 is r1519 { local tmp:8 = r1519:8; export tmp; } +rs1L: r1519 is r1519 { export r1519; } rs1L: zero is r1519 & zero & op1519=0 { export 0:8; } -rs2L: r2024 is r2024 { local tmp:8 = r2024:8; export tmp; } +rs2L: r2024 is r2024 { export r2024; } rs2L: zero is r2024 & zero & op2024=0 { export 0:8; } -#TODO dest may be bad, might need an assign macro rdL: r0711 is r0711 { export r0711; } -rdL: zero is r0711 & zero & op0711=0 { export 0:8; } +rdL: zero is r0711=0 & zero { local tmp:8 = 0; export tmp; } + + @endif diff --git a/pypcode/processors/Sparc/data/languages/SparcV9.sinc b/pypcode/processors/Sparc/data/languages/SparcV9.sinc index 9aeac3e..6891cb1 100644 --- a/pypcode/processors/Sparc/data/languages/SparcV9.sinc +++ b/pypcode/processors/Sparc/data/languages/SparcV9.sinc @@ -342,23 +342,23 @@ if (DECOMPILE_MODE) goto ; #There are special cases for source operands RS1 and RS2 which just return the constant 0 when the #specified register is g0 -RS1: rs1 is rs1 & rs1_zero=0 { export 0:$(SIZE); } -RS1: rs1 is rs1 { export rs1; } +RS1: "%"^rs1 is rs1 & rs1_zero=0 { export 0:$(SIZE); } +RS1: "%"^rs1 is rs1 { export rs1; } -RS2: rs2 is rs2 & rs2_zero=0 { export 0:$(SIZE); } -RS2: rs2 is rs2 { export rs2; } +RS2: "%"^rs2 is rs2 & rs2_zero=0 { export 0:$(SIZE); } +RS2: "%"^rs2 is rs2 { export rs2; } #For the destination operand RD, we export a temporary varnode with value 0. #This is because writes to g0 are allowed, but they have no visible effect (see the Sparc manual). #This way the value of g0 won't appear to change when using the pcode emulator. # -RD: rd is rd & rd_zero=0 { local tmp:$(SIZE) = 0; export tmp; } +RD: "%"^rd is rd & rd_zero=0 { local tmp:$(SIZE) = 0; export tmp; } # didrestore is picked up by call instruction only # this will cause any instruction that assigns to the o7 return address register # in the delay slot of a call instruction to turn the call into a call/return # -RD: rd is rd & rd_d=15 { didrestore = 1; export rd; } -RD: rd is rd { export rd; } +RD: "%"^rd is rd & rd_d=15 { didrestore = 1; export rd; } +RD: "%"^rd is rd { export rd; } regorimm: RS2 is i=0 & RS2 { export RS2; } regorimm: simm13 is i=1 & simm13 { export *[const]:$(SIZE) simm13; } diff --git a/pypcode/processors/SuperH/data/languages/superh.ldefs b/pypcode/processors/SuperH/data/languages/superh.ldefs index c105dbd..4daaca9 100644 --- a/pypcode/processors/SuperH/data/languages/superh.ldefs +++ b/pypcode/processors/SuperH/data/languages/superh.ldefs @@ -8,6 +8,7 @@ version="1.0" slafile="sh-2a.sla" processorspec="superh.pspec" + manualindexfile="../manuals/superh.idx" id="SuperH:BE:32:SH-2A"> SuperH SH-2A processor 32-bit big-endian @@ -19,6 +20,7 @@ version="1.0" slafile="sh-2.sla" processorspec="superh.pspec" + manualindexfile="../manuals/superh.idx" id="SuperH:BE:32:SH-2"> SuperH SH-2 processor 32-bit big-endian @@ -30,6 +32,7 @@ version="1.0" slafile="sh-1.sla" processorspec="superh.pspec" + manualindexfile="../manuals/superh.idx" id="SuperH:BE:32:SH-1"> SuperH SH-1 processor 32-bit big-endian diff --git a/pypcode/processors/SuperH/data/languages/superh.sinc b/pypcode/processors/SuperH/data/languages/superh.sinc index 44c9fde..53c61a4 100644 --- a/pypcode/processors/SuperH/data/languages/superh.sinc +++ b/pypcode/processors/SuperH/data/languages/superh.sinc @@ -1492,12 +1492,12 @@ MovMUReg2: MovMUReg2_15 is MovMUReg2_15 { :shad rm_04_07, rn_08_11 is opcode_12_15=0b0100 & rn_08_11 & rm_04_07 & opcode_00_03=0b1100 { if (rm_04_07 s> 0) goto ; - if (rm_04_07 s<= -32) goto ; + if ((rm_04_07 & 0x1f) == 0) goto ; # shift right - rn_08_11 = rn_08_11 s>> -rm_04_07; + rn_08_11 = rn_08_11 s>> ( ( ~rm_04_07 & 0x1f ) + 1 ); goto ; - rn_08_11 = rn_08_11 << (rm_04_07 & 0x0000001F); + rn_08_11 = rn_08_11 << (rm_04_07 & 0x1f); goto ; rn_08_11 = -1 * zext(rn_08_11 s< 0); @@ -1526,10 +1526,10 @@ MovMUReg2: MovMUReg2_15 is MovMUReg2_15 { if (rm_04_07 s> 0) goto ; if (rm_04_07 s<= -32) goto ; # shift right - rn_08_11 = rn_08_11 >> -rm_04_07; + rn_08_11 = rn_08_11 >> ( ( ~rm_04_07 & 0x1f ) + 1 ); goto ; - rn_08_11 = rn_08_11 << (rm_04_07 & 0x0000001F); + rn_08_11 = rn_08_11 << (rm_04_07 & 0x1f); goto ; rn_08_11 = 0; diff --git a/pypcode/processors/SuperH/data/manuals/superh.idx b/pypcode/processors/SuperH/data/manuals/superh.idx new file mode 100644 index 0000000..31825e1 --- /dev/null +++ b/pypcode/processors/SuperH/data/manuals/superh.idx @@ -0,0 +1,95 @@ +@ h12p0.pdf[SuperH RISC Engine SH-1/SH-2 Programming Manual September 3, 1996] +add, 64 +addc, 65 +addv, 66 +and, 67 +and.b, 67 +bf, 69 +bf/s, 70 +bra, 72 +braf, 74 +bsr, 76 +bsrf, 78 +bt, 79 +bt/s, 80 +clrmac, 82 +clrt, 83 +cmp/eq, 84 +cmp/ge, 84 +cmp/gt, 84 +cmp/hi, 84 +cmp/hs, 84 +cmp/pl, 84 +cmp/pz, 84 +cmp/str, 84 +div0s, 88 +div0u, 89 +div1, 90 +dmuls.l, 95 +dmulu.l, 97 +dt, 99 +exts.b, 100 +exts.w, 100 +extu.b, 101 +extu.w, 101 +jmp, 102 +jsr, 103 +ldc, 105 +ldc.l, 105 +lds, 107 +lds.l, 107 +mac.l, 109 +mac, 112 +mac.w, 113 +mov, 116 +mov.b, 116 +mov.w, 116 +mov.l, 116 +mova, 129 +movt, 130 +mul.l, 131 +muls.w, 132 +mulu.w, 133 +neg, 134 +negc, 135 +nop, 136 +not, 137 +or, 138 +or.b, 138 +rotcl, 140 +rotcr, 141 +rotl, 142 +rotr, 143 +rte, 144 +rts, 145 +sett, 147 +shal, 148 +shar, 149 +shll, 150 +shll2, 151 +shll8, 151 +shll16, 151 +shlr, 153 +shlr2, 154 +shlr8, 154 +shlr16, 154 +sleep, 156 +stc, 157 +stc.l, 157 +sts, 159 +sts.l, 159 +sub, 161 +subc, 162 +subv, 163 +swap, 164 +swap.b, 164 +swap.w, 164 +tas, 165 +tas.b, 165 +trapa, 166 +tst, 167 +tst.b, 167 +xor, 169 +xor.b, 169 +xtrct, 171 + diff --git a/pypcode/processors/SuperH4/data/languages/SuperH4.sinc b/pypcode/processors/SuperH4/data/languages/SuperH4.sinc index 1b0e76c..a0dac54 100644 --- a/pypcode/processors/SuperH4/data/languages/SuperH4.sinc +++ b/pypcode/processors/SuperH4/data/languages/SuperH4.sinc @@ -749,7 +749,7 @@ N_0txx: r0",@"^N_0 is r0 & N_0 { tmp:4 = N_0; export tmp; } # text bsr # arch arch_sh_up :bsr I_1tbranch is OP_0=0xb & I_1tbranch { - + PR = inst_next; delayslot(1); call I_1tbranch; } diff --git a/pypcode/processors/V850/data/languages/Helpers/Conditions.sinc b/pypcode/processors/V850/data/languages/Helpers/Conditions.sinc deleted file mode 100644 index e52ed22..0000000 --- a/pypcode/processors/V850/data/languages/Helpers/Conditions.sinc +++ /dev/null @@ -1,38 +0,0 @@ -##################################################### -##### Conditions ##### -##################################################### - - -c0003: "v" is op0003=0x0 { tmp:1 = ($(OV)) == 1; export tmp; } -c0003: "nv" is op0003=0x8 { tmp:1 = ($(OV)) == 0; export tmp; } -c0003: "c" is op0003=0x1 { tmp:1 = ($(CY)) == 1; export tmp; } -c0003: "nc" is op0003=0x9 { tmp:1 = ($(CY)) == 0; export tmp; } -c0003: "e" is op0003=0x2 { tmp:1 = ($(Z)) == 1; export tmp; } -c0003: "ne" is op0003=0xA { tmp:1 = ($(Z)) == 0; export tmp; } -c0003: "nh" is op0003=0x3 { tmp:1 = ($(CY) || $(Z)) == 1; export tmp; } -c0003: "h" is op0003=0xB { tmp:1 = ($(CY) || $(Z)) == 0; export tmp; } -c0003: "n" is op0003=0x4 { tmp:1 = ($(S)) == 1; export tmp; } -c0003: "p" is op0003=0xC { tmp:1 = ($(S)) == 0; export tmp; } -c0003: "t" is op0003=0x5 { tmp:1 = 1; export tmp; } -c0003: "sa" is op0003=0xD { tmp:1 = ($(SAT)) == 1; export tmp; } -c0003: "lt" is op0003=0x6 { tmp:1 = ($(S) ^^ $(OV)) == 1; export tmp; } -c0003: "ge" is op0003=0xE { tmp:1 = ($(S) ^^ $(OV)) == 0; export tmp; } -c0003: "le" is op0003=0x7 { tmp:1 = ($(S) ^^ $(OV) || $(Z)) == 1; export tmp; } -c0003: "gt" is op0003=0xF { tmp:1 = ($(S) ^^ $(OV) || $(Z)) == 0; export tmp; } - -c1720: "v" is op1720=0x0 { tmp:1 = ($(OV)) == 1; export tmp; } -c1720: "nv" is op1720=0x8 { tmp:1 = ($(OV)) == 0; export tmp; } -c1720: "c" is op1720=0x1 { tmp:1 = ($(CY)) == 1; export tmp; } -c1720: "nc" is op1720=0x9 { tmp:1 = ($(CY)) == 0; export tmp; } -c1720: "e" is op1720=0x2 { tmp:1 = ($(Z)) == 1; export tmp; } -c1720: "ne" is op1720=0xA { tmp:1 = ($(Z)) == 0; export tmp; } -c1720: "nh" is op1720=0x3 { tmp:1 = ($(CY) || $(Z)) == 1; export tmp; } -c1720: "h" is op1720=0xB { tmp:1 = ($(CY) || $(Z)) == 0; export tmp; } -c1720: "n" is op1720=0x4 { tmp:1 = ($(S)) == 1; export tmp; } -c1720: "p" is op1720=0xC { tmp:1 = ($(S)) == 0; export tmp; } -c1720: "t" is op1720=0x5 { tmp:1 = 1; export tmp; } -c1720: "sa" is op1720=0xD { tmp:1 = ($(SAT)) == 1; export tmp; } -c1720: "lt" is op1720=0x6 { tmp:1 = ($(S) ^^ $(OV)) == 1; export tmp; } -c1720: "ge" is op1720=0xE { tmp:1 = ($(S) ^^ $(OV)) == 0; export tmp; } -c1720: "le" is op1720=0x7 { tmp:1 = ($(S) ^^ $(OV) || $(Z)) == 1; export tmp; } -c1720: "gt" is op1720=0xF { tmp:1 = ($(S) ^^ $(OV) || $(Z)) == 0; export tmp; } diff --git a/pypcode/processors/V850/data/languages/Helpers/Extras.sinc b/pypcode/processors/V850/data/languages/Helpers/Extras.sinc deleted file mode 100644 index 6abc080..0000000 --- a/pypcode/processors/V850/data/languages/Helpers/Extras.sinc +++ /dev/null @@ -1,131 +0,0 @@ -##################################################### -##### Extras ##### -##################################################### - - -# read r0 always return zero -R0004: _R0004 is _R0004 & _R0004=0 { local x:4=0; export x; } -R0004: _R0004 is _R0004 { export _R0004; } - -R1115: _R1115 is _R1115 & _R1115=0 { local x:4=0; export x; } -R1115: _R1115 is _R1115 { export _R1115; } - -R2731: _R2731 is _R2731 & _R2731=0 { local x:4=0; export x; } -R2731: _R2731 is _R2731 { export _R2731; } - - -adr9: res is op0406 & s1115 -[ res = ((s1115 << 4) | (op0406 << 1)) + inst_start; ] -{ - export *:4 res; -} - -adr22: res is s0005; op1631 & op1616=0 -[ res = ((s0005 << 16) | op1631) + inst_start; ] -{ - export *:4 res; -} - -adr32: res is op1631 & op1616=0; op3247 -[ res = ((op3247 << 16) | op1631) + inst_start; ] -{ - export *:4 res; -} - -adr32i: res is op1631 & op1616=0; op3247 -[ res = ((op3247 << 16) | op1631); ] -{ - export *[const]:4 res; -} - -reg4: op0_1720 is op2323=0 & op0_1720 { export op0_1720; } -reg4: op1_1720 is op2323=1 & op1_1720 { export op1_1720; } - - - -##### Prep/Disp Loop ##### - -PrepList20: r20 is prep27=1 & r20 { push(r20); } -PrepList20: is prep27=0 { } - -PrepList21: r21 is prep26=1 & prep27=0 & r21 { push(r21); } -PrepList21: PrepList20,r21 is prep26=1 & PrepList20 & r21 { push(r21); } -PrepList21: PrepList20 is prep26=0 & PrepList20 { } - -PrepList22: r22 is prep25=1 & prep2627=0 & r22 { push(r22); } -PrepList22: PrepList21,r22 is prep25=1 & PrepList21 & r22 { push(r22); } -PrepList22: PrepList21 is prep25=0 & PrepList21 { } - -PrepList23: r23 is prep24=1 & prep2527=0 & r23 { push(r23); } -PrepList23: PrepList22,r23 is prep24=1 & PrepList22 & r23 { push(r23); } -PrepList23: PrepList22 is prep24=0 & PrepList22 { } - -PrepList24: r24 is prep31=1 & prep2427=0 & r24 { push(r24); } -PrepList24: PrepList23,r24 is prep31=1 & PrepList23 & r24 { push(r24); } -PrepList24: PrepList23 is prep31=0 & PrepList23 { } - -PrepList25: r25 is prep30=1 & prep2427=0 & prep31=0 & r25 { push(r25); } -PrepList25: PrepList24,r25 is prep30=1 & PrepList24 & r25 { push(r25); } -PrepList25: PrepList24 is prep30=0 & PrepList24 { } - -PrepList26: r26 is prep29=1 & prep2427=0 & prep3031=0 & r26 { push(r26); } -PrepList26: PrepList25,r26 is prep29=1 & PrepList25 & r26 { push(r26); } -PrepList26: PrepList25 is prep29=0 & PrepList25 { } - -PrepList27: r27 is prep28=1 & prep2427=0 & prep2931=0 & r27 { push(r27); } -PrepList27: PrepList26,r27 is prep28=1 & PrepList26 & r27 { push(r27); } -PrepList27: PrepList26 is prep28=0 & PrepList26 { } - -PrepList28: r28 is prep23=1 & prep2431=0 & r28 { push(r28); } -PrepList28: PrepList27,r28 is prep23=1 & PrepList27 & r28 { push(r28); } -PrepList28: PrepList27 is prep23=0 & PrepList27 { } - -PrepList29: r29 is prep22=1 & prep2431=0 & prep23=0 & r29 { push(r29); } -PrepList29: PrepList28,r29 is prep22=1 & PrepList28 & r29 { push(r29); } -PrepList29: PrepList28 is prep22=0 & PrepList28 { } - -PrepList30: ep is prep00=1 & prep2431=0 & prep2223=0 & ep { push(ep); } -PrepList30: PrepList29,ep is prep00=1 & PrepList29 & ep { push(ep); } -PrepList30: PrepList29 is prep00=0 & PrepList29 { } - -PrepList: { lp } is prep21=1 & prep2431=0 & prep2223=0 & prep00=0 & lp { push(lp); } -PrepList: { PrepList30,lp } is prep21=1 & PrepList30 & lp { push(lp); } -PrepList: { PrepList30 } is prep21=0 & PrepList30 { } - - - -DispList31: lp is prep21=1 & lp { pop(lp); } -DispList31: is prep21=0 { } - -DispList30: ep,DispList31 is DispList31 & prep00=1 & ep { pop(ep); } -DispList30: DispList31 is DispList31 & prep00=0 { } - -DispList29: r29,DispList30 is DispList30 & prep22=1 & r29 { pop(r29); } -DispList29: DispList30 is DispList30 & prep22=0 { } - -DispList28: r28,DispList29 is DispList29 & prep23=1 & r28 { pop(r28); } -DispList28: DispList29 is DispList29 & prep23=0 { } - -DispList27: r27,DispList28 is DispList28 & prep28=1 & r27 { pop(r27); } -DispList27: DispList28 is DispList28 & prep28=0 { } - -DispList26: r26,DispList27 is DispList27 & prep29=1 & r26 { pop(r26); } -DispList26: DispList27 is DispList27 & prep29=0 { } - -DispList25: r25,DispList26 is DispList26 & prep30=1 & r25 { pop(r25); } -DispList25: DispList26 is DispList26 & prep30=0 { } - -DispList24: r24,DispList25 is DispList25 & prep31=1 & r24 { pop(r24); } -DispList24: DispList25 is DispList25 & prep31=0 { } - -DispList23: r23,DispList24 is DispList24 & prep24=1 & r23 { pop(r23); } -DispList23: DispList24 is DispList24 & prep24=0 { } - -DispList22: r22,DispList23 is DispList23 & prep25=1 & r22 { pop(r22); } -DispList22: DispList23 is DispList23 & prep25=0 { } - -DispList21: r21,DispList22 is DispList22 & prep26=1 & r21 { pop(r21); } -DispList21: DispList22 is DispList22 & prep26=0 { } - -DispList: { r20,DispList21 } is DispList21 & prep27=1 & r20 { pop(r20); } -DispList: { DispList21 } is DispList21 & prep27=0 { } diff --git a/pypcode/processors/V850/data/languages/Helpers/Macros.sinc b/pypcode/processors/V850/data/languages/Helpers/Macros.sinc deleted file mode 100644 index 5985412..0000000 --- a/pypcode/processors/V850/data/languages/Helpers/Macros.sinc +++ /dev/null @@ -1,254 +0,0 @@ -##################################################### -##### Macros ##### -##################################################### - - -##### CARRY-Flag ##### - -macro set_CY_pos(var1, var2) -{ - $(CY) = carry(var1, var2); -} - -macro set_CY_pos2(var1, var2, var3) -{ - local var12 = var1 + var2; - $(CY) = carry(var1, var2) || carry(var12, var3); -} - -macro set_CY_neg(var1, var2) -{ - $(CY) = var1 < var2; -} - -macro set_CY_neg2(var1, var2, var3) -{ - local var23 = var2 + var3; - $(CY) = (var1 < var23); -} - - - -##### Overflow-Flag ##### - -macro set_OV_pos(var1, var2) -{ - $(OV) = scarry(var1, var2); -} - -macro set_OV_pos2(var1, var2, var3) -{ - local var12 = var1 + var2; - $(OV) = scarry(var1, var2) || scarry(var12, var3); -} - -macro set_OV_neg(var1, var2) -{ - local A:4 = var1; - local B:4 = var2; - local R = A - B; - - local A1 = A[31,1]; - local B1 = B[31,1]; - local R1 = R[31,1]; - - $(OV) = (A1 != B1) && (B1 == R1); - - #OV = 1 if: - #pos - neg = neg - #neg - pos = pos -} - -macro set_OV_neg2(var1, var2, var3) -{ - local A:4 = var1; - local B:4 = var2; - local C:4 = var3; - local R = A - B - C; - - local A1 = A[31,1]; - local B1 = B[31,1]; - local R1 = R[31,1]; - - $(OV) = (A1 != B1) && (B1 == R1); -} - - - -##### S/Z-Flags ##### - -macro set_S(flag) -{ - $(S) = flag s< 0; -} - -macro set_Z(var) -{ - $(Z) = var == 0; -} - - - -##### General-Flag-Macros ##### - -macro set_general_flags_pos(var1, var2) -{ - local res = var1 + var2; - set_CY_pos(var1, var2); - set_OV_pos(var1, var2); - set_S(res); - set_Z(res); -} - -macro set_general_flags_neg(var1, var2) -{ - local res = var1 - var2; - set_CY_neg(var1, var2); - set_OV_neg(var1, var2); - set_S(res); - set_Z(res); -} - -macro set_OV0_S_Z(var) -{ - $(OV) = 0; - set_S(var); - set_Z(var); -} - - - -##### General-Macros ##### - -# if condition is != 0 -macro either_or(res, cond, true, false) -{ - res = (true * zext(cond != 0)) + (false * zext(cond == 0)); -} - -# if condition is == 1 -macro either_or1(res, cond, true, false) -{ - res = (true * zext(cond == 1)) + (false * zext(cond != 1)); -} - -macro shift_right_logic(res, var, shift_) -{ - local shift = shift_ & 0x1f; - local mask = (zext(shift != 0) * var) & (1 << (shift - 1)); - res = var >> shift; - set_OV0_S_Z(res); - $(CY) = ((mask != 0) && (shift != 0)); -} - -macro shift_right_arith(res, var, shift_) -{ - local shift = shift_ & 0x1f; - local mask = (zext(shift != 0) * var) & (1 << (shift - 1)); - res = var s>> shift; - set_OV0_S_Z(res); - $(CY) = ((mask != 0) && (shift != 0)); -} - -macro shift_left_logic(res, var, shift_) -{ - local shift = shift_ & 0x1f; - local mask = (zext(shift != 0) * var) & (1 << (32 - shift)); - res = var << shift; - set_OV0_S_Z(res); - $(CY) = ((mask != 0) && (shift != 0)); -} - - - -##### Prep/Disp Macros ##### - -macro push(reg) -{ - sp = sp - 4; - *:4 sp = reg; -} - -macro pop(reg) -{ - reg = *:4 sp; - sp = sp + 4; -} - - - -##### Search Macros ##### - -macro SearchRight(res, var, char) -{ - local var_:4 = var; - res = 0; - - - if ((var_ & 0x1) == char) - goto ; - - var_ = var_ >> 1; - res = res + 1; - - if (res < 32) - goto ; - - res = 0; - - -} - -macro SearchLeft(res, var, char) -{ - local var_:4 = var; - res = 0; - - - if ((var_ >> 31) == char) - goto ; - - var_ = var_ << 1; - res = res + 1; - - if (res < 32) - goto ; - - res = 0; - - -} - -# macro saturate(var) -# { -# if (var s> 0x7FFFFFFF) -# goto ; - -# if (var s< -0x80000000) -# goto ; - -# goto ; - -# -# var = 0x7FFFFFFF; -# goto ; - -# -# var = -0x80000000; -# goto ; - -# -# } - - -##### Float-Macros ##### - -macro compare_float(res, fcond, reg1, reg2) -{ - local un = ((fcond & 1) == 1) & (nan(reg2) || nan(reg1)); - local eq = ((fcond & 2) == 2) & (!(nan(reg2) || nan(reg1))) & (reg2 f== reg1); - local le = ((fcond & 4) == 4) & (!(nan(reg2) || nan(reg1))) & (reg2 f< reg1); - #local ex = (fcond & 8) & ((nan(reg2) || nan(reg1))); - - res = zext(un|eq|le); -} diff --git a/pypcode/processors/V850/data/languages/Helpers/Register.sinc b/pypcode/processors/V850/data/languages/Helpers/Register.sinc deleted file mode 100644 index 9cc9824..0000000 --- a/pypcode/processors/V850/data/languages/Helpers/Register.sinc +++ /dev/null @@ -1,36 +0,0 @@ -##################################################### -##### Register ##### -##################################################### - - -##### General-purpose registers (r0 to r31) ##### - -define register offset=0x0 size=0x4 # offset = 0 because it's the start -[ - r0 r1 r2 sp gp tp r6 r7 r8 r9 - r10 r11 r12 r13 r14 r15 r16 r17 r18 r19 - r20 r21 r22 r23 r24 r25 r26 r27 r28 r29 - ep lp -]; - - - -##### Control/Special registers ##### - -define register offset=0x80 size=0x4 # offset = 0x80(128) = PreOffset+PreRegister*Size = 0+32*4 = 128 -[ - EIPC EIPSW FEPC FEPSW ECR PSW FPSR FPEPC FPST FPCC - FPCFG SCCFG SCBP EIIC FEIC DBIC CTPC CTPSW DBPC DBPSW - CTBP DIR DBG22 DBG23 DBG24 DBG25 DBG26 DBG27 EIWR FEWR - DBWR BSEL -]; - -define register offset=0x0 size=0x8 -[ - r0r1 r2sp r4r5 r6r7 r8r9 - r10r11 r12r13 r14r15 r16r17 r18r19 - r20r21 r22r23 r24r25 r26r27 r28r29 - eplp -]; - -define register offset=0x100 size=0x4 [ PC ]; # offset = 0x100(256) = PreOffset+PreRegister*Size = 128+32*4 = 256 diff --git a/pypcode/processors/V850/data/languages/Helpers/Tokens.sinc b/pypcode/processors/V850/data/languages/Helpers/Tokens.sinc deleted file mode 100644 index 8402ab0..0000000 --- a/pypcode/processors/V850/data/languages/Helpers/Tokens.sinc +++ /dev/null @@ -1,105 +0,0 @@ -##################################################### -##### Tokens ##### -##################################################### - - -define token instr(16) - op0000 = (0,0) - op0003 = (0,3) - op0004 = (0,4) - _R0004 = (0,4) - SR0004 = (0,4) - R0004x2 = (0,4) - s0004 = (0,4) signed - s0005 = (0,5) signed - op0005 = (0,5) - op0006 = (0,6) - op0010 = (0,10) - op0015 = (0,15) - op0106 = (1,6) - op0406 = (4,6) - op0410 = (4,10) - op0505 = (5,5) - op0510 = (5,10) - op0515 = (5,15) - op0610 = (6,10) - op0615 = (6,15) - op0710 = (7,10) - op1113 = (11,13) - op1114 = (11,14) - op1115 = (11,15) - _R1115 = (11,15) - SR1115 = (11,15) - R1115x2 = (11,15) - s1115 = (11,15) signed - op1415 = (14,15) - op1515 = (15,15) -; - -define token instr2(16) - op1616 = (0,0) - op1617 = (0,1) - op1619 = (0,3) - op1620 = (0,4) - R1620 = (0,4) - R1620x2 = (0,4) - op1626 = (0,10) - op1631 = (0,15) - s1631 = (0,15) signed - fcbit1719 = (1,3) - op1720 = (1,4) - op0_1720 = (1,4) - op1_1720 = (1,4) - s1731 = (1,15) signed - op1821 = (2,5) - s1821 = (2,5) signed - op2020 = (4,4) - op2026 = (4,10) - op2122 = (5,6) - op2126 = (5,10) - op2226 = (6,10) - op2323 = (7,7) - op2426 = (8,10) - op2729 = (11,13) - fcond2730 = (11,14) - op2731 = (11,15) - _R2731 = (11,15) - R2731x2 = (11,15) - op3031 = (14,15) - op3131 = (15,15) -; - -define token instr3(16) - op3247 = (0,15) - s3247 = (0,15) signed -; - -define token instr4(16) - op4863 = (0,15) -; - -# used in PREPARE/DISPOSE instructions -define token prep(32) - prep00 = (0,0) - prep0105 = (1,5) - prep0615 = (6,15) - prep1620 = (16,20) - prep21 = (21,21) - prep22 = (22,22) - prep2223 = (22,31) - prep23 = (23,23) - prep24 = (24,24) - prep2431 = (24,31) - prep25 = (25,25) - prep26 = (26,26) - prep27 = (27,27) - prep28 = (28,28) - prep29 = (29,29) - prep2931 = (29,31) - prep3031 = (30,31) - prep2427 = (24,27) - prep2527 = (25,27) - prep2627 = (26,27) - prep30 = (30,30) - prep31 = (31,31) -; diff --git a/pypcode/processors/V850/data/languages/Helpers/Variables.sinc b/pypcode/processors/V850/data/languages/Helpers/Variables.sinc deleted file mode 100644 index e427b03..0000000 --- a/pypcode/processors/V850/data/languages/Helpers/Variables.sinc +++ /dev/null @@ -1,49 +0,0 @@ -##################################################### -##### Variables ##### -##################################################### - - -attach variables [ _R0004 _R1115 _R2731 R1620 prep1620] -[ - r0 r1 r2 sp gp tp r6 r7 r8 r9 - r10 r11 r12 r13 r14 r15 r16 r17 r18 r19 - r20 r21 r22 r23 r24 r25 r26 r27 r28 r29 - ep lp -]; - -attach variables [ R0004x2 R1115x2 R1620x2 R2731x2 ] -[ - r0r1 _ r2sp _ r4r5 _ r6r7 _ r8r9 _ - r10r11 _ r12r13 _ r14r15 _ r16r17 _ r18r19 _ - r20r21 _ r22r23 _ r24r25 _ r26r27 _ r28r29 _ - eplp _ -]; - -attach variables [ SR0004 SR1115 ] -[ - EIPC EIPSW FEPC FEPSW ECR PSW FPSR FPEPC FPST FPCC - FPCFG SCCFG SCBP EIIC FEIC DBIC CTPC CTPSW DBPC DBPSW - CTBP DIR DBG22 DBG23 DBG24 DBG25 DBG26 DBG27 EIWR FEWR - DBWR BSEL -]; - - -attach variables [op0_1720] [r0 r2 gp r6 r8 r10 r12 r14 r16 r18 r20 r22 r24 r26 r28 ep]; -attach variables [op1_1720] [r1 sp tp r7 r9 r11 r13 r15 r17 r19 r21 r23 r25 r27 r29 lp]; - - -attach names [fcond2730] -["f" "un" "eq" "ueq" "olt" "ult" "ole" "ule" "sd" "ngle" "seq" "ngl" "lt" "nge" "le" "ngt"]; - - -@define NP "PSW[7,1]" -@define EP "PSW[6,1]" -@define ID "PSW[5,1]" -@define SAT "PSW[4,1]" -@define CY "PSW[3,1]" -@define OV "PSW[2,1]" -@define S "PSW[1,1]" -@define Z "PSW[0,1]" - -@define EICC "ECR[0,16]" -@define FECC "ECR[16,16]" diff --git a/pypcode/processors/V850/data/languages/Instructions/Arithmetic.sinc b/pypcode/processors/V850/data/languages/Instructions/Arithmetic.sinc deleted file mode 100644 index a546e24..0000000 --- a/pypcode/processors/V850/data/languages/Instructions/Arithmetic.sinc +++ /dev/null @@ -1,336 +0,0 @@ -# (3) Multiply instructions -# (4) Multiply-accumulate instructions -# (5) Arithmetic instructions -# (7) Saturated operation instructions -# (11) Divide instructions -# (12) High-speed divide instructions - - - -##################################################### -##### Multiply ##### -##################################################### - - -# MUL reg1, reg2, reg3 - rrrrr111111RRRRR|wwwww01000100000 -:mul R0004, R1115, R2731 is op0510=0x3F & R0004 & R1115; op1626=0x220 & R2731 -{ - local res:8 = sext(R1115) * sext(R0004); - R1115 = res:4; - R2731 = res[32,32]; -} - -# MUL imm9, reg2, reg3 - rrrrr111111iiiii|wwwww01001IIII00 -:mul imm9, R1115, R2731 is op0510=0x3F & op0004 & R1115; op2226=0x9 & op1617=0x0 & s1821 & R2731 -[ imm9 = (s1821 << 5) | op0004; ] -{ - local res:8 = sext(R1115) * imm9; - R1115 = res:4; - R2731 = res[32,32]; -} - -# MULH reg1, reg2 - rrrrr000111RRRRR -:mulh R0004, R1115 is op0510=0x07 & R0004 & R1115 & op1115!=0 -{ - R1115 = sext(R1115:2) * sext(R0004:2); -} - -# MULH imm5, reg2 - rrrrr010111iiiii -:mulh s0004, R1115 is op0510=0x17 & s0004 & R1115 -{ - R1115 = sext(R1115:2) * s0004; -} - -# MULHI imm16, reg1, reg2 - rrrrr110111RRRRR|iiiiiiiiiiiiiiii -:mulhi s1631, R0004, R1115 is op0510=0x37 & R1115 & R0004; s1631 -{ - R1115 = R0004 * s1631; -} - -# MULU reg1, reg2, reg3 - rrrrr111111RRRRR|wwwww01000100010 -:mulu R0004, R1115, R2731 is op0510=0x3F & R0004 & R1115; op1626=0x222 & R2731 -{ - local res:8 = zext(R1115) * zext(R0004); - R1115 = res:4; - R2731 = res[32,32]; -} - -# MULU imm9, reg2, reg3 - rrrrr111111iiiii|wwwww01001IIII10 -:mulu imm9, R1115, R2731 is op0510=0x3F & op0004 & R1115; op2226=0x9 & op1617=0x2 & op1821 & R2731 -[ imm9 = (op1821 << 5) | op0004; ] -{ - local res:8 = zext(R1115) * imm9; - R1115 = res:4; - R2731 = res[32,32]; -} - - - -##################################################### -##### MultiplyAccumulate ##### -##################################################### - - -# MAC reg1, reg2, reg3, reg4 - rrrrr111111RRRRR wwww0011110mmmm0 -:mac R0004, R1115, R2731x2, R1620x2 is op0510=0x3F & R0004 & R1115; op2126=0x1E & op1616=0 & R1620x2 & R2731x2 -{ - R1620x2 = sext(R1115) * sext(R0004) + R2731x2; -} - -# MACU reg1, reg2, reg3, reg4 - rrrrr111111RRRRR|wwww0011111mmmm0 -:macu R0004, R1115, R2731x2, R1620x2 is op0510=0x3F & R0004 & R1115; op2126=0x1F & op1616=0 & R1620x2 & R2731x2 -{ - R1620x2 = zext(R1115) * zext(R0004) + R2731x2; -} - - - -##################################################### -##### Arithmetic ##### -##################################################### - - -# ADD reg1, reg2 - rrrrr001110RRRRR -:add R0004, R1115 is op0510=0x0E & R0004 & R1115 -{ - set_general_flags_pos(R0004, R1115); - R1115 = R1115 + R0004; -} - -# ADD imm5, reg2 - rrrrr010010iiiii -:add s0004, R1115 is op0510=0x12 & s0004 & R1115 -{ - set_general_flags_pos(s0004, R1115); - R1115 = R1115 + s0004; -} - -# ADDI imm16, reg1, reg2 - rrrrr110000RRRRR|iiiiiiiiiiiiiiii -:addi s1631, R0004, R1115 is op0510=0x30 & R1115 & R0004; s1631 -{ - set_general_flags_pos(R0004, s1631); - R1115 = R0004 + s1631; -} - -# CMP reg1, reg2 - rrrrr001111RRRRR -:cmp R0004, R1115 is op0510=0x0F & R0004 & R1115 -{ - set_general_flags_neg(R1115, R0004); -} - -# CMP imm5, reg2 - rrrrr010011iiiii -:cmp s0004, R1115 is op0510=0x13 & s0004 & R1115 -{ - set_general_flags_neg(R1115, s0004); -} - -# MOV reg1, reg2 - rrrrr000000RRRRR -:mov R0004, R1115 is op0510=0x00 & R0004 & R1115 -{ - R1115 = R0004; -} - -# MOV imm5, reg2 - rrrrr010000iiiii -:mov s0004, R1115 is op0510=0x10 & s0004 & R1115 & op1115!=0 -{ - R1115 = s0004; -} - -# MOV imm32, reg1 - 00000110001RRRRR|iiiiiiiiiiiiiiii|IIIIIIIIIIIIIIII -:mov imm32, R0004 is op0515=0x031 & R0004; op1631; op3247 -[ imm32 = (op3247 << 16) | op1631; ] -{ - R0004 = imm32; -} - -# MOVEA imm16, reg1, reg2 - rrrrr110001RRRRR|iiiiiiiiiiiiiiii -:movea s1631, R0004, R1115 is op0510=0x31 & op1115!=0 & R0004 & R1115; s1631 -{ - R1115 = R0004 + s1631; -} - -# MOVHI imm16, reg1, reg2 - rrrrr110010RRRRR|iiiiiiiiiiiiiiii -:movhi s1631, R0004, R1115 is op0510=0x32 & op1115!=0 & R0004 & R1115; s1631 -{ - R1115 = R0004 + (s1631 << 16); -} - -# SUB reg1, reg2 - rrrrr001101RRRRR -:sub R0004, R1115 is op0510=0x0D & R0004 & R1115 -{ - set_general_flags_neg(R1115, R0004); - R1115 = R1115 - R0004; -} - -# SUBR reg1, reg2 - rrrrr001100RRRRR -:subr R0004, R1115 is op0510=0x0C & R0004 & R1115 -{ - set_general_flags_neg(R0004, R1115); - R1115 = R0004 - R1115; -} - - - -##################################################### -##### Saturated ##### -##################################################### - - -define pcodeop __saturate; - -# SATADD reg1, reg2 - rrrrr000110RRRRR -:satadd R0004, R1115 is op0510=0x06 & R0004 & R1115 & op1115!=0 -{ - set_general_flags_pos(R1115, R0004); - $(SAT) = $(SAT) || $(OV); - R1115 = R1115 + R0004; - __saturate(R1115); -} - -#SATADD imm5, reg2 - rrrrr010001iiiii -:satadd s0004, R1115 is op0510=0x11 & s0004 & R1115 & op1115!=0 -{ - set_general_flags_pos(R1115, s0004); - $(SAT) = $(SAT) || $(OV); - R1115 = R1115 + s0004; - __saturate(R1115); -} - -# SATADD reg1, reg2, reg3 - rrrrr111111RRRRR|wwwww01110111010 -:satadd R0004, R1115, R2731 is op0510=0x3F & R0004 & R1115; op1626=0x3BA & R2731 -{ - set_general_flags_pos(R1115, R0004); - $(SAT) = $(SAT) || $(OV); - R2731 = R1115 + R0004; - __saturate(R2731); -} - -# SATSUB reg1, reg2 - rrrrr000101RRRRR -:satsub R0004, R1115 is op0510=0x05 & R0004 & R1115 & op1115!=0 -{ - set_general_flags_neg(R1115, R0004); - $(SAT) = $(SAT) || $(OV); - R1115 = R1115 - R0004; - __saturate(R1115); -} - -# SATSUB reg1, reg2, reg3 - rrrrr111111RRRRR|wwwww01110011010 -:satsub R0004, R1115, R2731 is op0510=0x3F & R0004 & R1115; op1626=0x39A & R2731 -{ - set_general_flags_neg(R1115, R0004); - $(SAT) = $(SAT) || $(OV); - R2731 = R1115 - R0004; - __saturate(R2731); -} - -# SATSUBI imm16, reg1, reg2 -:satsubi s1631, R0004, R1115 is op0510=0x33 & op1115!=0 & R0004 & R1115; s1631 -{ - set_general_flags_neg(R0004, s1631); - $(SAT) = $(SAT) || $(OV); - R1115 = R0004 - s1631; - __saturate(R1115); -} - -# SATSUBR reg1, reg2 -:satsubr R0004, R1115 is op0510=0x04 & R0004 & R1115 & op1115!=0 -{ - set_general_flags_neg(R0004, R1115); - $(SAT) = $(SAT) || $(OV); - R1115 = R0004 - R1115; - __saturate(R1115); -} - - - -##################################################### -##### Divide ##### -##################################################### - - -# DIV reg1, reg2, reg3 - rrrrr111111RRRRR|wwwww01011000000 -:div R0004, R1115, R2731 is op0510=0x3F & R0004 & R1115; op1626=0x2C0 & R2731 -{ - local quot:4 = R1115 s/ R0004; - local mod:4 = R1115 s% R0004; - $(OV) = ((R1115 == 0x80000000 && R0004 == 0xFFFFFFFF) || R0004 == 0x0); - set_Z(R1115); - set_S(R1115); - R1115 = quot; - R2731 = mod; -} - -# DIVH reg1, reg2 - rrrrr000010RRRRR -:divh R0004, R1115 is op0510=0x02 & R0004 & R1115 -{ - $(OV) = ((R1115 == 0x80000000 && R0004 == 0xFFFFFFFF) || R0004 == 0x0); - R1115 = R1115 / R0004; - set_Z(R1115); - set_S(R1115); -} - -# DIVH reg1, reg2, reg3 - rrrrr111111RRRRR|wwwww01010000000 -:divh R0004, R1115, R2731 is op0510=0x3F & R0004 & R1115; op1626=0x280 & R2731 -{ - local quot:4 = R1115 s/ sext(R0004:2); - local mod:4 = R1115 s% sext(R0004:2); - $(OV) = ((R1115 == 0x80000000 && R0004 == 0xFFFFFFFF) || R0004 == 0x0); - set_Z(R1115); - set_S(R1115); - R1115 = quot; - R2731 = mod; -} - -# DIVHU reg1, reg2, reg3 - rrrrr111111RRRRR|wwwww01010000010 -:divhu R0004, R1115, R2731 is op0510=0x3F & R0004 & R1115; op1626=0x282 & R2731 -{ - local quot:4 = R1115 / sext(R0004:2); - local mod:4 = R1115 % sext(R0004:2); - $(OV) = (R0004 == 0); - set_Z(R1115); - set_S(R1115); - R1115 = quot; - R2731 = mod; -} - -# DIVU reg1, reg2, reg3 - rrrrr111111RRRRR|wwwww01011000010 -:divu R0004, R1115, R2731 is op0510=0x3F & R0004 & R1115; op1626=0x2C2 & R2731 -{ - local quot:4 = R1115 / R0004; - local mod:4 = R1115 % R0004; - $(OV) = (R0004 == 0); - set_Z(R1115); - set_S(R1115); - R1115 = quot; - R2731 = mod; -} - - - -##################################################### -##### HighSpeedDivide ##### -##################################################### - - -# DIVQ reg1, reg2, reg3 - rrrrr111111RRRRR|wwwww01011111100 -:divq R0004, R1115, R2731 is op0510=0x3F & R0004 & R1115; op1626=0x2FC & R2731 -{ - local quot:4 = R1115 s/ R0004; - local mod:4 = R1115 s% R0004; - $(OV) = ((R1115 == 0x80000000 && R0004 == 0xFFFFFFFF) || R0004 == 0x0); - set_Z(R1115); - set_S(R1115); - R2731 = mod; - R1115 = quot; -} - -# DIVQU reg1, reg2, reg3 - rrrrr111111RRRRR|wwwww01011111110 -:divqu R0004, R1115, R2731 is op0510=0x3F & R0004 & R1115; op1626=0x2FE & R2731 -{ - local quot:4 = R1115 / R0004; - local mod:4 = R1115 % R0004; - $(OV) = (R0004 == 0); - set_Z(R1115); - set_S(R1115); - R2731 = mod; - R1115 = quot; -} diff --git a/pypcode/processors/V850/data/languages/Instructions/Float.sinc b/pypcode/processors/V850/data/languages/Instructions/Float.sinc deleted file mode 100644 index d708864..0000000 --- a/pypcode/processors/V850/data/languages/Instructions/Float.sinc +++ /dev/null @@ -1,498 +0,0 @@ -##################################################### -##### Float ##### -##################################################### - - -# ABSF.D reg2, reg3 - rrrr011111100000|wwww010001011000 -:absf.d R1115x2, R2731x2 is R1115x2 & op0510=0x3F & op0004=0b00000; R2731x2 & op2126=0b100010 & op1620=0b11000 -{ - R2731x2 = abs(R1115x2); -} - -# ABSF.S reg2, reg3 - rrrrr11111100000|wwwww10001001000 -:absf.s R1115, R2731 is R1115 & op0510=0x3F & op0004=0b00000; R2731 & op2126=0b100010 & op1620=0b01000 -{ - R2731 = abs(R1115); -} - -# ADDF.D reg1, reg2, reg3 - rrrr0111111RRRR0|wwww010001110000 -:addf.d R0004x2, R1115x2, R2731x2 is R1115x2 & op0510=0x3F & R0004x2 ; R2731x2 & op2126=0b100011 & op1620=0b10000 -{ - R2731x2 = R1115x2 f+ R0004x2; -} - -# ADDF.S reg1, reg2, reg3 - rrrrr111111RRRRR|wwwww10001100000 -:addf.s R0004, R1115, R2731 is R1115 & op0510=0x3F & R0004 ; R2731 & op2126=0b100011 & op1620=0b00000 -{ - R2731 = R1115 f+ R0004; -} - -# CEILF.DL reg2, reg3 - rrrr011111100010|wwww010001010100 -:ceilf.dl R1115x2, R2731x2 is R1115x2 & op0510=0x3F & op0004=0b00010; R2731x2 & op2126=0b100010 & op1620=0b10100 -{ - local var:8 = ceil(float2float(R1115x2)); - R2731x2 = trunc(var); -} - -# CEILF.DUL reg2, reg3 - rrrr011111110010|wwww010001010100 -:ceilf.dul R1115x2, R2731x2 is R1115x2 & op0510=0x3F & op0004=0b10010; R2731x2 & op2126=0b100010 & op1620=0b10100 -{ - local var:8 = ceil(float2float(R1115x2)); - R2731x2 = trunc(var); -} - -# CEILF.DUW reg2, reg3 - rrrrr11111110010|wwwww10001010000 -:ceilf.duw R1115x2, R2731 is R1115x2 & op0510=0x3F & op0004=0b10010; R2731 & op2126=0b100010 & op1620=0b10000 -{ - R2731 = trunc(ceil(R1115x2)); -} - -# CEILF.DW reg2, reg3 - rrrrr11111100010|wwwww10001010000 -:ceilf.dw R1115x2, R2731 is R1115x2 & op0510=0x3F & op0004=0b00010; R2731 & op2126=0b100010 & op1620=0b10000 -{ - R2731 = trunc(ceil(R1115x2)); -} - -# CEILF.SL reg2, reg3 - rrrrr11111100010|wwww010001000100 -:ceilf.sl R1115, R2731x2 is R1115 & op0510=0x3F & op0004=0b00010; R2731x2 & op2126=0b100010 & op1620=0b00100 -{ - local var:8 = ceil(float2float(R1115)); - R2731x2 = trunc(var); -} - -# CEILF.SUL reg2, reg3 - rrrrr11111110010|wwwww10001000100 -:ceilf.sul R1115, R2731x2 is R1115 & op0510=0x3F & op0004=0b10010; R2731x2 & op2126=0b100010 & op1620=0b00100 -{ - local var:8 = ceil(float2float(R1115)); - R2731x2 = trunc(var); -} - -# CEILF.SUW reg2, reg3 - rrrrr11111110010|wwwww10001000000 -:ceilf.sul R1115, R2731 is R1115 & op0510=0x3F & op0004=0b10010; R2731 & op2126=0b100010 & op1620=0b00000 -{ - R2731 = trunc(ceil(R1115)); -} - -# CEILF.SW reg2, reg3 - rrrrr11111100010|wwwww10001000000 -:ceilf.sw R1115, R2731 is R1115 & op0510=0x3F & op0004=0b00010; R2731 & op2126=0b100010 & op1620=0b00000 -{ - R2731 = trunc(ceil(R1115)); -} - -# CMOVF.D fcbit, reg1, reg2, reg3 - rrrr0111111RRRR0|wwww01000001fff0 -:cmovf.d fcbit1719, R1115x2, R0004x2, R2731x2 is R1115x2 & op0510=0x3F & R0004x2; R2731x2 & op2126=0b100000 & op2020=1 & fcbit1719 & op1616=0 -{ - #CC0 = Bit 24 - local bit = (FPSR >> (fcbit1719 + 24:1)) & 0x1; - either_or1(R2731x2, bit, R0004x2, R1115x2); -} - -# CMOVF.S fcbit, reg1, reg2, reg3 - rrrrr111111RRRRR|wwwww1000000fff0 -:cmovf.s fcbit1719, R1115, R0004, R2731 is R1115 & op0510=0x3F & R0004; R2731 & op2126=0b100000 & op2020=0 & fcbit1719 & op1616=0 -{ - local bit = (FPSR >> (fcbit1719 + 24:1)) & 0x1; - either_or1(R2731, bit, R0004, R1115); -} - -# CMPF.D fcond, reg2, reg1, fcbit - rrrr0111111RRRRR|0FFFF1000011fff0 -:cmpf.d fcond2730, R1115x2, R0004x2, fcbit1719 is R1115x2 & op0510=0x3F & R0004x2; op3131=0 & fcond2730 & op2126=0b100001 & op2020=1 & fcbit1719 & op1616=0 -{ - #0 = Unordered - #1 = Equal to - #2 = Less than - #3 = Exeption - #bits = ex le eq un - - local bit:4 = 0; - compare_float(bit, fcond2730:1, R0004x2, R1115x2); - - local pos:4 = bit << (fcbit1719 + 24); #find position of the calculated bit - local mask:4 = 1 << (fcbit1719 + 24); #create mask to clean old bit in FPSR register - FPSR = (FPSR & ~mask) | pos; #set the new bit at the right position -} - -# CMPF.S fcond, reg2, reg1, fcbit - rrrrr111111RRRRR|0FFFF1000010fff0 -:cmpf.s fcond2730, R1115, R0004, fcbit1719 is R1115 & op0510=0x3F & R0004; op3131=0 & fcond2730 & op2126=0b100001 & op2020=0 & fcbit1719 & op1616=0 -{ - local bit:4 = 0; - compare_float(bit, fcond2730:1, R0004, R1115); - - local pos:4 = bit << (fcbit1719 + 24); #find position of the calculated bit - local mask:4 = 1 << (fcbit1719 + 24); #create mask to clean old bit in FPSR register - FPSR = (FPSR & ~mask) | pos; #set the new bit at the right position -} - -# CVTF.DL reg2, reg3 - rrrr011111100100|wwww010001010100 -:cvtf.dl R1115x2, R2731x2 is R1115x2 & op0510=0x3F & op0004=0b00100; R2731x2 & op2126=0b100010 & op1620=0b10100 -{ - R2731x2 = int2float(R1115x2); -} - -# CVTF.DS reg2, reg3 - rrrr011111100011|wwww010001010010 -:cvtf.ds R1115x2, R2731 is R1115x2 & op0510=0x3F & op0004=0b00011; R2731 & op2126=0b100010 & op1620=0b10010 -{ - R2731 = float2float(R1115x2); -} - -# CVTF.DUL reg2, reg3 - rrrr011111110100|wwww010001010100 -:cvtf.dul R1115x2, R2731x2 is R1115x2 & op0510=0x3F & op0004=0b10100; R2731x2 & op2126=0b100010 & op1620=0b10100 -{ - R2731x2 = trunc(R1115x2); -} - -# CVTF.DUW reg2, reg3 - rrrrr11111110100|wwwww10001010000 -:cvtf.duw R1115x2, R2731 is R1115x2 & op0510=0x3F & op0004=0b10100; R2731 & op2126=0b100010 & op1620=0b10000 -{ - R2731 = trunc(R1115x2); -} - -# CVTF.DW reg2, reg3 - rrrrr11111100100|wwwww10001010000 -:cvtf.sw R1115x2, R2731 is R1115x2 & op0510=0x3F & op0004=0b00100; R2731 & op2126=0b100010 & op1620=0b10000 -{ - R2731 = trunc(R1115x2); -} - -# CVTF.LD reg2, reg3 - rrrr011111100001|wwww010001010010 -:cvtf.ls R1115x2, R2731x2 is R1115x2 & op0510=0x3F & op0004=0b00001; R2731x2 & op2126=0b100010 & op1620=0b10010 -{ - R2731x2 = int2float(R1115x2); -} - -# CVTF.LS reg2, reg3 - rrrr011111100001|wwwww10001000010 -:cvtf.ls R1115x2, R2731 is R1115x2 & op0510=0x3F & op0004=0b00001; R2731 & op2126=0b100010 & op1620=0b00010 -{ - R2731 = int2float(R1115x2); -} - -# CVTF.SD reg2, reg3 - rrrrr11111100010|wwww010001010010 -:cvtf.sd R1115, R2731x2 is R1115 & op0510=0x3F & op0004=0b00010; R2731x2 & op2126=0b100010 & op1620=0b10010 -{ - R2731x2 = float2float(R1115); -} - -# CVTF.SL reg2, reg3 - rrrrr11111100100|wwwww10001000100 -:cvtf.sl R1115, R2731x2 is R1115 & op0510=0x3F & op0004=0b00100; R2731x2 & op2126=0b100010 & op1620=0b00100 -{ - R2731x2 = trunc(R1115); -} - -# CVTF.SUL reg2, reg3 - rrrrr11111110100|wwwww10001000100 -:cvtf.sul R1115, R2731x2 is R1115 & op0510=0x3F & op0004=0b10100; R2731x2 & op2126=0b100010 & op1620=0b00100 -{ - R2731x2 = trunc(R1115); -} - -# CVTF.SUW reg2, reg3 - rrrrr11111110100|wwwww10001000000 -:cvtf.suw R1115, R2731 is R1115 & op0510=0x3F & op0004=0b10100; R2731 & op2126=0b100010 & op1620=0b00000 -{ - R2731 = trunc(R1115); -} - -# CVTF.SW reg2, reg3 - rrrrr11111100100|wwwww10001000000 -:cvtf.sw R1115, R2731 is R1115 & op0510=0x3F & op0004=0b00100; R2731 & op2126=0b100010 & op1620=0b00000 -{ - R2731 = trunc(R1115); -} - -# CVTF.ULD reg2, reg3 - rrrr011111100001|wwww010001010010 -:cvtf.uls R1115x2, R2731x2 is R1115x2 & op0510=0x3F & op0004=0b10001; R2731x2 & op2126=0b100010 & op1620=0b10010 -{ - R2731x2 = int2float(R1115x2); -} - -# CVTF.ULS reg2, reg3 - rrrr011111110001|wwwww10001000010 -:cvtf.uls R1115x2, R2731 is R1115x2 & op0510=0x3F & op0004=0b10001; R2731 & op2126=0b100010 & op1620=0b00010 -{ - R2731 = int2float(R1115x2); -} - -# CVTF.UWD reg2, reg3 - rrrrr11111110000|wwwww10001010010 -:cvtf.uwd R1115, R2731x2 is R1115 & op0510=0x3F & op0004=0b10000; R2731x2 & op2126=0b100010 & op1620=0b10010 -{ - R2731x2 = int2float(R1115); -} - -# CVTF.UWS reg2, reg3 - rrrrr11111110000|wwwww10001000010 -:cvtf.uws R1115, R2731 is R1115 & op0510=0x3F & op0004=0b10000; R2731 & op2126=0b100010 & op1620=0b00010 -{ - R2731 = int2float(R1115); -} - -# CVTF.WD reg2, reg3 - rrrrr11111100000|wwwww10001010010 -:cvtf.wd R1115, R2731x2 is R1115 & op0510=0x3F & op0004=0b00000; R2731x2 & op2126=0b100010 & op1620=0b10010 -{ - R2731x2 = int2float(R1115); -} - -# CVTF.WS reg2, reg3 - rrrrr11111100000|wwwww10001000010 -:cvtf.ws R1115, R2731 is R1115 & op0510=0x3F & op0004=0b00000; R2731 & op2126=0b100010 & op1620=0b00010 -{ - R2731 = int2float(R1115); -} - -# DIVF.D reg1, reg2, reg3 - rrrr0111111RRRR0|wwww010001111110 -:divf.s R0004x2, R1115x2, R2731x2 is R0004x2 & op0510=0x3F & R1115x2; R2731x2 & op2126=0b100011 & op1620=0b11110 -{ - R2731x2 = R1115x2 f/ R0004x2; -} - -# DIVF.S reg1, reg2, reg3 - rrrrr111111RRRRR|wwwww10001101110 -:divf.s R0004, R1115, R2731 is R0004 & op0510=0x3F & R1115; R2731 & op2126=0b100011 & op1620=0b01110 -{ - R2731 = R1115 f/ R0004; -} - -# FLOORF.DL reg2, reg3 - rrrr011111100011|wwww010001010100 -:floorf.dl R1115x2, R2731x2 is R1115x2 & op0510=0x3F & op0004=0b00011; R2731x2 & op2126=0b100010 & op1620=0b10100 -{ - local var:8 = floor(float2float(R1115x2)); - R2731x2 = trunc(var); -} - -# FLOORF.DUL reg2, reg3 - rrrr011111110011|wwww010001010100 -:floorf.dul R1115x2, R2731x2 is R1115x2 & op0510=0x3F & op0004=0b10011; R2731x2 & op2126=0b100010 & op1620=0b10100 -{ - local var:8 = floor(float2float(R1115x2)); - R2731x2 = trunc(var); -} - -# FLOORF.DUW reg2, reg3 - rrrrr11111110011|wwwww10001010000 -:floorf.duw R1115x2, R2731 is R1115x2 & op0510=0x3F & op0004=0b10011; R2731 & op2126=0b100010 & op1620=0b10000 -{ - R2731 = trunc(floor(R1115x2)); -} - -# FLOORF.DW reg2, reg3 - rrrrr11111100011|wwwww10001010000 -:floorf.dw R1115x2, R2731 is R1115x2 & op0510=0x3F & op0004=0b00011; R2731 & op2126=0b100010 & op1620=0b10000 -{ - R2731 = trunc(floor(R1115x2)); -} - -# FLOORF.SL reg2, reg3 - rrrrr11111100011|wwww010001000100 -:floorf.sl R1115, R2731x2 is R1115 & op0510=0x3F & op0004=0b00011; R2731x2 & op2126=0b100010 & op1620=0b00100 -{ - local var:8 = floor(float2float(R1115)); - R2731x2 = trunc(var); -} - -# FLOORF.SUL reg2, reg3 - rrrrr11111110011|wwwww10001000100 -:floorf.sul R1115, R2731x2 is R1115 & op0510=0x3F & op0004=0b10011; R2731x2 & op2126=0b100010 & op1620=0b00100 -{ - local var:8 = floor(float2float(R1115)); - R2731x2 = trunc(var); -} - -# FLOORF.SUW reg2, reg3 - rrrrr11111110011|wwwww10001000000 -:floorf.suw R1115, R2731 is R1115 & op0510=0x3F & op0004=0b10011; R2731 & op2126=0b100010 & op1620=0b00000 -{ - R2731 = trunc(floor(R1115)); -} - -# FLOORF.SW reg2, reg3 - rrrrr11111100011|wwwww10001000000 -:floorf.suw R1115, R2731 is R1115 & op0510=0x3F & op0004=0b00011; R2731 & op2126=0b100010 & op1620=0b00000 -{ - R2731 = trunc(floor(R1115)); -} - -# FMAF.S reg1, reg2, reg3 - rrrrr111111RRRRR|wwwww10011100000 -:fmaf.s R0004, R1115, R2731 is R0004 & op0510=0x3F & R1115; R2731 & op2126=0b100111 & op1620=0b00000 -{ - R2731 = (R1115 f* R0004) f+ R2731; -} - -# FMSF.S reg1, reg2, reg3 - rrrrr111111RRRRR|wwwww10011100010 -:fmsf.s R0004, R1115, R2731 is R0004 & op0510=0x3F & R1115; R2731 & op2126=0b100111 & op1620=0b00010 -{ - R2731 = (R1115 f* R0004) f- R2731; -} - -# FNMAF.S reg1, reg2, reg3 - rrrrr111111RRRRR|wwwww10011100100 -:fnmaf.s R0004, R1115, R2731 is R0004 & op0510=0x3F & R1115; R2731 & op2126=0b100111 & op1620=0b00100 -{ - R2731 = -1 f* ((R1115 f* R0004) f+ R2731); -} - -# FNMSF.S reg1, reg2, reg3 - rrrrr111111RRRRR|wwwww10011100110 -:fnmfs.s R0004, R1115, R2731 is R0004 & op0510=0x3F & R1115; R2731 & op2126=0b100111 & op1620=0b00110 -{ - R2731 = -1 f* ((R1115 f* R0004) f- R2731); -} - -# MADDF.S reg1, reg2, reg3, reg4 - rrrrr111111RRRRR|wwwww101W00WWWW0 -:maddf.s R0004, R1115, R2731, reg4 is R0004 & op0510=0x3F & R1115; R2731 & op2426=0b101 & op2122=0b00 & op1616=0 & reg4 -{ - reg4 = (R1115 f* R0004) f+ R2731; -} - -# MAXF.D reg1, reg2, reg3 - rrrr0111111RRRR0|wwww010001111000 -:maxf.d R0004x2, R1115x2, R2731x2 is R0004x2 & op0510=0x3F & R1115x2; R2731x2 & op2126=0b100011 & op1620=0b11000 -{ - local bigger:1 = R1115x2 f> R0004x2; - either_or(R2731x2, bigger, R1115x2, R0004x2); -} - -# MAXF.S reg1, reg2, reg3 - rrrrr111111RRRRR|wwwww10001101000 -:maxf.s R0004, R1115, R2731 is R0004 & op0510=0x3F & R1115; R2731 & op2126=0b100011 & op1620=0b01000 -{ - local bigger:1 = R1115 f> R0004; - either_or(R2731, bigger, R1115, R0004); -} - -# MINF.D reg1, reg2, reg3 - rrrr0111111RRRR0|wwww010001111010 -:minf.d R0004x2, R1115x2, R2731x2 is R0004x2 & op0510=0x3F & R1115x2; R2731x2 & op2126=0b100011 & op1620=0b11010 -{ - local bigger:1 = R1115x2 f< R0004x2; - either_or(R2731x2, bigger, R1115x2, R0004x2); -} - -# MINF.S reg1, reg2, reg3 - rrrr0111111RRRRR|wwwww10001101010 -:minf.s R0004, R1115, R2731 is R0004 & op0510=0x3F & R1115; R2731 & op2126=0b100011 & op1620=0b01010 -{ - local bigger:1 = R1115 f< R0004; - either_or(R2731, bigger, R1115, R0004); -} - -# MSUBF.S reg1, reg2, reg3, reg4 - rrrrr111111RRRRR|wwwww101W01WWWW0 -:msubf.s R0004, R1115, R2731, reg4 is R0004 & op0510=0x3F & R1115; R2731 & op2426=0b101 & op2122=0b01 & op1616=0 & reg4 -{ - reg4 = (R1115 f* R0004) f- R2731; -} - -# MULF.D reg1, reg2, reg3 - rrrr0111111RRRR0|wwww010001110100 -:mulf.d R0004x2, R1115x2, R2731x2 is R0004x2 & op0510=0x3F & R1115x2; R2731x2 & op2126=0b100011 & op1620=0b10100 -{ - R2731x2 = R1115x2 f* R0004x2; -} - -# MULF.S reg1, reg2, reg3 - rrrr0111111RRRRR|wwwww10001100100 -:mulf.s R0004, R1115, R2731 is R0004 & op0510=0x3F & R1115; R2731 & op2126=0b100011 & op1620=0b00100 -{ - R2731 = R1115 f* R0004; -} - -# NEGF.D reg2, reg3 - rrrr011111100001|wwww010001011000 -:negf.d R1115x2, R2731x2 is R1115x2 & op0510=0x3F & op0004=0b00001; R2731x2 & op2126=0b100010 & op1620=0b11000 -{ - R2731x2 = f- R1115x2; -} - -# NEGF.S reg2, reg3 - rrrrr11111100001|wwwww10001001000 -:negf.s R1115, R2731 is R1115 & op0510=0x3F & op0004=0b00001; R2731 & op2126=0b100010 & op1620=0b01000 -{ - R2731 = f- R1115; -} - -# NMADDF.S reg1, reg2, reg3, reg4 - rrrrr111111RRRRR|wwwww101W10WWWW0 -:nmaddf.s R0004, R1115, R2731, reg4 is R0004 & op0510=0x3F & R1115; R2731 & op2426=0b101 & op2122=0b10 & op1616=0 & reg4 -{ - reg4 = f-((R1115 f* R0004) f+ R2731); -} - -# NMSUBF.S reg1, reg2, reg3, reg4 - rrrrr111111RRRRR|wwwww101W11WWWW0 -:nmsubf.s R0004, R1115, R2731, reg4 is R0004 & op0510=0x3F & R1115; R2731 & op2426=0b101 & op2122=0b11 & op1616=0 & reg4 -{ - reg4 = f-((R1115 f* R0004) f- R2731); -} - -# RECIPF.D reg2, reg3 - rrrr011111100001|wwww010001011110 -:recipf.d R1115x2, R2731x2 is R1115x2 & op0510=0x3F & op0004=0b00001; R2731x2 & op2126=0b100010 & op1620=0b11110 -{ - R2731x2 = 1 f/ R1115x2; -} - -# RECIPF.S reg2, reg3 - rrrrr11111100001|wwwww10001001110 -:recipf.s R1115, R2731 is R1115 & op0510=0x3F & op0004=0b00001; R2731 & op2126=0b100010 & op1620=0b01110 -{ - R2731 = 1 f/ R1115; -} - -# RSQRTF.D reg2, reg3 - rrrr011111100010|wwwww10001011110 -:rsqrtf.d R1115x2, R2731x2 is R1115x2 & op0510=0x3F & op0004=0b00010; R2731x2 & op2126=0b100010 & op1620=0b11110 -{ - R2731x2 = 1 f/ sqrt(R1115x2); -} - -# RSQRTF.S reg2, reg3 - rrrrr11111100010|wwwww10001001110 -:rsqrtf.s R1115, R2731 is R1115 & op0510=0x3F & op0004=0b00010; R2731 & op2126=0b100010 & op1620=0b01110 -{ - R2731 = 1 f/ sqrt(R1115); -} - -# SQRTF.D reg2, reg3 - rrrr011111100000|wwww010001011110 -:sqrtf.d R1115x2, R2731x2 is R1115x2 & op0510=0x3F & op0004=0b00000; R2731x2 & op2126=0b100010 & op1620=0b11110 -{ - R2731x2 = sqrt(R1115x2); -} - -# SQRTF.S reg2, reg3 - rrrrr11111100000|wwwww10001001110 -:sqrtf.s R1115, R2731 is R1115 & op0510=0x3F & op0004=0b00000; R2731 & op2126=0b100010 & op1620=0b01110 -{ - R2731 = sqrt(R1115); -} - -# SUBF.D reg1, reg2, reg3 - rrrr0111111RRRR0|wwww010001110010 -:subf.d R0004x2, R1115x2, R2731x2 is R0004x2 & op0510=0x3F & R1115x2; R2731x2 & op2126=0b100011 & op1620=0b10010 -{ - R2731x2 = R1115x2 f- R0004x2; -} - -# SUBF.S reg1, reg2, reg3 - rrrrr111111RRRRR|wwwww10001100010 -:subf.s R0004, R1115, R2731 is R0004 & op0510=0x3F & R1115; R2731 & op2126=0b100011 & op1620=0b00010 -{ - R2731 = R1115 f- R0004; -} - -# TRFSR fcbit - 0000011111100000|000001000000fff0 -:trfsr fcbit1719 is op1115=0 & op0510=0x3F & op0004=0; op2731=0 & op2126=0b100000 & op2020=0 & fcbit1719 & op1616=0 -{ - local var:4 = FPSR & (1 << (fcbit1719 + 24)); - $(Z) = (var != 0); -} - -# TRNCF.DL reg2, reg3 - rrrr011111100001|wwww010001010100 -:trncf.dl R1115x2, R2731x2 is R1115x2 & op0510=0x3F & op0004=0b00001; R2731x2 & op2126=0b100010 & op1620=0b10100 -{ - R2731x2 = trunc(R1115x2); -} - -# TRNCF.DUL reg2, reg3 - rrrr011111110001|wwww010001010100 -:trncf.dul R1115x2, R2731x2 is R1115x2 & op0510=0x3F & op0004=0b10001; R2731x2 & op2126=0b100010 & op1620=0b10100 -{ - R2731x2 = trunc(R1115x2); -} - -# TRNCF.DUW reg2, reg3 - rrrrr11111110001|wwwww10001010000 -:trncf.duw R1115x2, R2731 is R1115x2 & op0510=0x3F & op0004=0b10001; R2731 & op2126=0b100010 & op1620=0b10000 -{ - R2731 = trunc(R1115x2); -} - -# TRNCF.DW reg2, reg3 - rrrrr11111100001|wwwww10001010000 -:trncf.dw R1115x2, R2731 is R1115x2 & op0510=0x3F & op0004=0b00001; R2731 & op2126=0b100010 & op1620=0b10000 -{ - R2731 = trunc(R1115x2); -} - -# TRNCF.SL reg2, reg3 - rrrrr11111100001|wwww010001000100 -:trncf.sl R1115, R2731x2 is R1115 & op0510=0x3F & op0004=0b00001; R2731x2 & op2126=0b100010 & op1620=0b00100 -{ - R2731x2 = trunc(R1115); -} - -# TRNCF.SUL reg2, reg3 - rrrrr11111110001|wwww010001000100 -:trncf.sul R1115, R2731x2 is R1115 & op0510=0x3F & op0004=0b10001; R2731x2 & op2126=0b100010 & op1620=0b00100 -{ - R2731x2 = trunc(R1115); -} - -# TRNCF.SUW reg2, reg3 - rrrrr11111110001|wwwww10001000000 -:trncf.suw R1115, R2731 is R1115 & op0510=0x3F & op0004=0b10001; R2731 & op2126=0b100010 & op1620=0b00000 -{ - R2731 = trunc(R1115); -} - -# TRNCF.SW reg2, reg3 - rrrrr11111100001|wwwww10001000000 -:trncf.sw R1115, R2731 is R1115 & op0510=0x3F & op0004=0b00001; R2731 & op2126=0b100010 & op1620=0b00000 -{ - R2731 = trunc(R1115); -} diff --git a/pypcode/processors/V850/data/languages/Instructions/Load_Store.sinc b/pypcode/processors/V850/data/languages/Instructions/Load_Store.sinc deleted file mode 100644 index 4ec2889..0000000 --- a/pypcode/processors/V850/data/languages/Instructions/Load_Store.sinc +++ /dev/null @@ -1,368 +0,0 @@ -# (1) Load instructions -# (2) Store instructions -# (9) Data manipulation instructions - - - -##################################################### -##### Load ##### -##################################################### - - -# LD.B disp16[reg1], reg2 - rrrrr111000RRRRR|dddddddddddddddd -:ld.b s1631[R0004], R1115 is op0510=0x38 & R0004 & R1115; s1631 -{ - local adr:4 = R0004 + s1631; - R1115 = sext(*:1 adr); -} - -# LD.B disp23[reg1], reg3 - rrrrr111100RRRRR|wwwwwddddddd0101|DDDDDDDDDDDDDDDD -:ld.b disp23[R0004], R2731 is op0515=0x3C & R0004; R2731 & op2026 & op1619=0x5; s3247 -[ disp23 = (s3247 << 7) | op2026; ] -{ - local adr:4 = R0004 + disp23; - R2731 = sext(*:1 adr); -} - -# LD.BU disp16[reg1], reg2 - rrrrr11110bRRRRR|ddddddddddddddd1 -:ld.bu disp16[R0004], R1115 is op0610=0x1E & R0004 & R1115 & op0505; op1616=0x1 & s1731 -[ disp16 = (s1731 << 1) | op0505; ] -{ - local adr:4 = R0004 + disp16; - R1115 = zext(*:1 adr); -} - -# LD.BU disp23[reg1], reg3 - 00000111101RRRRR|wwwwwddddddd0101|DDDDDDDDDDDDDDDD -:ld.bu disp23[R0004], R2731 is op0515=0x3D & R0004; R2731 & op2026 & op1619=0x5; s3247 -[ disp23 = (s3247 << 7) | op2026; ] -{ - local adr:4 = R0004 + disp23; - R2731 = zext(*:1 adr); -} - -# LD.H disp16[reg1], reg2 - rrrrr111001RRRRR|ddddddddddddddd0 -:ld.h s1631[R0004], R1115 is op0510=0x39 & R0004 & R1115; s1631 & op1616=0x0 -{ - local adr:4 = R0004 + s1631; - R1115 = sext(*:2 adr); -} - -# LD.H disp23[reg1], reg3 - 00000111100RRRRR|wwwwwdddddd00111|DDDDDDDDDDDDDDDD -:ld.h disp23[R0004], R2731 is op0515=0x3C & R0004; R2731 & op2126 & op1620=0x7; s3247 -[ disp23 = (s3247 << 7) | (op2126 << 1); ] -{ - local adr:4 = R0004 + disp23; - R2731 = sext(*:2 adr); -} - -# LD.HU disp16[reg1], reg2 - rrrrr111111RRRRR|ddddddddddddddd1 -:ld.hu disp16[R0004], R1115 is op0510=0x3F & R0004 & R1115; op1616=0x1 & s1731 -[ disp16 = s1731 << 1; ] -{ - local adr:4 = R0004 + disp16; - R1115 = zext(*:2 adr); -} - -# LD.HU disp23[reg1], reg3 - 00000111101RRRRR|wwwwwdddddd00111|DDDDDDDDDDDDDDDD -:ld.hu disp23[R0004], R2731 is op0515=0x3D & R0004; R2731 & op2026 & op1619=0x7; s3247 -[ disp23 = (s3247 << 7) | op2026; ] -{ - local adr:4 = R0004 + disp23; - R2731 = zext(*:2 adr); -} - -# LD.W disp16[reg1], reg2 - rrrrr111001RRRRR|ddddddddddddddd1 -:ld.w disp16[R0004], R1115 is op0510=0x39 & R0004 & R1115; s1731 & op1616=0x1 -[ disp16 = s1731 * 2; ] -{ - local adr:4 = R0004 + disp16; - R1115 = *:4 adr; -} - -# LD.W disp23[reg1], reg3 - 00000111100RRRRR|wwwwwdddddd01001|DDDDDDDDDDDDDDDD -:ld.w disp23[R0004], R2731 is op0515=0x03C & R0004; R2731 & op2126 & op1620=0x9; s3247 -[ disp23 = (s3247 << 7) | (op2126 << 1); ] -{ - local adr:4 = R0004 + disp23; - R2731 = *:4 adr; -} - -# SLD.B disp7[ep], reg2 - rrrrr0110ddddddd -:sld.b op0006[ep], R1115 is op0710=0x06 & op0006 & R1115 & ep -{ - local adr:4 = ep + op0006; - R1115 = sext(*:1 adr); -} - -# SLD.BU disp4[ep], reg2 - rrrrr0000110dddd -:sld.bu op0003[ep], R1115 is op0410=0x06 & R1115 & op0003 & ep -{ - local adr:4 = ep + op0003; - R1115 = zext(*:1 adr); -} - -# SLD.H disp8[ep], reg2 - rrrrr1000ddddddd -:sld.h disp8[ep], R1115 is op0710=0x08 & op0006 & R1115 & ep -[ disp8 = op0006 * 2; ] -{ - local adr:4 = ep + disp8; - R1115 = sext(*:2 adr); -} - -# SLD.HU disp5[ep], reg2 - rrrrr0000111dddd -:sld.hu disp5[ep], R1115 is op0410=0x07 & R1115 & op0003 & ep -[ disp5 = op0003 * 2; ] -{ - local adr:4 = ep + disp5; - R1115 = zext(*:2 adr); -} - -# SLD.W disp8[ep], reg2 - rrrrr1010dddddd0 -:sld.w disp8[ep], R1115 is op0710=0x0A & op0000=0x0 & op0106 & R1115 & ep -[ disp8 = op0106 * 4; ] -{ - local adr:4 = ep + disp8; - R1115 = *:4 adr; -} - - - -##################################################### -##### Store ##### -##################################################### - - -# SST.B reg2, disp7[ep] - rrrrr0111ddddddd -:sst.b R1115, op0006[ep] is op0710=0x07 & op0006 & R1115 & ep -{ - local adr:4 = ep + op0006; - local tmp:4 = R1115; - *:1 adr = tmp:1; -} - -# SST.H reg2, disp8[ep] - rrrrr1001ddddddd -:sst.h R1115, disp8[ep] is op0710=0x09 & op0006 & R1115 & ep -[ disp8 = op0006 * 2; ] -{ - local adr:4 = ep + disp8; - local tmp:4 = R1115; - *:2 adr = tmp:2; -} - -# SST.W reg2, disp8[ep] - rrrrr1010dddddd1 -:sst.w R1115, disp8[ep] is op0710=0x0A & op0000=0x1 & op0106 & R1115 & ep -[ disp8 = op0106 * 4; ] -{ - local adr:4 = ep + disp8; - local tmp:4 = R1115; - *:4 adr = tmp; -} - -# ST.B reg2, disp16[reg1] - rrrrr111010RRRRR|dddddddddddddddd -:st.b R1115, s1631[R0004] is op0510=0x3A & R0004 & R1115; s1631 -{ - local adr:4 = R0004 + s1631; - local tmp:4 = R1115; - *:1 adr = tmp:1; -} - -# ST.B reg3, disp23[reg1] - 00000111100RRRRR|dddddddddddddddd -:st.b R2731, disp23[R0004] is op0515=0x3C & R0004; R2731 & op2026 & op1619=0xD; s3247 -[ disp23 = (s3247 << 7) | op2026; ] -{ - local adr:4 = R0004 + disp23; - local tmp:4 = R2731; - *:1 adr = tmp:1; -} - -# ST.H reg2, disp16[reg1] - rrrrr111011RRRRR|ddddddddddddddd0 -:st.h R1115, s1631[R0004] is op0510=0x3B & R0004 & R1115; s1631 & op1616=0x0 -{ - local adr:4 = R0004 + s1631; - local tmp:4 = R1115; - *:2 adr = tmp:2; -} - -# ST.H reg3, disp23[reg1] - 00000111101RRRRR|wwwwwdddddd01101|DDDDDDDDDDDDDDDD -:st.h R2731, disp23[R0004] is op0515=0x3D & R0004; R2731 & op2126 & op1620=0xD; s3247 -[ disp23 = (s3247 << 7) | (op2126 << 1); ] -{ - local adr:4 = R0004 + disp23; - local tmp:4 = R2731; - *:2 adr = tmp:2; -} - -# ST.W reg2, disp16[reg1] - rrrrr111011RRRRR|ddddddddddddddd1 -:st.w R1115, disp16[R0004] is op0510=0x3B & R0004 & R1115; s1731 & op1616=0x1 -[ disp16 = s1731 * 2; ] -{ - local adr:4 = R0004 + disp16; - local tmp:4 = R1115; - *:4 adr = tmp; -} - -# ST.W reg3, disp23[reg1] - 00000111100RRRRR|wwwwwdddddd01111|DDDDDDDDDDDDDDDD -:st.w R2731, disp23[R0004] is op0515=0x3C & R0004; R2731 & op2126 & op1620=0xF; s3247 -[ disp23 = (s3247 << 7) | (op2126 << 1); ] -{ - local adr:4 = R0004 + disp23; - local tmp:4 = R2731; - *:2 adr = tmp:2; -} - - - -##################################################### -##### DataManipulation ##### -##################################################### - - -# BSH reg2, reg3 - rrrrr11111100000|wwwww01101000010 -:bsh R1115, R2731 is op0010=0x7E0 & R1115; op1626=0x342 & R2731 -{ - local x1 = R1115[0,8]; - local x2 = R1115[8,8]; - local x3 = R1115[16,8]; - local x4 = R1115[24,8]; - R2731 = zext(x3 << 24) | zext(x4 << 16) | zext(x1 << 8) | zext(x2); - set_S(R2731); - $(OV) = 0; - $(Z) = (x1 == 0) && (x2 == 0); - $(CY) = (x1 == 0) || (x2 == 0); -} - -# BSW reg2, reg3 - rrrrr11111100000|wwwww01101000000 -:bsw R1115, R2731 is op0010=0x7E0 & R1115; op1626=0x340 & R2731 -{ - local x1 = R1115[0,8]; - local x2 = R1115[8,8]; - local x3 = R1115[16,8]; - local x4 = R1115[24,8]; - R2731 = zext(x1 << 24) | zext(x2 << 16) | zext(x3 << 8) | zext(x4); - set_OV0_S_Z(R2731); - $(CY) = (x1 == 0) || (x2 == 0) || (x3 == 0) || (x4 == 0); -} - -# CMOV cccc, reg1, reg2, reg3 - rrrrr111111RRRRR|wwwww011001cccc0 -:cmov^c1720 R0004, R1115, R2731 is op0510=0x3F & R0004 & R1115; op2126=0x19 & op1616=0 & c1720 & R2731 -{ - local result:4 = zext(c1720); - R2731 = R0004 * zext(result != 0) + R1115 * zext(result == 0); -} - -# CMOV cccc, imm5, reg2, reg3 - rrrrr111111iiiii|wwwww011000cccc0 -:cmov^c1720 s0004, R1115, R2731 is op0510=0x3F & s0004 & R1115; op2126=0x18 & op1616=0 & c1720 & R2731 -{ - local result:4 = zext(c1720); - R2731 = s0004 * zext(result != 0) + R1115 * zext(result == 0); -} - -# HSH reg2, reg3 - rrrrr11111100000|wwwww01101000110 -:hsh R1115, R2731 is op0010=0x7E0 & R1115; op1626=0x346 & R2731 -{ - R2731 = R1115; - set_S(R2731); - $(OV) = 0; - $(Z) = (R2731:2 == 0); - $(CY) = $(Z); -} - -# HSW reg2, reg3 - rrrrr11111100000|wwwww01101000100 -:hsw R1115, R2731 is op0010=0x7E0 & R1115; op1626=0x344 & R2731 -{ - local x1 = R1115:2; - local x2 = R1115[16,16]; - R2731 = zext(x1 << 16) | zext(x2); - set_OV0_S_Z(R2731); - $(CY) = (x1 == 0) || (x2 == 0); -} - -# SAR reg1, reg2 - rrrrr111111RRRRR|0000000010100000 -:sar R0004, R1115 is op0510=0x3F & R0004 & R1115; op1631=0xA0 -{ - shift_right_arith(R1115, R1115, R0004); -} - -# SAR imm5, reg2 - rrrrr010101iiiii -:sar op0004, R1115 is op0510=0x15 & op0004 & R1115 -{ - shift_right_arith(R1115, R1115, op0004:5); -} - -# SAR reg1, reg2, reg3 - rrrrr111111RRRRR|wwwww00010100010 -:sar R0004, R1115, R2731 is op0510=0x3F & R0004 & R1115; op1626=0xA2 & R2731 -{ - shift_right_arith(R2731, R1115, R0004); -} - -# SASF cccc, reg2 - rrrrr1111110cccc|0000001000000000 -:sasf^c0003 R1115 is op0410=0x7E & c0003 & R1115; op1631=0x0200 -{ - R1115 = (R1115 << 1) | zext(c0003); -} - -# SETF cond, reg2 - rrrrr1111110cccc|0000000000000000 -:setf^c0003 R1115 is op0410=0x7E & c0003 & R1115; op1631=0x0 -{ - R1115 = zext(c0003); -} - -# SHL reg1, reg2 - rrrrr111111RRRRR|0000000011000000 -:shl R0004, R1115 is op0510=0x3F & R0004 & R1115; op1631=0xC0 -{ - shift_left_logic(R1115, R1115, R0004); -} - -# SHL imm5, reg2 - rrrrr010110iiiii -:shl op0004, R1115 is op0510=0x16 & op0004 & R1115 -{ - shift_left_logic(R1115, R1115, op0004:5); -} - -# SHL reg1, reg2, reg3 - rrrrr111111RRRRR|wwwww00011000010 -:shl R0004, R1115, R2731 is op0510=0x3F & R0004 & R1115; op1626=0xC2 & R2731 -{ - shift_left_logic(R2731, R1115, R0004); -} - -# SHR reg1, reg2 - rrrrr111111RRRRR|0000000010000000 -:shr R0004, R1115 is op0510=0x3F & R0004 & R1115; op1631=0x80 -{ - shift_right_logic(R1115, R1115, R0004); -} - -# SHR imm5, reg2 - rrrrr010100iiiii -:shr op0004, R1115 is op0510=0x14 & op0004 & R1115 -{ - shift_right_logic(R1115, R1115, op0004:5); -} - -# SHR reg1, reg2, reg3 - rrrrr111111RRRRR|wwwww00010000010 -:shr R0004, R1115, R2731 is op0510=0x3F & R0004 & R1115; op1626=0x82 & R2731 -{ - shift_right_logic(R2731, R1115, R0004); -} - -# SXB reg1 - 00000000101RRRRR -:sxb R0004 is op0515=0x05 & R0004 -{ - R0004 = sext(R0004:1); -} - -# SXH reg1 - 00000000111RRRRR -:sxh R0004 is op0515=0x07 & R0004 -{ - R0004 = sext(R0004:2); -} - -# ZXB reg1 - 00000000100RRRRR -:zxb R0004 is op0515=0x004 & R0004 -{ - R0004 = zext(R0004:1); -} - -# ZXH reg1 - 00000000110RRRRR -:zxh R0004 is op0515=0x006 & R0004 -{ - R0004 = zext(R0004:2); -} diff --git a/pypcode/processors/V850/data/languages/Instructions/Logic.sinc b/pypcode/processors/V850/data/languages/Instructions/Logic.sinc deleted file mode 100644 index e0a5112..0000000 --- a/pypcode/processors/V850/data/languages/Instructions/Logic.sinc +++ /dev/null @@ -1,167 +0,0 @@ -# (6) Conditional arithmetic instructions -# (8) Logical instructions -# (14) Bit manipulation instructions - - - -##################################################### -##### Conditional ##### -##################################################### - - -# ADF cccc, reg1, reg2, reg3 - rrrrr111111RRRRR|wwwww011101cccc0 -:adf^c1720 R0004, R1115, R2731 is op0510=0x3F & R0004 & R1115; op2126=0x1D & op1616=0 & c1720 & R2731 -{ - local cond = zext(c1720); - set_OV_pos2(R1115, R0004, cond); - set_CY_pos2(R1115, R0004, cond); - R2731 = R1115 + R0004 + cond; - set_S(R2731); - set_Z(R2731); -} - -# SBF cccc, reg1, reg2, reg3 - rrrrr111111RRRRR|wwwww011100cccc0 -:sbf^c1720 R0004, R1115, R2731 is op0510=0x3F & R0004 & R1115; op2126=0x1C & op1616=0 & c1720 & R2731 -{ - local cond = zext(c1720); - set_OV_neg2(R1115, R0004, cond); - set_CY_neg2(R1115, R0004, cond); - R2731 = R1115 - R0004 - cond; - set_S(R2731); - set_Z(R2731); -} - - - -##################################################### -##### Logic ##### -##################################################### - - -# AND reg1, reg2 - rrrrr001010RRRRR -:and R0004, R1115 is op0510=0x0A & R0004 & R1115 -{ - R1115 = R1115 & R0004; - set_OV0_S_Z(R1115); -} - -# ANDI imm16, reg1, reg2 - rrrrr110110RRRRR|iiiiiiiiiiiiiiii -:andi op1631, R0004, R1115 is op0510=0x36 & R1115 & R0004; op1631 -{ - R1115 = R0004 & op1631; - set_OV0_S_Z(R1115); -} - -# NOT reg1, reg2 - rrrrr000001RRRRR -:not R0004, R1115 is op0510=0x01 & R0004 & R1115 -{ - R1115 = ~R0004; - set_OV0_S_Z(R1115); -} - -# OR reg1, reg2 - rrrrr001000RRRRR -:or R0004, R1115 is op0510=0x08 & R0004 & R1115 -{ - R1115 = R1115 | R0004; - set_OV0_S_Z(R1115); -} - -# ORI imm16, reg1, reg2 - rrrrr110100RRRRR|iiiiiiiiiiiiiiii -:ori op1631, R0004, R1115 is op0510=0x34 & R1115 & R0004; op1631 -{ - R1115 = R0004 | op1631; - set_OV0_S_Z(R1115); -} - -# TST reg1, reg2 - rrrrr001011RRRRR -:tst R0004, R1115 is op0510=0x0B & R0004 & R1115 -{ - set_OV0_S_Z(R1115 & R0004); -} - -# XOR reg1, reg2 - rrrrr001001RRRRR -:xor R0004, R1115 is op0510=0x09 & R0004 & R1115 -{ - R1115 = R1115 ^ R0004; - set_OV0_S_Z(R1115); -} - -# XORI imm16, reg1, reg2 - rrrrr110101RRRRR|iiiiiiiiiiiiiiii -:xori op1631, R0004, R1115 is op0510=0x35 & R1115 & R0004; op1631 -{ - R1115 = R0004 ^ op1631; - set_OV0_S_Z(R1115); -} - - - -##################################################### -##### BitManipulation ##### -##################################################### - - -# CLR1 bit#3, disp16[reg1] - 10bbb111110RRRRR|dddddddddddddddd -:clr1 op1113, s1631[R0004] is op0510=0x3E & op1415=2 & op1113 & R0004; s1631 -{ - local adr:4 = R0004 + s1631; - local tkn = *:1 adr; - *:1 adr = tkn & ~(1 << op1113); - set_Z(tkn & (1 << op1113)); -} - -# CLR1 reg2, [reg1] - rrrrr111111RRRRR|0000000011100100 -:clr1 R1115, [R0004] is op0510=0x3F & R0004 & R1115; op1631=0xE4 -{ - local tkn = *:1 R0004; - *:1 R0004 = tkn & ~(1 << R1115); - set_Z(tkn & (1 << R1115)); -} - -# NOT1 bit#3, disp16[reg1] - 01bbb111110RRRRR|dddddddddddddddd -:not1 op1113, s1631[R0004] is op0510=0x3E & op1415=1 & op1113 & R0004; s1631 -{ - local adr:4 = R0004 + s1631; - local tkn = *:1 adr; - *:1 adr = tkn ^ (1 << op1113); - set_Z(tkn & (1 << op1113)); -} - -# NOT1 reg2, [reg1] - rrrrr111111RRRRR|0000000011100010 -:not1 R1115, [R0004] is op0510=0x3F & R0004 & R1115; op1631=0xE2 -{ - local tkn = *:1 R0004; - *:1 R0004 = tkn ^ (1 << R1115); - set_Z(tkn & (1 << R1115)); -} - -# SET1 bit#3, disp16[reg1] - 00bbb111110RRRRR|dddddddddddddddd -:set1 op1113, s1631[R0004] is op0510=0x3E & op1415=0 & op1113 & R0004; s1631 -{ - local adr:4 = R0004 + s1631; - local tkn = *:1 adr; - *:1 adr = tkn | (1 << op1113); - set_Z(tkn & (1 << op1113)); -} - -# SET1 reg2, [reg1] - rrrrr111111RRRRR|0000000011100000 -:set1 R1115, [R0004] is op0510=0x3F & R0004 & R1115; op1631=0xE0 -{ - local tkn = *:1 R0004; - *:1 R0004 = tkn | (1 << R1115); - set_Z(tkn & (1 << R1115)); -} - -# TST1 bit#3, disp16[reg1] - 11bbb111110RRRRR|dddddddddddddddd -:tst1 op1113, s1631[R0004] is op0510=0x3E & op1415=3 & op1113 & R0004; s1631 -{ - local adr:4 = R0004 + s1631; - local tkn = *:1 adr; - set_Z(tkn & (1 << op1113)); -} - -# TST1 reg2, [reg1] - rrrrr111111RRRRR|0000000011100110 -:tst1 R0004, [R1115] is op0510=0x3F & R0004 & R1115; op1631=0xE6 -{ - local tkn = *:1 R0004; - set_Z(tkn & (1 << R1115)); -} diff --git a/pypcode/processors/V850/data/languages/Instructions/Special.sinc b/pypcode/processors/V850/data/languages/Instructions/Special.sinc deleted file mode 100644 index f94250e..0000000 --- a/pypcode/processors/V850/data/languages/Instructions/Special.sinc +++ /dev/null @@ -1,372 +0,0 @@ -# (10) Bit search instructions -# (13) Branch instructions -# (15) Special instructions - - - -##################################################### -##### BitSearch ##### -##################################################### - - -# SCH0L reg2, reg3 - rrrrr11111100000|wwwww01101100100 -:sch0l R1115, R2731 is op0010=0x7E0 & R1115; op1626=0x364 & R2731 -{ - SearchLeft(R2731, R1115, 0); - $(CY) = (R1115 != 0xFFFFFFFF); # zero bit found - $(Z) = (R1115 == 0xFFFFFFFF); # zero bit not found -} - -# SCH0R reg2, reg3 - rrrrr11111100000|wwwww01101100000 -:sch0r R1115, R2731 is op0010=0x7E0 & R1115; op1626=0x360 & R2731 -{ - SearchRight(R2731, R1115, 0); - $(CY) = (R1115 != 0xFFFFFFFF); # zero bit found - $(Z) = (R1115 == 0xFFFFFFFF); # zero bit not found -} - -# SCH1L reg2, reg3 - rrrrr11111100000|wwwww01101100110 -:sch1l R1115, R2731 is op0010=0x7E0 & R1115; op1626=0x366 & R2731 -{ - SearchLeft(R2731, R1115, 1); - $(CY) = (R1115 != 0x0); # one bit found - $(Z) = (R1115 == 0x0); # one bit not found -} - -# SCH1R reg2, reg3 -:sch1r R1115, R2731 is op0010=0x7E0 & R1115; op1626=0x362 & R2731 -{ - SearchRight(R2731, R1115, 1); - $(CY) = (R1115 != 0x0); # one bit found - $(Z) = (R1115 == 0x0); # one bit not found -} - - - -##################################################### -##### Branch ##### -##################################################### - - -#Bcond adr9 - ddddd1011dddcccc -:b^c0003 adr9 is op0710=0xB & c0003 & adr9 -{ - if (c0003) - goto adr9; -} -:br adr9 is op0710=0xB & op0003=0x5 & adr9 -{ - goto adr9; -} - -# JARL disp22, reg2 - rrrrr11110dddddd|ddddddddddddddd0 -:jarl adr22, R1115 is (op0610=0x1E & R1115) ... & adr22 -{ - R1115 = inst_next; - call adr22; -} - -# JARL disp32, reg1 - 00000010111RRRRR|ddddddddddddddd0|DDDDDDDDDDDDDDDD -:jarl adr32, R0004 is op0515=0x017 & R0004; adr32 -{ - R0004 = inst_next; - call adr32; -} - -# JMP [reg1] - 00000000011RRRRR -:jmp [R0004] is op0515=0x03 & R0004 & op0004=0x1F -{ - return [R0004]; -} -:jmp [R0004] is op0515=0x03 & R0004 & op0004!=0x1F -{ - call [R0004]; -} - -# JMP disp32[reg1] - 00000110111RRRRR|ddddddddddddddd0|DDDDDDDDDDDDDDDD -:jmp adr32i[R0004] is op0515=0x037 & R0004; adr32i -{ - local adr = adr32i + R0004; - goto [adr]; -} - -# JR disp22 - 00000111110ddddd|ddddddddddddddd0 -:jr adr22 is op0615=0x1E ... & adr22 -{ - goto adr22; -} - -# JR disp32 - 0000001011100000|ddddddddddddddd0|DDDDDDDDDDDDDDDD -:jr adr32 is op0015=0x2E0; adr32 -{ - goto adr32; -} - - - -##################################################### -##### Special ##### -##################################################### - - -# CALLT imm6 - 0000001000iiiiii -:callt op0005 is op0615=0x8 & op0005 -{ - CTPC = inst_next; - CTPSW = PSW; - local adr:4 = CTBP + (op0005 << 1); - PC = CTBP + zext(*:2 adr); - call [PC]; -} - -# CAXI [reg1], reg2, reg3 - rrrrr111111RRRRR|wwwww00011101110 -:caxi [R0004], R1115, R2731 is op0510=0x3F & R0004 & R1115; op1626=0xEE & R2731 -{ - local tkn = *:4 (R0004 & ~(0x3)); - local result = R1115 - tkn; - *:4 R0004 = tkn * zext(result != 0) + R2731 * zext(result == 0); - R2731 = tkn; - set_general_flags_neg(R1115, tkn); -} - -# CTRET - 0000011111100000|0000000101000100 -:ctret is op0515=0x3F; op1631=0x144 -{ - PC = CTPC; - PSW = CTPSW; - return [PC]; -} - -# DI - 0000011111100000|0000000101100000 -define pcodeop __disable_irq; -:di is op0015=0x7E0; op1631=0x160 -{ - $(ID) = 1; - __disable_irq(); -} - -# DISPOSE imm5, list12 - 0000011001iiiiiL|LLLLLLLLLLL00000 -:dispose prep0105, DispList is prep0615=0x19 & prep1620=0x0 & prep0105 & DispList -{ - sp = sp + (prep0105 << 2); - build DispList; -} - -# DISPOSE imm5, list12, [reg1] - 0000011001iiiiiL|LLLLLLLLLLLRRRRR -:dispose prep0105, DispList, [prep1620] is prep0615=0x19 & prep1620 & prep0105 & DispList -{ - sp = sp + (prep0105 << 2); - build DispList; - PC = prep1620; - return [PC]; -} - -# EI - 1000011111100000|0000000101100000 -define pcodeop __enable_irq; -:ei is op0015=0x87E0; op1631=0x160 -{ - $(ID) = 0; - __enable_irq(); -} - -# EIRET - 0000011111100000|0000000101001000 -:eiret is op0515=0x3F; op1631=0x148 -{ - PC = EIPC; - PSW = EIPSW; - return [PC]; -} - -# FERET - 0000011111100000|0000000101001010 -:feret is op0515=0x3F; op1631=0x14A -{ - PC = FEPC; - PSW = FEPSW; - return [PC]; -} - -# FETRAP vector4 - 0vvvv00001000000 -:fetrap op1114 is op0010=0x40 & op1515=0 & op1114 & op1115!=0 -{ - FEPC = inst_next; - FEPSW = PSW; - $(FECC) = op1114 + 0x30; # exception code 0x30..0x3F - FEIC = op1114 + 0x30; # exception code 0x30..0x3F - $(EP) = 1; - $(ID) = 1; - $(NP) = 1; - PC = 0x30; - goto [PC]; -} - -# HALT - 0000011111100000|0000000100100000 -define pcodeop __halt; -:halt is op0015=0x7E0; op1631=0x120 -{ - __halt(); -} - -# LDSR reg2, regID - rrrrr111111RRRRR|0000000000100000 -:ldsr R0004, SR1115 is op0510=0x3F & SR1115 & R0004; op1631=0x20 -{ - SR1115 = R0004; -} - -# NOP - 0000000000000000 -:nop is op0015=0x0 -{ - PC = inst_next; -} - -# PREPARE list12, imm5 - 0000011110iiiiiL|LLLLLLLLLLL00001 -:prepare PrepList, prep0105 is prep0615=0x1E & prep0105 & prep1620=0x1 & PrepList -{ - build PrepList; - sp = sp - (prep0105 << 2); -} - -# PREPARE list12, imm5, sp - 0000011110iiiiiL|LLLLLLLLLLL00011 -:prepare PrepList, prep0105, sp is prep0615=0x1E & prep0105 & prep1620=0x3 & PrepList & sp -{ - build PrepList; - sp = sp - (prep0105 << 2); - ep = sp; -} - -# PREPARE list12, imm5, imm16 (low) - 0000011110iiiiiL|LLLLLLLLLLL01011|iiiiiiiiiiiiiiii -:prepare PrepList, prep0105, s3247 is prep0615=0x1E & prep0105 & prep1620=0xB & PrepList; s3247 -{ - build PrepList; - sp = sp - (prep0105 << 2); - ep = s3247; -} - -# PREPARE list12, imm5, imm16 (high) - 0000011110iiiiiL|LLLLLLLLLLL10011|iiiiiiiiiiiiiiii -:prepare PrepList, prep0105, s3247 is prep0615=0x1E & prep0105 & prep1620=0x13 & PrepList; s3247 -{ - build PrepList; - sp = sp - (prep0105 << 2); - ep = s3247 << 16; -} - -# PREPARE list12, imm5, imm32 - 0000011110iiiiiL|LLLLLLLLLLL11011|iiiiiiiiiiiiiiii|iiiiiiiiiiiiiiii -:prepare PrepList, prep0105, imm32 is prep0615=0x1E & prep0105 & prep1620=0x1B & PrepList; op3247; op4863 -[ imm32 = (op4863 << 16) | op3247; ] -{ - build PrepList; - sp = sp - (prep0105 << 2); - ep = imm32; -} - -# RETI - 0000011111100000|0000000101000000 -:reti is op0515=0x3F; op1631=0x140 -{ - if($(EP)!=1) - goto ; - - PC = EIPC; - PSW = EIPSW; - goto ; - - - if($(NP)!=1) - goto ; - - PC = FEPC; - PSW = FEPSW; - goto ; - - - PC = EIPC; - PSW = EIPSW; - - - return[PC]; -} - -# RIE - 0000000001000000 -:rie is op0015=0x40 -{ - FEPC = PC; - FEPSW = PSW; - $(NP) = 1; - $(EP) = 1; - $(ID) = 1; - PC = 0x30; - goto [PC]; -} - -# RIE imm5, imm4 - iiiii1111111IIII|0000000000000000 -:rie op1115, op0003 is op0410=0x7F & op1115 & op0003; op1631=0x0 -{ - FEPC = PC; - FEPSW = PSW; - $(NP) = 1; - $(EP) = 1; - $(ID) = 1; - PC = 0x30; - goto [PC]; -} - -# STSR regID, reg2 - rrrrr111111RRRRR|0000000001000000 -:stsr SR0004, R1115 is op0510=0x3F & R1115 & SR0004; op1631=0x40 -{ - R1115 = SR0004; -} - -# SWITCH reg1 - 00000000010RRRRR -:switch R0004 is op0515=0x2 & R0004 -{ - local adr:4 = inst_next + (R0004 << 1); - PC = inst_next + (sext(*:2 adr) << 1); - goto [PC]; -} - -# SYNCE - 0000000000011101 -define pcodeop __synchronize; -:synce is op0015=0x1D -{ - __synchronize(); -} - -# SYNCM - 0000000000011110 -:syncm is op0015=0x1E -{ - __synchronize(); -} - -# SYNCP - 0000000000011111 -:syncp is op0015=0x1F -{ - __synchronize(); -} - -# SYSCALL vector8 - 11010111111vvvvv|00VVV00101100000 -:syscall vector8 is op0515=0x6BF & op0004; op3031=0 & op2729 & op1626=0x160 -[ vector8 = (op2729 << 5) | op0004; ] -{ - EIPC = inst_next; - EIPSW = PSW; - EIIC = vector8 + 0x8000; # exception code 0x8000..0x80FF - $(EICC) = vector8 + 0x8000; # exception code 0x8000..0x80FF - $(EP) = 1; - $(ID) = 1; - local adr:4; - either_or(adr, (vector8 <= SCCFG), SCBP + (vector8 << 2), SCBP); - PC = SCBP + (*:4 adr); - call [PC]; -} - -# TRAP imm5 - 00000111111vvvvv|0000000100000000 -:trap op0004 is op0515=0x3F & op0004; op1631=0x100 -{ - local vector5:4 = op0004; - EIPC = inst_next; - EIPSW = PSW; - EIIC = vector5 + 0x40; # exception code 0x40..0x5F - $(EICC) = vector5:2 + 0x40; # exception code 0x40..0x5F - $(EP) = 1; - $(ID) = 1; - either_or(PC, (vector5 <= 15), 0x40, 0x50); - call [PC]; -} diff --git a/pypcode/processors/V850/data/languages/V850.dwarf b/pypcode/processors/V850/data/languages/V850.dwarf new file mode 100644 index 0000000..0fa85f4 --- /dev/null +++ b/pypcode/processors/V850/data/languages/V850.dwarf @@ -0,0 +1,14 @@ + + + + + + + + + + + + + + diff --git a/pypcode/processors/V850/data/languages/V850.ldefs b/pypcode/processors/V850/data/languages/V850.ldefs index d0e197a..954f23a 100644 --- a/pypcode/processors/V850/data/languages/V850.ldefs +++ b/pypcode/processors/V850/data/languages/V850.ldefs @@ -5,12 +5,29 @@ endian="little" size="32" variant="E1, E2, E2M" - version="1.0" + version="1.1" slafile="V850.sla" processorspec="V850.pspec" manualindexfile="../manuals/v850.idx" id="V850:LE:32:default"> Renesas V850 family + + + + + + Renesas V850 family + + + diff --git a/pypcode/processors/V850/data/languages/V850.opinion b/pypcode/processors/V850/data/languages/V850.opinion index 94a0279..fcc5016 100644 --- a/pypcode/processors/V850/data/languages/V850.opinion +++ b/pypcode/processors/V850/data/languages/V850.opinion @@ -1,6 +1,10 @@ - - + + + + \ No newline at end of file diff --git a/pypcode/processors/V850/data/languages/V850.pspec b/pypcode/processors/V850/data/languages/V850.pspec index 02fa940..a55655e 100644 --- a/pypcode/processors/V850/data/languages/V850.pspec +++ b/pypcode/processors/V850/data/languages/V850.pspec @@ -9,5 +9,10 @@ - + + + + + + diff --git a/pypcode/processors/V850/data/languages/V850.sinc b/pypcode/processors/V850/data/languages/V850.sinc new file mode 100644 index 0000000..a1a0fa7 --- /dev/null +++ b/pypcode/processors/V850/data/languages/V850.sinc @@ -0,0 +1,748 @@ +########################################### +##### ##### +##### V850 SLEIGH specification ##### +##### ##### +########################################### +define endian = little; +define alignment = 2; + +# Size & default are required +define space ram type=ram_space size=4 default; +define space register type=register_space size=4; +define space sysreg type=ram_space size=2; + +########################## +##### Register ##### +########################## + + +##### General-purpose registers (r0 to r31) ##### + +define register offset=0x0 size=0x4 +[ + r0 r1 r2 sp gp tp r6 r7 r8 r9 + r10 r11 r12 r13 r14 r15 r16 r17 r18 r19 + r20 r21 r22 r23 r24 r25 r26 r27 r28 r29 + ep lp +]; + + +@define UM "UMf"#"PSW[30,1]" +@define NP "NPf"#"PSW[7,1]" +@define EP "EPf"#"PSW[6,1]" +@define ID "IDf"#"PSW[5,1]" +@define SAT "SATf"#"PSW[4,1]" +@define CY "CYf"#"PSW[3,1]" +@define OV "OVf"#"PSW[2,1]" +@define S "Sf"#"PSW[1,1]" +@define Z "Zf"#"PSW[0,1]" + +define register offset=0x800 size=1 +[ + Zf Sf OVf CYf SATf IDf EPf NPf UMf +]; + +##### Control/Special registers ##### + +@ifndef V850E3 +define sysreg offset=0x0 size=0x4 +[ + EIPC EIPSW FEPC FEPSW ECR PSW FPSR FPEPC FPST FPCC + FPCFG SCCFG SCBP EIIC FEIC DBIC CTPC CTPSW DBPC DBPSW + CTBP DIR DBG22 DBG23 DBG24 DBG25 DBG26 DBG27 EIWR FEWR + DBWR BSEL +]; + + + +@else +# The v850e3 uses a selID selector for system registers +# selID 0 +define sysreg offset=0x0 size=0x4 +[ + EIPC EIPSW FEPC FEPSW _ PSW FPSR FPEPC + FPST FPCC FPCFG FPEC _ EIIC FEIC _ + CTPC CTPSW DBPC DBPSW CTBP _ _ _ + _ _ _ _ EIWR FEWR _ BSEL +]; + +# selID 1 +define sysreg offset=0x80 size=0x4 +[ + MCFG0 MCFG1 RBASE EBASE INTBP MCTL PID FPIPR + _ _ TCSEL SCCFG SCBP HVCCFG HVCBP VSEL + VMPRT0 VMPRT1 VMPRT2 _ _ _ _ VMSCCTL + VMSCTBL0 VMSCTBL1 VMSCTBL2 VMSCTBL3 _ _ _ _ +]; + +# selID 2 +define sysreg offset=0x100 size=0x4 +[ + HTCFG0 _ _ _ _ HTCTL MEA ASID + MEI ISPR PMR ICSR INTCFG _ _ _ + TLBSCH _ _ _ _ _ _ HTSCCTL + HTSCTBL0 HTSCTBL1 HTSCTBL2 HTSCTBL3 HTSCTBL4 HTSCTBL5 HTSCTBL6 HTSCTBL7 +]; + +# no selID 3 +# selID 4 +define sysreg offset=0x200 size=0x4 +[ + TLBIDX _ _ _ TELO0 TELO1 TEHI0 TEHI1 + _ _ TLBCFG _ BWERRL BWERRH BRERRL BRERRH + ICTAGL ICTAGH ICDATL ICDATH DCTAGL DCTAGH DCDATL DCDATH + ICCTRL DCCTRL ICCFG DCCFG ICERR DCERR _ _ +]; + +# selID 5 +define sysreg offset=0x280 size=0x4 +[ + MPM MPRC _ _ MPBRGN MPTRGN _ _ + MCA MCS MCC MCR _ _ _ _ + _ _ _ _ MPPRT0 MPPRT1 MPPRT2 _ + _ _ _ _ _ _ _ _ +]; + +# selID 6 +define sysreg offset=0x300 size=0x4 +[ + MPLA0 MPUA0 MPAT0 _ MPLA1 MPUA1 MPAT1 _ + MPLA2 MPUA2 MPAT2 _ MPLA3 MPUA3 MPAT3 _ + MPLA4 MPUA4 MPAT4 _ MPLA5 MPUA5 MPAT5 _ + MPLA6 MPUA6 MPAT6 _ MPLA7 MPUA7 MPAT7 _ +]; + +# selID 7 +define sysreg offset=0x380 size=0x4 +[ + MPLA8 MPUA8 MPAT8 _ MPLA9 MPUA9 MPAT9 _ + MPLA10 MPUA10 MPAT10 _ MPLA11 MPUA11 MPAT11 _ + MPLA12 MPUA12 MPAT12 _ MPLA13 MPUA13 MPAT13 _ + MPLA14 MPUA14 MPAT14 _ MPLA15 MPUA15 MPAT15 _ +]; + +@endif #ndef V850E3 + +define register offset=0x0 size=0x8 +[ + r0r1 r2sp r4r5 r6r7 r8r9 + r10r11 r12r13 r14r15 r16r17 r18r19 + r20r21 r22r23 r24r25 r26r27 r28r29 + eplp +]; + +define register offset=0x100 size=0x4 [ PC ]; # offset = 0x100(256) = PreOffset+PreRegister*Size = 128+32*4 = 256 + +define register offset=0x200 size=4 [ _sp ]; +define register offset=0x1000 size=4 contextreg; + +define context contextreg +regNum = (17,21) +counter=(27,31) +; + +######################## +##### Tokens ##### +######################## + + +define token instr(16) + op0000 = (0,0) + op0003 = (0,3) + op0004 = (0,4) + _R0004 = (0,4) + SR0004 = (0,4) + R0004x2 = (0,4) + s0004 = (0,4) signed + s0005 = (0,5) signed + op0005 = (0,5) + op0006 = (0,6) + op0010 = (0,10) + op0015 = (0,15) + op0106 = (1,6) + s0404 = (4,4) + op0406 = (4,6) + op0410 = (4,10) + op0505 = (5,5) + op0510 = (5,10) + op0515 = (5,15) + op0610 = (6,10) + op0615 = (6,15) + op0710 = (7,10) + op1112 = (11,12) + op1113 = (11,13) + op1114 = (11,14) + op1115 = (11,15) + _R1115 = (11,15) + SR1115 = (11,15) + R1115x2 = (11,15) + regId = (11,15) + s1115 = (11,15) signed + op1315 = (13,15) + op1415 = (14,15) + op1515 = (15,15) +; + +define token instr2(16) + op1616 = (0,0) + op1617 = (0,1) + op1619 = (0,3) + op1620 = (0,4) + R1620 = (0,4) + R1620x2 = (0,4) + op1626 = (0,10) + op1631 = (0,15) + s1631 = (0,15) signed + fcbit1719 = (1,3) + op1719 = (1,3) + op1720 = (1,4) + op0_1720 = (1,4) + op1_1720 = (1,4) + op1731 = (1,15) + s1731 = (1,15) signed + op1821 = (2,5) + s1821 = (2,5) signed + op2020 = (4,4) + op2026 = (4,10) + op2122 = (5,6) + op2126 = (5,10) + op2226 = (6,10) + op2323 = (7,7) + op2426 = (8,10) + op2727 = (11,11) + op2729 = (11,13) + fcond2730 = (11,14) + op2731 = (11,15) + op2831 = (12,15) + _R2731 = (11,15) + R2731x2 = (11,15) + selId = (11,15) + op3031 = (14,15) + op3131 = (15,15) +; + +define token instr3(16) + op3247 = (0,15) + s3247 = (0,15) signed +; + +define token instr4(16) + op4863 = (0,15) +; + +# used in PREPARE/DISPOSE instructions +define token prep(32) + prep00 = (0,0) + prep0105 = (1,5) + prep0615 = (6,15) + prep1620 = (16,20) + prep21 = (21,21) + prep22 = (22,22) + prep2223 = (22,31) + prep23 = (23,23) + prep24 = (24,24) + prep25 = (25,25) + prep26 = (26,26) + prep27 = (27,27) + prep28 = (28,28) + prep2831 = (28,31) + prep29 = (29,29) + prep2931 = (29,31) + prep3031 = (30,31) + prep2231 = (22,31) + prep2331 = (23,31) + prep2431 = (24,31) + prep2427 = (24,27) + prep2527 = (25,27) + prep2627 = (26,27) + prep30 = (30,30) + prep31 = (31,31) +; + +########################### +##### Variables ##### +########################### + + +attach variables [ _R0004 _R1115 _R2731 R1620 prep1620 ] +[ + r0 r1 r2 sp gp tp r6 r7 r8 r9 + r10 r11 r12 r13 r14 r15 r16 r17 r18 r19 + r20 r21 r22 r23 r24 r25 r26 r27 r28 r29 + ep lp +]; + +attach variables [ R0004x2 R1115x2 R1620x2 R2731x2 ] +[ + r0r1 _ r2sp _ r4r5 _ r6r7 _ r8r9 _ + r10r11 _ r12r13 _ r14r15 _ r16r17 _ r18r19 _ + r20r21 _ r22r23 _ r24r25 _ r26r27 _ r28r29 _ + eplp _ +]; + +@ifndef V850E3 +attach variables [ SR0004 SR1115 ] +[ + EIPC EIPSW FEPC FEPSW ECR PSW FPSR FPEPC FPST FPCC + FPCFG SCCFG SCBP EIIC FEIC DBIC CTPC CTPSW DBPC DBPSW + CTBP DIR DBG22 DBG23 DBG24 DBG25 DBG26 DBG27 EIWR FEWR + DBWR BSEL +]; +@else + +@endif #ndef V850E3 + +attach variables [op0_1720] [r0 r2 gp r6 r8 r10 r12 r14 r16 r18 r20 r22 r24 r26 r28 ep]; +attach variables [op1_1720] [r1 sp tp r7 r9 r11 r13 r15 r17 r19 r21 r23 r25 r27 r29 lp]; + + +attach names [fcond2730] +["f" "un" "eq" "ueq" "olt" "ult" "ole" "ule" "sd" "ngle" "seq" "ngl" "lt" "nge" "le" "ngt"]; + + + +@define EICC "ECR[0,16]" +@define FECC "ECR[16,16]" + +######################## +##### Macros ##### +######################## + + +##### CARRY-Flag ##### + +macro set_CY_pos(op1, op2) +{ + $(CY) = carry(op1, op2); +} + +macro set_CY_pos2(op1, op2, carryIn) +{ + local res = op1 + op2; + $(CY) = carry(op1, op2) || carry(res, carryIn); +} + +macro set_CY_neg(op1, op2) +{ + $(CY) = op1 < op2; +} + +macro set_CY_neg2(op1, op2, carryIn) +{ + local res = op2 + carryIn; + $(CY) = (op1 < res); +} + + + +##### Overflow-Flag ##### + +macro set_OV_pos(op1, op2) +{ + $(OV) = scarry(op1, op2); +} + +macro set_OV_pos2(op1, op2, carryIn) +{ + local result = op1 + op2; + $(OV) = scarry(op1, op2) ^^ scarry(result, carryIn); +} + +macro set_OV_neg(op1, op2) +{ + $(OV) = sborrow(op1,op2); +} + +macro set_OV_neg2(op1, op2, carryIn) +{ + local borrowIn = (1-carryIn); + local result = op1 - op2; + $(OV) = sborrow( op1, op2 ) ^^ sborrow( result, borrowIn ); +} + + + +##### S/Z-Flags ##### + +macro set_S(flag) +{ + $(S) = flag s< 0; +} + +macro set_Z(var) +{ + $(Z) = var == 0; +} + + + +##### General-Flag-Macros ##### + +macro set_general_flags_pos(var1, var2) +{ + local res = var1 + var2; + set_CY_pos(var1, var2); + set_OV_pos(var1, var2); + set_S(res); + set_Z(res); +} + +macro set_general_flags_neg(var1, var2) +{ + local res = var1 - var2; + $(CY) = var1 < var2; + $(OV) = sborrow(var1, var2); + $(S) = res s< 0; + $(Z) = res == 0; +} + +macro set_OV0_S_Z(var) +{ + $(OV) = 0; + set_S(var); + set_Z(var); +} + + + +##### General-Macros ##### + +# if condition is != 0 + +macro either_or(res, cond, trueVal, falseVal) { + res = zext(cond) * trueVal | zext(!cond) * falseVal; +} +# if condition is == 1 +macro either_or1(res, cond, trueVal, falseVal) +{ + res = (trueVal * zext(cond == 1)) + (falseVal * zext(cond != 1)); +} + +macro shift_right_logic(res, var, shift_) +{ + local shift = shift_ & 0x1f; + local mask = var & (zext(shift != 0) << (shift - 1)); + res = var >> shift; + set_OV0_S_Z(res); + $(CY) = ((mask != 0) && (shift != 0)); +} + +macro shift_right_arith(res, var, shift_) +{ + local shift = shift_ & 0x1f; + local mask = (zext(shift != 0) * var) & (1 << (shift - 1)); + res = var s>> shift; + set_OV0_S_Z(res); + $(CY) = ((mask != 0) && (shift != 0)); +} + +macro shift_left_logic(res, var, shift_) +{ + local shift = shift_ & 0x1f; + local mask = (zext(shift != 0) * var) & (1 << (32 - shift)); + res = var << shift; + set_OV0_S_Z(res); + $(CY) = ((mask != 0) && (shift != 0)); +} + + +macro bfmask (res, off, width) { + res = ((1 << width) - 1) << (32 - off - width); +} + +##### Stack Macros ##### + +macro push(reg) +{ + sp = sp - 4; + *:4 sp = reg; +} + +macro pop(reg) +{ + reg = *:4 sp; + sp = sp + 4; +} + +macro pushsp(reg) +{ + _sp = _sp - 4; + *:4 _sp = reg; +} + +macro popsp(reg) +{ + reg = *:4 _sp; + _sp = _sp + 4; +} + +##### Search Macros ##### + +macro SearchRight(res, var, char) +{ + local var_:4 = var; + res = 0; + + + if ((var_ & 0x1) == char) + goto ; + + var_ = var_ >> 1; + res = res + 1; + + if (res < 32) + goto ; + + res = 0; + + +} + +macro SearchLeft(res, var, char) +{ + local var_:4 = var; + res = 0; + + + if ((var_ >> 31) == char) + goto ; + + var_ = var_ << 1; + res = res + 1; + + if (res < 32) + goto ; + + res = 0; + + +} + +# macro saturate(var) +# { +# if (var s> 0x7FFFFFFF) +# goto ; + +# if (var s< -0x80000000) +# goto ; + +# goto ; + +# +# var = 0x7FFFFFFF; +# goto ; + +# +# var = -0x80000000; +# goto ; + +# +# } + + +##### Float-Macros ##### + +macro compare_float(res, fcond, reg1, reg2) +{ + local un = ((fcond & 1) == 1) & (nan(reg2) || nan(reg1)); + local eq = ((fcond & 2) == 2) & (!(nan(reg2) || nan(reg1))) & (reg2 f== reg1); + local le = ((fcond & 4) == 4) & (!(nan(reg2) || nan(reg1))) & (reg2 f< reg1); + #local ex = (fcond & 8) & ((nan(reg2) || nan(reg1))); + + res = zext(un|eq|le); +} + + +########################### +##### Conditions #### +########################### + + +c0003: "v" is op0003=0x0 { tmp:1 = ($(OV)) == 1; export tmp; } +c0003: "nv" is op0003=0x8 { tmp:1 = ($(OV)) == 0; export tmp; } +c0003: "c" is op0003=0x1 { tmp:1 = ($(CY)) == 1; export tmp; } +c0003: "nc" is op0003=0x9 { tmp:1 = ($(CY)) == 0; export tmp; } +c0003: "e" is op0003=0x2 { tmp:1 = ($(Z)) == 1; export tmp; } +c0003: "ne" is op0003=0xA { tmp:1 = ($(Z)) == 0; export tmp; } +c0003: "nh" is op0003=0x3 { tmp:1 = ($(CY) || $(Z)) == 1; export tmp; } +c0003: "h" is op0003=0xB { tmp:1 = ($(CY) || $(Z)) == 0; export tmp; } +c0003: "n" is op0003=0x4 { tmp:1 = ($(S)) == 1; export tmp; } +c0003: "p" is op0003=0xC { tmp:1 = ($(S)) == 0; export tmp; } +c0003: "t" is op0003=0x5 { tmp:1 = 1; export tmp; } +c0003: "sa" is op0003=0xD { tmp:1 = ($(SAT)) == 1; export tmp; } +c0003: "lt" is op0003=0x6 { tmp:1 = ($(S) ^^ $(OV)) == 1; export tmp; } +c0003: "ge" is op0003=0xE { tmp:1 = ($(S) ^^ $(OV)) == 0; export tmp; } +c0003: "le" is op0003=0x7 { tmp:1 = ($(S) ^^ $(OV) || $(Z)) == 1; export tmp; } +c0003: "gt" is op0003=0xF { tmp:1 = ($(S) ^^ $(OV) || $(Z)) == 0; export tmp; } + +c1720: "v" is op1720=0x0 { tmp:1 = ($(OV)) == 1; export tmp; } +c1720: "nv" is op1720=0x8 { tmp:1 = ($(OV)) == 0; export tmp; } +c1720: "c" is op1720=0x1 { tmp:1 = ($(CY)) == 1; export tmp; } +c1720: "nc" is op1720=0x9 { tmp:1 = ($(CY)) == 0; export tmp; } +c1720: "e" is op1720=0x2 { tmp:1 = ($(Z)) == 1; export tmp; } +c1720: "ne" is op1720=0xA { tmp:1 = ($(Z)) == 0; export tmp; } +c1720: "nh" is op1720=0x3 { tmp:1 = ($(CY) || $(Z)) == 1; export tmp; } +c1720: "h" is op1720=0xB { tmp:1 = ($(CY) || $(Z)) == 0; export tmp; } +c1720: "n" is op1720=0x4 { tmp:1 = ($(S)) == 1; export tmp; } +c1720: "p" is op1720=0xC { tmp:1 = ($(S)) == 0; export tmp; } +c1720: "t" is op1720=0x5 { tmp:1 = 1; export tmp; } +c1720: "sa" is op1720=0xD { tmp:1 = ($(SAT)) == 1; export tmp; } +c1720: "lt" is op1720=0x6 { tmp:1 = ($(S) ^^ $(OV)) == 1; export tmp; } +c1720: "ge" is op1720=0xE { tmp:1 = ($(S) ^^ $(OV)) == 0; export tmp; } +c1720: "le" is op1720=0x7 { tmp:1 = ($(S) ^^ $(OV) || $(Z)) == 1; export tmp; } +c1720: "gt" is op1720=0xF { tmp:1 = ($(S) ^^ $(OV) || $(Z)) == 0; export tmp; } + +################################## +##### Sub-Constructors ##### +################################## + + +# read r0 always return zero +R0004: _R0004 is _R0004 & _R0004=0 { local x:4=0; export x; } +R0004: _R0004 is _R0004 { export _R0004; } + +R1115: _R1115 is _R1115 & _R1115=0 { local x:4=0; export x; } +R1115: _R1115 is _R1115 { export _R1115; } + +R2731: _R2731 is _R2731 & _R2731=0 { local x:4=0; export x; } +R2731: _R2731 is _R2731 { export _R2731; } + + +adr9: res is op0406 & s1115 +[ res = ((s1115 << 4) | (op0406 << 1)) + inst_start; ] +{ + export *:4 res; +} +adr17: res is s0404; s1731 +[ res = ((s0404 << 16) | (s1731 << 1)) + inst_start; ] +{ + export *:4 res; +} +adr22: res is s0005; op1631 & op1616=0 +[ res = ((s0005 << 16) | op1631) + inst_start; ] +{ + export *:4 res; +} + +adr22off4: res is s0005; op1631 & op1616=0 +[ res = ((s0005 << 16) | op1631) + inst_start + 4; ] +{ + export *:4 res; +} + +adr32: res is op1631 & op1616=0; op3247 +[ res = ((op3247 << 16) | op1631) + inst_start; ] +{ + export *:4 res; +} + +adr32i: res is op1631 & op1616=0; op3247 +[ res = ((op3247 << 16) | op1631); ] +{ + export *[const]:4 res; +} + +reg4: op0_1720 is op2323=0 & op0_1720 { export op0_1720; } +reg4: op1_1720 is op2323=1 & op1_1720 { export op1_1720; } + + + +##### Prep/Disp Loop ##### + +PrepList20: r20 is prep27=1 & r20 { push(r20); } +PrepList20: is prep27=0 { } + +PrepList21: r21 is prep26=1 & prep27=0 & r21 { push(r21); } +PrepList21: PrepList20,r21 is prep26=1 & PrepList20 & r21 { push(r21); } +PrepList21: PrepList20 is prep26=0 & PrepList20 { } + +PrepList22: r22 is prep25=1 & prep2627=0 & r22 { push(r22); } +PrepList22: PrepList21,r22 is prep25=1 & PrepList21 & r22 { push(r22); } +PrepList22: PrepList21 is prep25=0 & PrepList21 { } + +PrepList23: r23 is prep24=1 & prep2527=0 & r23 { push(r23); } +PrepList23: PrepList22,r23 is prep24=1 & PrepList22 & r23 { push(r23); } +PrepList23: PrepList22 is prep24=0 & PrepList22 { } + +PrepList24: r24 is prep31=1 & prep2427=0 & r24 { push(r24); } +PrepList24: PrepList23,r24 is prep31=1 & PrepList23 & r24 { push(r24); } +PrepList24: PrepList23 is prep31=0 & PrepList23 { } + +PrepList25: r25 is prep30=1 & prep2427=0 & prep31=0 & r25 { push(r25); } +PrepList25: PrepList24,r25 is prep30=1 & PrepList24 & r25 { push(r25); } +PrepList25: PrepList24 is prep30=0 & PrepList24 { } + +PrepList26: r26 is prep29=1 & prep2427=0 & prep3031=0 & r26 { push(r26); } +PrepList26: PrepList25,r26 is prep29=1 & PrepList25 & r26 { push(r26); } +PrepList26: PrepList25 is prep29=0 & PrepList25 { } + +PrepList27: r27 is prep28=1 & prep2427=0 & prep2931=0 & r27 { push(r27); } +PrepList27: PrepList26,r27 is prep28=1 & PrepList26 & r27 { push(r27); } +PrepList27: PrepList26 is prep28=0 & PrepList26 { } + +PrepList28: r28 is prep23=1 & prep2431=0 & r28 { push(r28); } +PrepList28: PrepList27,r28 is prep23=1 & PrepList27 & r28 { push(r28); } +PrepList28: PrepList27 is prep23=0 & PrepList27 { } + +PrepList29: r29 is prep22=1 & prep2431=0 & prep23=0 & r29 { push(r29); } +PrepList29: PrepList28,r29 is prep22=1 & PrepList28 & r29 { push(r29); } +PrepList29: PrepList28 is prep22=0 & PrepList28 { } + +PrepList30: ep is prep00=1 & prep2431=0 & prep2223=0 & ep { push(ep); } +PrepList30: PrepList29,ep is prep00=1 & PrepList29 & ep { push(ep); } +PrepList30: PrepList29 is prep00=0 & PrepList29 { } + +PrepList: { lp } is prep21=1 & prep2431=0 & prep2223=0 & prep00=0 & lp { push(lp); } +PrepList: { PrepList30,lp } is prep21=1 & PrepList30 & lp { push(lp); } +PrepList: { PrepList30 } is prep21=0 & PrepList30 { } + + + +DispList31: ,lp is prep21=1 & lp { pop(lp); } +DispList31: lp is prep21=1 & prep00=0 & prep2231=0 & lp { pop(lp); } +DispList31: is prep21=0 { } + +DispList30: ep^DispList31 is DispList31 & prep00=1 & ep { pop(ep); } +DispList30: ,ep^DispList31 is DispList31 & prep00=1 & prep2231=0 & ep { pop(ep); } +DispList30: DispList31 is DispList31 & prep00=0 { } + +DispList29: ,r29^DispList30 is DispList30 & prep22=1 & r29 { pop(r29); } +DispList29: r29^DispList30 is DispList30 & prep22=1 & prep2331=0 & r29 { pop(r29); } +DispList29: DispList30 is DispList30 & prep22=0 { } + +DispList28: ,r28^DispList29 is DispList29 & prep23=1 & r28 { pop(r28); } +DispList28: r28^DispList29 is DispList29 & prep23=1 & prep2831=0 & prep2427=0 & r28 { pop(r28); } +DispList28: DispList29 is DispList29 & prep23=0 { } + +DispList27: ,r27^DispList28 is DispList28 & prep28=1 & r27 { pop(r27); } +DispList27: r27^DispList28 is DispList28 & prep28=1 & prep2931=0 & prep2427=0 & r27 { pop(r27); } +DispList27: DispList28 is DispList28 & prep28=0 { } + +DispList26: ,r26^DispList27 is DispList27 & prep29=1 & r26 { pop(r26); } +DispList26: r26^DispList27 is DispList27 & prep29=1 & prep3031=0 & prep2427=0 & r26 { pop(r26); } +DispList26: DispList27 is DispList27 & prep29=0 { } + +DispList25: ,r25^DispList26 is DispList26 & prep30=1 & r25 { pop(r25); } +DispList25: r25^DispList26 is DispList26 & prep30=1 & prep31=0 & prep2427=0 & r25 { pop(r25); } +DispList25: DispList26 is DispList26 & prep30=0 { } + +DispList24: ,r24^DispList25 is DispList25 & prep31=1 & r24 { pop(r24); } +DispList24: r24^DispList25 is DispList25 & prep31=1 & prep2427=0 & r24 { pop(r24); } +DispList24: DispList25 is DispList25 & prep31=0 { } + +DispList23: ,r23^DispList24 is DispList24 & prep24=1 & r23 { pop(r23); } +DispList23: r23^DispList24 is DispList24 & prep24=1 & prep2527=0 & r23 { pop(r23); } +DispList23: DispList24 is DispList24 & prep24=0 { } + +DispList22: ,r22^DispList23 is DispList23 & prep25=1 & r22 { pop(r22); } +DispList22: r22^DispList23 is DispList23 & prep25=1 & prep2627=0 & r22 { pop(r22); } +DispList22: DispList23 is DispList23 & prep25=0 { } + +DispList21: ,r21^DispList22 is DispList22 & prep26=1 & r21 { pop(r21); } +DispList21: r21^DispList22 is DispList22 & prep26=1 & prep27=0 & r21 { pop(r21); } +DispList21: DispList22 is DispList22 & prep26=0 { } + +DispList: { r20^DispList21 } is DispList21 & prep27=1 & r20 { pop(r20); } +DispList: { DispList21 } is DispList21 & prep27=0 { } + + diff --git a/pypcode/processors/V850/data/languages/V850.slaspec b/pypcode/processors/V850/data/languages/V850.slaspec index 633e0e3..7bc060d 100644 --- a/pypcode/processors/V850/data/languages/V850.slaspec +++ b/pypcode/processors/V850/data/languages/V850.slaspec @@ -1,37 +1,16 @@ -##################################################### -##### ##### -##### V850E2M SLEIGH specification ##### -##### ##### -##################################################### +################################################ +##### ##### +##### V850E2M SLEIGH specification ##### +##### ##### +################################################ -define endian = little; -define alignment = 2; +@include "V850.sinc" -# Size & default are required -define space ram type=ram_space size=4 default; -define space register type=register_space size=4; +################################ +##### Instructions ##### +################################ -##################################################### -##### Helpers ##### -##################################################### +@include "V850_instructions.sinc" -@include "./Helpers/Register.sinc" -@include "./Helpers/Tokens.sinc" -@include "./Helpers/Variables.sinc" -@include "./Helpers/Conditions.sinc" -@include "./Helpers/Macros.sinc" -@include "./Helpers/Extras.sinc" - - - -##################################################### -##### Instructions ##### -##################################################### - -@include "./Instructions/Arithmetic.sinc" -@include "./Instructions/Float.sinc" -@include "./Instructions/Load_Store.sinc" -@include "./Instructions/Logic.sinc" -@include "./Instructions/Special.sinc" diff --git a/pypcode/processors/V850/data/languages/V850_instructions.sinc b/pypcode/processors/V850/data/languages/V850_instructions.sinc new file mode 100644 index 0000000..f1d531b --- /dev/null +++ b/pypcode/processors/V850/data/languages/V850_instructions.sinc @@ -0,0 +1,1764 @@ + +##################################################### +##### Multiply ##### +##################################################### + + +# MUL reg1, reg2, reg3 - rrrrr111111RRRRR|wwwww01000100000 +:mul R0004, R1115, R2731 is op0510=0x3F & R0004 & R1115; op1626=0x220 & R2731 +{ + local res:8 = sext(R1115) * sext(R0004); + R1115 = res:4; + R2731 = res[32,32]; +} + +# MUL imm9, reg2, reg3 - rrrrr111111iiiii|wwwww01001IIII00 +:mul imm9, R1115, R2731 is op0510=0x3F & op0004 & R1115; op2226=0x9 & op1617=0x0 & s1821 & R2731 +[ imm9 = (s1821 << 5) | op0004; ] +{ + local res:8 = sext(R1115) * imm9; + R1115 = res:4; + R2731 = res[32,32]; +} + +# MULH reg1, reg2 - rrrrr000111RRRRR +:mulh R0004, R1115 is op0510=0x07 & R0004 & R1115 & op1115!=0 +{ + R1115 = sext(R1115:2) * sext(R0004:2); +} + +# MULH imm5, reg2 - rrrrr010111iiiii +:mulh s0004, R1115 is op0510=0x17 & s0004 & R1115 +{ + R1115 = sext(R1115:2) * s0004; +} + +# MULHI imm16, reg1, reg2 - rrrrr110111RRRRR|iiiiiiiiiiiiiiii +:mulhi s1631, R0004, R1115 is op0510=0x37 & R1115 & R0004; s1631 +{ + R1115 = R0004 * s1631; +} + +# MULU reg1, reg2, reg3 - rrrrr111111RRRRR|wwwww01000100010 +:mulu R0004, R1115, R2731 is op0510=0x3F & R0004 & R1115; op1626=0x222 & R2731 +{ + local res:8 = zext(R1115) * zext(R0004); + R1115 = res:4; + R2731 = res[32,32]; +} + +# MULU imm9, reg2, reg3 - rrrrr111111iiiii|wwwww01001IIII10 +:mulu imm9, R1115, R2731 is op0510=0x3F & op0004 & R1115; op2226=0x9 & op1617=0x2 & op1821 & R2731 +[ imm9 = (op1821 << 5) | op0004; ] +{ + local res:8 = zext(R1115) * imm9; + R1115 = res:4; + R2731 = res[32,32]; +} + + +##################################################### +##### MultiplyAccumulate ##### +##################################################### + + +# MAC reg1, reg2, reg3, reg4 - rrrrr111111RRRRR wwww0011110mmmm0 +:mac R0004, R1115, R2731x2, R1620x2 is op0510=0x3F & R0004 & R1115; op2126=0x1E & op1616=0 & R1620x2 & R2731x2 +{ + R1620x2 = sext(R1115) * sext(R0004) + R2731x2; +} + +# MACU reg1, reg2, reg3, reg4 - rrrrr111111RRRRR|wwww0011111mmmm0 +:macu R0004, R1115, R2731x2, R1620x2 is op0510=0x3F & R0004 & R1115; op2126=0x1F & op1616=0 & R1620x2 & R2731x2 +{ + R1620x2 = zext(R1115) * zext(R0004) + R2731x2; +} + + +##################################################### +##### Arithmetic ##### +##################################################### + + +# ADD reg1, reg2 - rrrrr001110RRRRR +:add R0004, R1115 is op0510=0x0E & R0004 & R1115 +{ + set_general_flags_pos(R0004, R1115); + R1115 = R1115 + R0004; +} + +# ADD imm5, reg2 - rrrrr010010iiiii +:add s0004, R1115 is op0510=0x12 & s0004 & R1115 +{ + set_general_flags_pos(s0004, R1115); + R1115 = R1115 + s0004; +} + +# ADDI imm16, reg1, reg2 - rrrrr110000RRRRR|iiiiiiiiiiiiiiii +:addi s1631, R0004, R1115 is op0510=0x30 & R1115 & R0004; s1631 +{ + set_general_flags_pos(R0004, s1631); + R1115 = R0004 + s1631; +} + +# CMP reg1, reg2 - rrrrr001111RRRRR +:cmp R0004, R1115 is op0510=0x0F & R0004 & R1115 +{ + set_general_flags_neg(R1115, R0004); +} + +# CMP imm5, reg2 - rrrrr010011iiiii +:cmp s0004, R1115 is op0510=0x13 & s0004 & R1115 +{ + set_general_flags_neg(R1115, s0004); +} + +# MOV reg1, reg2 - rrrrr000000RRRRR +:mov R0004, R1115 is op0510=0x00 & R0004 & R1115 +{ + R1115 = R0004; +} + +# MOV imm5, reg2 - rrrrr010000iiiii +:mov s0004, R1115 is op0510=0x10 & s0004 & R1115 & op1115!=0 +{ + R1115 = s0004; +} + +# MOV imm32, reg1 - 00000110001RRRRR|iiiiiiiiiiiiiiii|IIIIIIIIIIIIIIII +:mov imm32, R0004 is op0515=0x031 & R0004; op1631; op3247 +[ imm32 = (op3247 << 16) | op1631; ] +{ + R0004 = imm32; +} + +# MOVEA imm16, reg1, reg2 - rrrrr110001RRRRR|iiiiiiiiiiiiiiii +:movea s1631, R0004, R1115 is op0510=0x31 & op1115!=0 & R0004 & R1115; s1631 +{ + R1115 = R0004 + s1631; +} + +# MOVHI imm16, reg1, reg2 - rrrrr110010RRRRR|iiiiiiiiiiiiiiii +:movhi s1631, R0004, R1115 is op0510=0x32 & op1115!=0 & R0004 & R1115; s1631 +{ + R1115 = R0004 + (s1631 << 16); +} + +# SUB reg1, reg2 - rrrrr001101RRRRR +:sub R0004, R1115 is op0510=0x0D & R0004 & R1115 +{ + set_general_flags_neg(R1115, R0004); + R1115 = R1115 - R0004; +} + +# SUBR reg1, reg2 - rrrrr001100RRRRR +:subr R0004, R1115 is op0510=0x0C & R0004 & R1115 +{ + set_general_flags_neg(R0004, R1115); + R1115 = R0004 - R1115; +} + + +##################################################### +##### Saturated ##### +##################################################### + + +define pcodeop __saturate; + +# SATADD reg1, reg2 - rrrrr000110RRRRR +:satadd R0004, R1115 is op0510=0x06 & R0004 & R1115 & op1115!=0 +{ + set_CY_pos(R1115, R0004); + set_OV_pos(R1115, R0004); + $(SAT) = $(SAT) || $(OV); + + R1115 = R1115 + R0004; + R1115 = __saturate(R1115); + + set_S(R1115); + set_Z(R1115); +} + +#SATADD imm5, reg2 - rrrrr010001iiiii +:satadd s0004, R1115 is op0510=0x11 & s0004 & R1115 & op1115!=0 +{ + set_CY_pos(R1115, s0004); + set_OV_pos(R1115, s0004); + $(SAT) = $(SAT) || $(OV); + + R1115 = R1115 + s0004; + R1115 = __saturate(R1115); + + set_S(R1115); + set_Z(R1115); +} + +# SATADD reg1, reg2, reg3 - rrrrr111111RRRRR|wwwww01110111010 +:satadd R0004, R1115, R2731 is op0510=0x3F & R0004 & R1115; op1626=0x3BA & R2731 +{ + set_CY_pos(R1115, R0004); + set_OV_pos(R1115, R0004); + $(SAT) = $(SAT) || $(OV); + + R2731 = R1115 + R0004; + R2731 = __saturate(R2731); + + set_S(R2731); + set_Z(R2731); +} + +# SATSUB reg1, reg2 - rrrrr000101RRRRR +:satsub R0004, R1115 is op0510=0x05 & R0004 & R1115 & op1115!=0 +{ + + $(CY) = R1115 < R0004; + $(OV) = sborrow(R1115, R0004); + $(SAT) = $(SAT) || $(OV); + + R1115 = R1115 - R0004; + R1115 = __saturate(R1115); + + $(S) = R1115 s< 0; + $(Z) = R1115 == 0; +} + +# SATSUB reg1, reg2, reg3 - rrrrr111111RRRRR|wwwww01110011010 +:satsub R0004, R1115, R2731 is op0510=0x3F & R0004 & R1115; op1626=0x39A & R2731 +{ + $(CY) = R1115 < R0004; + $(OV) = sborrow(R1115, R0004); + $(SAT) = $(SAT) || $(OV); + + R2731 = R1115 - R0004; + R2731 = __saturate(R2731); + + $(S) = R2731 s< 0; + $(Z) = R2731 == 0; +} + +# SATSUBI imm16, reg1, reg2 +:satsubi s1631, R0004, R1115 is op0510=0x33 & op1115!=0 & R0004 & R1115; s1631 +{ + $(CY) = R1115 < s1631; + $(OV) = sborrow(R1115, s1631); + $(SAT) = $(SAT) || $(OV); + + R1115 = R1115 - s1631; + R1115 = __saturate(R1115); + + $(S) = R1115 s< 0; + $(Z) = R1115 == 0; +} + +# SATSUBR reg1, reg2 +:satsubr R0004, R1115 is op0510=0x04 & R0004 & R1115 & op1115!=0 +{ + $(CY) = R0004 < R1115; + $(OV) = sborrow(R0004, R1115); + $(SAT) = $(SAT) || $(OV); + + R1115 = R0004 - R1115; + R1115 = __saturate(R1115); + + $(S) = R1115 s< 0; + $(Z) = R1115 == 0; +} + + +##################################################### +##### Divide ##### +##################################################### + + +# DIV reg1, reg2, reg3 - rrrrr111111RRRRR|wwwww01011000000 +:div R0004, R1115, R2731 is op0510=0x3F & R0004 & R1115; op1626=0x2C0 & R2731 +{ + local quot:4 = R1115 s/ R0004; + local mod:4 = R1115 s% R0004; + $(OV) = ((R1115 == 0x80000000 && R0004 == 0xFFFFFFFF) || R0004 == 0x0); + R1115 = quot; + R2731 = mod; + set_Z(R1115); + set_S(R1115); +} + +# DIVH reg1, reg2 - rrrrr000010RRRRR +:divh R0004, R1115 is op0510=0x02 & R0004 & R1115 +{ + $(OV) = ((R1115 == 0x80000000 && R0004 == 0xFFFFFFFF) || R0004 == 0x0); + R1115 = R1115 / R0004; + set_Z(R1115); + set_S(R1115); +} + +# DIVH reg1, reg2, reg3 - rrrrr111111RRRRR|wwwww01010000000 +:divh R0004, R1115, R2731 is op0510=0x3F & R0004 & R1115; op1626=0x280 & R2731 +{ + local quot:4 = R1115 s/ sext(R0004:2); + local mod:4 = R1115 s% sext(R0004:2); + $(OV) = ((R1115 == 0x80000000 && R0004 == 0xFFFFFFFF) || R0004 == 0x0); + R1115 = quot; + R2731 = mod; + set_Z(R1115); + set_S(R1115); +} + +# DIVHU reg1, reg2, reg3 - rrrrr111111RRRRR|wwwww01010000010 +:divhu R0004, R1115, R2731 is op0510=0x3F & R0004 & R1115; op1626=0x282 & R2731 +{ + local quot:4 = R1115 / zext(R0004:2); + local mod:4 = R1115 % zext(R0004:2); + R1115 = quot; + R2731 = mod; + $(OV) = (R0004 == 0); + set_Z(R1115); + set_S(R1115); +} + +# DIVU reg1, reg2, reg3 - rrrrr111111RRRRR|wwwww01011000010 +:divu R0004, R1115, R2731 is op0510=0x3F & R0004 & R1115; op1626=0x2C2 & R2731 +{ + local quot:4 = R1115 / R0004; + local mod:4 = R1115 % R0004; + $(OV) = (R0004 == 0); + R1115 = quot; + R2731 = mod; + set_Z(R1115); + set_S(R1115); +} + + +##################################################### +##### HighSpeedDivide ##### +##################################################### + + +# DIVQ reg1, reg2, reg3 - rrrrr111111RRRRR|wwwww01011111100 +:divq R0004, R1115, R2731 is op0510=0x3F & R0004 & R1115; op1626=0x2FC & R2731 +{ + local quot:4 = R1115 s/ R0004; + local mod:4 = R1115 s% R0004; + $(OV) = ((R1115 == 0x80000000 && R0004 == 0xFFFFFFFF) || R0004 == 0x0); + R2731 = mod; + R1115 = quot; + set_Z(R1115); + set_S(R1115); +} + +# DIVQU reg1, reg2, reg3 - rrrrr111111RRRRR|wwwww01011111110 +:divqu R0004, R1115, R2731 is op0510=0x3F & R0004 & R1115; op1626=0x2FE & R2731 +{ + local quot:4 = R1115 / R0004; + local mod:4 = R1115 % R0004; + $(OV) = (R0004 == 0); + R2731 = mod; + R1115 = quot; + set_Z(R1115); + set_S(R1115); +} + + +##################################################### +##### Conditional ##### +##################################################### + + +# ADF cccc, reg1, reg2, reg3 - rrrrr111111RRRRR|wwwww011101cccc0 +:adf^c1720 R0004, R1115, R2731 is op0510=0x3F & R0004 & R1115; op2126=0x1D & op1616=0 & c1720 & R2731 +{ + local cond = zext(c1720); + set_OV_pos2(R1115, R0004, cond); + set_CY_pos2(R1115, R0004, cond); + R2731 = R1115 + R0004 + cond; + set_S(R2731); + set_Z(R2731); +} + +# SBF cccc, reg1, reg2, reg3 - rrrrr111111RRRRR|wwwww011100cccc0 +:sbf^c1720 R0004, R1115, R2731 is op0510=0x3F & R0004 & R1115; op2126=0x1C & op1616=0 & c1720 & R2731 +{ + local cond = zext(c1720); + set_OV_neg2(R1115, R0004, cond); + set_CY_neg2(R1115, R0004, cond); + R2731 = R1115 - R0004 - cond; + set_S(R2731); + set_Z(R2731); +} + + +##################################################### +##### Logic ##### +##################################################### + + +# AND reg1, reg2 - rrrrr001010RRRRR +:and R0004, R1115 is op0510=0x0A & R0004 & R1115 +{ + R1115 = R1115 & R0004; + set_OV0_S_Z(R1115); +} + +# ANDI imm16, reg1, reg2 - rrrrr110110RRRRR|iiiiiiiiiiiiiiii +:andi op1631, R0004, R1115 is op0510=0x36 & R1115 & R0004; op1631 +{ + R1115 = R0004 & op1631; + set_OV0_S_Z(R1115); +} + +# NOT reg1, reg2 - rrrrr000001RRRRR +:not R0004, R1115 is op0510=0x01 & R0004 & R1115 +{ + R1115 = ~R0004; + set_OV0_S_Z(R1115); +} + +# OR reg1, reg2 - rrrrr001000RRRRR +:or R0004, R1115 is op0510=0x08 & R0004 & R1115 +{ + R1115 = R1115 | R0004; + set_OV0_S_Z(R1115); +} + +# ORI imm16, reg1, reg2 - rrrrr110100RRRRR|iiiiiiiiiiiiiiii +:ori op1631, R0004, R1115 is op0510=0x34 & R1115 & R0004; op1631 +{ + R1115 = R0004 | op1631; + set_OV0_S_Z(R1115); +} + +# TST reg1, reg2 - rrrrr001011RRRRR +:tst R0004, R1115 is op0510=0x0B & R0004 & R1115 +{ + set_OV0_S_Z(R1115 & R0004); +} + +# XOR reg1, reg2 - rrrrr001001RRRRR +:xor R0004, R1115 is op0510=0x09 & R0004 & R1115 +{ + R1115 = R1115 ^ R0004; + set_OV0_S_Z(R1115); +} + +# XORI imm16, reg1, reg2 - rrrrr110101RRRRR|iiiiiiiiiiiiiiii +:xori op1631, R0004, R1115 is op0510=0x35 & R1115 & R0004; op1631 +{ + R1115 = R0004 ^ op1631; + set_OV0_S_Z(R1115); +} + + +##################################################### +##### BitManipulation ##### +##################################################### + + +# CLR1 bit#3, disp16[reg1] - 10bbb111110RRRRR|dddddddddddddddd +:clr1 op1113, s1631[R0004] is op0510=0x3E & op1415=2 & op1113 & R0004; s1631 +{ + local adr:4 = R0004 + s1631; + local tkn = *:1 adr; + *:1 adr = tkn & ~(1 << op1113); + set_Z(tkn & (1 << op1113)); +} + +# CLR1 reg2, [reg1] - rrrrr111111RRRRR|0000000011100100 +:clr1 R1115, [R0004] is op0510=0x3F & R0004 & R1115; op1631=0xE4 +{ + local tkn = *:1 R0004; + *:1 R0004 = tkn & ~(1 << R1115); + set_Z(tkn & (1 << R1115)); +} + +# NOT1 bit#3, disp16[reg1] - 01bbb111110RRRRR|dddddddddddddddd +:not1 op1113, s1631[R0004] is op0510=0x3E & op1415=1 & op1113 & R0004; s1631 +{ + local adr:4 = R0004 + s1631; + local tkn = *:1 adr; + *:1 adr = tkn ^ (1 << op1113); + set_Z(tkn & (1 << op1113)); +} + +# NOT1 reg2, [reg1] - rrrrr111111RRRRR|0000000011100010 +:not1 R1115, [R0004] is op0510=0x3F & R0004 & R1115; op1631=0xE2 +{ + local tkn = *:1 R0004; + *:1 R0004 = tkn ^ (1 << R1115); + set_Z(tkn & (1 << R1115)); +} + +# SET1 bit#3, disp16[reg1] - 00bbb111110RRRRR|dddddddddddddddd +:set1 op1113, s1631[R0004] is op0510=0x3E & op1415=0 & op1113 & R0004; s1631 +{ + local adr:4 = R0004 + s1631; + local tkn = *:1 adr; + *:1 adr = tkn | (1 << op1113); + set_Z(tkn & (1 << op1113)); +} + +# SET1 reg2, [reg1] - rrrrr111111RRRRR|0000000011100000 +:set1 R1115, [R0004] is op0510=0x3F & R0004 & R1115; op1631=0xE0 +{ + local tkn = *:1 R0004; + *:1 R0004 = tkn | (1 << R1115); + set_Z(tkn & (1 << R1115)); +} + +# TST1 bit#3, disp16[reg1] - 11bbb111110RRRRR|dddddddddddddddd +:tst1 op1113, s1631[R0004] is op0510=0x3E & op1415=3 & op1113 & R0004; s1631 +{ + local adr:4 = R0004 + s1631; + local tkn = *:1 adr; + set_Z(tkn & (1 << op1113)); +} + +# TST1 reg2, [reg1] - rrrrr111111RRRRR|0000000011100110 +:tst1 R0004, [R1115] is op0510=0x3F & R0004 & R1115; op1631=0xE6 +{ + local tkn = *:1 R0004; + set_Z(tkn & (1 << R1115)); +} + + +##################################################### +##### BitSearch ##### +##################################################### + + +# SCH0L reg2, reg3 - rrrrr11111100000|wwwww01101100100 +:sch0l R1115, R2731 is op0010=0x7E0 & R1115; op1626=0x364 & R2731 +{ + SearchLeft(R2731, R1115, 0); + $(CY) = (R1115 != 0xFFFFFFFF); # zero bit found + $(Z) = (R1115 == 0xFFFFFFFF); # zero bit not found +} + +# SCH0R reg2, reg3 - rrrrr11111100000|wwwww01101100000 +:sch0r R1115, R2731 is op0010=0x7E0 & R1115; op1626=0x360 & R2731 +{ + SearchRight(R2731, R1115, 0); + $(CY) = (R1115 != 0xFFFFFFFF); # zero bit found + $(Z) = (R1115 == 0xFFFFFFFF); # zero bit not found +} + +# SCH1L reg2, reg3 - rrrrr11111100000|wwwww01101100110 +:sch1l R1115, R2731 is op0010=0x7E0 & R1115; op1626=0x366 & R2731 +{ + SearchLeft(R2731, R1115, 1); + $(CY) = (R1115 != 0x0); # one bit found + $(Z) = (R1115 == 0x0); # one bit not found +} + +# SCH1R reg2, reg3 +:sch1r R1115, R2731 is op0010=0x7E0 & R1115; op1626=0x362 & R2731 +{ + SearchRight(R2731, R1115, 1); + $(CY) = (R1115 != 0x0); # one bit found + $(Z) = (R1115 == 0x0); # one bit not found +} + + +##################################################### +##### Branch ##### +##################################################### + + +#Bcond adr9 - ddddd1011dddcccc +:b^c0003 adr9 is op0710=0xB & c0003 & adr9 +{ + if (c0003) + goto adr9; +} +:br adr9 is op0710=0xB & op0003=0x5 & adr9 +{ + goto adr9; +} + +# JARL disp22, reg2 - rrrrr11110dddddd|ddddddddddddddd0 +:jarl adr22, R1115 is (op0610=0x1E & R1115) ... & adr22 +{ + R1115 = inst_next; + call adr22; +} + +# JARL disp32, reg1 - 00000010111RRRRR|ddddddddddddddd0|DDDDDDDDDDDDDDDD +:jarl adr32, R0004 is op0515=0x017 & R0004; adr32 +{ + R0004 = inst_next; + call adr32; +} + +# JMP [reg1] - 00000000011RRRRR +:jmp [R0004] is op0515=0x03 & R0004 & op0004=0x1F +{ + return [R0004]; +} + +:jmp [R0004] is op0515=0x03 & R0004 +{ + goto [R0004]; +} + +# JMP disp32[reg1] - 00000110111RRRRR|ddddddddddddddd0|DDDDDDDDDDDDDDDD +:jmp adr32i[R0004] is op0515=0x037 & R0004; adr32i +{ + local adr = adr32i + R0004; + goto [adr]; +} + +# JR disp22 - 00000111110ddddd|ddddddddddddddd0 +:jr adr22 is op0615=0x1E ... & adr22 +{ + goto adr22; +} + +# JR disp32 - 0000001011100000|ddddddddddddddd0|DDDDDDDDDDDDDDDD +:jr adr32 is op0015=0x2E0; adr32 +{ + goto adr32; +} + + +##################################################### +##### Special ##### +##################################################### + + +# CALLT imm6 - 0000001000iiiiii +:callt op0005 is op0615=0x8 & op0005 +{ + CTPC = inst_next; + CTPSW = PSW; + local adr:4 = CTBP + (op0005 << 1); + PC = CTBP + zext(*:2 adr); + call [PC]; +} + +# CAXI [reg1], reg2, reg3 - rrrrr111111RRRRR|wwwww00011101110 +:caxi [R0004], R1115, R2731 is op0510=0x3F & R0004 & R1115; op1626=0xEE & R2731 +{ + local tkn = *:4 (R0004 & ~(0x3)); + local result = R1115 - tkn; + *:4 R0004 = tkn * zext(result != 0) + R2731 * zext(result == 0); + R2731 = tkn; + set_general_flags_neg(R1115, tkn); +} + +# CTRET - 0000011111100000|0000000101000100 +:ctret is op0515=0x3F; op1631=0x144 +{ + PC = CTPC; + PSW = CTPSW; + return [PC]; +} + +# DI - 0000011111100000|0000000101100000 +define pcodeop __disable_irq; +:di is op0015=0x7E0; op1631=0x160 +{ + $(ID) = 1; + __disable_irq(); +} + +# DISPOSE imm5, list12 - 0000011001iiiiiL|LLLLLLLLLLL00000 +:dispose prep0105, DispList is prep0615=0x19 & prep1620=0x0 & prep0105 & DispList +{ + sp = sp + (prep0105 << 2); + build DispList; +} + +# DISPOSE imm5, list12, [reg1] - 0000011001iiiiiL|LLLLLLLLLLLRRRRR +:dispose prep0105, DispList, [prep1620] is prep0615=0x19 & prep1620 & prep0105 & DispList +{ + sp = sp + (prep0105 << 2); + build DispList; + PC = prep1620; + return [PC]; +} + +# EI - 1000011111100000|0000000101100000 +define pcodeop __enable_irq; +:ei is op0015=0x87E0; op1631=0x160 +{ + $(ID) = 0; + __enable_irq(); +} + +# EIRET - 0000011111100000|0000000101001000 +:eiret is op0515=0x3F; op1631=0x148 +{ + PC = EIPC; + PSW = EIPSW; + return [PC]; +} + +# FERET - 0000011111100000|0000000101001010 +:feret is op0515=0x3F; op1631=0x14A +{ + PC = FEPC; + PSW = FEPSW; + return [PC]; +} + +# FETRAP vector4 - 0vvvv00001000000 +:fetrap op1114 is op0010=0x40 & op1515=0 & op1114 & op1115!=0 +{ + FEPC = inst_next; + FEPSW = PSW; + FEIC = op1114 + 0x30; # exception code 0x30..0x3F +@ifndef V850E3 + $(FECC) = op1114 + 0x30; # exception code 0x30..0x3F +@else + $(UM) = 0; +@endif + $(EP) = 1; + $(ID) = 1; + $(NP) = 1; + PC = 0x30; + goto [PC]; +} + +# HALT - 0000011111100000|0000000100100000 +define pcodeop __halt; +:halt is op0015=0x7E0; op1631=0x120 +{ + goto inst_start; +} + +@ifndef V850E3 +# LDSR reg2, regID - rrrrr111111RRRRR|0000000000100000 +:ldsr R0004, SR1115 is op0510=0x3F & SR1115 & R0004; op1631=0x20 +{ + SR1115 = R0004; +} +@endif + +# NOP - 0000000000000000 +:nop is op0015=0x0 +{ } + +# PREPARE list12, imm5 - 0000011110iiiiiL|LLLLLLLLLLL00001 +:prepare PrepList, prep0105 is prep0615=0x1E & prep0105 & prep1620=0x1 & PrepList +{ + build PrepList; + sp = sp - (prep0105 << 2); +} + +# PREPARE list12, imm5, sp - 0000011110iiiiiL|LLLLLLLLLLL00011 +:prepare PrepList, prep0105, sp is prep0615=0x1E & prep0105 & prep1620=0x3 & PrepList & sp +{ + build PrepList; + sp = sp - (prep0105 << 2); + ep = sp; +} + +# PREPARE list12, imm5, imm16 (low) - 0000011110iiiiiL|LLLLLLLLLLL01011|iiiiiiiiiiiiiiii +:prepare PrepList, prep0105, s3247 is prep0615=0x1E & prep0105 & prep1620=0xB & PrepList; s3247 +{ + build PrepList; + sp = sp - (prep0105 << 2); + ep = s3247; +} + +# PREPARE list12, imm5, imm16 (high) - 0000011110iiiiiL|LLLLLLLLLLL10011|iiiiiiiiiiiiiiii +:prepare PrepList, prep0105, s3247 is prep0615=0x1E & prep0105 & prep1620=0x13 & PrepList; s3247 +{ + build PrepList; + sp = sp - (prep0105 << 2); + ep = s3247 << 16; +} + +# PREPARE list12, imm5, imm32 - 0000011110iiiiiL|LLLLLLLLLLL11011|iiiiiiiiiiiiiiii|iiiiiiiiiiiiiiii +:prepare PrepList, prep0105, imm32 is prep0615=0x1E & prep0105 & prep1620=0x1B & PrepList; op3247; op4863 +[ imm32 = (op4863 << 16) | op3247; ] +{ + build PrepList; + sp = sp - (prep0105 << 2); + ep = imm32; +} + +# RETI - 0000011111100000|0000000101000000 +:reti is op0515=0x3F; op1631=0x140 +{ + if($(EP)!=1) + goto ; + + PC = EIPC; + PSW = EIPSW; + goto ; + + + if($(NP)!=1) + goto ; + + PC = FEPC; + PSW = FEPSW; + goto ; + + + PC = EIPC; + PSW = EIPSW; + + + return[PC]; +} + +# RIE - 0000000001000000 +:rie is op0015=0x40 +{ + FEPC = PC; + FEPSW = PSW; + $(NP) = 1; + $(EP) = 1; + $(ID) = 1; + PC = 0x30; + goto [PC]; +} + +# RIE imm5, imm4 - iiiii1111111IIII|0000000000000000 +:rie op1115, op0003 is op0410=0x7F & op1115 & op0003; op1631=0x0 +{ + FEPC = PC; + FEPSW = PSW; + $(NP) = 1; + $(EP) = 1; + $(ID) = 1; + PC = 0x30; + goto [PC]; +} + +@ifndef V850E3 +# STSR regID, reg2 - rrrrr111111RRRRR|0000000001000000 +:stsr SR0004, R1115 is op0510=0x3F & R1115 & SR0004; op1631=0x40 +{ + R1115 = SR0004; +} +@endif + +# SWITCH reg1 - 00000000010RRRRR +:switch R0004 is op0515=0x2 & R0004 +{ + local adr:4 = inst_next + (R0004 << 1); + PC = inst_next + (sext(*:2 adr) << 1); + goto [PC]; +} + +# SYNCE - 0000000000011101 +define pcodeop __synchronize; +:synce is op0015=0x1D +{ + __synchronize(); +} + +# SYNCM - 0000000000011110 +:syncm is op0015=0x1E +{ + __synchronize(); +} + +# SYNCP - 0000000000011111 +:syncp is op0015=0x1F +{ + __synchronize(); +} + +# SYSCALL vector8 - 11010111111vvvvv|00VVV00101100000 +:syscall vector8 is op0515=0x6BF & op0004; op3031=0 & op2729 & op1626=0x160 +[ vector8 = (op2729 << 5) | op0004; ] +{ + EIPC = inst_next; + EIPSW = PSW; + EIIC = vector8 + 0x8000; # exception code 0x8000..0x80FF +@ifndef V850E3 + $(EICC) = vector8 + 0x8000; # exception code 0x8000..0x80FF +@else + $(UM) = 0; +@endif + $(EP) = 1; + $(ID) = 1; + local adr:4; + either_or(adr, (vector8 <= SCCFG), SCBP + (vector8 << 2), SCBP); + PC = SCBP + (*:4 adr); + call [PC]; +} + +# TRAP imm5 - 00000111111vvvvv|0000000100000000 +:trap op0004 is op0515=0x3F & op0004; op1631=0x100 +{ + local vector5:4 = op0004; + EIPC = inst_next; + EIPSW = PSW; + EIIC = vector5 + 0x40; # exception code 0x40..0x5F +@ifndef V850E3 + $(EICC) = vector5:2 + 0x40; # exception code 0x40..0x5F +@else + $(UM) = 0; +@endif + $(EP) = 1; + $(ID) = 1; + either_or(PC, (vector5 <= 15), 0x40, 0x50); + call [PC]; +} + + +##################################################### +##### Load ##### +##################################################### + + +# LD.B disp16[reg1], reg2 - rrrrr111000RRRRR|dddddddddddddddd +:ld.b s1631[R0004], R1115 is op0510=0x38 & R0004 & R1115; s1631 +{ + local adr:4 = R0004 + s1631; + R1115 = sext(*:1 adr); +} + +# LD.B disp23[reg1], reg3 - rrrrr111100RRRRR|wwwwwddddddd0101|DDDDDDDDDDDDDDDD +:ld.b disp23[R0004], R2731 is op0515=0x3C & R0004; R2731 & op2026 & op1619=0x5; s3247 +[ disp23 = (s3247 << 7) | op2026; ] +{ + local adr:4 = R0004 + disp23; + R2731 = sext(*:1 adr); +} + +# LD.BU disp16[reg1], reg2 - rrrrr11110bRRRRR|ddddddddddddddd1 +:ld.bu disp16[R0004], R1115 is op0610=0x1E & R0004 & R1115 & op0505; op1616=0x1 & s1731 +[ disp16 = (s1731 << 1) | op0505; ] +{ + local adr:4 = R0004 + disp16; + R1115 = zext(*:1 adr); +} + +# LD.BU disp23[reg1], reg3 - 00000111101RRRRR|wwwwwddddddd0101|DDDDDDDDDDDDDDDD +:ld.bu disp23[R0004], R2731 is op0515=0x3D & R0004; R2731 & op2026 & op1619=0x5; s3247 +[ disp23 = (s3247 << 7) | op2026; ] +{ + local adr:4 = R0004 + disp23; + R2731 = zext(*:1 adr); +} + +# LD.H disp16[reg1], reg2 - rrrrr111001RRRRR|ddddddddddddddd0 +:ld.h s1631[R0004], R1115 is op0510=0x39 & R0004 & R1115; s1631 & op1616=0x0 +{ + local adr:4 = R0004 + s1631; + R1115 = sext(*:2 adr); +} + +# LD.H disp23[reg1], reg3 - 00000111100RRRRR|wwwwwdddddd00111|DDDDDDDDDDDDDDDD +:ld.h disp23[R0004], R2731 is op0515=0x3C & R0004; R2731 & op2126 & op1620=0x7; s3247 +[ disp23 = (s3247 << 7) | (op2126 << 1); ] +{ + local adr:4 = R0004 + disp23; + R2731 = sext(*:2 adr); +} + +# LD.HU disp16[reg1], reg2 - rrrrr111111RRRRR|ddddddddddddddd1 +:ld.hu disp16[R0004], R1115 is op0510=0x3F & R0004 & R1115; op1616=0x1 & s1731 +[ disp16 = s1731 << 1; ] +{ + local adr:4 = R0004 + disp16; + R1115 = zext(*:2 adr); +} + +# LD.HU disp23[reg1], reg3 - 00000111101RRRRR|wwwwwdddddd00111|DDDDDDDDDDDDDDDD +:ld.hu disp23[R0004], R2731 is op0515=0x3D & R0004; R2731 & op2026 & op1619=0x7; s3247 +[ disp23 = (s3247 << 7) | op2026; ] +{ + local adr:4 = R0004 + disp23; + R2731 = zext(*:2 adr); +} + +# LD.W disp16[reg1], reg2 - rrrrr111001RRRRR|ddddddddddddddd1 +:ld.w disp16[R0004], R1115 is op0510=0x39 & R0004 & R1115; s1731 & op1616=0x1 +[ disp16 = s1731 * 2; ] +{ + local adr:4 = R0004 + disp16; + R1115 = *:4 adr; +} + +# LD.W disp23[reg1], reg3 - 00000111100RRRRR|wwwwwdddddd01001|DDDDDDDDDDDDDDDD +:ld.w disp23[R0004], R2731 is op0515=0x03C & R0004; R2731 & op2126 & op1620=0x9; s3247 +[ disp23 = (s3247 << 7) | (op2126 << 1); ] +{ + local adr:4 = R0004 + disp23; + R2731 = *:4 adr; +} + +# SLD.B disp7[ep], reg2 - rrrrr0110ddddddd +:sld.b op0006[ep], R1115 is op0710=0x06 & op0006 & R1115 & ep +{ + local adr:4 = ep + op0006; + R1115 = sext(*:1 adr); +} + +# SLD.BU disp4[ep], reg2 - rrrrr0000110dddd +:sld.bu op0003[ep], R1115 is op0410=0x06 & R1115 & op0003 & ep +{ + local adr:4 = ep + op0003; + R1115 = zext(*:1 adr); +} + +# SLD.H disp8[ep], reg2 - rrrrr1000ddddddd +:sld.h disp8[ep], R1115 is op0710=0x08 & op0006 & R1115 & ep +[ disp8 = op0006 * 2; ] +{ + local adr:4 = ep + disp8; + R1115 = sext(*:2 adr); +} + +# SLD.HU disp5[ep], reg2 - rrrrr0000111dddd +:sld.hu disp5[ep], R1115 is op0410=0x07 & R1115 & op0003 & ep +[ disp5 = op0003 * 2; ] +{ + local adr:4 = ep + disp5; + R1115 = zext(*:2 adr); +} + +# SLD.W disp8[ep], reg2 - rrrrr1010dddddd0 +:sld.w disp8[ep], R1115 is op0710=0x0A & op0000=0x0 & op0106 & R1115 & ep +[ disp8 = op0106 * 4; ] +{ + local adr:4 = ep + disp8; + R1115 = *:4 adr; +} + + +##################################################### +##### Store ##### +##################################################### + + +# SST.B reg2, disp7[ep] - rrrrr0111ddddddd +:sst.b R1115, op0006[ep] is op0710=0x07 & op0006 & R1115 & ep +{ + local adr:4 = ep + op0006; + local tmp:4 = R1115; + *:1 adr = tmp:1; +} + +# SST.H reg2, disp8[ep] - rrrrr1001ddddddd +:sst.h R1115, disp8[ep] is op0710=0x09 & op0006 & R1115 & ep +[ disp8 = op0006 * 2; ] +{ + local adr:4 = ep + disp8; + local tmp:4 = R1115; + *:2 adr = tmp:2; +} + +# SST.W reg2, disp8[ep] - rrrrr1010dddddd1 +:sst.w R1115, disp8[ep] is op0710=0x0A & op0000=0x1 & op0106 & R1115 & ep +[ disp8 = op0106 * 4; ] +{ + local adr:4 = ep + disp8; + local tmp:4 = R1115; + *:4 adr = tmp; +} + +# ST.B reg2, disp16[reg1] - rrrrr111010RRRRR|dddddddddddddddd +:st.b R1115, s1631[R0004] is op0510=0x3A & R0004 & R1115; s1631 +{ + local adr:4 = R0004 + s1631; + local tmp:4 = R1115; + *:1 adr = tmp:1; +} + +# ST.B reg3, disp23[reg1] - 00000111100RRRRR|dddddddddddddddd +:st.b R2731, disp23[R0004] is op0515=0x3C & R0004; R2731 & op2026 & op1619=0xD; s3247 +[ disp23 = (s3247 << 7) | op2026; ] +{ + local adr:4 = R0004 + disp23; + local tmp:4 = R2731; + *:1 adr = tmp:1; +} + +# ST.H reg2, disp16[reg1] - rrrrr111011RRRRR|ddddddddddddddd0 +:st.h R1115, s1631[R0004] is op0510=0x3B & R0004 & R1115; s1631 & op1616=0x0 +{ + local adr:4 = R0004 + s1631; + local tmp:4 = R1115; + *:2 adr = tmp:2; +} + +# ST.H reg3, disp23[reg1] - 00000111101RRRRR|wwwwwdddddd01101|DDDDDDDDDDDDDDDD +:st.h R2731, disp23[R0004] is op0515=0x3D & R0004; R2731 & op2126 & op1620=0xD; s3247 +[ disp23 = (s3247 << 7) | (op2126 << 1); ] +{ + local adr:4 = R0004 + disp23; + local tmp:4 = R2731; + *:2 adr = tmp:2; +} + +# ST.W reg2, disp16[reg1] - rrrrr111011RRRRR|ddddddddddddddd1 +:st.w R1115, disp16[R0004] is op0510=0x3B & R0004 & R1115; s1731 & op1616=0x1 +[ disp16 = s1731 * 2; ] +{ + local adr:4 = R0004 + disp16; + local tmp:4 = R1115; + *:4 adr = tmp; +} + +# ST.W reg3, disp23[reg1] - 00000111100RRRRR|wwwwwdddddd01111|DDDDDDDDDDDDDDDD +:st.w R2731, disp23[R0004] is op0515=0x3C & R0004; R2731 & op2126 & op1620=0xF; s3247 +[ disp23 = (s3247 << 7) | (op2126 << 1); ] +{ + local adr:4 = R0004 + disp23; + local tmp:4 = R2731; + *:2 adr = tmp:2; +} + + +##################################################### +##### DataManipulation ##### +##################################################### + + +# BSH reg2, reg3 - rrrrr11111100000|wwwww01101000010 +:bsh R1115, R2731 is op0010=0x7E0 & R1115; op1626=0x342 & R2731 +{ + local x1 = R1115[0,8]; + local x2 = R1115[8,8]; + local x3 = R1115[16,8]; + local x4 = R1115[24,8]; + R2731 = zext(x3 << 24) | zext(x4 << 16) | zext(x1 << 8) | zext(x2); + set_S(R2731); + $(OV) = 0; + $(Z) = (x1 == 0) && (x2 == 0); + $(CY) = (x1 == 0) || (x2 == 0); +} + +# BSW reg2, reg3 - rrrrr11111100000|wwwww01101000000 +:bsw R1115, R2731 is op0010=0x7E0 & R1115; op1626=0x340 & R2731 +{ + local x1 = R1115[0,8]; + local x2 = R1115[8,8]; + local x3 = R1115[16,8]; + local x4 = R1115[24,8]; + R2731 = zext(x1 << 24) | zext(x2 << 16) | zext(x3 << 8) | zext(x4); + set_OV0_S_Z(R2731); + $(CY) = (x1 == 0) || (x2 == 0) || (x3 == 0) || (x4 == 0); +} + +# CMOV cccc, reg1, reg2, reg3 - rrrrr111111RRRRR|wwwww011001cccc0 +:cmov^c1720 R0004, R1115, R2731 is op0510=0x3F & R0004 & R1115; op2126=0x19 & op1616=0 & c1720 & R2731 +{ + local result:4 = zext(c1720); + R2731 = R0004 * zext(result != 0) + R1115 * zext(result == 0); +} + +# CMOV cccc, imm5, reg2, reg3 - rrrrr111111iiiii|wwwww011000cccc0 +:cmov^c1720 s0004, R1115, R2731 is op0510=0x3F & s0004 & R1115; op2126=0x18 & op1616=0 & c1720 & R2731 +{ + local result:4 = zext(c1720); + R2731 = s0004 * zext(result != 0) + R1115 * zext(result == 0); +} + +# HSH reg2, reg3 - rrrrr11111100000|wwwww01101000110 +:hsh R1115, R2731 is op0010=0x7E0 & R1115; op1626=0x346 & R2731 +{ + R2731 = R1115; + set_S(R2731); + $(OV) = 0; + $(Z) = (R2731:2 == 0); + $(CY) = $(Z); +} + +# HSW reg2, reg3 - rrrrr11111100000|wwwww01101000100 +:hsw R1115, R2731 is op0010=0x7E0 & R1115; op1626=0x344 & R2731 +{ + local x1 = R1115:2; + local x2 = R1115[16,16]; + R2731 = zext(x1 << 16) | zext(x2); + set_OV0_S_Z(R2731); + $(CY) = (x1 == 0) || (x2 == 0); +} + +# SAR reg1, reg2 - rrrrr111111RRRRR|0000000010100000 +:sar R0004, R1115 is op0510=0x3F & R0004 & R1115; op1631=0xA0 +{ + shift_right_arith(R1115, R1115, R0004); +} + +# SAR imm5, reg2 - rrrrr010101iiiii +:sar op0004, R1115 is op0510=0x15 & op0004 & R1115 +{ + shift_right_arith(R1115, R1115, op0004:5); +} + +# SAR reg1, reg2, reg3 - rrrrr111111RRRRR|wwwww00010100010 +:sar R0004, R1115, R2731 is op0510=0x3F & R0004 & R1115; op1626=0xA2 & R2731 +{ + shift_right_arith(R2731, R1115, R0004); +} + +# SASF cccc, reg2 - rrrrr1111110cccc|0000001000000000 +:sasf^c0003 R1115 is op0410=0x7E & c0003 & R1115; op1631=0x0200 +{ + R1115 = (R1115 << 1) | zext(c0003); +} + +# SETF cond, reg2 - rrrrr1111110cccc|0000000000000000 +:setf^c0003 R1115 is op0410=0x7E & c0003 & R1115; op1631=0x0 +{ + R1115 = zext(c0003); +} + +# SHL reg1, reg2 - rrrrr111111RRRRR|0000000011000000 +:shl R0004, R1115 is op0510=0x3F & R0004 & R1115; op1631=0xC0 +{ + shift_left_logic(R1115, R1115, R0004); +} + +# SHL imm5, reg2 - rrrrr010110iiiii +:shl op0004, R1115 is op0510=0x16 & op0004 & R1115 +{ + shift_left_logic(R1115, R1115, op0004:5); +} + +# SHL reg1, reg2, reg3 - rrrrr111111RRRRR|wwwww00011000010 +:shl R0004, R1115, R2731 is op0510=0x3F & R0004 & R1115; op1626=0xC2 & R2731 +{ + shift_left_logic(R2731, R1115, R0004); +} + +# SHR reg1, reg2 - rrrrr111111RRRRR|0000000010000000 +:shr R0004, R1115 is op0510=0x3F & R0004 & R1115; op1631=0x80 +{ + shift_right_logic(R1115, R1115, R0004); +} + +# SHR imm5, reg2 - rrrrr010100iiiii +:shr op0004, R1115 is op0510=0x14 & op0004 & R1115 +{ + shift_right_logic(R1115, R1115, op0004:5); +} + +# SHR reg1, reg2, reg3 - rrrrr111111RRRRR|wwwww00010000010 +:shr R0004, R1115, R2731 is op0510=0x3F & R0004 & R1115; op1626=0x82 & R2731 +{ + shift_right_logic(R2731, R1115, R0004); +} + +# SXB reg1 - 00000000101RRRRR +:sxb R0004 is op0515=0x05 & R0004 +{ + R0004 = sext(R0004:1); +} + +# SXH reg1 - 00000000111RRRRR +:sxh R0004 is op0515=0x07 & R0004 +{ + R0004 = sext(R0004:2); +} + +# ZXB reg1 - 00000000100RRRRR +:zxb R0004 is op0515=0x004 & R0004 +{ + R0004 = zext(R0004:1); +} + +# ZXH reg1 - 00000000110RRRRR +:zxh R0004 is op0515=0x006 & R0004 +{ + R0004 = zext(R0004:2); +} + + +##################################################### +##### Float ##### +##################################################### + + +# ABSF.D reg2, reg3 - rrrr011111100000|wwww010001011000 +:absf.d R1115x2, R2731x2 is R1115x2 & op0510=0x3F & op0004=0b00000; R2731x2 & op2126=0b100010 & op1620=0b11000 +{ + R2731x2 = abs(R1115x2); +} + +# ABSF.S reg2, reg3 - rrrrr11111100000|wwwww10001001000 +:absf.s R1115, R2731 is R1115 & op0510=0x3F & op0004=0b00000; R2731 & op2126=0b100010 & op1620=0b01000 +{ + R2731 = abs(R1115); +} + +# ADDF.D reg1, reg2, reg3 - rrrr0111111RRRR0|wwww010001110000 +:addf.d R0004x2, R1115x2, R2731x2 is R1115x2 & op0510=0x3F & R0004x2 ; R2731x2 & op2126=0b100011 & op1620=0b10000 +{ + R2731x2 = R1115x2 f+ R0004x2; +} + +# ADDF.S reg1, reg2, reg3 - rrrrr111111RRRRR|wwwww10001100000 +:addf.s R0004, R1115, R2731 is R1115 & op0510=0x3F & R0004 ; R2731 & op2126=0b100011 & op1620=0b00000 +{ + R2731 = R1115 f+ R0004; +} + +# CEILF.DL reg2, reg3 - rrrr011111100010|wwww010001010100 +:ceilf.dl R1115x2, R2731x2 is R1115x2 & op0510=0x3F & op0004=0b00010; R2731x2 & op2126=0b100010 & op1620=0b10100 +{ + local var:8 = ceil(float2float(R1115x2)); + R2731x2 = trunc(var); +} + +# CEILF.DUL reg2, reg3 - rrrr011111110010|wwww010001010100 +:ceilf.dul R1115x2, R2731x2 is R1115x2 & op0510=0x3F & op0004=0b10010; R2731x2 & op2126=0b100010 & op1620=0b10100 +{ + local var:8 = ceil(float2float(R1115x2)); + R2731x2 = trunc(var); +} + +# CEILF.DUW reg2, reg3 - rrrrr11111110010|wwwww10001010000 +:ceilf.duw R1115x2, R2731 is R1115x2 & op0510=0x3F & op0004=0b10010; R2731 & op2126=0b100010 & op1620=0b10000 +{ + R2731 = trunc(ceil(R1115x2)); +} + +# CEILF.DW reg2, reg3 - rrrrr11111100010|wwwww10001010000 +:ceilf.dw R1115x2, R2731 is R1115x2 & op0510=0x3F & op0004=0b00010; R2731 & op2126=0b100010 & op1620=0b10000 +{ + R2731 = trunc(ceil(R1115x2)); +} + +# CEILF.SL reg2, reg3 - rrrrr11111100010|wwww010001000100 +:ceilf.sl R1115, R2731x2 is R1115 & op0510=0x3F & op0004=0b00010; R2731x2 & op2126=0b100010 & op1620=0b00100 +{ + local var:8 = ceil(float2float(R1115)); + R2731x2 = trunc(var); +} + +# CEILF.SUL reg2, reg3 - rrrrr11111110010|wwwww10001000100 +:ceilf.sul R1115, R2731x2 is R1115 & op0510=0x3F & op0004=0b10010; R2731x2 & op2126=0b100010 & op1620=0b00100 +{ + local var:8 = ceil(float2float(R1115)); + R2731x2 = trunc(var); +} + +# CEILF.SUW reg2, reg3 - rrrrr11111110010|wwwww10001000000 +:ceilf.sul R1115, R2731 is R1115 & op0510=0x3F & op0004=0b10010; R2731 & op2126=0b100010 & op1620=0b00000 +{ + R2731 = trunc(ceil(R1115)); +} + +# CEILF.SW reg2, reg3 - rrrrr11111100010|wwwww10001000000 +:ceilf.sw R1115, R2731 is R1115 & op0510=0x3F & op0004=0b00010; R2731 & op2126=0b100010 & op1620=0b00000 +{ + R2731 = trunc(ceil(R1115)); +} + +# CMOVF.D fcbit, reg1, reg2, reg3 - rrrr0111111RRRR0|wwww01000001fff0 +:cmovf.d fcbit1719, R1115x2, R0004x2, R2731x2 is R1115x2 & op0510=0x3F & R0004x2; R2731x2 & op2126=0b100000 & op2020=1 & fcbit1719 & op1616=0 +{ + #CC0 = Bit 24 + local bit = (FPSR >> (fcbit1719 + 24:1)) & 0x1; + either_or1(R2731x2, bit, R0004x2, R1115x2); +} + +# CMOVF.S fcbit, reg1, reg2, reg3 - rrrrr111111RRRRR|wwwww1000000fff0 +:cmovf.s fcbit1719, R1115, R0004, R2731 is R1115 & op0510=0x3F & R0004; R2731 & op2126=0b100000 & op2020=0 & fcbit1719 & op1616=0 +{ + local bit = (FPSR >> (fcbit1719 + 24:1)) & 0x1; + either_or1(R2731, bit, R0004, R1115); +} + +# CMPF.D fcond, reg2, reg1, fcbit - rrrr0111111RRRRR|0FFFF1000011fff0 +:cmpf.d fcond2730, R1115x2, R0004x2, fcbit1719 is R1115x2 & op0510=0x3F & R0004x2; op3131=0 & fcond2730 & op2126=0b100001 & op2020=1 & fcbit1719 & op1616=0 +{ + #0 = Unordered + #1 = Equal to + #2 = Less than + #3 = Exeption + #bits = ex le eq un + + local bit:4 = 0; + compare_float(bit, fcond2730:1, R0004x2, R1115x2); + + local pos:4 = bit << (fcbit1719 + 24); #find position of the calculated bit + local mask:4 = 1 << (fcbit1719 + 24); #create mask to clean old bit in FPSR register + FPSR = (FPSR & ~mask) | pos; #set the new bit at the right position +} + +# CMPF.S fcond, reg2, reg1, fcbit - rrrrr111111RRRRR|0FFFF1000010fff0 +:cmpf.s fcond2730, R1115, R0004, fcbit1719 is R1115 & op0510=0x3F & R0004; op3131=0 & fcond2730 & op2126=0b100001 & op2020=0 & fcbit1719 & op1616=0 +{ + local bit:4 = 0; + compare_float(bit, fcond2730:1, R0004, R1115); + + local pos:4 = bit << (fcbit1719 + 24); #find position of the calculated bit + local mask:4 = 1 << (fcbit1719 + 24); #create mask to clean old bit in FPSR register + FPSR = (FPSR & ~mask) | pos; #set the new bit at the right position +} + +# CVTF.DL reg2, reg3 - rrrr011111100100|wwww010001010100 +:cvtf.dl R1115x2, R2731x2 is R1115x2 & op0510=0x3F & op0004=0b00100; R2731x2 & op2126=0b100010 & op1620=0b10100 +{ + R2731x2 = int2float(R1115x2); +} + +# CVTF.DS reg2, reg3 - rrrr011111100011|wwww010001010010 +:cvtf.ds R1115x2, R2731 is R1115x2 & op0510=0x3F & op0004=0b00011; R2731 & op2126=0b100010 & op1620=0b10010 +{ + R2731 = float2float(R1115x2); +} + +# CVTF.DUL reg2, reg3 - rrrr011111110100|wwww010001010100 +:cvtf.dul R1115x2, R2731x2 is R1115x2 & op0510=0x3F & op0004=0b10100; R2731x2 & op2126=0b100010 & op1620=0b10100 +{ + R2731x2 = trunc(R1115x2); +} + +# CVTF.DUW reg2, reg3 - rrrrr11111110100|wwwww10001010000 +:cvtf.duw R1115x2, R2731 is R1115x2 & op0510=0x3F & op0004=0b10100; R2731 & op2126=0b100010 & op1620=0b10000 +{ + R2731 = trunc(R1115x2); +} + +# CVTF.DW reg2, reg3 - rrrrr11111100100|wwwww10001010000 +:cvtf.sw R1115x2, R2731 is R1115x2 & op0510=0x3F & op0004=0b00100; R2731 & op2126=0b100010 & op1620=0b10000 +{ + R2731 = trunc(R1115x2); +} + +# CVTF.LD reg2, reg3 - rrrr011111100001|wwww010001010010 +:cvtf.ls R1115x2, R2731x2 is R1115x2 & op0510=0x3F & op0004=0b00001; R2731x2 & op2126=0b100010 & op1620=0b10010 +{ + R2731x2 = int2float(R1115x2); +} + +# CVTF.LS reg2, reg3 - rrrr011111100001|wwwww10001000010 +:cvtf.ls R1115x2, R2731 is R1115x2 & op0510=0x3F & op0004=0b00001; R2731 & op2126=0b100010 & op1620=0b00010 +{ + R2731 = int2float(R1115x2); +} + +# CVTF.SD reg2, reg3 - rrrrr11111100010|wwww010001010010 +:cvtf.sd R1115, R2731x2 is R1115 & op0510=0x3F & op0004=0b00010; R2731x2 & op2126=0b100010 & op1620=0b10010 +{ + R2731x2 = float2float(R1115); +} + +# CVTF.SL reg2, reg3 - rrrrr11111100100|wwwww10001000100 +:cvtf.sl R1115, R2731x2 is R1115 & op0510=0x3F & op0004=0b00100; R2731x2 & op2126=0b100010 & op1620=0b00100 +{ + R2731x2 = trunc(R1115); +} + +# CVTF.SUL reg2, reg3 - rrrrr11111110100|wwwww10001000100 +:cvtf.sul R1115, R2731x2 is R1115 & op0510=0x3F & op0004=0b10100; R2731x2 & op2126=0b100010 & op1620=0b00100 +{ + R2731x2 = trunc(R1115); +} + +# CVTF.SUW reg2, reg3 - rrrrr11111110100|wwwww10001000000 +:cvtf.suw R1115, R2731 is R1115 & op0510=0x3F & op0004=0b10100; R2731 & op2126=0b100010 & op1620=0b00000 +{ + R2731 = trunc(R1115); +} + +# CVTF.SW reg2, reg3 - rrrrr11111100100|wwwww10001000000 +:cvtf.sw R1115, R2731 is R1115 & op0510=0x3F & op0004=0b00100; R2731 & op2126=0b100010 & op1620=0b00000 +{ + R2731 = trunc(R1115); +} + +# CVTF.ULD reg2, reg3 - rrrr011111100001|wwww010001010010 +:cvtf.uls R1115x2, R2731x2 is R1115x2 & op0510=0x3F & op0004=0b10001; R2731x2 & op2126=0b100010 & op1620=0b10010 +{ + R2731x2 = int2float(R1115x2); +} + +# CVTF.ULS reg2, reg3 - rrrr011111110001|wwwww10001000010 +:cvtf.uls R1115x2, R2731 is R1115x2 & op0510=0x3F & op0004=0b10001; R2731 & op2126=0b100010 & op1620=0b00010 +{ + R2731 = int2float(R1115x2); +} + +# CVTF.UWD reg2, reg3 - rrrrr11111110000|wwwww10001010010 +:cvtf.uwd R1115, R2731x2 is R1115 & op0510=0x3F & op0004=0b10000; R2731x2 & op2126=0b100010 & op1620=0b10010 +{ + R2731x2 = int2float(R1115); +} + +# CVTF.UWS reg2, reg3 - rrrrr11111110000|wwwww10001000010 +:cvtf.uws R1115, R2731 is R1115 & op0510=0x3F & op0004=0b10000; R2731 & op2126=0b100010 & op1620=0b00010 +{ + R2731 = int2float(R1115); +} + +# CVTF.WD reg2, reg3 - rrrrr11111100000|wwwww10001010010 +:cvtf.wd R1115, R2731x2 is R1115 & op0510=0x3F & op0004=0b00000; R2731x2 & op2126=0b100010 & op1620=0b10010 +{ + R2731x2 = int2float(R1115); +} + +# CVTF.WS reg2, reg3 - rrrrr11111100000|wwwww10001000010 +:cvtf.ws R1115, R2731 is R1115 & op0510=0x3F & op0004=0b00000; R2731 & op2126=0b100010 & op1620=0b00010 +{ + R2731 = int2float(R1115); +} + +# DIVF.D reg1, reg2, reg3 - rrrr0111111RRRR0|wwww010001111110 +:divf.s R0004x2, R1115x2, R2731x2 is R0004x2 & op0510=0x3F & R1115x2; R2731x2 & op2126=0b100011 & op1620=0b11110 +{ + R2731x2 = R1115x2 f/ R0004x2; +} + +# DIVF.S reg1, reg2, reg3 - rrrrr111111RRRRR|wwwww10001101110 +:divf.s R0004, R1115, R2731 is R0004 & op0510=0x3F & R1115; R2731 & op2126=0b100011 & op1620=0b01110 +{ + R2731 = R1115 f/ R0004; +} + +# FLOORF.DL reg2, reg3 - rrrr011111100011|wwww010001010100 +:floorf.dl R1115x2, R2731x2 is R1115x2 & op0510=0x3F & op0004=0b00011; R2731x2 & op2126=0b100010 & op1620=0b10100 +{ + local var:8 = floor(float2float(R1115x2)); + R2731x2 = trunc(var); +} + +# FLOORF.DUL reg2, reg3 - rrrr011111110011|wwww010001010100 +:floorf.dul R1115x2, R2731x2 is R1115x2 & op0510=0x3F & op0004=0b10011; R2731x2 & op2126=0b100010 & op1620=0b10100 +{ + local var:8 = floor(float2float(R1115x2)); + R2731x2 = trunc(var); +} + +# FLOORF.DUW reg2, reg3 - rrrrr11111110011|wwwww10001010000 +:floorf.duw R1115x2, R2731 is R1115x2 & op0510=0x3F & op0004=0b10011; R2731 & op2126=0b100010 & op1620=0b10000 +{ + R2731 = trunc(floor(R1115x2)); +} + +# FLOORF.DW reg2, reg3 - rrrrr11111100011|wwwww10001010000 +:floorf.dw R1115x2, R2731 is R1115x2 & op0510=0x3F & op0004=0b00011; R2731 & op2126=0b100010 & op1620=0b10000 +{ + R2731 = trunc(floor(R1115x2)); +} + +# FLOORF.SL reg2, reg3 - rrrrr11111100011|wwww010001000100 +:floorf.sl R1115, R2731x2 is R1115 & op0510=0x3F & op0004=0b00011; R2731x2 & op2126=0b100010 & op1620=0b00100 +{ + local var:8 = floor(float2float(R1115)); + R2731x2 = trunc(var); +} + +# FLOORF.SUL reg2, reg3 - rrrrr11111110011|wwwww10001000100 +:floorf.sul R1115, R2731x2 is R1115 & op0510=0x3F & op0004=0b10011; R2731x2 & op2126=0b100010 & op1620=0b00100 +{ + local var:8 = floor(float2float(R1115)); + R2731x2 = trunc(var); +} + +# FLOORF.SUW reg2, reg3 - rrrrr11111110011|wwwww10001000000 +:floorf.suw R1115, R2731 is R1115 & op0510=0x3F & op0004=0b10011; R2731 & op2126=0b100010 & op1620=0b00000 +{ + R2731 = trunc(floor(R1115)); +} + +# FLOORF.SW reg2, reg3 - rrrrr11111100011|wwwww10001000000 +:floorf.suw R1115, R2731 is R1115 & op0510=0x3F & op0004=0b00011; R2731 & op2126=0b100010 & op1620=0b00000 +{ + R2731 = trunc(floor(R1115)); +} + +# FMAF.S reg1, reg2, reg3 - rrrrr111111RRRRR|wwwww10011100000 +:fmaf.s R0004, R1115, R2731 is R0004 & op0510=0x3F & R1115; R2731 & op2126=0b100111 & op1620=0b00000 +{ + R2731 = (R1115 f* R0004) f+ R2731; +} + +# FMSF.S reg1, reg2, reg3 - rrrrr111111RRRRR|wwwww10011100010 +:fmsf.s R0004, R1115, R2731 is R0004 & op0510=0x3F & R1115; R2731 & op2126=0b100111 & op1620=0b00010 +{ + R2731 = (R1115 f* R0004) f- R2731; +} + +# FNMAF.S reg1, reg2, reg3 - rrrrr111111RRRRR|wwwww10011100100 +:fnmaf.s R0004, R1115, R2731 is R0004 & op0510=0x3F & R1115; R2731 & op2126=0b100111 & op1620=0b00100 +{ + R2731 = f- ((R1115 f* R0004) f+ R2731); +} + +# FNMSF.S reg1, reg2, reg3 - rrrrr111111RRRRR|wwwww10011100110 +:fnmfs.s R0004, R1115, R2731 is R0004 & op0510=0x3F & R1115; R2731 & op2126=0b100111 & op1620=0b00110 +{ + R2731 = f- ((R1115 f* R0004) f- R2731); +} + +# MADDF.S reg1, reg2, reg3, reg4 - rrrrr111111RRRRR|wwwww101W00WWWW0 +:maddf.s R0004, R1115, R2731, reg4 is R0004 & op0510=0x3F & R1115; R2731 & op2426=0b101 & op2122=0b00 & op1616=0 & reg4 +{ + reg4 = (R1115 f* R0004) f+ R2731; +} + +# MAXF.D reg1, reg2, reg3 - rrrr0111111RRRR0|wwww010001111000 +:maxf.d R0004x2, R1115x2, R2731x2 is R0004x2 & op0510=0x3F & R1115x2; R2731x2 & op2126=0b100011 & op1620=0b11000 +{ + local bigger:1 = R1115x2 f> R0004x2; + either_or(R2731x2, bigger, R1115x2, R0004x2); +} + +# MAXF.S reg1, reg2, reg3 - rrrrr111111RRRRR|wwwww10001101000 +:maxf.s R0004, R1115, R2731 is R0004 & op0510=0x3F & R1115; R2731 & op2126=0b100011 & op1620=0b01000 +{ + local bigger:1 = R1115 f> R0004; + either_or(R2731, bigger, R1115, R0004); +} + +# MINF.D reg1, reg2, reg3 - rrrr0111111RRRR0|wwww010001111010 +:minf.d R0004x2, R1115x2, R2731x2 is R0004x2 & op0510=0x3F & R1115x2; R2731x2 & op2126=0b100011 & op1620=0b11010 +{ + local bigger:1 = R1115x2 f< R0004x2; + either_or(R2731x2, bigger, R1115x2, R0004x2); +} + +# MINF.S reg1, reg2, reg3 - rrrr0111111RRRRR|wwwww10001101010 +:minf.s R0004, R1115, R2731 is R0004 & op0510=0x3F & R1115; R2731 & op2126=0b100011 & op1620=0b01010 +{ + local bigger:1 = R1115 f< R0004; + either_or(R2731, bigger, R1115, R0004); +} + +# MSUBF.S reg1, reg2, reg3, reg4 - rrrrr111111RRRRR|wwwww101W01WWWW0 +:msubf.s R0004, R1115, R2731, reg4 is R0004 & op0510=0x3F & R1115; R2731 & op2426=0b101 & op2122=0b01 & op1616=0 & reg4 +{ + reg4 = (R1115 f* R0004) f- R2731; +} + +# MULF.D reg1, reg2, reg3 - rrrr0111111RRRR0|wwww010001110100 +:mulf.d R0004x2, R1115x2, R2731x2 is R0004x2 & op0510=0x3F & R1115x2; R2731x2 & op2126=0b100011 & op1620=0b10100 +{ + R2731x2 = R1115x2 f* R0004x2; +} + +# MULF.S reg1, reg2, reg3 - rrrr0111111RRRRR|wwwww10001100100 +:mulf.s R0004, R1115, R2731 is R0004 & op0510=0x3F & R1115; R2731 & op2126=0b100011 & op1620=0b00100 +{ + R2731 = R1115 f* R0004; +} + +# NEGF.D reg2, reg3 - rrrr011111100001|wwww010001011000 +:negf.d R1115x2, R2731x2 is R1115x2 & op0510=0x3F & op0004=0b00001; R2731x2 & op2126=0b100010 & op1620=0b11000 +{ + R2731x2 = f- R1115x2; +} + +# NEGF.S reg2, reg3 - rrrrr11111100001|wwwww10001001000 +:negf.s R1115, R2731 is R1115 & op0510=0x3F & op0004=0b00001; R2731 & op2126=0b100010 & op1620=0b01000 +{ + R2731 = f- R1115; +} + +# NMADDF.S reg1, reg2, reg3, reg4 - rrrrr111111RRRRR|wwwww101W10WWWW0 +:nmaddf.s R0004, R1115, R2731, reg4 is R0004 & op0510=0x3F & R1115; R2731 & op2426=0b101 & op2122=0b10 & op1616=0 & reg4 +{ + reg4 = f-((R1115 f* R0004) f+ R2731); +} + +# NMSUBF.S reg1, reg2, reg3, reg4 - rrrrr111111RRRRR|wwwww101W11WWWW0 +:nmsubf.s R0004, R1115, R2731, reg4 is R0004 & op0510=0x3F & R1115; R2731 & op2426=0b101 & op2122=0b11 & op1616=0 & reg4 +{ + reg4 = f-((R1115 f* R0004) f- R2731); +} + +# RECIPF.D reg2, reg3 - rrrr011111100001|wwww010001011110 +:recipf.d R1115x2, R2731x2 is R1115x2 & op0510=0x3F & op0004=0b00001; R2731x2 & op2126=0b100010 & op1620=0b11110 +{ + R2731x2 = 1 f/ R1115x2; +} + +# RECIPF.S reg2, reg3 - rrrrr11111100001|wwwww10001001110 +:recipf.s R1115, R2731 is R1115 & op0510=0x3F & op0004=0b00001; R2731 & op2126=0b100010 & op1620=0b01110 +{ + R2731 = 1 f/ R1115; +} + +# RSQRTF.D reg2, reg3 - rrrr011111100010|wwwww10001011110 +:rsqrtf.d R1115x2, R2731x2 is R1115x2 & op0510=0x3F & op0004=0b00010; R2731x2 & op2126=0b100010 & op1620=0b11110 +{ + R2731x2 = 1 f/ sqrt(R1115x2); +} + +# RSQRTF.S reg2, reg3 - rrrrr11111100010|wwwww10001001110 +:rsqrtf.s R1115, R2731 is R1115 & op0510=0x3F & op0004=0b00010; R2731 & op2126=0b100010 & op1620=0b01110 +{ + R2731 = 1 f/ sqrt(R1115); +} + +# SQRTF.D reg2, reg3 - rrrr011111100000|wwww010001011110 +:sqrtf.d R1115x2, R2731x2 is R1115x2 & op0510=0x3F & op0004=0b00000; R2731x2 & op2126=0b100010 & op1620=0b11110 +{ + R2731x2 = sqrt(R1115x2); +} + +# SQRTF.S reg2, reg3 - rrrrr11111100000|wwwww10001001110 +:sqrtf.s R1115, R2731 is R1115 & op0510=0x3F & op0004=0b00000; R2731 & op2126=0b100010 & op1620=0b01110 +{ + R2731 = sqrt(R1115); +} + +# SUBF.D reg1, reg2, reg3 - rrrr0111111RRRR0|wwww010001110010 +:subf.d R0004x2, R1115x2, R2731x2 is R0004x2 & op0510=0x3F & R1115x2; R2731x2 & op2126=0b100011 & op1620=0b10010 +{ + R2731x2 = R1115x2 f- R0004x2; +} + +# SUBF.S reg1, reg2, reg3 - rrrrr111111RRRRR|wwwww10001100010 +:subf.s R0004, R1115, R2731 is R0004 & op0510=0x3F & R1115; R2731 & op2126=0b100011 & op1620=0b00010 +{ + R2731 = R1115 f- R0004; +} + +# TRFSR fcbit - 0000011111100000|000001000000fff0 +:trfsr fcbit1719 is op1115=0 & op0510=0x3F & op0004=0; op2731=0 & op2126=0b100000 & op2020=0 & fcbit1719 & op1616=0 +{ + local var:4 = FPSR & (1 << (fcbit1719 + 24)); + $(Z) = (var != 0); +} + +# TRNCF.DL reg2, reg3 - rrrr011111100001|wwww010001010100 +:trncf.dl R1115x2, R2731x2 is R1115x2 & op0510=0x3F & op0004=0b00001; R2731x2 & op2126=0b100010 & op1620=0b10100 +{ + R2731x2 = trunc(R1115x2); +} + +# TRNCF.DUL reg2, reg3 - rrrr011111110001|wwww010001010100 +:trncf.dul R1115x2, R2731x2 is R1115x2 & op0510=0x3F & op0004=0b10001; R2731x2 & op2126=0b100010 & op1620=0b10100 +{ + R2731x2 = trunc(R1115x2); +} + +# TRNCF.DUW reg2, reg3 - rrrrr11111110001|wwwww10001010000 +:trncf.duw R1115x2, R2731 is R1115x2 & op0510=0x3F & op0004=0b10001; R2731 & op2126=0b100010 & op1620=0b10000 +{ + R2731 = trunc(R1115x2); +} + +# TRNCF.DW reg2, reg3 - rrrrr11111100001|wwwww10001010000 +:trncf.dw R1115x2, R2731 is R1115x2 & op0510=0x3F & op0004=0b00001; R2731 & op2126=0b100010 & op1620=0b10000 +{ + R2731 = trunc(R1115x2); +} + +# TRNCF.SL reg2, reg3 - rrrrr11111100001|wwww010001000100 +:trncf.sl R1115, R2731x2 is R1115 & op0510=0x3F & op0004=0b00001; R2731x2 & op2126=0b100010 & op1620=0b00100 +{ + R2731x2 = trunc(R1115); +} + +# TRNCF.SUL reg2, reg3 - rrrrr11111110001|wwww010001000100 +:trncf.sul R1115, R2731x2 is R1115 & op0510=0x3F & op0004=0b10001; R2731x2 & op2126=0b100010 & op1620=0b00100 +{ + R2731x2 = trunc(R1115); +} + +# TRNCF.SUW reg2, reg3 - rrrrr11111110001|wwwww10001000000 +:trncf.suw R1115, R2731 is R1115 & op0510=0x3F & op0004=0b10001; R2731 & op2126=0b100010 & op1620=0b00000 +{ + R2731 = trunc(R1115); +} + +# TRNCF.SW reg2, reg3 - rrrrr11111100001|wwwww10001000000 +:trncf.sw R1115, R2731 is R1115 & op0510=0x3F & op0004=0b00001; R2731 & op2126=0b100010 & op1620=0b00000 +{ + R2731 = trunc(R1115); +} + diff --git a/pypcode/processors/V850/data/languages/V850e3.pspec b/pypcode/processors/V850/data/languages/V850e3.pspec new file mode 100644 index 0000000..380ac41 --- /dev/null +++ b/pypcode/processors/V850/data/languages/V850e3.pspec @@ -0,0 +1,23 @@ + + + + + + + + + + + + + + + + + + + + + + + diff --git a/pypcode/processors/V850/data/languages/V850e3.sinc b/pypcode/processors/V850/data/languages/V850e3.sinc new file mode 100644 index 0000000..3f3883b --- /dev/null +++ b/pypcode/processors/V850/data/languages/V850e3.sinc @@ -0,0 +1,323 @@ +#BCOND adr17 - 00000111111DCCCC | ddddddddddddddd1 +:b^c0003 adr17 is (op0515=0x3F & c0003; op1616=1) & adr17 +{ + if (c0003) goto adr17; +} + + +# BINS reg1, pos, width, reg2 - rrrrr111111RRRRR | MMMMK0001001LLL0 (msb >= 16, lsb >= 16) +:bins _R1115, pos, width, R0004 is R1115 & _R1115 & op0510=0x3f & R0004; op2831 & op2727 & op2026=0x9 & op1719 & op1616=0 +[ pos = (op2727 << 3) | op1719 + 16; width= op2831 - pos + 17; ] +{ + local mask:4 = 0; + bfmask(mask, pos, width); + local result = (R1115 & ~mask) | (R0004 & mask); + _R1115 = result; + set_Z(result); + set_S(result); +} + +# BINS reg1, pos, width, reg2 - rrrrr111111RRRRR | MMMMK0001011LLL0 (msb >= 16, lsb < 16) +:bins _R1115, pos, width, R0004 is R1115 & _R1115 & op0510=0x3f & R0004; op2831 & op2727 & op2026=0xb & op1719 & op1616=0 +[ pos = (op2727 << 3) | op1719; width= op2831 - pos + 17; ] +{ + local mask:4 = 0; + bfmask(mask, pos, width); + local result = (R1115 & ~mask) | (R0004 & mask); + _R1115 = result; + set_Z(result); + set_S(result); +} + +# BINS reg1, pos, width, reg2 - rrrrr111111RRRRR | MMMMK0001101LLL0 (msb < 16, lsb < 16) +:bins _R1115, pos, width, R0004 is R1115 & _R1115 & op0510=0x3f & R0004; op2831 & op2727 & op2026=0xd & op1719 & op1616=0 +[ pos = (op2727 << 3) | op1719; width= op2831 - pos + 1; ] +{ + local mask:4 = 0; + bfmask(mask, pos, width); + local result = (R1115 & ~mask) | (R0004 & mask); + _R1115 = result; + set_Z(result); + set_S(result); +} + +define pcodeop cacheHitBlockInvalidate; +define pcodeop cacheIndexedBlockInvalidate; +define pcodeop cacheFetchAndLock; +define pcodeop cacheIndexedStore; +define pcodeop cacheIndexedLoad; +define pcodeop clearLoadLinkBit; + +cacheop: "CHBII", R0004 is op1112=0 & R0004; op2731=0 +{ + cacheHitBlockInvalidate(R0004); +} + +cacheop: "CIBII", R0004 is op1112=1 & R0004; op2731=0 +{ + cacheIndexedBlockInvalidate(R0004); +} + +cacheop: "CFALI", R0004 is op1112=2 & R0004; op2731=0 +{ + cacheFetchAndLock(R0004); +} + +cacheop: "CISTI", R0004 is op1112=3 & R0004; op2731=0 +{ + cacheIndexedStore(R0004); +} + +cacheop: "CILDI", R0004 is op1112=3 & R0004; op2731=1 +{ + cacheIndexedLoad(R0004); +} + +cacheop: "CLL" is op1112=3; op2731=0x1e +{ + clearLoadLinkBit(); +} + +# CACHE cacheop, [reg1] - 111pp111111RRRRR | PPPPP00101100000 +:cache cacheop is (op1315=0x7 & op0510=0x3f; op1626=0x160) & cacheop { + build cacheop; +} + +# CLL - 1111111111111111 | 1111000101100000 +:cll is op0015=0xffff; op1631=0xf160 +{ + clearLoadLinkBit(); +} +# CVTF.HS reg2, reg3 - rrrrr11111100010|wwwwww10001000010 +:cvtf.hs R1115, R2731 is R1115 & op0510=0x3F & op0004=0b00010; R2731 & op2126=0b100010 & op1620=0b00010 +{ + R2731 = float2float(R1115:2); +} + +# CVTF.SH reg2, reg3 - rrrrr11111100100|wwwwww10001000100 +:cvtf.sh R1115, R2731 is R1115 & op0510=0x3F & op0004=0b00011; R2731 & op2126=0b100010 & op1620=0b00010 +{ + local res:2 = float2float(R1115); + R2731 = zext(res); +} + + +define pcodeop debugCheckpoint; +# dbcp - 1110100001000000 +:dbcp is op0015=0xe840 +{ + debugCheckpoint(); +} + +define pcodeop debugHVTrap; +# dbhvtrap - 1110000001000000 +:dbhvtrap is op0015=0xe040 +{ + debugHVTrap(); +} + +define pcodeop debugPush; +# dbpush - 01011111111RRRRR | rrrrr11111111111 +:dbpush _R0004, _R2731 is op0515=0x2ff & _R0004; _R2731 & op1626=0x7ff +{ + debugPush(_R0004, _R2731); +} + +# dbret - 0000011111100000 | 0000000101000110 +:dbret is op0015=0x07e0; op1631=0x0146 +{ + PC = DBPC; + PSW = DBPSW; + goto [DBPC]; +} + +define pcodeop debugTag; +# dbtag imm10u - 01011111111IIIII | iiiii11111111111 +:dbtag imm10u is op0515=0x67f & op0004; op2731 & op1626=0x7ff +[ imm10u = (op0004 << 5) | op2731; ] +{ + local tag:2 = imm10u; + debugTag(tag); +} + +# dbtrap +:dbtrap is op0015=0xf840; op1631=0xffff +{ + DBPC = inst_next; + DBPSW = PSW; + $(NP) = 1; + $(EP) = 1; + $(ID) = 1; + PC = 0x00000060; + goto [PC]; +} + +define pcodeop dst; +# dst - 0x07e0, 0x0134 +:dst is op0015=0x07e0; op1631=0x0134 +{ + dst(); +} + +define pcodeop est; +# est - 0x07e0, 0x0132 +:est is op0015=0x07e0; op1631=0x0132 +{ + est(); +} + +# JARL [reg1], reg3 - 11000111111RRRRR|WWWWW00101100000 +:jarl [R0004], R2731 is op0515=0x63F & R0004; op1626=0x160 & R2731 +{ + R2731 = inst_next; + call [R0004]; +} + +# LD.DW disp23[reg1], reg3 - 00000111101RRRRR | wwwwwdddddd01001 | DDDDDDDDDDDDDDDD +:ld.dw disp23[R0004], R2731x2 is op0515=0x3d & R0004; R2731x2 & op2126 & op1620=0x9; s3247 +[ disp23 = (s3247 << 7) | (op2126 << 1); ] +{ + local adr:4 = R0004 + disp23; + R2731x2 = sext(*:8 adr); +} + +#LDL.W [reg1], reg3 - 00000111111RRRRR | wwwww01101111000 +define pcodeop ldl; +:ldl.w R0004, R2731 is op0515=0x3f & R0004; R2731 & op1626=0x378 +{ + ldl(R0004, R2731); +} + +# LDSR reg2, regID, selID - rrrrr111111RRRRR|sssss00000100000 +:ldsr R0004, regId, selId is (regId & op0510=0x3f & R0004; selId & op1626=0x20) +{ + local sysReg:2 = (selId:2 << 5) | regId:2; + R0004 = *[sysreg]:4 sysReg; +} + +disp16: reladdr is op1731 [reladdr = inst_start - (op1731 << 1); ]{ export *:4 reladdr; } + +# LOOP reg1, disp16 - 00000110111RRRRR | ddddddddddddddd1 +:loop R0004, disp16 is op0515=0x037 & R0004; disp16 & op1616=1 +{ + set_OV_neg(R0004, -1:4); + R0004 = R0004 - 1; + if (R0004 == 0) goto inst_next; + goto disp16; +} + +ListReg: r0 is r0 & regNum=0 { export r0; } +ListReg: r1 is r1 & regNum=1 { export r1; } +ListReg: r2 is r2 & regNum=2 { export r2; } +ListReg: sp is sp & regNum=3 { export sp; } +ListReg: gp is gp & regNum=4 { export gp; } +ListReg: tp is tp & regNum=5 { export tp; } +ListReg: r6 is r6 & regNum=6 { export r6; } +ListReg: r7 is r7 & regNum=7 { export r7; } +ListReg: r8 is r8 & regNum=8 { export r8; } +ListReg: r9 is r9 & regNum=9 { export r9; } +ListReg: r10 is r10 & regNum=10 { export r10; } +ListReg: r11 is r11 & regNum=11 { export r11; } +ListReg: r12 is r12 & regNum=12 { export r12; } +ListReg: r13 is r13 & regNum=13 { export r13; } +ListReg: r14 is r14 & regNum=14 { export r14; } +ListReg: r15 is r15 & regNum=15 { export r15; } +ListReg: r16 is r16 & regNum=16 { export r16; } +ListReg: r17 is r17 & regNum=17 { export r17; } +ListReg: r18 is r18 & regNum=18 { export r18; } +ListReg: r19 is r19 & regNum=19 { export r19; } +ListReg: r20 is r20 & regNum=20 { export r20; } +ListReg: r21 is r21 & regNum=21 { export r21; } +ListReg: r22 is r22 & regNum=22 { export r22; } +ListReg: r23 is r23 & regNum=23 { export r23; } +ListReg: r24 is r24 & regNum=24 { export r24; } +ListReg: r25 is r25 & regNum=25 { export r25; } +ListReg: r26 is r26 & regNum=26 { export r26; } +ListReg: r27 is r27 & regNum=27 { export r27; } +ListReg: r28 is r28 & regNum=28 { export r28; } +ListReg: r29 is r29 & regNum=29 { export r29; } +ListReg: ep is ep & regNum=30 { export ep; } +ListReg: lp is lp & regNum=31 { export lp; } + + +PopSPList: ListReg is ListReg & counter=1 [ counter=0; regNum=regNum-1; ] { pushsp(ListReg); } +PopSPList: ListReg is ListReg & PopSPList [ counter=counter-1; regNum=regNum-1; ] { pushsp(ListReg); build PopSPList; } + +#POPSP reg1, reg2 - 01100111111RRRRR | wwwww00101100000 +:popsp R0004, R2731 is op0515=0x33f & R0004 & op0004; R2731 & op2731 & op1626=0x160 & PopSPList +[counter=op2731-op0004+1; regNum=op2731; ] +{ + _sp = sp; + build PopSPList; + sp = _sp; +} + +#PUSHSP reg1, reg2 - 01000111111RRRRR | wwwww00101100000 +PushSPList: ListReg is ListReg & counter=1 [ counter=0; regNum=regNum+1; ] { pushsp(ListReg); } +PushSPList: ListReg is ListReg & PushSPList [ counter=counter-1; regNum=regNum+1; ] { pushsp(ListReg); build PushSPList; } + +:pushsp R0004, R2731 is R0004 & op0004; R2731 & op2731 & PushSPList +[ counter=op2731-op0004+1; regNum=op0004; ] +{ + _sp = sp; + build PushSPList; + sp = _sp; +} + +#ROTL imm5, reg2, reg3 - rrrrr111111iiiii | wwwww00011000100 +:rotl op0004, R1115, _R2731 is op0004 & R1115 & op0510=0x3f; _R2731 & op1626=0x0c4 +{ + local shift = op0004; + local res = (R1115 << shift) | (R1115 >> (32 - shift)); + set_OV0_S_Z(res); + $(CY) = (shift != 0); + _R2731 = res; +} + +#ROTL reg1, reg2, reg3 - rrrrr111111RRRRR | wwwww00011000110 +:rotl R0004, R1115, _R2731 is R0004 & R1115 & op0510=0x3f; _R2731 & op1626=0x0c6 +{ + local shift = R0004 & 0x1f; + local res = (R1115 << shift) | (R1115 >> (32 - shift)); + set_OV0_S_Z(res); + $(CY) = (shift != 0); + _R2731 = res; +} + +#SNOOZE - 0000111111100000 | 0000000100100000 +define pcodeop snooze; +:snooze is op0015=0x0fe0;op1631=0x0120 +{ + snooze(); +} + +# ST.DW reg3, disp23[reg1] - 00000111101RRRRR | wwwwwdddddd01111 | DDDDDDDDDDDDDDDD +:st.dw R2731x2, disp23[R0004] is op0515=0x3d & R0004; R2731x2 & op2126 & op1620=0xf; s3247 +[ disp23 = (s3247 << 7) | (op2126 << 1); ] +{ + local addr:4 = R0004 + disp23; + *:8 addr = R2731x2; +} + +#STC.W reg3, [reg1] - 00000111111RRRRR | wwwww01101111010 +define pcodeop stc; +:stc.w R2731, R0004 is op0515=0x3f & R0004; R2731 & op1626=0x37a +{ + stc(R0004, R2731); +} + +#STSR regID, reg2, selID - rrrrr111111RRRRR | sssss00001000000 +:stsr regId, R0004, selId is (regId & op0510=0x3f & R0004; selId & op1626=0x40) +{ + local sysReg:2 = (selId:2 << 5) | regId:2; + *[sysreg]:4 sysReg = R0004; +} + +#SYNCI - 0000000000011100 +define pcodeop synci; +:synci is op0015=0x001c +{ + synci(); +} + + diff --git a/pypcode/processors/V850/data/languages/V850e3.slaspec b/pypcode/processors/V850/data/languages/V850e3.slaspec new file mode 100644 index 0000000..be608bf --- /dev/null +++ b/pypcode/processors/V850/data/languages/V850e3.slaspec @@ -0,0 +1,16 @@ +############################################## +##### ##### +##### V850E3 SLEIGH specification ##### +##### ##### +############################################## + +@define V850E3 "" + +@include "V850.sinc" + +################################ +##### Instructions ##### +################################ + +@include "V850_instructions.sinc" +@include "V850e3.sinc" diff --git a/pypcode/processors/V850/data/manuals/v850.idx b/pypcode/processors/V850/data/manuals/v850.idx index b09c169..8899a9d 100644 --- a/pypcode/processors/V850/data/manuals/v850.idx +++ b/pypcode/processors/V850/data/manuals/v850.idx @@ -1,4 +1,4 @@ -@r01us0001ej0100_v850e2m.pdf [V850E2M User’s Manual: Architecture RENESAS MCU V850E2M Microprocessor Core] +@r01us0001ej0100_v850e2m.pdf [V850E2M User�s Manual: Architecture RENESAS MCU V850E2M Microprocessor Core] ADD, 71 ADDI, 72 @@ -172,3 +172,19 @@ TRNCF.SL, 403 TRNCF.SUL, 404 TRNCF.SUW, 405 TRNCF.SW, 406 + +@r01us0143ej0130-rh850g3mh.pdf [RH850G3MH User's Manual: Software Renesas microcontroller] + +BINS, 162 +CACHE, 303 +CLL, 169 +LD.DW, 204 +LDL.W, 211 +LOOP, 213 +POPSP, 232 +PUSHSP, 237 +ROTL, 240 +SNOOZE, 268 +ST.DW, 274 +STC.W, 279 +SYNCI, 288 \ No newline at end of file diff --git a/pypcode/processors/tricore/data/languages/tricore.sinc b/pypcode/processors/tricore/data/languages/tricore.sinc index 137ffa1..84df391 100644 --- a/pypcode/processors/tricore/data/languages/tricore.sinc +++ b/pypcode/processors/tricore/data/languages/tricore.sinc @@ -1145,18 +1145,24 @@ SC: [a10]const0815Z10zz is PCPMode=0 & a10 & const0815Z10zz & op0003=8 & op0404= # ADDC D[c], D[a], D[b] (RR) :addc Rd2831,Rd0811,Rd1215 is PCPMode=0 & Rd0811 & Rd1215 & op0007=0xb ; Rd2831 & op1627=0x50 { - local tmp:5 = zext(Rd0811) + zext(Rd1215) + zext($(PSW_C)); - Rd2831 = tmp[0,32]; - $(PSW_C) = tmp[32,1]; + local op1:4 = Rd0811; + local op2:4 = Rd1215; + local tmp:4 = op1 + op2; + local tmp_c = zext($(PSW_C)); + Rd2831 = tmp + tmp_c; + $(PSW_C) = carry(op1, op2) || carry(tmp,tmp_c); overflowflags(Rd2831); } # ADDC D[c], D[a], const9 (RC) :addc Rd2831,Rd0811,const1220S is PCPMode=0 & ( Rd0811 & op0007=0x8b ; Rd2831 & op2127=0x5 ) & const1220S { - local tmp:5 = zext(Rd0811) + zext(const1220S) + zext($(PSW_C)); - Rd2831 = tmp[0,32]; - $(PSW_C) = tmp[32,1]; + local op1:4 = Rd0811; + local op2:4 = const1220S; + local tmp:4 = op1 + op2; + local tmp_c = zext($(PSW_C)); + Rd2831 = tmp + tmp_c; + $(PSW_C) = carry(op1, op2) || carry(tmp,tmp_c); overflowflags(Rd2831); } @@ -8166,9 +8172,11 @@ macro multiply_u_u(mres0, rega, regb, n) { # SUBC D[c], D[a], D[b] (RR) :subc Rd2831,Rd0811,Rd1215 is PCPMode=0 & Rd0811 & Rd1215 & op0007=0xb ; Rd2831 & op1627=0xd0 { - local tmp:5 = zext(Rd0811) - zext(Rd1215) + zext($(PSW_C)) - 1; - Rd2831 = tmp[0,32]; - $(PSW_C) = tmp[32,1]; + local result = Rd0811 - Rd1215; + local n_old_C:1 = !$(PSW_C); + $(PSW_C) = (Rd0811 < Rd1215) || (result < zext(n_old_C)); + # + PSW.C - 1 is equivalent to - !PSW.C + Rd2831 = result - zext(!n_old_C); overflowflags(Rd2831); } @@ -8220,8 +8228,7 @@ macro multiply_u_u(mres0, rega, regb, n) { :subx Rd2831,Rd0811,Rd1215 is PCPMode=0 & Rd0811 & Rd1215 & op0007=0xb ; Rd2831 & op1627=0xc0 { Rd2831 = Rd0811 - Rd1215; - local tmp:5 = zext(Rd0811) + ~zext(Rd1215) + 1; - $(PSW_C) = tmp[32,1]; + $(PSW_C) = Rd0811 < Rd1215; overflowflags(Rd2831); } diff --git a/pypcode/processors/x86/data/languages/avx.sinc b/pypcode/processors/x86/data/languages/avx.sinc index 23170f5..3bf015e 100644 --- a/pypcode/processors/x86/data/languages/avx.sinc +++ b/pypcode/processors/x86/data/languages/avx.sinc @@ -95,63 +95,97 @@ define pcodeop vaddsubps_avx ; } # ANDPD 3-64 PAGE 634 LINE 34821 -define pcodeop vandpd_avx ; :VANDPD XmmReg1, vexVVVV_XmmReg, XmmReg2_m128 is $(VEX_NDS) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & vexVVVV_XmmReg; byte=0x54; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128 { - local tmp:16 = vandpd_avx( vexVVVV_XmmReg, XmmReg2_m128 ); - ZmmReg1 = zext(tmp); + local m:16 = XmmReg2_m128; + XmmReg1[0,64] = vexVVVV_XmmReg[0,64] & m[0,64]; + XmmReg1[64,64] = vexVVVV_XmmReg[64,64] & m[64,64]; + ZmmReg1 = zext(XmmReg1); } # ANDPD 3-64 PAGE 634 LINE 34824 :VANDPD YmmReg1, vexVVVV_YmmReg, YmmReg2_m256 is $(VEX_NDS) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F) & vexVVVV_YmmReg; byte=0x54; (YmmReg1 & ZmmReg1) ... & YmmReg2_m256 { - local tmp:32 = vandpd_avx( vexVVVV_YmmReg, YmmReg2_m256 ); - ZmmReg1 = zext(tmp); + local m:32 = YmmReg2_m256; + YmmReg1[0,64] = vexVVVV_YmmReg[0,64] & m[0,64]; + YmmReg1[64,64] = vexVVVV_YmmReg[64,64] & m[64,64]; + YmmReg1[128,64] = vexVVVV_YmmReg[128,64] & m[128,64]; + YmmReg1[192,64] = vexVVVV_YmmReg[192,64] & m[192,64]; + ZmmReg1 = zext(YmmReg1); } # ANDPS 3-67 PAGE 637 LINE 34947 -define pcodeop vandps_avx ; :VANDPS XmmReg1, vexVVVV_XmmReg, XmmReg2_m128 is $(VEX_NDS) & $(VEX_L128) & $(VEX_PRE_NONE) & $(VEX_0F) & vexVVVV_XmmReg; byte=0x54; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128 { - local tmp:16 = vandps_avx( vexVVVV_XmmReg, XmmReg2_m128 ); - ZmmReg1 = zext(tmp); + local tmp:16 = XmmReg2_m128; + XmmReg1[0,32] = vexVVVV_XmmReg[0,32] & tmp[0,32]; + XmmReg1[32,32] = vexVVVV_XmmReg[32,32] & tmp[32,32]; + XmmReg1[64,32] = vexVVVV_XmmReg[64,32] & tmp[64,32]; + XmmReg1[96,32] = vexVVVV_XmmReg[96,32] & tmp[96,32]; + ZmmReg1 = zext(XmmReg1); } # ANDPS 3-67 PAGE 637 LINE 34950 :VANDPS YmmReg1, vexVVVV_YmmReg, YmmReg2_m256 is $(VEX_NDS) & $(VEX_L256) & $(VEX_PRE_NONE) & $(VEX_0F) & vexVVVV_YmmReg; byte=0x54; (YmmReg1 & ZmmReg1) ... & YmmReg2_m256 { - local tmp:32 = vandps_avx( vexVVVV_YmmReg, YmmReg2_m256 ); - ZmmReg1 = zext(tmp); + local tmp:32 = YmmReg2_m256; + YmmReg1[0,32] = vexVVVV_YmmReg[0,32] & tmp[0,32]; + YmmReg1[32,32] = vexVVVV_YmmReg[32,32] & tmp[32,32]; + YmmReg1[64,32] = vexVVVV_YmmReg[64,32] & tmp[64,32]; + YmmReg1[96,32] = vexVVVV_YmmReg[96,32] & tmp[96,32]; + YmmReg1[128,32] = vexVVVV_YmmReg[128,32] & tmp[128,32]; + YmmReg1[160,32] = vexVVVV_YmmReg[160,32] & tmp[160,32]; + YmmReg1[192,32] = vexVVVV_YmmReg[192,32] & tmp[192,32]; + YmmReg1[224,32] = vexVVVV_YmmReg[224,32] & tmp[224,32]; + + ZmmReg1 = zext(YmmReg1); } # ANDNPD 3-70 PAGE 640 LINE 35081 -define pcodeop vandnpd_avx ; :VANDNPD XmmReg1, vexVVVV_XmmReg, XmmReg2_m128 is $(VEX_NDS) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & vexVVVV_XmmReg; byte=0x55; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128 { - local tmp:16 = vandnpd_avx( vexVVVV_XmmReg, XmmReg2_m128 ); - ZmmReg1 = zext(tmp); + local m:16 = XmmReg2_m128; + XmmReg1[0,64] = ~vexVVVV_XmmReg[0,64] & m[0,64]; + XmmReg1[64,64] = ~vexVVVV_XmmReg[64,64] & m[64,64]; + ZmmReg1 = zext(XmmReg1); } # ANDNPD 3-70 PAGE 640 LINE 35084 :VANDNPD YmmReg1, vexVVVV_YmmReg, YmmReg2_m256 is $(VEX_NDS) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F) & vexVVVV_YmmReg; byte=0x55; (YmmReg1 & ZmmReg1) ... & YmmReg2_m256 { - local tmp:32 = vandnpd_avx( vexVVVV_YmmReg, YmmReg2_m256 ); - ZmmReg1 = zext(tmp); + local m:32 = YmmReg2_m256; + YmmReg1[0,64] = ~vexVVVV_YmmReg[0,64] & m[0,64]; + YmmReg1[64,64] = ~vexVVVV_YmmReg[64,64] & m[64,64]; + YmmReg1[128,64] = ~vexVVVV_YmmReg[128,64] & m[128,64]; + YmmReg1[192,64] = ~vexVVVV_YmmReg[192,64] & m[192,64]; + ZmmReg1 = zext(YmmReg1); } # ANDNPS 3-73 PAGE 643 LINE 35207 define pcodeop vandnps_avx ; :VANDNPS XmmReg1, vexVVVV_XmmReg, XmmReg2_m128 is $(VEX_NDS) & $(VEX_L128) & $(VEX_PRE_NONE) & $(VEX_0F) & vexVVVV_XmmReg; byte=0x55; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128 { - local tmp:16 = vandnps_avx( vexVVVV_XmmReg, XmmReg2_m128 ); - ZmmReg1 = zext(tmp); + local tmp:16 = XmmReg2_m128; + XmmReg1[0,32] = ~vexVVVV_XmmReg[0,32] & tmp[0,32]; + XmmReg1[32,32] = ~vexVVVV_XmmReg[32,32] & tmp[32,32]; + XmmReg1[64,32] = ~vexVVVV_XmmReg[64,32] & tmp[64,32]; + XmmReg1[96,32] = ~vexVVVV_XmmReg[96,32] & tmp[96,32]; + ZmmReg1 = zext(XmmReg1); } # ANDNPS 3-73 PAGE 643 LINE 35210 :VANDNPS YmmReg1, vexVVVV_YmmReg, YmmReg2_m256 is $(VEX_NDS) & $(VEX_L256) & $(VEX_PRE_NONE) & $(VEX_0F) & vexVVVV_YmmReg; byte=0x55; (YmmReg1 & ZmmReg1) ... & YmmReg2_m256 { - local tmp:32 = vandnps_avx( vexVVVV_YmmReg, YmmReg2_m256 ); - ZmmReg1 = zext(tmp); + local tmp:32 = YmmReg2_m256; + YmmReg1[0,32] = ~vexVVVV_YmmReg[0,32] & tmp[0,32]; + YmmReg1[32,32] = ~vexVVVV_YmmReg[32,32] & tmp[32,32]; + YmmReg1[64,32] = ~vexVVVV_YmmReg[64,32] & tmp[64,32]; + YmmReg1[96,32] = ~vexVVVV_YmmReg[96,32] & tmp[96,32]; + YmmReg1[128,32] = ~vexVVVV_YmmReg[128,32] & tmp[128,32]; + YmmReg1[160,32] = ~vexVVVV_YmmReg[160,32] & tmp[160,32]; + YmmReg1[192,32] = ~vexVVVV_YmmReg[192,32] & tmp[192,32]; + YmmReg1[224,32] = ~vexVVVV_YmmReg[224,32] & tmp[224,32]; + ZmmReg1 = zext(YmmReg1); } # BLENDPD 3-78 PAGE 648 LINE 35433 @@ -627,10 +661,10 @@ define pcodeop vcvtps2pd_avx ; } # CVTSD2SI 3-253 PAGE 823 LINE 44315 -:VCVTSD2SI Reg32, XmmReg2_m64 is $(VEX_NONE) & $(VEX_L128) & $(VEX_PRE_F2) & $(VEX_0F) & $(VEX_W0); byte=0x2D; Reg32 ... & XmmReg2_m64 +:VCVTSD2SI Reg32, XmmReg2_m64 is $(VEX_NONE) & $(VEX_L128) & $(VEX_PRE_F2) & $(VEX_0F) & $(VEX_W0); byte=0x2D; (Reg32 & check_Reg32_dest) ... & XmmReg2_m64 { Reg32 = trunc(round(XmmReg2_m64[0,64])); - # TODO Reg64 = zext(Reg32) + build check_Reg32_dest; } # CVTSD2SI 3-253 PAGE 823 LINE 44317 @@ -964,11 +998,9 @@ define pcodeop vldmxcsr_avx ; } # MASKMOVDQU 4-8 PAGE 1128 LINE 59041 -define pcodeop vmaskmovdqu_avx ; -:VMASKMOVDQU XmmReg1, XmmReg2 is $(VEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG); byte=0xF7; XmmReg1 & (mod=0x3 & XmmReg2) +:VMASKMOVDQU XmmReg1, XmmReg2 is $(VEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG); byte=0xF7; XmmReg1 & mod=0x3 & XmmReg2 & maskMovDI { - vmaskmovdqu_avx( XmmReg1, XmmReg2 ); - # TODO missing destination or side effects + maskMovDI = maskmovdqu( XmmReg1, XmmReg2 ); } # MAXPD 4-12 PAGE 1132 LINE 59201 @@ -1078,9 +1110,10 @@ define pcodeop vminss_avx ; @endif # MOVD/MOVQ 4-55 PAGE 1175 LINE 61362 -:VMOVD rm32, XmmReg1 is $(VEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W0); byte=0x7E; XmmReg1 ... & rm32 +:VMOVD rm32, XmmReg1 is $(VEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W0); byte=0x7E; (XmmReg1 & check_rm32_dest) ... & rm32 { rm32 = XmmReg1 [0,32]; + build check_rm32_dest; } # MOVD/MOVQ 4-55 PAGE 1175 LINE 61364 @@ -1219,32 +1252,32 @@ define pcodeop vmovlps_avx ; # MOVMSKPD 4-88 PAGE 1208 LINE 62906 define pcodeop vmovmskpd_avx ; -:VMOVMSKPD Reg32, XmmReg2 is $(VEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG); byte=0x50; Reg32 & (mod=0x3 & XmmReg2) +:VMOVMSKPD Reg32, XmmReg2 is $(VEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG); byte=0x50; Reg32 & check_Reg32_dest & (mod=0x3 & XmmReg2) { Reg32 = vmovmskpd_avx( XmmReg2 ); - # TODO Reg64 = zext(Reg32) + build check_Reg32_dest; } # MOVMSKPD 4-88 PAGE 1208 LINE 62910 -:VMOVMSKPD Reg32, YmmReg2 is $(VEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG); byte=0x50; Reg32 & (mod=0x3 & YmmReg2) +:VMOVMSKPD Reg32, YmmReg2 is $(VEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG); byte=0x50; Reg32 & check_Reg32_dest & (mod=0x3 & YmmReg2) { Reg32 = vmovmskpd_avx( YmmReg2 ); - # TODO Reg64 = zext(Reg32) + build check_Reg32_dest; } # MOVMSKPS 4-90 PAGE 1210 LINE 62986 define pcodeop vmovmskps_avx ; -:VMOVMSKPS Reg32, XmmReg2 is $(VEX_NONE) & $(VEX_L128) & $(VEX_PRE_NONE) & $(VEX_0F) & $(VEX_WIG); byte=0x50; Reg32 & (mod=0x3 & XmmReg2) +:VMOVMSKPS Reg32, XmmReg2 is $(VEX_NONE) & $(VEX_L128) & $(VEX_PRE_NONE) & $(VEX_0F) & $(VEX_WIG); byte=0x50; Reg32 & check_Reg32_dest & (mod=0x3 & XmmReg2) { Reg32 = vmovmskps_avx( XmmReg2 ); - # TODO Reg64 = zext(Reg32) + build check_Reg32_dest; } # MOVMSKPS 4-90 PAGE 1210 LINE 62990 -:VMOVMSKPS Reg32, YmmReg2 is $(VEX_NONE) & $(VEX_L256) & $(VEX_PRE_NONE) & $(VEX_0F) & $(VEX_WIG); byte=0x50; Reg32 & (mod=0x3 & YmmReg2) +:VMOVMSKPS Reg32, YmmReg2 is $(VEX_NONE) & $(VEX_L256) & $(VEX_PRE_NONE) & $(VEX_0F) & $(VEX_WIG); byte=0x50; Reg32 & check_Reg32_dest & (mod=0x3 & YmmReg2) { Reg32 = vmovmskps_avx( YmmReg2 ); - # TODO Reg64 = zext(Reg32) + build check_Reg32_dest; } # MOVNTDQA 4-92 PAGE 1212 LINE 63084 @@ -1453,6 +1486,7 @@ define pcodeop vmpsadbw_avx ; YmmReg1[128,32] = vexVVVV_YmmReg[128,32] f* m[128,32]; YmmReg1[160,32] = vexVVVV_YmmReg[160,32] f* m[160,32]; YmmReg1[192,32] = vexVVVV_YmmReg[192,32] f* m[192,32]; + YmmReg1[224,32] = vexVVVV_YmmReg[224,32] f* m[224,32]; ZmmReg1 = zext(YmmReg1); } @@ -1474,30 +1508,30 @@ define pcodeop vmpsadbw_avx ; define pcodeop vorpd_avx ; :VORPD XmmReg1, vexVVVV_XmmReg, XmmReg2_m128 is $(VEX_NDS) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & vexVVVV_XmmReg; byte=0x56; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128 { - local tmp:16 = vorpd_avx( vexVVVV_XmmReg, XmmReg2_m128 ); - ZmmReg1 = zext(tmp); + XmmReg1 = vexVVVV_XmmReg | XmmReg2_m128; + ZmmReg1 = zext(XmmReg1); } # ORPD 4-168 PAGE 1288 LINE 66722 :VORPD YmmReg1, vexVVVV_YmmReg, YmmReg2_m256 is $(VEX_NDS) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F) & vexVVVV_YmmReg; byte=0x56; (YmmReg1 & ZmmReg1) ... & YmmReg2_m256 { - local tmp:32 = vorpd_avx( vexVVVV_YmmReg, YmmReg2_m256 ); - ZmmReg1 = zext(tmp); + YmmReg1 = vexVVVV_YmmReg | YmmReg2_m256; + ZmmReg1 = zext(YmmReg1); } # ORPS 4-171 PAGE 1291 LINE 66846 define pcodeop vorps_avx ; :VORPS XmmReg1, vexVVVV_XmmReg, XmmReg2_m128 is $(VEX_NDS) & $(VEX_L128) & $(VEX_PRE_NONE) & $(VEX_0F) & vexVVVV_XmmReg; byte=0x56; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128 { - local tmp:16 = vorps_avx( vexVVVV_XmmReg, XmmReg2_m128 ); - ZmmReg1 = zext(tmp); + XmmReg1 = vexVVVV_XmmReg | XmmReg2_m128; + ZmmReg1 = zext(XmmReg1); } # ORPS 4-171 PAGE 1291 LINE 66848 :VORPS YmmReg1, vexVVVV_YmmReg, YmmReg2_m256 is $(VEX_NDS) & $(VEX_L256) & $(VEX_PRE_NONE) & $(VEX_0F) & vexVVVV_YmmReg; byte=0x56; (YmmReg1 & ZmmReg1) ... & YmmReg2_m256 { - local tmp:32 = vorps_avx( vexVVVV_YmmReg, YmmReg2_m256 ); - ZmmReg1 = zext(tmp); + YmmReg1 = vexVVVV_YmmReg | YmmReg2_m256; + ZmmReg1 = zext(YmmReg1); } # PABSB/PABSW/PABSD/PABSQ 4-180 PAGE 1300 LINE 67302 @@ -1560,24 +1594,53 @@ define pcodeop vpackuswb_avx ; define pcodeop vpaddb_avx ; :VPADDB XmmReg1, vexVVVV_XmmReg, XmmReg2_m128 is $(VEX_NDS) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & vexVVVV_XmmReg; byte=0xFC; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128 { - local tmp:16 = vpaddb_avx( vexVVVV_XmmReg, XmmReg2_m128 ); - ZmmReg1 = zext(tmp); + local result:16 = 0; + result[0,8] = vexVVVV_XmmReg[0,8] + XmmReg2_m128[0,8]; + result[8,8] = vexVVVV_XmmReg[8,8] + XmmReg2_m128[8,8]; + result[16,8] = vexVVVV_XmmReg[16,8] + XmmReg2_m128[16,8]; + result[24,8] = vexVVVV_XmmReg[24,8] + XmmReg2_m128[24,8]; + result[32,8] = vexVVVV_XmmReg[32,8] + XmmReg2_m128[32,8]; + result[40,8] = vexVVVV_XmmReg[40,8] + XmmReg2_m128[40,8]; + result[48,8] = vexVVVV_XmmReg[48,8] + XmmReg2_m128[48,8]; + result[56,8] = vexVVVV_XmmReg[56,8] + XmmReg2_m128[56,8]; + result[64,8] = vexVVVV_XmmReg[64,8] + XmmReg2_m128[64,8]; + result[72,8] = vexVVVV_XmmReg[72,8] + XmmReg2_m128[72,8]; + result[80,8] = vexVVVV_XmmReg[80,8] + XmmReg2_m128[80,8]; + result[88,8] = vexVVVV_XmmReg[88,8] + XmmReg2_m128[88,8]; + result[96,8] = vexVVVV_XmmReg[96,8] + XmmReg2_m128[96,8]; + result[104,8] = vexVVVV_XmmReg[104,8] + XmmReg2_m128[104,8]; + result[112,8] = vexVVVV_XmmReg[112,8] + XmmReg2_m128[112,8]; + result[120,8] = vexVVVV_XmmReg[120,8] + XmmReg2_m128[120,8]; + + ZmmReg1 = zext(result); } # PADDB/PADDW/PADDD/PADDQ 4-204 PAGE 1324 LINE 68660 -define pcodeop vpaddw_avx ; :VPADDW XmmReg1, vexVVVV_XmmReg, XmmReg2_m128 is $(VEX_NDS) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & vexVVVV_XmmReg; byte=0xFD; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128 { - local tmp:16 = vpaddw_avx( vexVVVV_XmmReg, XmmReg2_m128 ); - ZmmReg1 = zext(tmp); + local result:16 = 0; + result[0,16] = vexVVVV_XmmReg[0,16] + XmmReg2_m128[0,16]; + result[16,16] = vexVVVV_XmmReg[16,16] + XmmReg2_m128[16,16]; + result[32,16] = vexVVVV_XmmReg[32,16] + XmmReg2_m128[32,16]; + result[48,16] = vexVVVV_XmmReg[48,16] + XmmReg2_m128[48,16]; + result[64,16] = vexVVVV_XmmReg[64,16] + XmmReg2_m128[64,16]; + result[80,16] = vexVVVV_XmmReg[80,16] + XmmReg2_m128[80,16]; + result[96,16] = vexVVVV_XmmReg[96,16] + XmmReg2_m128[96,16]; + result[112,16] = vexVVVV_XmmReg[112,16] + XmmReg2_m128[112,16]; + + ZmmReg1 = zext(result); } # PADDB/PADDW/PADDD/PADDQ 4-204 PAGE 1324 LINE 68662 -define pcodeop vpaddd_avx ; :VPADDD XmmReg1, vexVVVV_XmmReg, XmmReg2_m128 is $(VEX_NDS) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & vexVVVV_XmmReg; byte=0xFE; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128 { - local tmp:16 = vpaddd_avx( vexVVVV_XmmReg, XmmReg2_m128 ); - ZmmReg1 = zext(tmp); + local result:16 = 0; + result[0,32] = vexVVVV_XmmReg[0,32] + XmmReg2_m128[0,32]; + result[32,32] = vexVVVV_XmmReg[32,32] + XmmReg2_m128[32,32]; + result[64,32] = vexVVVV_XmmReg[64,32] + XmmReg2_m128[64,32]; + result[96,32] = vexVVVV_XmmReg[96,32] + XmmReg2_m128[96,32]; + + ZmmReg1 = zext(result); } # PADDB/PADDW/PADDD/PADDQ 4-204 PAGE 1324 LINE 68664 @@ -1702,20 +1765,34 @@ define pcodeop vpcmpeqd_avx ; # PCMPESTRI 4-253 PAGE 1373 LINE 71311 define pcodeop vpcmpestri_avx ; -:VPCMPESTRI XmmReg1, XmmReg2_m128, imm8 is $(VEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F3A); byte=0x61; XmmReg1 ... & XmmReg2_m128; imm8 +:VPCMPESTRI XmmReg1, XmmReg2_m128, imm8 is $(VEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W0); byte=0x61 & check_ECX_dest; XmmReg1 ... & XmmReg2_m128; imm8 { - vpcmpestri_avx( XmmReg1, XmmReg2_m128, imm8:1 ); - # TODO missing destination or side effects + ECX = vpcmpestri_avx( XmmReg1, XmmReg2_m128, imm8:1, EAX, EDX ); + build check_ECX_dest; } +@ifdef IA64 +:VPCMPESTRI XmmReg1, XmmReg2_m128, imm8 is $(VEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W1); byte=0x61 & check_ECX_dest; XmmReg1 ... & XmmReg2_m128; imm8 +{ + ECX = vpcmpestri_avx( XmmReg1, XmmReg2_m128, imm8:1, RAX, RDX ); + build check_ECX_dest; +} +@endif + # PCMPESTRM 4-255 PAGE 1375 LINE 71395 define pcodeop vpcmpestrm_avx ; -:VPCMPESTRM XmmReg1, XmmReg2_m128, imm8 is $(VEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F3A); byte=0x60; XmmReg1 ... & XmmReg2_m128; imm8 +:VPCMPESTRM XmmReg1, XmmReg2_m128, imm8 is $(VEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W0); byte=0x60; XmmReg1 ... & XmmReg2_m128; imm8 { - vpcmpestrm_avx( XmmReg1, XmmReg2_m128, imm8:1 ); - # TODO missing destination or side effects + XMM0 = vpcmpestrm_avx( XmmReg1, XmmReg2_m128, imm8:1, EAX, EDX ); } +@ifdef IA64 +:VPCMPESTRM XmmReg1, XmmReg2_m128, imm8 is $(VEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W1); byte=0x60; XmmReg1 ... & XmmReg2_m128; imm8 +{ + XMM0 = vpcmpestrm_avx( XmmReg1, XmmReg2_m128, imm8:1, RAX, RDX ); +} +@endif + # PCMPGTB/PCMPGTW/PCMPGTD 4-257 PAGE 1377 LINE 71499 define pcodeop vpcmpgtb_avx ; :VPCMPGTB XmmReg1, vexVVVV_XmmReg, XmmReg2_m128 is $(VEX_NDS) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & vexVVVV_XmmReg; byte=0x64; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128 @@ -1750,76 +1827,95 @@ define pcodeop vpcmpgtq_avx ; # PCMPISTRI 4-266 PAGE 1386 LINE 71966 define pcodeop vpcmpistri_avx ; -:VPCMPISTRI XmmReg1, XmmReg2_m128, imm8 is $(VEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_WIG); byte=0x63; XmmReg1 ... & XmmReg2_m128; imm8 +:VPCMPISTRI XmmReg1, XmmReg2_m128, imm8 is $(VEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_WIG); byte=0x63 & check_ECX_dest; XmmReg1 ... & XmmReg2_m128; imm8 { - vpcmpistri_avx( XmmReg1, XmmReg2_m128, imm8:1 ); - # TODO missing destination or side effects + ECX = vpcmpistri_avx( XmmReg1, XmmReg2_m128, imm8:1 ); + build check_ECX_dest; } # PCMPISTRM 4-268 PAGE 1388 LINE 72052 define pcodeop vpcmpistrm_avx ; :VPCMPISTRM XmmReg1, XmmReg2_m128, imm8 is $(VEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_WIG); byte=0x62; XmmReg1 ... & XmmReg2_m128; imm8 { - vpcmpistrm_avx( XmmReg1, XmmReg2_m128, imm8:1 ); - # TODO missing destination or side effects + XMM0 = vpcmpistrm_avx( XmmReg1, XmmReg2_m128, imm8:1 ); } # PEXTRB/PEXTRD/PEXTRQ 4-274 PAGE 1394 LINE 72322 -define pcodeop vpextrb_avx ; :VPEXTRB Rmr32, XmmReg1, imm8 is $(VEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W0); byte=0x14; mod=3 & XmmReg1 & Rmr32 & check_Rmr32_dest; imm8 { - local tmp8:1 = imm8; - local tmp = XmmReg1 >> (tmp8[0,3]*8); + local tmp8:1 = imm8 & 0xf; + local tmp = XmmReg1 >> (tmp8*8); Rmr32 = zext(tmp[0,8]); build check_Rmr32_dest; } :VPEXTRB m8, XmmReg1, imm8 is $(VEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W0); byte=0x14; (XmmReg1 ... & m8); imm8 { - local tmp8:1 = imm8; - local tmp = XmmReg1 >> (tmp8[0,3]*8); + local tmp8:1 = imm8 & 0xf; + local tmp = XmmReg1 >> (tmp8*8); m8 = tmp[0,8]; } # PEXTRB/PEXTRD/PEXTRQ 4-274 PAGE 1394 LINE 72326 -define pcodeop vpextrd_avx ; :VPEXTRD Rmr32, XmmReg1, imm8 is $(VEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W0); byte=0x16; mod=3 & XmmReg1 & Rmr32 & check_Rmr32_dest; imm8 { - local tmp = XmmReg1 >> (imm8*32); + local tmp8:1 = imm8 & 3; + local tmp = XmmReg1 >> (tmp8*32); Rmr32 = tmp(0); build check_Rmr32_dest; } :VPEXTRD m32, XmmReg1, imm8 is $(VEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W0); byte=0x16; XmmReg1 ... & m32; imm8 { - local tmp = XmmReg1 >> (imm8*32); + local tmp8:1 = imm8 & 3; + local tmp = XmmReg1 >> (tmp8*32); m32 = tmp(0); } # PEXTRB/PEXTRD/PEXTRQ 4-274 PAGE 1394 LINE 72330 -define pcodeop vpextrq_avx ; @ifdef IA64 :VPEXTRQ rm64, XmmReg1, imm8 is $(VEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W1); byte=0x16; XmmReg1 ... & rm64; imm8 { - rm64 = vpextrq_avx( XmmReg1, imm8:1 ); + local tmp8:1 = imm8 & 1; + local tmp = XmmReg1 >> (tmp8*64); + rm64 = tmp(0); } @endif # PEXTRW 4-277 PAGE 1397 LINE 72478 -define pcodeop vpextrw_avx ; -:VPEXTRW Reg32, XmmReg2, imm8 is $(VEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W0); byte=0xC5; Reg32 & (mod=0x3 & XmmReg2); imm8 +:VPEXTRW Reg32, XmmReg2, imm8 is $(VEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG); byte=0xC5; Reg32 & check_Reg32_dest & (mod=0x3 & XmmReg2); imm8 { - Reg32 = vpextrw_avx( XmmReg2, imm8:1 ); - # TODO Reg64 = zext(Reg32) + local sel:1 = imm8 & 0x7; + local tmp = XmmReg2 >> (sel * 16); + Reg32 = zext(tmp[0,16]); + build check_Reg32_dest; } # PEXTRW 4-277 PAGE 1397 LINE 72483 -:VPEXTRW Reg32_m16, XmmReg1, imm8 is $(VEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W0); byte=0x15; XmmReg1 ... & Reg32_m16; imm8 +:VPEXTRW Reg32, XmmReg1, imm8 is $(VEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_WIG); byte=0x15; XmmReg1 & mod=3 & Reg32 & check_Reg32_dest; imm8 +{ + local sel:1 = imm8 & 0x7; + local tmp = XmmReg1 >> (sel * 16); + Reg32 = zext(tmp[0,16]); + build check_Reg32_dest; +} + +:VPEXTRW m16, XmmReg1, imm8 is $(VEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_WIG); byte=0x15; XmmReg1 ... & m16; imm8 { - Reg32_m16 = vpextrw_avx( XmmReg1, imm8:1 ); - # TODO Reg64 = zext(Reg32) + local sel:1 = imm8 & 7; + local tmp = XmmReg1 >> (sel*16); + m16 = tmp[0,16]; } +:VPEXTRW m16, XmmReg1, imm8 is $(VEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W0); byte=0x15; XmmReg1 ... & m16; imm8 +{ + local sel:1 = imm8 & 0x7; + local tmp = XmmReg1 >> (sel * 16); + local res:2 = tmp(0); + m16 = res; +} + + # PHADDW/PHADDD 4-280 PAGE 1400 LINE 72627 define pcodeop vphaddw_avx ; :VPHADDW XmmReg1, vexVVVV_XmmReg, XmmReg2_m128 is $(VEX_NDS) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_WIG) & vexVVVV_XmmReg; byte=0x01; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128 @@ -1884,27 +1980,18 @@ define pcodeop vpinsrb_avx ; ZmmReg1 = zext(tmp); } -# PINSRB/PINSRD/PINSRQ 4-293 PAGE 1413 LINE 73324 -define pcodeop vpinsrd_avx ; -:VPINSRD XmmReg1, vexVVVV_XmmReg, rm32, imm8 is $(VEX_NDS) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W0) & vexVVVV_XmmReg; byte=0x22; (XmmReg1 & ZmmReg1) ... & rm32; imm8 -{ - local tmp:16 = vpinsrd_avx( vexVVVV_XmmReg, rm32, imm8:1 ); - ZmmReg1 = zext(tmp); -} - -# PINSRB/PINSRD/PINSRQ 4-293 PAGE 1413 LINE 73327 -define pcodeop vpinsrq_avx ; +# PINSRW 4-296 PAGE 1416 LINE 73446 +define pcodeop vpinsrw_avx ; @ifdef IA64 -:VPINSRQ XmmReg1, vexVVVV_XmmReg, rm64, imm8 is $(VEX_NDS) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W1) & vexVVVV_XmmReg; byte=0x22; (XmmReg1 & ZmmReg1) ... & rm64; imm8 +:VPINSRW XmmReg1, vexVVVV_XmmReg, Reg32_m16, imm8 is $(LONGMODE_ON) & $(VEX_NDS) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & vexVVVV_XmmReg; byte=0xC4; (XmmReg1 & ZmmReg1) ... & Reg32_m16; imm8 { - local tmp:16 = vpinsrq_avx( vexVVVV_XmmReg, rm64, imm8:1 ); + local tmp:16 = vpinsrw_avx( vexVVVV_XmmReg, Reg32_m16, imm8:1 ); ZmmReg1 = zext(tmp); } @endif -# PINSRW 4-296 PAGE 1416 LINE 73446 -define pcodeop vpinsrw_avx ; -:VPINSRW XmmReg1, vexVVVV_XmmReg, Reg32_m16, imm8 is $(VEX_NDS) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W0) & vexVVVV_XmmReg; byte=0xC4; (XmmReg1 & ZmmReg1) ... & Reg32_m16; imm8 +# Footnote in manual: In 64-bit mode, VEX.W1 is ignored for VPINSRW (similar to legacy REX.W=1 prefix in PINSRW). +:VPINSRW XmmReg1, vexVVVV_XmmReg, Reg32_m16, imm8 is $(LONGMODE_OFF) & $(VEX_NDS) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W0) & vexVVVV_XmmReg; byte=0xC4; (XmmReg1 & ZmmReg1) ... & Reg32_m16; imm8 { local tmp:16 = vpinsrw_avx( vexVVVV_XmmReg, Reg32_m16, imm8:1 ); ZmmReg1 = zext(tmp); @@ -2687,19 +2774,21 @@ define pcodeop vsqrtps_avx ; } # SQRTSD 4-638 PAGE 1758 LINE 91272 -define pcodeop vsqrtsd_avx ; :VSQRTSD XmmReg1, vexVVVV_XmmReg, XmmReg2_m64 is $(VEX_NDS) & $(VEX_L128) & $(VEX_PRE_F2) & $(VEX_0F) & $(VEX_WIG) & vexVVVV_XmmReg; byte=0x51; (XmmReg1 & ZmmReg1) ... & XmmReg2_m64 { - local tmp:16 = vsqrtsd_avx( vexVVVV_XmmReg, XmmReg2_m64 ); - ZmmReg1 = zext(tmp); + local m:16 = XmmReg2_m64; + XmmReg1[0,64] = sqrt(vexVVVV_XmmReg[0,64]); + XmmReg1[64,64]= m[64,64]; + ZmmReg1 = zext(XmmReg1); } # SQRTSS 4-640 PAGE 1760 LINE 91367 -define pcodeop vsqrtss_avx ; :VSQRTSS XmmReg1, vexVVVV_XmmReg, XmmReg2_m32 is $(VEX_NDS) & $(VEX_L128) & $(VEX_PRE_F3) & $(VEX_0F) & $(VEX_WIG) & vexVVVV_XmmReg; byte=0x51; (XmmReg1 & ZmmReg1) ... & XmmReg2_m32 { - local tmp:16 = vsqrtss_avx( vexVVVV_XmmReg, XmmReg2_m32 ); - ZmmReg1 = zext(tmp); + local m:16 = XmmReg2_m32; + XmmReg1[0,32] = sqrt(vexVVVV_XmmReg[0,32]); + XmmReg1[32,96]= m[32,96]; + ZmmReg1 = zext(XmmReg1); } # STMXCSR 4-647 PAGE 1767 LINE 91697 @@ -3054,9 +3143,9 @@ define pcodeop vtestps_avx ; local val1 = YmmReg2_m256; local val2 = YmmReg1; local ztest = val1 & val2; - ZF = (ztest[31,1] | ztest[63,1] | ztest[95,1] | ztest[127,1] | ztest[160,1] | ztest[191,1] | ztest[224,1] | ztest[255,1]) == 0; + ZF = (ztest[31,1] | ztest[63,1] | ztest[95,1] | ztest[127,1] | ztest[159,1] | ztest[191,1] | ztest[223,1] | ztest[255,1]) == 0; local ctest = val1 & ~val2; - CF = (ctest[31,1] | ctest[63,1] | ctest[95,1] | ctest[127,1] | ctest[160,1] | ctest[191,1] | ctest[224,1] | ctest[255,1]) == 0; + CF = (ctest[31,1] | ctest[63,1] | ctest[95,1] | ctest[127,1] | ctest[159,1] | ctest[191,1] | ctest[223,1] | ctest[255,1]) == 0; AF = 0; OF = 0; PF = 0; diff --git a/pypcode/processors/x86/data/languages/avx2.sinc b/pypcode/processors/x86/data/languages/avx2.sinc index 5bba08c..b465d62 100644 --- a/pypcode/processors/x86/data/languages/avx2.sinc +++ b/pypcode/processors/x86/data/languages/avx2.sinc @@ -75,35 +75,95 @@ define pcodeop vpackuswb_avx2 ; } # PADDB/PADDW/PADDD/PADDQ 4-204 PAGE 1324 LINE 68666 -define pcodeop vpaddb_avx2 ; :VPADDB YmmReg1, vexVVVV_YmmReg, YmmReg2_m256 is $(VEX_NDS) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & vexVVVV_YmmReg; byte=0xFC; (YmmReg1 & ZmmReg1) ... & YmmReg2_m256 { - local tmp:32 = vpaddb_avx2( vexVVVV_YmmReg, YmmReg2_m256 ); - ZmmReg1 = zext(tmp); + local result:32 = 0; + result[0,8] = vexVVVV_YmmReg[0,8] + YmmReg2_m256[0,8]; + result[8,8] = vexVVVV_YmmReg[8,8] + YmmReg2_m256[8,8]; + result[16,8] = vexVVVV_YmmReg[16,8] + YmmReg2_m256[16,8]; + result[24,8] = vexVVVV_YmmReg[24,8] + YmmReg2_m256[24,8]; + result[32,8] = vexVVVV_YmmReg[32,8] + YmmReg2_m256[32,8]; + result[40,8] = vexVVVV_YmmReg[40,8] + YmmReg2_m256[40,8]; + result[48,8] = vexVVVV_YmmReg[48,8] + YmmReg2_m256[48,8]; + result[56,8] = vexVVVV_YmmReg[56,8] + YmmReg2_m256[56,8]; + result[64,8] = vexVVVV_YmmReg[64,8] + YmmReg2_m256[64,8]; + result[72,8] = vexVVVV_YmmReg[72,8] + YmmReg2_m256[72,8]; + result[80,8] = vexVVVV_YmmReg[80,8] + YmmReg2_m256[80,8]; + result[88,8] = vexVVVV_YmmReg[88,8] + YmmReg2_m256[88,8]; + result[96,8] = vexVVVV_YmmReg[96,8] + YmmReg2_m256[96,8]; + result[104,8] = vexVVVV_YmmReg[104,8] + YmmReg2_m256[104,8]; + result[112,8] = vexVVVV_YmmReg[112,8] + YmmReg2_m256[112,8]; + result[120,8] = vexVVVV_YmmReg[120,8] + YmmReg2_m256[120,8]; + result[128,8] = vexVVVV_YmmReg[128,8] + YmmReg2_m256[128,8]; + result[136,8] = vexVVVV_YmmReg[136,8] + YmmReg2_m256[136,8]; + result[144,8] = vexVVVV_YmmReg[144,8] + YmmReg2_m256[144,8]; + result[152,8] = vexVVVV_YmmReg[152,8] + YmmReg2_m256[152,8]; + result[160,8] = vexVVVV_YmmReg[160,8] + YmmReg2_m256[160,8]; + result[168,8] = vexVVVV_YmmReg[168,8] + YmmReg2_m256[168,8]; + result[176,8] = vexVVVV_YmmReg[176,8] + YmmReg2_m256[176,8]; + result[184,8] = vexVVVV_YmmReg[184,8] + YmmReg2_m256[184,8]; + result[192,8] = vexVVVV_YmmReg[192,8] + YmmReg2_m256[192,8]; + result[200,8] = vexVVVV_YmmReg[200,8] + YmmReg2_m256[200,8]; + result[208,8] = vexVVVV_YmmReg[208,8] + YmmReg2_m256[208,8]; + result[216,8] = vexVVVV_YmmReg[216,8] + YmmReg2_m256[216,8]; + result[224,8] = vexVVVV_YmmReg[224,8] + YmmReg2_m256[224,8]; + result[232,8] = vexVVVV_YmmReg[232,8] + YmmReg2_m256[232,8]; + result[240,8] = vexVVVV_YmmReg[240,8] + YmmReg2_m256[240,8]; + result[248,8] = vexVVVV_YmmReg[248,8] + YmmReg2_m256[248,8]; + + ZmmReg1 = zext(result); } # PADDB/PADDW/PADDD/PADDQ 4-204 PAGE 1324 LINE 68668 -define pcodeop vpaddw_avx2 ; :VPADDW YmmReg1, vexVVVV_YmmReg, YmmReg2_m256 is $(VEX_NDS) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & vexVVVV_YmmReg; byte=0xFD; (YmmReg1 & ZmmReg1) ... & YmmReg2_m256 { - local tmp:32 = vpaddw_avx2( vexVVVV_YmmReg, YmmReg2_m256 ); - ZmmReg1 = zext(tmp); + local result:32 = 0; + result[0,16] = vexVVVV_YmmReg[0,16] + YmmReg2_m256[0,16]; + result[16,16] = vexVVVV_YmmReg[16,16] + YmmReg2_m256[16,16]; + result[32,16] = vexVVVV_YmmReg[32,16] + YmmReg2_m256[32,16]; + result[48,16] = vexVVVV_YmmReg[48,16] + YmmReg2_m256[48,16]; + result[64,16] = vexVVVV_YmmReg[64,16] + YmmReg2_m256[64,16]; + result[80,16] = vexVVVV_YmmReg[80,16] + YmmReg2_m256[80,16]; + result[96,16] = vexVVVV_YmmReg[96,16] + YmmReg2_m256[96,16]; + result[112,16] = vexVVVV_YmmReg[112,16] + YmmReg2_m256[112,16]; + result[128,16] = vexVVVV_YmmReg[128,16] + YmmReg2_m256[128,16]; + result[144,16] = vexVVVV_YmmReg[144,16] + YmmReg2_m256[144,16]; + result[160,16] = vexVVVV_YmmReg[160,16] + YmmReg2_m256[160,16]; + result[176,16] = vexVVVV_YmmReg[176,16] + YmmReg2_m256[176,16]; + result[192,16] = vexVVVV_YmmReg[192,16] + YmmReg2_m256[192,16]; + result[208,16] = vexVVVV_YmmReg[208,16] + YmmReg2_m256[208,16]; + result[224,16] = vexVVVV_YmmReg[224,16] + YmmReg2_m256[224,16]; + result[240,16] = vexVVVV_YmmReg[240,16] + YmmReg2_m256[240,16]; + + ZmmReg1 = zext(result); } # PADDB/PADDW/PADDD/PADDQ 4-204 PAGE 1324 LINE 68670 -define pcodeop vpaddd_avx2 ; :VPADDD YmmReg1, vexVVVV_YmmReg, YmmReg2_m256 is $(VEX_NDS) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & vexVVVV_YmmReg; byte=0xFE; (YmmReg1 & ZmmReg1) ... & YmmReg2_m256 { - local tmp:32 = vpaddd_avx2( vexVVVV_YmmReg, YmmReg2_m256 ); - ZmmReg1 = zext(tmp); + local result:32 = 0; + result[0,32] = vexVVVV_YmmReg[0,32] + YmmReg2_m256[0,32]; + result[32,32] = vexVVVV_YmmReg[32,32] + YmmReg2_m256[32,32]; + result[64,32] = vexVVVV_YmmReg[64,32] + YmmReg2_m256[64,32]; + result[96,32] = vexVVVV_YmmReg[96,32] + YmmReg2_m256[96,32]; + result[128,32] = vexVVVV_YmmReg[128,32] + YmmReg2_m256[128,32]; + result[160,32] = vexVVVV_YmmReg[160,32] + YmmReg2_m256[160,32]; + result[192,32] = vexVVVV_YmmReg[192,32] + YmmReg2_m256[192,32]; + result[224,32] = vexVVVV_YmmReg[224,32] + YmmReg2_m256[224,32]; + + ZmmReg1 = zext(result); } # PADDB/PADDW/PADDD/PADDQ 4-204 PAGE 1324 LINE 68672 -define pcodeop vpaddq_avx2 ; :VPADDQ YmmReg1, vexVVVV_YmmReg, YmmReg2_m256 is $(VEX_NDS) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & vexVVVV_YmmReg; byte=0xD4; (YmmReg1 & ZmmReg1) ... & YmmReg2_m256 { - local tmp:32 = vpaddq_avx2( vexVVVV_YmmReg, YmmReg2_m256 ); - ZmmReg1 = zext(tmp); + local result:32 = 0; + result[0,64] = vexVVVV_YmmReg[0,64] + YmmReg2_m256[0,64]; + result[64,64] = vexVVVV_YmmReg[64,64] + YmmReg2_m256[64,64]; + result[128,64] = vexVVVV_YmmReg[128,64] + YmmReg2_m256[128,64]; + result[192,64] = vexVVVV_YmmReg[192,64] + YmmReg2_m256[192,64]; + + ZmmReg1 = zext(result); } # PADDSB/PADDSW 4-211 PAGE 1331 LINE 69045 diff --git a/pypcode/processors/x86/data/languages/avx2_manual.sinc b/pypcode/processors/x86/data/languages/avx2_manual.sinc index ad61779..7fdaafa 100644 --- a/pypcode/processors/x86/data/languages/avx2_manual.sinc +++ b/pypcode/processors/x86/data/languages/avx2_manual.sinc @@ -1,13 +1,15 @@ # VINSERTI128/VINSERTI32x4/VINSERTI64x2/VINSERTI32x8/VINSERTI64x4 5-314 PAGE 2138 LINE 109785 -define pcodeop vinserti128 ; -:VINSERTI128 YmmReg1, vexVVVV_YmmReg, XmmReg2_m128, imm8 is $(VEX_NDS) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W0) & vexVVVV_YmmReg; byte=0x38; YmmReg1 ... & XmmReg2_m128; imm8 & imm8_0 { - local tmp:16 = XmmReg2_m128; - local cond0:16 = zext((imm8_0:1 & 0x1) == 0); - local cond1:16 = zext((imm8_0:1 & 0x1) == 1); - # ignoring all but the least significant bit - YmmReg1[0,128] = (cond0 * tmp) + (cond1 * vexVVVV_YmmReg[0,128]); - YmmReg1[128,128] = (cond0 * vexVVVV_YmmReg[128,128]) + (cond1 * tmp); - +:VINSERTI128 YmmReg1, vexVVVV_YmmReg, XmmReg2_m128, imm8 is $(VEX_NDS) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W0) & vexVVVV_YmmReg; byte=0x38; YmmReg1 ... & XmmReg2_m128; imm8 & imm8_0{ + local scr1l:16 = vexVVVV_YmmReg[0,128]; + local scr1h:16 = vexVVVV_YmmReg[128,128]; + local src2:16 = XmmReg2_m128; + local vcond:1 = (imm8_0:1 & 0x1) == 0; + local part1:16 = 0; + conditionalAssign(part1, vcond, src2, scr1l); + local part2:16 = 0; + conditionalAssign(part2, vcond, scr1h, src2); + YmmReg1[0,128] = part1; + YmmReg1[128,128] = part2; } # VGATHERDPD/VGATHERQPD 5-251 PAGE 2075 LINE 106903 diff --git a/pypcode/processors/x86/data/languages/avx512.sinc b/pypcode/processors/x86/data/languages/avx512.sinc index f0d8908..b58d129 100644 --- a/pypcode/processors/x86/data/languages/avx512.sinc +++ b/pypcode/processors/x86/data/languages/avx512.sinc @@ -147,9 +147,10 @@ define pcodeop vandps_avx512vl ; :VANDPS YmmReg1^YmmOpMask32, evexV5_YmmReg, YmmReg2_m256_m32bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_NONE) & $(VEX_0F) & $(VEX_W0) & evexV5_YmmReg; byte=0x54; (YmmReg1 & ZmmReg1 & YmmOpMask32) ... & YmmReg2_m256_m32bcst [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) { - local tmp:32 = vandps_avx512vl( evexV5_YmmReg, YmmReg2_m256_m32bcst ); + YmmResult = vandps_avx512vl( evexV5_YmmReg, YmmReg2_m256_m32bcst ); + YmmMask = YmmReg1; build YmmOpMask32; - + ZmmReg1 = zext(YmmResult); } @@ -510,11 +511,11 @@ define pcodeop vcvtps2pd_avx512f ; # CVTSD2SI 3-253 PAGE 823 LINE 44320 define pcodeop vcvtsd2si_avx512f ; -:VCVTSD2SI Reg32, XmmReg2_m64 is $(EVEX_NONE) & $(VEX_LIG) & $(VEX_PRE_F2) & $(VEX_0F) & $(VEX_W0); byte=0x2D; Reg32 ... & XmmReg2_m64 +:VCVTSD2SI Reg32, XmmReg2_m64 is $(EVEX_NONE) & $(VEX_LIG) & $(VEX_PRE_F2) & $(VEX_0F) & $(VEX_W0); byte=0x2D; (Reg32 & check_Reg32_dest) ... & XmmReg2_m64 [ evexD8Type = 1; evexTType = 5; ] # (TupleType T1F) { Reg32 = vcvtsd2si_avx512f( XmmReg2_m64 ); - # TODO Reg64 = zext(Reg32) + build check_Reg32_dest; } # CVTSD2SI 3-253 PAGE 823 LINE 44322 @@ -590,11 +591,11 @@ define pcodeop vcvtss2sd_avx512f ; # CVTSS2SI 3-263 PAGE 833 LINE 44839 define pcodeop vcvtss2si_avx512f ; -:VCVTSS2SI Reg32, XmmReg2_m32 is $(EVEX_NONE) & $(VEX_LIG) & $(VEX_PRE_F3) & $(VEX_0F) & $(VEX_W0); byte=0x2D; Reg32 ... & XmmReg2_m32 +:VCVTSS2SI Reg32, XmmReg2_m32 is $(EVEX_NONE) & $(VEX_LIG) & $(VEX_PRE_F3) & $(VEX_0F) & $(VEX_W0); byte=0x2D; (Reg32 & check_Reg32_dest) ... & XmmReg2_m32 [ evexD8Type = 1; evexTType = 5; ] # (TupleType T1F) { Reg32 = vcvtss2si_avx512f( XmmReg2_m32 ); - # TODO Reg64 = zext(Reg32) + build check_Reg32_dest; } # CVTSS2SI 3-263 PAGE 833 LINE 44841 @@ -672,11 +673,11 @@ define pcodeop vcvttps2dq_avx512f ; # CVTTSD2SI 3-274 PAGE 844 LINE 45385 define pcodeop vcvttsd2si_avx512f ; -:VCVTTSD2SI Reg32, XmmReg2_m64 is $(EVEX_NONE) & $(VEX_LIG) & $(VEX_PRE_F2) & $(VEX_0F) & $(VEX_W0); byte=0x2C; Reg32 ... & XmmReg2_m64 +:VCVTTSD2SI Reg32, XmmReg2_m64 is $(EVEX_NONE) & $(VEX_LIG) & $(VEX_PRE_F2) & $(VEX_0F) & $(VEX_W0); byte=0x2C; (Reg32 & check_Reg32_dest) ... & XmmReg2_m64 [ evexD8Type = 1; evexTType = 5; ] # (TupleType T1F) { Reg32 = vcvttsd2si_avx512f( XmmReg2_m64 ); - # TODO Reg64 = zext(Reg32) + build check_Reg32_dest; } # CVTTSD2SI 3-274 PAGE 844 LINE 45388 @@ -690,11 +691,11 @@ define pcodeop vcvttsd2si_avx512f ; # CVTTSS2SI 3-276 PAGE 846 LINE 45479 define pcodeop vcvttss2si_avx512f ; -:VCVTTSS2SI Reg32, XmmReg2_m32 is $(EVEX_NONE) & $(VEX_LIG) & $(VEX_PRE_F3) & $(VEX_0F) & $(VEX_W0); byte=0x2C; Reg32 ... & XmmReg2_m32 +:VCVTTSS2SI Reg32, XmmReg2_m32 is $(EVEX_NONE) & $(VEX_LIG) & $(VEX_PRE_F3) & $(VEX_0F) & $(VEX_W0); byte=0x2C; (Reg32 & check_Reg32_dest) ... & XmmReg2_m32 [ evexD8Type = 1; evexTType = 5; ] # (TupleType T1F) { Reg32 = vcvttss2si_avx512f( XmmReg2_m32 ); - # TODO Reg64 = zext(Reg32) + build check_Reg32_dest; } # CVTTSS2SI 3-276 PAGE 846 LINE 45482 @@ -1174,10 +1175,11 @@ define pcodeop vmovaps_avx512f ; @endif # MOVD/MOVQ 4-55 PAGE 1175 LINE 61370 -:VMOVD rm32, XmmReg1 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W0); byte=0x7E; XmmReg1 ... & rm32 +:VMOVD rm32, XmmReg1 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W0); byte=0x7E; (XmmReg1 & check_rm32_dest) ... & rm32 [ evexD8Type = 1; evexTType = 3; ] # (TupleType T1S-MR) { rm32 = XmmReg1[0,32]; + build check_rm32_dest; } # MOVD/MOVQ 4-55 PAGE 1175 LINE 61372 @@ -1545,7 +1547,7 @@ define pcodeop vmovdqu64_avx512f ; local src1 = evexV5_XmmReg[64,64]; local src2 = XmmReg2[64,64]; XmmReg1[0,64] = src2; - XmmReg1[64,64] = src2; + XmmReg1[64,64] = src1; ZmmReg1 = zext(XmmReg1); } @@ -1556,7 +1558,7 @@ define pcodeop vmovhpd_avx512f ; { local src1 = evexV5_XmmReg[0,64]; local src2 = m64[0,64]; - XmmReg1[0,64] = src2; + XmmReg1[0,64] = src1; XmmReg1[64,64] = src2; ZmmReg1 = zext(XmmReg1); } @@ -2139,11 +2141,10 @@ define pcodeop vmulss_avx512f ; } # ORPD 4-168 PAGE 1288 LINE 66724 -define pcodeop vorpd_avx512vl ; :VORPD XmmReg1^XmmOpMask64, evexV5_XmmReg, XmmReg2_m128_m64bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W1) & evexV5_XmmReg; byte=0x56; (XmmReg1 & ZmmReg1 & XmmOpMask64) ... & XmmReg2_m128_m64bcst [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) { - XmmResult = vorpd_avx512vl( evexV5_XmmReg, XmmReg2_m128_m64bcst ); + XmmResult = evexV5_XmmReg | XmmReg2_m128_m64bcst; XmmMask = XmmReg1; build XmmOpMask64; ZmmReg1 = zext(XmmResult); @@ -2153,29 +2154,27 @@ define pcodeop vorpd_avx512vl ; :VORPD YmmReg1^YmmOpMask64, evexV5_YmmReg, YmmReg2_m256_m64bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W1) & evexV5_YmmReg; byte=0x56; (YmmReg1 & ZmmReg1 & YmmOpMask64) ... & YmmReg2_m256_m64bcst [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) { - YmmResult = vorpd_avx512vl( evexV5_YmmReg, YmmReg2_m256_m64bcst ); + YmmResult = evexV5_YmmReg | YmmReg2_m256_m64bcst; YmmMask = YmmReg1; build YmmOpMask64; ZmmReg1 = zext(YmmResult); } # ORPD 4-168 PAGE 1288 LINE 66730 -define pcodeop vorpd_avx512dq ; :VORPD ZmmReg1^ZmmOpMask64, evexV5_ZmmReg, ZmmReg2_m512_m64bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W1) & evexV5_ZmmReg; byte=0x56; (ZmmReg1 & ZmmOpMask64) ... & ZmmReg2_m512_m64bcst [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) { - ZmmResult = vorpd_avx512dq( evexV5_ZmmReg, ZmmReg2_m512_m64bcst ); + ZmmResult = evexV5_ZmmReg | ZmmReg2_m512_m64bcst; ZmmMask = ZmmReg1; build ZmmOpMask64; ZmmReg1 = ZmmResult; } # ORPS 4-171 PAGE 1291 LINE 66850 -define pcodeop vorps_avx512vl ; :VORPS XmmReg1^XmmOpMask32, evexV5_XmmReg, XmmReg2_m128_m32bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_NONE) & $(VEX_0F) & $(VEX_W0) & evexV5_XmmReg; byte=0x56; (XmmReg1 & ZmmReg1 & XmmOpMask32) ... & XmmReg2_m128_m32bcst [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) { - XmmResult = vorps_avx512vl( evexV5_XmmReg, XmmReg2_m128_m32bcst ); + XmmResult = evexV5_XmmReg | XmmReg2_m128_m32bcst; XmmMask = XmmReg1; build XmmOpMask32; ZmmReg1 = zext(XmmResult); @@ -2185,18 +2184,17 @@ define pcodeop vorps_avx512vl ; :VORPS YmmReg1^YmmOpMask32, evexV5_YmmReg, YmmReg2_m256_m32bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_NONE) & $(VEX_0F) & $(VEX_W0) & evexV5_YmmReg; byte=0x56; (YmmReg1 & ZmmReg1 & YmmOpMask32) ... & YmmReg2_m256_m32bcst [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) { - YmmResult = vorps_avx512vl( evexV5_YmmReg, YmmReg2_m256_m32bcst ); + YmmResult = evexV5_YmmReg | YmmReg2_m256_m32bcst; YmmMask = YmmReg1; build YmmOpMask32; ZmmReg1 = zext(YmmResult); } # ORPS 4-171 PAGE 1291 LINE 66856 -define pcodeop vorps_avx512dq ; :VORPS ZmmReg1^ZmmOpMask32, evexV5_ZmmReg, ZmmReg2_m512_m32bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_NONE) & $(VEX_0F) & $(VEX_W0) & evexV5_ZmmReg; byte=0x56; (ZmmReg1 & ZmmOpMask32) ... & ZmmReg2_m512_m32bcst [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) { - ZmmResult = vorps_avx512dq( evexV5_ZmmReg, ZmmReg2_m512_m32bcst ); + ZmmResult = evexV5_ZmmReg | ZmmReg2_m512_m32bcst; ZmmMask = ZmmReg1; build ZmmOpMask32; ZmmReg1 = ZmmResult; @@ -2716,20 +2714,20 @@ define pcodeop vpaddusw_avx512bw ; # PALIGNR 4-219 PAGE 1339 LINE 69495 define pcodeop vpalignr_avx512vl ; -:VPALIGNR XmmReg1^XmmOpMask8, evexV5_XmmReg, XmmReg2_m128 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_WIG) & evexV5_XmmReg; byte=0x0F; (XmmReg1 & ZmmReg1 & XmmOpMask8) ... & XmmReg2_m128 +:VPALIGNR XmmReg1^XmmOpMask8, evexV5_XmmReg, XmmReg2_m128, imm8 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_WIG) & evexV5_XmmReg; byte=0x0F; (XmmReg1 & ZmmReg1 & XmmOpMask8) ... & XmmReg2_m128; imm8 [ evexD8Type = 1; evexTType = 0; ] # (TupleType FVM) { - XmmResult = vpalignr_avx512vl( evexV5_XmmReg, XmmReg2_m128 ); + XmmResult = vpalignr_avx512vl( evexV5_XmmReg, XmmReg2_m128, imm8:1 ); XmmMask = XmmReg1; build XmmOpMask8; ZmmReg1 = zext(XmmResult); } # PALIGNR 4-219 PAGE 1339 LINE 69499 -:VPALIGNR YmmReg1^YmmOpMask8, evexV5_YmmReg, YmmReg2_m256 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_WIG) & evexV5_YmmReg; byte=0x0F; (YmmReg1 & ZmmReg1 & YmmOpMask8) ... & YmmReg2_m256 +:VPALIGNR YmmReg1^YmmOpMask8, evexV5_YmmReg, YmmReg2_m256, imm8 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_WIG) & evexV5_YmmReg; byte=0x0F; (YmmReg1 & ZmmReg1 & YmmOpMask8) ... & YmmReg2_m256; imm8 [ evexD8Type = 1; evexTType = 0; ] # (TupleType FVM) { - YmmResult = vpalignr_avx512vl( evexV5_YmmReg, YmmReg2_m256 ); + YmmResult = vpalignr_avx512vl( evexV5_YmmReg, YmmReg2_m256, imm8:1 ); YmmMask = YmmReg1; build YmmOpMask8; ZmmReg1 = zext(YmmResult); @@ -2737,15 +2735,16 @@ define pcodeop vpalignr_avx512vl ; # PALIGNR 4-219 PAGE 1339 LINE 69505 define pcodeop vpalignr_avx512bw ; -:VPALIGNR ZmmReg1^ZmmOpMask8, evexV5_ZmmReg, ZmmReg2_m512 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_WIG) & evexV5_ZmmReg; byte=0x0F; (ZmmReg1 & ZmmOpMask8) ... & ZmmReg2_m512 +:VPALIGNR ZmmReg1^ZmmOpMask8, evexV5_ZmmReg, ZmmReg2_m512, imm8 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_WIG) & evexV5_ZmmReg; byte=0x0F; (ZmmReg1 & ZmmOpMask8) ... & ZmmReg2_m512; imm8 [ evexD8Type = 1; evexTType = 0; ] # (TupleType FVM) { - ZmmResult = vpalignr_avx512bw( evexV5_ZmmReg, ZmmReg2_m512 ); + ZmmResult = vpalignr_avx512bw( evexV5_ZmmReg, ZmmReg2_m512, imm8:1 ); ZmmMask = ZmmReg1; build ZmmOpMask8; ZmmReg1 = ZmmResult; } + # PAND 4-223 PAGE 1343 LINE 69684 define pcodeop vpandd_avx512vl ; :VPANDD XmmReg1^XmmOpMask32, evexV5_XmmReg, XmmReg2_m128_m32bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W0) & evexV5_XmmReg; byte=0xDB; (XmmReg1 & ZmmReg1 & XmmOpMask32) ... & XmmReg2_m128_m32bcst @@ -3148,73 +3147,57 @@ define pcodeop vpcmpgtq_avx512f ; } # PEXTRB/PEXTRD/PEXTRQ 4-274 PAGE 1394 LINE 72334 -@ifdef IA64 -:VPEXTRB Reg32, XmmReg1, imm8 is $(LONGMODE_ON) & $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_WIG); byte=0x14; XmmReg1 & mod=3 & Reg32 & Reg64; imm8 -{ - local tmp = XmmReg1 >> (imm8*8); - Reg64 = zext(tmp[0,8]); -} -@endif - -:VPEXTRB Reg32, XmmReg1, imm8 is $(LONGMODE_OFF) & $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_WIG); byte=0x14; XmmReg1 & mod=3 & Reg32; imm8 +:VPEXTRB Rmr32, XmmReg1, imm8 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_WIG); byte=0x14; XmmReg1 & mod=3 & Rmr32 & check_Rmr32_dest; imm8 { - local tmp = XmmReg1 >> (imm8*8); - Reg32 = zext(tmp[0,8]); + local tmp8:1 = imm8 & 0xf; + local tmp = XmmReg1 >> (tmp8*8); + Rmr32 = zext(tmp[0,8]); + build check_Rmr32_dest; } :VPEXTRB m8, XmmReg1, imm8 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_WIG); byte=0x14; XmmReg1 ... & m8; imm8 { - local tmp = XmmReg1 >> (imm8*8); + local tmp8:1 = imm8 & 0xf; + local tmp = XmmReg1 >> (tmp8*8); m8 = tmp[0,8]; } # PEXTRB/PEXTRD/PEXTRQ 4-274 PAGE 1394 LINE 72339 -:VPEXTRD rm32, XmmReg1, imm8 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W0); byte=0x16; XmmReg1 ... & rm32; imm8 +:VPEXTRD rm32, XmmReg1, imm8 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W0); byte=0x16; XmmReg1 ... & (rm32 & check_rm32_dest); imm8 { - local tmp = XmmReg1 >> (imm8*32); + local tmp8:1 = imm8 & 0x3; + local tmp = XmmReg1 >> (tmp8*32); rm32 = tmp[0,32]; + build check_rm32_dest; } # PEXTRB/PEXTRD/PEXTRQ 4-274 PAGE 1394 LINE 72343 @ifdef IA64 :VPEXTRQ rm64, XmmReg1, imm8 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W1); byte=0x16; XmmReg1 ... & rm64; imm8 { - local tmp = XmmReg1 >> (imm8*64); + local tmp8:1 = imm8 & 0x1; + local tmp = XmmReg1 >> (tmp8*64); rm64 = tmp[0,64]; } @endif # PEXTRW 4-277 PAGE 1397 LINE 72488 -@ifdef IA64 -:VPEXTRW Reg32, XmmReg2, imm8 is $(LONGMODE_ON) & $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG); byte=0xC5; Reg32 & Reg64 & (mod=0x3 & XmmReg2); imm8 -{ - local tmp = XmmReg2 >> (imm8*16); - Reg64 = zext(tmp[0,16]); -} -@endif - -:VPEXTRW Reg32, XmmReg2, imm8 is $(LONGMODE_OFF) & $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG); byte=0xC5; Reg32 & (mod=0x3 & XmmReg2); imm8 +:VPEXTRW Reg32, XmmReg2, imm8 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG); byte=0xC5; Reg32 & check_Reg32_dest & (mod=0x3 & XmmReg2); imm8 { local tmp = XmmReg2 >> (imm8*16); Reg32 = zext(tmp[0,16]); + build check_Reg32_dest; } -# PEXTRW 4-277 PAGE 1397 LINE 72494 -@ifdef IA64 -:VPEXTRW Reg32, XmmReg1, imm8 is $(LONGMODE_ON) & $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_WIG); byte=0x15; XmmReg1 & mod=3 & Reg32 & Reg64; imm8 -{ - local tmp = XmmReg1 >> (imm8*16); - Reg64 = zext(tmp[0,16]); -} -@endif -:VPEXTRW Reg32, XmmReg1, imm8 is $(LONGMODE_OFF) & $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_WIG); byte=0x15; XmmReg1 & mod=3 & Reg32; imm8 +# PEXTRW 4-277 PAGE 1397 LINE 72494 +:VPEXTRW Rmr32, XmmReg1, imm8 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_WIG); byte=0x15; XmmReg1 & mod=3 & Rmr32 & check_Rmr32_dest; imm8 { local tmp = XmmReg1 >> (imm8*16); - Reg32 = zext(tmp[0,16]); + Rmr32 = zext(tmp[0,16]); + build check_Rmr32_dest; } - :VPEXTRW m16, XmmReg1, imm8 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_WIG); byte=0x15; XmmReg1 ... & m16; imm8 { local tmp = XmmReg1 >> (imm8*16); @@ -5486,10 +5469,11 @@ define pcodeop vpsubsw_avx512vl ; } # PSUBSB/PSUBSW 4-480 PAGE 1600 LINE 83302 -define pcodeop psubsw_avx512bw ; -:PSUBSW ZmmReg1^ZmmOpMask16, evexV5_ZmmReg, ZmmReg2_m512 is $(VEX_NDS) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & evexV5_ZmmReg; byte=0xE9; (ZmmReg1 & ZmmOpMask16) ... & ZmmReg2_m512 +define pcodeop vpsubsw_avx512bw ; +:VPSUBSW ZmmReg1^ZmmOpMask16, evexV5_ZmmReg, ZmmReg2_m512 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & evexV5_ZmmReg; byte=0xE9; (ZmmReg1 & ZmmOpMask16) ... & ZmmReg2_m512 { - ZmmReg1 = psubsw_avx512bw( evexV5_ZmmReg, ZmmReg2_m512 ); + ZmmResult = vpsubsw_avx512bw( evexV5_ZmmReg, ZmmReg2_m512 ); + ZmmMask = ZmmReg1; build ZmmOpMask16; ZmmReg1 = ZmmResult; } @@ -5814,70 +5798,6 @@ define pcodeop vpunpcklqdq_avx512f ; ZmmReg1 = ZmmResult; } -# PXOR 4-518 PAGE 1638 LINE 85503 -define pcodeop vpxord_avx512vl ; -:VPXORD XmmReg1^XmmOpMask32, evexV5_XmmReg, XmmReg2_m128_m32bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W0) & evexV5_XmmReg; byte=0xEF; (XmmReg1 & ZmmReg1 & XmmOpMask32) ... & XmmReg2_m128_m32bcst -[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) -{ - XmmResult = vpxord_avx512vl( evexV5_XmmReg, XmmReg2_m128_m32bcst ); - XmmMask = XmmReg1; - build XmmOpMask32; - ZmmReg1 = zext(XmmResult); -} - -# PXOR 4-518 PAGE 1638 LINE 85505 -:VPXORD YmmReg1^YmmOpMask32, evexV5_YmmReg, YmmReg2_m256_m32bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W0) & evexV5_YmmReg; byte=0xEF; (YmmReg1 & ZmmReg1 & YmmOpMask32) ... & YmmReg2_m256_m32bcst -[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) -{ - YmmResult = vpxord_avx512vl( evexV5_YmmReg, YmmReg2_m256_m32bcst ); - YmmMask = YmmReg1; - build YmmOpMask32; - ZmmReg1 = zext(YmmResult); -} - -# PXOR 4-518 PAGE 1638 LINE 85507 -define pcodeop vpxord_avx512f ; -:VPXORD ZmmReg1^ZmmOpMask32, evexV5_ZmmReg, ZmmReg2_m512_m32bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W0) & evexV5_ZmmReg; byte=0xEF; (ZmmReg1 & ZmmOpMask32) ... & ZmmReg2_m512_m32bcst -[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) -{ - ZmmResult = vpxord_avx512f( evexV5_ZmmReg, ZmmReg2_m512_m32bcst ); - ZmmMask = ZmmReg1; - build ZmmOpMask32; - ZmmReg1 = ZmmResult; -} - -# PXOR 4-518 PAGE 1638 LINE 85514 -define pcodeop vpxorq_avx512vl ; -:VPXORQ XmmReg1^XmmOpMask64, evexV5_XmmReg, XmmReg2_m128_m64bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W1) & evexV5_XmmReg; byte=0xEF; (XmmReg1 & ZmmReg1 & XmmOpMask64) ... & XmmReg2_m128_m64bcst -[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) -{ - XmmResult = vpxorq_avx512vl( evexV5_XmmReg, XmmReg2_m128_m64bcst ); - XmmMask = XmmReg1; - build XmmOpMask64; - ZmmReg1 = zext(XmmResult); -} - -# PXOR 4-518 PAGE 1638 LINE 85521 -:VPXORQ YmmReg1^YmmOpMask64, evexV5_YmmReg, YmmReg2_m256_m64bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W1) & evexV5_YmmReg; byte=0xEF; (YmmReg1 & ZmmReg1 & YmmOpMask64) ... & YmmReg2_m256_m64bcst -[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) -{ - YmmResult = vpxorq_avx512vl( evexV5_YmmReg, YmmReg2_m256_m64bcst ); - YmmMask = YmmReg1; - build YmmOpMask64; - ZmmReg1 = zext(YmmResult); -} - -# PXOR 4-518 PAGE 1638 LINE 85523 -define pcodeop vpxorq_avx512f ; -:VPXORQ ZmmReg1^ZmmOpMask64, evexV5_ZmmReg, ZmmReg2_m512_m64bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W1) & evexV5_ZmmReg; byte=0xEF; (ZmmReg1 & ZmmOpMask64) ... & ZmmReg2_m512_m64bcst -[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) -{ - ZmmResult = vpxorq_avx512f( evexV5_ZmmReg, ZmmReg2_m512_m64bcst ); - ZmmMask = ZmmReg1; - build ZmmOpMask64; - ZmmReg1 = ZmmResult; -} - # SHUFPD 4-617 PAGE 1737 LINE 90231 define pcodeop vshufpd_avx512vl ; :VSHUFPD XmmReg1^XmmOpMask64, evexV5_XmmReg, XmmReg2_m128_m64bcst, imm8 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W1) & evexV5_XmmReg; byte=0xC6; (XmmReg1 & ZmmReg1 & XmmOpMask64) ... & XmmReg2_m128_m64bcst; imm8 @@ -6007,25 +5927,27 @@ define pcodeop vsqrtps_avx512f ; } # SQRTSD 4-638 PAGE 1758 LINE 91276 -define pcodeop vsqrtsd_avx512f ; -:VSQRTSD XmmReg1^XmmOpMask64, evexV5_XmmReg, XmmReg2_m64 is $(EVEX_NONE) & $(VEX_LIG) & $(VEX_PRE_F2) & $(VEX_0F) & $(VEX_W1) & evexV5_XmmReg; byte=0x51; (XmmReg1 & ZmmReg1 & XmmOpMask64) ... & XmmReg2_m64 +:VSQRTSD XmmReg1^XmmOpMask, evexV5_XmmReg, XmmReg2_m64 is $(EVEX_NONE) & $(VEX_LIG) & $(VEX_PRE_F2) & $(VEX_0F) & $(VEX_W1) & evexV5_XmmReg; byte=0x51; (XmmReg1 & ZmmReg1 & XmmOpMask) ... & XmmReg2_m64 [ evexD8Type = 1; evexTType = 3; ] # (TupleType T1S) { - XmmResult = vsqrtsd_avx512f( evexV5_XmmReg, XmmReg2_m64 ); + XmmResult[0,64] = sqrt(XmmReg2_m64[0,64]); XmmMask = XmmReg1; - build XmmOpMask64; - ZmmReg1 = zext(XmmResult); + conditionalAssign(XmmResult[0,64], XmmOpMask[0,1], XmmResult[0,64], XmmMask[0,64]); + XmmReg1[0,64] = XmmResult[0,64]; + XmmReg1[64,64]= evexV5_XmmReg[64,64]; + ZmmReg1 = zext(XmmReg1); } # SQRTSS 4-640 PAGE 1760 LINE 91371 -define pcodeop vsqrtss_avx512f ; -:VSQRTSS XmmReg1^XmmOpMask32, evexV5_XmmReg, XmmReg2_m32 is $(EVEX_NONE) & $(VEX_LIG) & $(VEX_PRE_F3) & $(VEX_0F) & $(VEX_W0) & evexV5_XmmReg; byte=0x51; (XmmReg1 & ZmmReg1 & XmmOpMask32) ... & XmmReg2_m32 +:VSQRTSS XmmReg1^XmmOpMask, evexV5_XmmReg, XmmReg2_m32 is $(EVEX_NONE) & $(VEX_LIG) & $(VEX_PRE_F3) & $(VEX_0F) & $(VEX_W0) & evexV5_XmmReg; byte=0x51; (XmmReg1 & ZmmReg1 & XmmOpMask) ... & XmmReg2_m32 [ evexD8Type = 1; evexTType = 3; ] # (TupleType T1S) { - XmmResult = vsqrtss_avx512f( evexV5_XmmReg, XmmReg2_m32 ); + XmmResult[0,32] = sqrt(XmmReg2_m32[0,32]); XmmMask = XmmReg1; - build XmmOpMask32; - ZmmReg1 = zext(XmmResult); + conditionalAssign(XmmResult[0,32], XmmOpMask[0,1], XmmResult[0,32], XmmMask[0,32]); + XmmReg1[0,32] = XmmResult[0,32]; + XmmReg1[32,96]=evexV5_XmmReg[32,96]; + ZmmReg1 = zext(XmmReg1); } # SUBPD 4-656 PAGE 1776 LINE 92120 @@ -6119,9 +6041,7 @@ define pcodeop vucomisd_avx512f ; :VUCOMISD XmmReg1, XmmReg2_m64 is $(EVEX_NONE) & $(VEX_LIG) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W1); byte=0x2E; (XmmReg1 & ZmmReg1) ... & XmmReg2_m64 [ evexD8Type = 1; evexTType = 3; ] # (TupleType T1S) { - local tmp:16 = vucomisd_avx512f( XmmReg2_m64 ); - ZmmReg1 = zext(tmp); - # TODO set flags AF, CF, OF, PF, SF, ZF + fucompe(XmmReg1[0,64], XmmReg2_m64[0,64]); } # UCOMISS 4-685 PAGE 1805 LINE 93507 @@ -6129,9 +6049,7 @@ define pcodeop vucomiss_avx512f ; :VUCOMISS XmmReg1, XmmReg2_m32 is $(EVEX_NONE) & $(VEX_LIG) & $(VEX_PRE_NONE) & $(VEX_0F) & $(VEX_W0); byte=0x2E; (XmmReg1 & ZmmReg1) ... & XmmReg2_m32 [ evexD8Type = 1; evexTType = 3; ] # (TupleType T1S) { - local tmp:16 = vucomiss_avx512f( XmmReg2_m32 ); - ZmmReg1 = zext(tmp); - # TODO set flags AF, CF, OF, PF, SF, ZF + fucompe(XmmReg1[0,32], XmmReg2_m32[0,32]); } # UNPCKHPD 4-688 PAGE 1808 LINE 93629 @@ -6993,11 +6911,11 @@ define pcodeop vcvtqq2ps_avx512dq ; # VCVTSD2USI 5-54 PAGE 1878 LINE 96907 define pcodeop vcvtsd2usi_avx512f ; -:VCVTSD2USI Reg32, XmmReg2_m64 is $(EVEX_NONE) & $(VEX_LIG) & $(VEX_PRE_F2) & $(VEX_0F) & $(VEX_W0); byte=0x79; Reg32 ... & XmmReg2_m64 +:VCVTSD2USI Reg32, XmmReg2_m64 is $(EVEX_NONE) & $(VEX_LIG) & $(VEX_PRE_F2) & $(VEX_0F) & $(VEX_W0); byte=0x79; (Reg32 & check_Reg32_dest) ... & XmmReg2_m64 [ evexD8Type = 1; evexTType = 5; ] # (TupleType T1F) { Reg32 = vcvtsd2usi_avx512f( XmmReg2_m64 ); - # TODO Reg64 = zext(Reg32) + build check_Reg32_dest; } # VCVTSD2USI 5-54 PAGE 1878 LINE 96909 @@ -7011,11 +6929,11 @@ define pcodeop vcvtsd2usi_avx512f ; # VCVTSS2USI 5-55 PAGE 1879 LINE 96967 define pcodeop vcvtss2usi_avx512f ; -:VCVTSS2USI Reg32, XmmReg2_m32 is $(EVEX_NONE) & $(VEX_LIG) & $(VEX_PRE_F3) & $(VEX_0F) & $(VEX_W0); byte=0x79; Reg32 ... & XmmReg2_m32 +:VCVTSS2USI Reg32, XmmReg2_m32 is $(EVEX_NONE) & $(VEX_LIG) & $(VEX_PRE_F3) & $(VEX_0F) & $(VEX_W0); byte=0x79; (Reg32 & check_Reg32_dest) ... & XmmReg2_m32 [ evexD8Type = 1; evexTType = 5; ] # (TupleType T1F) { Reg32 = vcvtss2usi_avx512f( XmmReg2_m32 ); - # TODO Reg64 = zext(Reg32) + build check_Reg32_dest; } # VCVTSS2USI 5-55 PAGE 1879 LINE 96969 @@ -7221,11 +7139,11 @@ define pcodeop vcvttps2uqq_avx512dq ; # VCVTTSD2USI 5-70 PAGE 1894 LINE 97722 define pcodeop vcvttsd2usi_avx512f ; -:VCVTTSD2USI Reg32, XmmReg2_m64 is $(EVEX_NONE) & $(VEX_LIG) & $(VEX_PRE_F2) & $(VEX_0F) & $(VEX_W0); byte=0x78; Reg32 ... & XmmReg2_m64 +:VCVTTSD2USI Reg32, XmmReg2_m64 is $(EVEX_NONE) & $(VEX_LIG) & $(VEX_PRE_F2) & $(VEX_0F) & $(VEX_W0); byte=0x78; (Reg32 & check_Reg32_dest) ... & XmmReg2_m64 [ evexD8Type = 1; evexTType = 5; ] # (TupleType T1F) { Reg32 = vcvttsd2usi_avx512f( XmmReg2_m64 ); - # TODO Reg64 = zext(Reg32) + build check_Reg32_dest; } # VCVTTSD2USI 5-70 PAGE 1894 LINE 97725 @@ -7239,11 +7157,11 @@ define pcodeop vcvttsd2usi_avx512f ; # VCVTTSS2USI 5-71 PAGE 1895 LINE 97782 define pcodeop vcvttss2usi_avx512f ; -:VCVTTSS2USI Reg32, XmmReg2_m32 is $(EVEX_NONE) & $(VEX_LIG) & $(VEX_PRE_F3) & $(VEX_0F) & $(VEX_W0); byte=0x78; Reg32 ... & XmmReg2_m32 +:VCVTTSS2USI Reg32, XmmReg2_m32 is $(EVEX_NONE) & $(VEX_LIG) & $(VEX_PRE_F3) & $(VEX_0F) & $(VEX_W0); byte=0x78; (Reg32 & check_Reg32_dest) ... & XmmReg2_m32 [ evexD8Type = 1; evexTType = 5; ] # (TupleType T1F) { Reg32 = vcvttss2usi_avx512f( XmmReg2_m32 ); - # TODO Reg64 = zext(Reg32) + build check_Reg32_dest; } # VCVTTSS2USI 5-71 PAGE 1895 LINE 97785 @@ -9330,18 +9248,18 @@ define pcodeop vfpclassps_avx512dq ; # VFPCLASSSD 5-247 PAGE 2071 LINE 106722 define pcodeop vfpclasssd_avx512dq ; -:VFPCLASSSD KReg_reg AVXOpMask, XmmReg2_m64 is $(EVEX_NONE) & $(VEX_LIG) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W1) & AVXOpMask; byte=0x67; KReg_reg ... & XmmReg2_m64 +:VFPCLASSSD KReg_reg AVXOpMask, XmmReg2_m64, imm8 is $(EVEX_NONE) & $(VEX_LIG) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W1) & AVXOpMask; byte=0x67; KReg_reg ... & XmmReg2_m64; imm8 [ evexD8Type = 1; evexTType = 3; ] # (TupleType T1S) { - KReg_reg = vfpclasssd_avx512dq( XmmReg2_m64, AVXOpMask ); + KReg_reg = vfpclasssd_avx512dq( XmmReg2_m64, AVXOpMask, imm8:1 ); } # VFPCLASSSS 5-249 PAGE 2073 LINE 106810 define pcodeop vfpclassss_avx512dq ; -:VFPCLASSSS KReg_reg AVXOpMask, XmmReg2_m32 is $(EVEX_NONE) & $(VEX_LIG) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W0) & AVXOpMask; byte=0x67; KReg_reg ... & XmmReg2_m32 +:VFPCLASSSS KReg_reg AVXOpMask, XmmReg2_m32, imm8 is $(EVEX_NONE) & $(VEX_LIG) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W0) & AVXOpMask; byte=0x67; KReg_reg ... & XmmReg2_m32; imm8 [ evexD8Type = 1; evexTType = 3; ] # (TupleType T1S) { - KReg_reg = vfpclassss_avx512dq( XmmReg2_m32, AVXOpMask ); + KReg_reg = vfpclassss_avx512dq( XmmReg2_m32, AVXOpMask, imm8:1 ); } # VGATHERDPS/VGATHERDPD 5-261 PAGE 2085 LINE 107357 @@ -12782,10 +12700,10 @@ define pcodeop vrangesd_avx512dq ; # VRANGESS 5-482 PAGE 2306 LINE 118473 define pcodeop vrangess_avx512dq ; -:VRANGESS XmmReg1^XmmOpMask32, evexV5_XmmReg, XmmReg2_m32 is $(EVEX_NONE) & $(VEX_LIG) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W0) & evexV5_XmmReg; byte=0x51; (XmmReg1 & ZmmReg1 & XmmOpMask32) ... & XmmReg2_m32 +:VRANGESS XmmReg1^XmmOpMask32, evexV5_XmmReg, XmmReg2_m32, imm8 is $(EVEX_NONE) & $(VEX_LIG) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W0) & evexV5_XmmReg; byte=0x51; (XmmReg1 & ZmmReg1 & XmmOpMask32) ... & XmmReg2_m32; imm8 [ evexD8Type = 1; evexTType = 3; ] # (TupleType T1S) { - XmmResult = vrangess_avx512dq( evexV5_XmmReg, XmmReg2_m32 ); + XmmResult = vrangess_avx512dq( evexV5_XmmReg, XmmReg2_m32, imm8:1 ); XmmMask = XmmReg1; build XmmOpMask32; ZmmReg1 = zext(XmmResult); @@ -13747,102 +13665,6 @@ define pcodeop vaesenclast_vaes ; ZmmReg1 = vaesenclast_vaes( evexV5_ZmmReg, ZmmReg2_m512 ); } -# GF2P8AFFINEINVQB 3-476 PAGE 1046 LINE 56498 -define pcodeop vgf2p8affineinvqb_avx512vl ; -:VGF2P8AFFINEINVQB XmmReg1 XmmOpMask8, evexV5_XmmReg, XmmReg2_m128_m64bcst, imm8 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W1) & XmmOpMask8 & evexV5_XmmReg; byte=0xCF; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128_m64bcst; imm8 -[ evexD8Type = 0; evexTType = 0; ] # (TupleType Full) -{ - XmmResult = vgf2p8affineinvqb_avx512vl( evexV5_XmmReg, XmmReg2_m128_m64bcst, imm8:1 ); - XmmMask = XmmReg1; - build XmmOpMask8; - ZmmReg1 = zext(XmmResult); -} - -# GF2P8AFFINEINVQB 3-476 PAGE 1046 LINE 56501 -:VGF2P8AFFINEINVQB YmmReg1 YmmOpMask8, evexV5_YmmReg, YmmReg2_m256_m64bcst, imm8 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W1) & YmmOpMask8 & evexV5_YmmReg; byte=0xCF; (YmmReg1 & ZmmReg1) ... & YmmReg2_m256_m64bcst; imm8 -[ evexD8Type = 0; evexTType = 0; ] # (TupleType Full) -{ - YmmResult = vgf2p8affineinvqb_avx512vl( evexV5_YmmReg, YmmReg2_m256_m64bcst, imm8:1 ); - YmmMask = YmmReg1; - build YmmOpMask8; - ZmmReg1 = zext(YmmResult); -} - -# GF2P8AFFINEINVQB 3-476 PAGE 1046 LINE 56504 -define pcodeop vgf2p8affineinvqb_avx512f ; -:VGF2P8AFFINEINVQB ZmmReg1 ZmmOpMask8, evexV5_ZmmReg, ZmmReg2_m512_m64bcst, imm8 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W1) & ZmmOpMask8 & evexV5_ZmmReg; byte=0xCF; ZmmReg1 ... & ZmmReg2_m512_m64bcst; imm8 -[ evexD8Type = 0; evexTType = 0; ] # (TupleType Full) -{ - ZmmResult = vgf2p8affineinvqb_avx512f( evexV5_ZmmReg, ZmmReg2_m512_m64bcst, imm8:1 ); - ZmmMask = ZmmReg1; - build ZmmOpMask8; - ZmmReg1 = ZmmResult; -} - -# GF2P8AFFINEQB 3-479 PAGE 1049 LINE 56642 -define pcodeop vgf2p8affineqb_avx512vl ; -:VGF2P8AFFINEQB XmmReg1 XmmOpMask8, evexV5_XmmReg, XmmReg2_m128_m64bcst, imm8 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W1) & XmmOpMask8 & evexV5_XmmReg; byte=0xCE; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128_m64bcst; imm8 -[ evexD8Type = 0; evexTType = 0; ] # (TupleType Full) -{ - XmmResult = vgf2p8affineqb_avx512vl( evexV5_XmmReg, XmmReg2_m128_m64bcst, imm8:1 ); - XmmMask = XmmReg1; - build XmmOpMask8; - ZmmReg1 = zext(XmmResult); -} - -# GF2P8AFFINEQB 3-479 PAGE 1049 LINE 56645 -:VGF2P8AFFINEQB YmmReg1 YmmOpMask8, evexV5_YmmReg, YmmReg2_m256_m64bcst, imm8 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W1) & YmmOpMask8 & evexV5_YmmReg; byte=0xCE; (YmmReg1 & ZmmReg1) ... & YmmReg2_m256_m64bcst; imm8 -[ evexD8Type = 0; evexTType = 0; ] # (TupleType Full) -{ - YmmResult = vgf2p8affineqb_avx512vl( evexV5_YmmReg, YmmReg2_m256_m64bcst, imm8:1 ); - YmmMask = YmmReg1; - build YmmOpMask8; - ZmmReg1 = zext(YmmResult); -} - -# GF2P8AFFINEQB 3-479 PAGE 1049 LINE 56648 -define pcodeop vgf2p8affineqb_avx512f ; -:VGF2P8AFFINEQB ZmmReg1 ZmmOpMask8, evexV5_ZmmReg, ZmmReg2_m512_m64bcst, imm8 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W1) & ZmmOpMask8 & evexV5_ZmmReg; byte=0xCE; ZmmReg1 ... & ZmmReg2_m512_m64bcst; imm8 -[ evexD8Type = 0; evexTType = 0; ] # (TupleType Full) -{ - ZmmResult = vgf2p8affineqb_avx512f( evexV5_ZmmReg, ZmmReg2_m512_m64bcst, imm8:1 ); - ZmmMask = ZmmReg1; - build ZmmOpMask8; - ZmmReg1 = ZmmResult; -} - -# GF2P8MULB 3-481 PAGE 1051 LINE 56754 -define pcodeop vgf2p8mulb_avx512vl ; -:VGF2P8MULB XmmReg1 XmmOpMask8, evexV5_XmmReg, XmmReg2_m128 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & XmmOpMask8 & evexV5_XmmReg; byte=0xCF; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128 -[ evexD8Type = 1; evexTType = 0; ] # (TupleType Full Mem) -{ - XmmResult = vgf2p8mulb_avx512vl( evexV5_XmmReg, XmmReg2_m128 ); - XmmMask = XmmReg1; - build XmmOpMask8; - ZmmReg1 = zext(XmmResult); -} - -# GF2P8MULB 3-481 PAGE 1051 LINE 56757 -:VGF2P8MULB YmmReg1 YmmOpMask8, evexV5_YmmReg, YmmReg2_m256 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & YmmOpMask8 & evexV5_YmmReg; byte=0xCF; (YmmReg1 & ZmmReg1) ... & YmmReg2_m256 -[ evexD8Type = 1; evexTType = 0; ] # (TupleType Full Mem) -{ - YmmResult = vgf2p8mulb_avx512vl( evexV5_YmmReg, YmmReg2_m256 ); - YmmMask = YmmReg1; - build YmmOpMask8; - ZmmReg1 = zext(YmmResult); -} - -# GF2P8MULB 3-481 PAGE 1051 LINE 56760 -define pcodeop vgf2p8mulb_avx512f ; -:VGF2P8MULB ZmmReg1 ZmmOpMask8, evexV5_ZmmReg, ZmmReg2_m512 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & ZmmOpMask8 & evexV5_ZmmReg; byte=0xCF; ZmmReg1 ... & ZmmReg2_m512 -[ evexD8Type = 1; evexTType = 0; ] # (TupleType Full Mem) -{ - ZmmResult = vgf2p8mulb_avx512f( evexV5_ZmmReg, ZmmReg2_m512 ); - ZmmMask = ZmmReg1; - build ZmmOpMask8; - ZmmReg1 = ZmmResult; -} - # PCLMULQDQ 4-242 PAGE 1362 LINE 76037 define pcodeop vpclmulqdq_vpclmulqdq ; :VPCLMULQDQ XmmReg1, evexV5_XmmReg, XmmReg2_m128, imm8 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_WIG) & evexV5_XmmReg; byte=0x44; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128; imm8 @@ -14535,9 +14357,10 @@ define pcodeop vcvtsh2sd_avx512fp16 ; # VCVTSH2SI 5-86 PAGE 1910 LINE 105738 define pcodeop vcvtsh2si_avx512fp16 ; -:VCVTSH2SI Reg32, XmmReg2_m16 is $(EVEX_NONE) & $(EVEX_LLIG) & $(VEX_PRE_F3) & $(VEX_MAP5) & $(VEX_W0); byte=0x2D; Reg32 ... & XmmReg2_m16 +:VCVTSH2SI Reg32, XmmReg2_m16 is $(EVEX_NONE) & $(EVEX_LLIG) & $(VEX_PRE_F3) & $(VEX_MAP5) & $(VEX_W0); byte=0x2D; (Reg32 & check_Reg32_dest) ... & XmmReg2_m16 { Reg32 = vcvtsh2si_avx512fp16( XmmReg2_m16 ); + build check_Reg32_dest; } # VCVTSH2SI 5-86 PAGE 1910 LINE 105740 @@ -14562,9 +14385,10 @@ define pcodeop vcvtsh2ss_avx512fp16 ; # VCVTSH2USI 5-88 PAGE 1912 LINE 105851 define pcodeop vcvtsh2usi_avx512fp16 ; -:VCVTSH2USI Reg32, XmmReg2_m16 is $(EVEX_NONE) & $(EVEX_LLIG) & $(VEX_PRE_F3) & $(VEX_MAP5) & $(VEX_W0); byte=0x79; Reg32 ... & XmmReg2_m16 +:VCVTSH2USI Reg32, XmmReg2_m16 is $(EVEX_NONE) & $(EVEX_LLIG) & $(VEX_PRE_F3) & $(VEX_MAP5) & $(VEX_W0); byte=0x79; (Reg32 & check_Reg32_dest) ... & XmmReg2_m16 { Reg32 = vcvtsh2usi_avx512fp16( XmmReg2_m16 ); + build check_Reg32_dest; } # VCVTSH2USI 5-88 PAGE 1912 LINE 105853 @@ -14786,9 +14610,10 @@ define pcodeop vcvttph2w_avx512fp16 ; # VCVTTSH2SI 5-119 PAGE 1943 LINE 107355 define pcodeop vcvttsh2si_avx512fp16 ; -:VCVTTSH2SI Reg32, XmmReg2_m16 is $(EVEX_NONE) & $(EVEX_LLIG) & $(VEX_PRE_F3) & $(VEX_MAP5) & $(VEX_W0); byte=0x2C; Reg32 ... & XmmReg2_m16 +:VCVTTSH2SI Reg32, XmmReg2_m16 is $(EVEX_NONE) & $(EVEX_LLIG) & $(VEX_PRE_F3) & $(VEX_MAP5) & $(VEX_W0); byte=0x2C; (Reg32 & check_Reg32_dest)... & XmmReg2_m16 { Reg32 = vcvttsh2si_avx512fp16( XmmReg2_m16 ); + build check_Reg32_dest; } # VCVTTSH2SI 5-119 PAGE 1943 LINE 107358 @@ -14801,9 +14626,10 @@ define pcodeop vcvttsh2si_avx512fp16 ; # VCVTTSH2USI 5-120 PAGE 1944 LINE 107409 define pcodeop vcvttsh2usi_avx512fp16 ; -:VCVTTSH2USI Reg32, XmmReg2_m16 is $(EVEX_NONE) & $(EVEX_LLIG) & $(VEX_PRE_F3) & $(VEX_MAP5) & $(VEX_W0); byte=0x78; Reg32 ... & XmmReg2_m16 +:VCVTTSH2USI Reg32, XmmReg2_m16 is $(EVEX_NONE) & $(EVEX_LLIG) & $(VEX_PRE_F3) & $(VEX_MAP5) & $(VEX_W0); byte=0x78; (Reg32 & check_Reg32_dest) ... & XmmReg2_m16 { Reg32 = vcvttsh2usi_avx512fp16( XmmReg2_m16 ); + build check_Reg32_dest; } # VCVTTSH2USI 5-120 PAGE 1944 LINE 107412 @@ -17648,11 +17474,10 @@ define pcodeop vsqrtph_avx512fp16 ; define pcodeop vsqrtsh_avx512fp16 ; :VSQRTSH XmmReg1^XmmOpMask, evexV5_XmmReg, XmmReg2_m16 is $(EVEX_NONE) & $(EVEX_LLIG) & $(VEX_PRE_F3) & $(VEX_MAP5) & $(VEX_W0) & XmmOpMask & evexV5_XmmReg; byte=0x51; (XmmReg1 & ZmmReg1) ... & XmmReg2_m16 { - XmmResult = vsqrtsh_avx512fp16( evexV5_XmmReg, XmmReg2_m16 ); + XmmResult[0,16] = sqrt(XmmReg2_m16[0,16]); XmmMask = XmmReg1; - build XmmOpMask; conditionalAssign(XmmResult[0,16], XmmOpMask[0,1], XmmResult[0,16], XmmMask[0,16]); - XmmResult[16,112] = XmmReg1[16,112]; # DEST[127:16] remains unchanged + XmmResult[16,112] = evexV5_XmmReg[16,112]; # DEST[127:16] = src1[127:16] ZmmReg1 = zext(XmmResult); } diff --git a/pypcode/processors/x86/data/languages/avx512_manual.sinc b/pypcode/processors/x86/data/languages/avx512_manual.sinc index ef603b1..80501bb 100644 --- a/pypcode/processors/x86/data/languages/avx512_manual.sinc +++ b/pypcode/processors/x86/data/languages/avx512_manual.sinc @@ -159,15 +159,17 @@ } # KMOVW/KMOVB/KMOVQ/KMOVD 3-499 PAGE 1069 LINE 56184 -:KMOVW Reg32, KReg_rm is $(VEX_NONE) & $(VEX_L128) & $(VEX_PRE_NONE) & $(VEX_0F) & $(VEX_W0); byte=0x93; Reg32 & KReg_rm +:KMOVW Reg32, KReg_rm is $(VEX_NONE) & $(VEX_L128) & $(VEX_PRE_NONE) & $(VEX_0F) & $(VEX_W0); byte=0x93; Reg32 & KReg_rm & check_Reg32_dest { Reg32 = zext(KReg_rm[0,16]); + build check_Reg32_dest; } # KMOVW/KMOVB/KMOVQ/KMOVD 3-499 PAGE 1069 LINE 56186 -:KMOVB Reg32, KReg_rm is $(VEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W0); byte=0x93; Reg32 & KReg_rm +:KMOVB Reg32, KReg_rm is $(VEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W0); byte=0x93; Reg32 & KReg_rm & check_Reg32_dest { Reg32 = zext(KReg_rm[0,8]); + build check_Reg32_dest; } # KMOVW/KMOVB/KMOVQ/KMOVD 3-499 PAGE 1069 LINE 56188 @@ -179,9 +181,10 @@ @endif # KMOVW/KMOVB/KMOVQ/KMOVD 3-499 PAGE 1069 LINE 56190 -:KMOVD Reg32, KReg_rm is $(VEX_NONE) & $(VEX_L128) & $(VEX_PRE_F2) & $(VEX_0F) & $(VEX_W0); byte=0x93; Reg32 & KReg_rm +:KMOVD Reg32, KReg_rm is $(VEX_NONE) & $(VEX_L128) & $(VEX_PRE_F2) & $(VEX_0F) & $(VEX_W0); byte=0x93; Reg32 & KReg_rm & check_Reg32_dest { Reg32 = KReg_rm[0,32]; + build check_Reg32_dest; } # KNOTW/KNOTB/KNOTQ/KNOTD 3-501 PAGE 1071 LINE 56266 @@ -1582,4 +1585,65 @@ define pcodeop vpmovuswb_avx512bw ; YmmMask = m256; build YmmOpMask8; m256 = zext(YmmResult); -} \ No newline at end of file +} + +# PXOR 4-518 PAGE 1638 LINE 85503 +:VPXORD XmmReg1^XmmOpMask32, evexV5_XmmReg, XmmReg2_m128_m32bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W0) & evexV5_XmmReg; byte=0xEF; (XmmReg1 & ZmmReg1 & XmmOpMask32) ... & XmmReg2_m128_m32bcst +[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) +{ + XmmResult = evexV5_XmmReg ^ XmmReg2_m128_m32bcst; + XmmMask = XmmReg1; + build XmmOpMask32; + ZmmReg1 = zext(XmmResult); +} + +# PXOR 4-518 PAGE 1638 LINE 85505 +:VPXORD YmmReg1^YmmOpMask32, evexV5_YmmReg, YmmReg2_m256_m32bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W0) & evexV5_YmmReg; byte=0xEF; (YmmReg1 & ZmmReg1 & YmmOpMask32) ... & YmmReg2_m256_m32bcst +[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) +{ + YmmResult = evexV5_YmmReg ^ YmmReg2_m256_m32bcst; + YmmMask = YmmReg1; + build YmmOpMask32; + ZmmReg1 = zext(YmmResult); +} + +# PXOR 4-518 PAGE 1638 LINE 85507 +:VPXORD ZmmReg1^ZmmOpMask32, evexV5_ZmmReg, ZmmReg2_m512_m32bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W0) & evexV5_ZmmReg; byte=0xEF; (ZmmReg1 & ZmmOpMask32) ... & ZmmReg2_m512_m32bcst +[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) +{ + ZmmResult = evexV5_ZmmReg ^ ZmmReg2_m512_m32bcst; + ZmmMask = ZmmReg1; + build ZmmOpMask32; + ZmmReg1 = ZmmResult; +} + +# PXOR 4-518 PAGE 1638 LINE 85514 +:VPXORQ XmmReg1^XmmOpMask64, evexV5_XmmReg, XmmReg2_m128_m64bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W1) & evexV5_XmmReg; byte=0xEF; (XmmReg1 & ZmmReg1 & XmmOpMask64) ... & XmmReg2_m128_m64bcst +[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) +{ + XmmResult = evexV5_XmmReg ^ XmmReg2_m128_m64bcst; + XmmMask = XmmReg1; + build XmmOpMask64; + ZmmReg1 = zext(XmmResult); +} + +# PXOR 4-518 PAGE 1638 LINE 85521 +:VPXORQ YmmReg1^YmmOpMask64, evexV5_YmmReg, YmmReg2_m256_m64bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W1) & evexV5_YmmReg; byte=0xEF; (YmmReg1 & ZmmReg1 & YmmOpMask64) ... & YmmReg2_m256_m64bcst +[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) +{ + YmmResult = evexV5_YmmReg ^ YmmReg2_m256_m64bcst; + YmmMask = YmmReg1; + build YmmOpMask64; + ZmmReg1 = zext(YmmResult); +} + +# PXOR 4-518 PAGE 1638 LINE 85523 +:VPXORQ ZmmReg1^ZmmOpMask64, evexV5_ZmmReg, ZmmReg2_m512_m64bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W1) & evexV5_ZmmReg; byte=0xEF; (ZmmReg1 & ZmmOpMask64) ... & ZmmReg2_m512_m64bcst +[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) +{ + ZmmResult = evexV5_ZmmReg ^ ZmmReg2_m512_m64bcst; + ZmmMask = ZmmReg1; + build ZmmOpMask64; + ZmmReg1 = ZmmResult; +} + diff --git a/pypcode/processors/x86/data/languages/avx_manual.sinc b/pypcode/processors/x86/data/languages/avx_manual.sinc index 9b84e34..15ab16d 100644 --- a/pypcode/processors/x86/data/languages/avx_manual.sinc +++ b/pypcode/processors/x86/data/languages/avx_manual.sinc @@ -192,6 +192,36 @@ ZmmReg1 = zext(XmmReg1); } +# PINSRB/PINSRD/PINSRQ 4-293 PAGE 1413 LINE 73324 +#define pcodeop vpinsrd_avx ; +:VPINSRD XmmReg1, vexVVVV_XmmReg, rm32, imm8 is $(VEX_NDS) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W0) & vexVVVV_XmmReg; byte=0x22; (XmmReg1 & ZmmReg1) ... & rm32; imm8 +{ + local tmp:4 = rm32; + local cond0:1 = (imm8:1 & 0x3) == 0; + local cond1:1 = (imm8:1 & 0x3) == 1; + local cond2:1 = (imm8:1 & 0x3) == 2; + local cond3:1 = (imm8:1 & 0x3) == 3; + conditionalAssign(XmmReg1[ 0,32], cond0, tmp, vexVVVV_XmmReg[ 0,32]); + conditionalAssign(XmmReg1[32,32], cond0, tmp, vexVVVV_XmmReg[32,32]); + conditionalAssign(XmmReg1[64,32], cond0, tmp, vexVVVV_XmmReg[64,32]); + conditionalAssign(XmmReg1[96,32], cond0, tmp, vexVVVV_XmmReg[96,32]); + ZmmReg1 = zext(XmmReg1); +} + +# PINSRB/PINSRD/PINSRQ 4-293 PAGE 1413 LINE 73327 +#define pcodeop vpinsrq_avx ; +@ifdef IA64 +:VPINSRQ XmmReg1, vexVVVV_XmmReg, rm64, imm8 is $(VEX_NDS) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W1) & vexVVVV_XmmReg; byte=0x22; (XmmReg1 & ZmmReg1) ... & rm64; imm8 +{ + local tmp:8 = rm64; + local cond0:8 = zext((imm8:1 & 0x1) == 0); + local cond1:8 = zext((imm8:1 & 0x1) == 1); + # ignoring all but the least significant bit + XmmReg1[0,64] = (cond0 * tmp) + (cond1 * vexVVVV_XmmReg[0,64]); + XmmReg1[64,64] = (cond0 * vexVVVV_XmmReg[64,64]) + (cond1 * tmp); + ZmmReg1 = zext(XmmReg1); +} +@endif # PMOVMSKB 4-338 PAGE 1458 LINE 75651 :VPMOVMSKB Reg32, XmmReg2 is $(VEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG); byte=0xD7; Reg32 & (mod=0x3 & XmmReg2) & check_Reg32_dest diff --git a/pypcode/processors/x86/data/languages/cet.sinc b/pypcode/processors/x86/data/languages/cet.sinc index 2d5d9ae..c29dbc9 100644 --- a/pypcode/processors/x86/data/languages/cet.sinc +++ b/pypcode/processors/x86/data/languages/cet.sinc @@ -50,7 +50,7 @@ define pcodeop writeToUserShadowStack; writeToShadowStack(rm32, Reg32); } @ifdef IA64 -:WRSSQ rm64,Reg64 is $(LONGMODE_ON) & vexMode=0 & $(REX_W) & byte=0x0f; byte=0x0f; byte=0x38; byte=0xf6; rm64 & Reg64 ... { +:WRSSQ rm64,Reg64 is $(LONGMODE_ON) & vexMode=0 & $(REX_W) & byte=0x0f; byte=0x38; byte=0xf6; rm64 & Reg64 ... { writeToShadowStack(rm64, Reg64); } @endif @@ -59,7 +59,7 @@ define pcodeop writeToUserShadowStack; writeToUserShadowStack(rm32, Reg32); } @ifdef IA64 -:WRUSSQ rm64,Reg64 is $(LONGMODE_ON) & vexMode=0 & $(PRE_66) & $(REX_W) & byte=0x0f; byte=0x0f; byte=0x38; byte=0xf5; rm64 & Reg64 ... { +:WRUSSQ rm64,Reg64 is $(LONGMODE_ON) & vexMode=0 & $(PRE_66) & $(REX_W) & byte=0x0f; byte=0x38; byte=0xf5; rm64 & Reg64 ... { writeToUserShadowStack(rm64, Reg64); } @endif diff --git a/pypcode/processors/x86/data/languages/cmpccxadd.sinc b/pypcode/processors/x86/data/languages/cmpccxadd.sinc new file mode 100644 index 0000000..037ebf7 --- /dev/null +++ b/pypcode/processors/x86/data/languages/cmpccxadd.sinc @@ -0,0 +1,27 @@ +#### +#### CMPccXADD instructions +#### + +@ifdef IA64 +:CMP^cc^"XADD" m32, Reg32, vexVVVV_r32 is $(VEX_NDS) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & vexVVVV_r32 & row=0xe & cc; Reg32 ... & m32 { + local op1 = m32; + local op2 = Reg32; + subflags(op1, op2); + local tmp = op1 - op2; + resultflags(tmp); + build cc; + if (!cc) goto inst_next; + m32 = vexVVVV_r32; +} + +:CMP^cc^"XADD" m64, Reg64, vexVVVV_r64 is $(VEX_NDS) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & vexVVVV_r64 & row=0xe & cc; Reg64 ... & m64 { + local op1 = m64; + local op2 = Reg64; + subflags(op1, op2); + local tmp = op1 - op2; + resultflags(tmp); + build cc; + if (!cc) goto inst_next; + m64 = vexVVVV_r64; +} +@endif \ No newline at end of file diff --git a/pypcode/processors/x86/data/languages/fma.sinc b/pypcode/processors/x86/data/languages/fma.sinc index b7b7b9d..297d3af 100644 --- a/pypcode/processors/x86/data/languages/fma.sinc +++ b/pypcode/processors/x86/data/languages/fma.sinc @@ -1,740 +1,981 @@ # # x86 FMA instructions # +macro fmadd(dest, src1, src2, src3) { + dest = (src1 f* src2) f+ src3; +} +macro fmadd132(dest, src1, src2, src3) { + fmadd(dest, src1, src3, src2); +} + +macro fmadd213(dest, src1, src2, src3) { + fmadd(dest, src2, src1, src3); +} + +macro fmadd231(dest, src1, src2, src3) { + fmadd(dest, src2, src3, src1); +} + +macro fmsub(dest, src1, src2, src3) { + dest = (src1 f* src2) f- src3; +} + +macro fmsub132(dest, src1, src2, src3) { + fmsub(dest, src1, src3, src2); +} + +macro fmsub213(dest, src1, src2, src3) { + fmsub(dest, src2, src1, src3); +} -# VFIXUPIMMSD 5-120 PAGE 1944 LINE 101211 -define pcodeop vfmadd132pd_fma ; +macro fmsub231(dest, src1, src2, src3) { + fmsub(dest, src2, src3, src1); +} + +macro fnmadd(dest, src1, src2, src3) { + dest = f- (src1 f* src2) f+ src3; +} + +macro fnmadd132(dest, src1, src2, src3) { + fnmadd(dest, src1, src3, src2); +} + +macro fnmadd213(dest, src1, src2, src3) { + fnmadd(dest, src2, src1, src3); +} + +macro fnmadd231(dest, src1, src2, src3) { + fnmadd(dest, src2, src3, src1); +} + +macro fnmsub(dest, src1, src2, src3) { + dest = f- (src1 f* src2) f- src3; +} + +macro fnmsub132(dest, src1, src2, src3) { + fnmsub(dest, src1, src3, src2); +} + +macro fnmsub213(dest, src1, src2, src3) { + fnmsub(dest, src2, src1, src3); +} + +macro fnmsub231(dest, src1, src2, src3) { + fnmsub(dest, src2, src3, src1); +} + +# VFMADD132PD/VFMADD213PD/VFMADD231PD :VFMADD132PD XmmReg1, vexVVVV_XmmReg, XmmReg2_m128 is $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & vexVVVV_XmmReg; byte=0x98; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128 { - local tmp:16 = vfmadd132pd_fma( XmmReg1, vexVVVV_XmmReg, XmmReg2_m128 ); - ZmmReg1 = zext(tmp); + fmadd132(XmmReg1[ 0,64],XmmReg1[ 0,64],vexVVVV_XmmReg[ 0,64],XmmReg2_m128[ 0,64]); + fmadd132(XmmReg1[64,64],XmmReg1[64,64],vexVVVV_XmmReg[64,64],XmmReg2_m128[64,64]); + ZmmReg1 = zext(XmmReg1); } -# VFIXUPIMMSD 5-120 PAGE 1944 LINE 101214 -define pcodeop vfmadd213pd_fma ; :VFMADD213PD XmmReg1, vexVVVV_XmmReg, XmmReg2_m128 is $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & vexVVVV_XmmReg; byte=0xA8; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128 { - local tmp:16 = vfmadd213pd_fma( XmmReg1, vexVVVV_XmmReg, XmmReg2_m128 ); - ZmmReg1 = zext(tmp); + + fmadd213(XmmReg1[ 0,64],XmmReg1[ 0,64],vexVVVV_XmmReg[ 0,64],XmmReg2_m128[ 0,64]); + fmadd213(XmmReg1[64,64],XmmReg1[64,64],vexVVVV_XmmReg[64,64],XmmReg2_m128[64,64]); + ZmmReg1 = zext(XmmReg1); } -# VFIXUPIMMSD 5-120 PAGE 1944 LINE 101217 -define pcodeop vfmadd231pd_fma ; :VFMADD231PD XmmReg1, vexVVVV_XmmReg, XmmReg2_m128 is $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & vexVVVV_XmmReg; byte=0xB8; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128 { - local tmp:16 = vfmadd231pd_fma( XmmReg1, vexVVVV_XmmReg, XmmReg2_m128 ); - ZmmReg1 = zext(tmp); + fmadd231(XmmReg1[ 0,64],XmmReg1[ 0,64],vexVVVV_XmmReg[ 0,64],XmmReg2_m128[ 0,64]); + fmadd231(XmmReg1[64,64],XmmReg1[64,64],vexVVVV_XmmReg[64,64],XmmReg2_m128[64,64]); + ZmmReg1 = zext(XmmReg1); } -# VFIXUPIMMSD 5-120 PAGE 1944 LINE 101220 :VFMADD132PD YmmReg1, vexVVVV_YmmReg, YmmReg2_m256 is $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & vexVVVV_YmmReg; byte=0x98; (YmmReg1 & ZmmReg1) ... & YmmReg2_m256 { - local tmp:16 = vfmadd132pd_fma( YmmReg1, vexVVVV_YmmReg, YmmReg2_m256 ); - ZmmReg1 = zext(tmp); + fmadd132(YmmReg1[ 0,64], YmmReg1[ 0,64], vexVVVV_YmmReg[ 0,64], YmmReg2_m256[ 0,64]); + fmadd132(YmmReg1[ 64,64], YmmReg1[ 64,64], vexVVVV_YmmReg[ 64,64], YmmReg2_m256[ 64,64]); + fmadd132(YmmReg1[128,64], YmmReg1[128,64], vexVVVV_YmmReg[128,64], YmmReg2_m256[128,64]); + fmadd132(YmmReg1[192,64], YmmReg1[192,64], vexVVVV_YmmReg[192,64], YmmReg2_m256[192,64]); + ZmmReg1 = zext(YmmReg1); } -# VFIXUPIMMSD 5-120 PAGE 1944 LINE 101223 :VFMADD213PD YmmReg1, vexVVVV_YmmReg, YmmReg2_m256 is $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & vexVVVV_YmmReg; byte=0xA8; (YmmReg1 & ZmmReg1) ... & YmmReg2_m256 { - local tmp:16 = vfmadd213pd_fma( YmmReg1, vexVVVV_YmmReg, YmmReg2_m256 ); - ZmmReg1 = zext(tmp); + fmadd213(YmmReg1[ 0,64], YmmReg1[ 0,64], vexVVVV_YmmReg[ 0,64], YmmReg2_m256[ 0,64]); + fmadd213(YmmReg1[ 64,64], YmmReg1[ 64,64], vexVVVV_YmmReg[ 64,64], YmmReg2_m256[ 64,64]); + fmadd213(YmmReg1[128,64], YmmReg1[128,64], vexVVVV_YmmReg[128,64], YmmReg2_m256[128,64]); + fmadd213(YmmReg1[192,64], YmmReg1[192,64], vexVVVV_YmmReg[192,64], YmmReg2_m256[192,64]); + ZmmReg1 = zext(YmmReg1); } -# VFIXUPIMMSD 5-120 PAGE 1944 LINE 101226 :VFMADD231PD YmmReg1, vexVVVV_YmmReg, YmmReg2_m256 is $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & vexVVVV_YmmReg; byte=0xB8; (YmmReg1 & ZmmReg1) ... & YmmReg2_m256 { - local tmp:16 = vfmadd231pd_fma( YmmReg1, vexVVVV_YmmReg, YmmReg2_m256 ); - ZmmReg1 = zext(tmp); + fmadd231(YmmReg1[ 0,64], YmmReg1[ 0,64], vexVVVV_YmmReg[ 0,64], YmmReg2_m256[ 0,64]); + fmadd231(YmmReg1[ 64,64], YmmReg1[ 64,64], vexVVVV_YmmReg[ 64,64], YmmReg2_m256[ 64,64]); + fmadd231(YmmReg1[128,64], YmmReg1[128,64], vexVVVV_YmmReg[128,64], YmmReg2_m256[128,64]); + fmadd231(YmmReg1[192,64], YmmReg1[192,64], vexVVVV_YmmReg[192,64], YmmReg2_m256[192,64]); + ZmmReg1 = zext(YmmReg1); } -# VFIXUPIMMSS 5-127 PAGE 1951 LINE 101572 -define pcodeop vfmadd132ps_fma ; +# VFMADD132PS/VFMADD213PS/VFMADD231PS :VFMADD132PS XmmReg1, vexVVVV_XmmReg, XmmReg2_m128 is $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & vexVVVV_XmmReg; byte=0x98; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128 { - local tmp:16 = vfmadd132ps_fma( XmmReg1, vexVVVV_XmmReg, XmmReg2_m128 ); - ZmmReg1 = zext(tmp); + fmadd132(XmmReg1[ 0,32], XmmReg1[ 0,32], vexVVVV_XmmReg[ 0,32], XmmReg2_m128[ 0,32]); + fmadd132(XmmReg1[32,32], XmmReg1[32,32], vexVVVV_XmmReg[32,32], XmmReg2_m128[32,32]); + fmadd132(XmmReg1[64,32], XmmReg1[64,32], vexVVVV_XmmReg[64,32], XmmReg2_m128[64,32]); + fmadd132(XmmReg1[96,32], XmmReg1[96,32], vexVVVV_XmmReg[96,32], XmmReg2_m128[96,32]); + ZmmReg1 = zext(XmmReg1); } -# VFIXUPIMMSS 5-127 PAGE 1951 LINE 101575 -define pcodeop vfmadd213ps_fma ; :VFMADD213PS XmmReg1, vexVVVV_XmmReg, XmmReg2_m128 is $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & vexVVVV_XmmReg; byte=0xA8; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128 { - local tmp:16 = vfmadd213ps_fma( XmmReg1, vexVVVV_XmmReg, XmmReg2_m128 ); - ZmmReg1 = zext(tmp); + fmadd213(XmmReg1[ 0,32], XmmReg1[ 0,32], vexVVVV_XmmReg[ 0,32], XmmReg2_m128[ 0,32]); + fmadd213(XmmReg1[32,32], XmmReg1[32,32], vexVVVV_XmmReg[32,32], XmmReg2_m128[32,32]); + fmadd213(XmmReg1[64,32], XmmReg1[64,32], vexVVVV_XmmReg[64,32], XmmReg2_m128[64,32]); + fmadd213(XmmReg1[96,32], XmmReg1[96,32], vexVVVV_XmmReg[96,32], XmmReg2_m128[96,32]); + ZmmReg1 = zext(XmmReg1); } -# VFIXUPIMMSS 5-127 PAGE 1951 LINE 101578 -define pcodeop vfmadd231ps_fma ; :VFMADD231PS XmmReg1, vexVVVV_XmmReg, XmmReg2_m128 is $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & vexVVVV_XmmReg; byte=0xB8; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128 { - local tmp:16 = vfmadd231ps_fma( XmmReg1, vexVVVV_XmmReg, XmmReg2_m128 ); - ZmmReg1 = zext(tmp); + fmadd231(XmmReg1[ 0,32], XmmReg1[ 0,32], vexVVVV_XmmReg[ 0,32], XmmReg2_m128[ 0,32]); + fmadd231(XmmReg1[32,32], XmmReg1[32,32], vexVVVV_XmmReg[32,32], XmmReg2_m128[32,32]); + fmadd231(XmmReg1[64,32], XmmReg1[64,32], vexVVVV_XmmReg[64,32], XmmReg2_m128[64,32]); + fmadd231(XmmReg1[96,32], XmmReg1[96,32], vexVVVV_XmmReg[96,32], XmmReg2_m128[96,32]); + ZmmReg1 = zext(XmmReg1); } -# VFIXUPIMMSS 5-127 PAGE 1951 LINE 101581 :VFMADD132PS YmmReg1, vexVVVV_YmmReg, YmmReg2_m256 is $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & vexVVVV_YmmReg; byte=0x98; (YmmReg1 & ZmmReg1) ... & YmmReg2_m256 { - local tmp:16 = vfmadd132ps_fma( YmmReg1, vexVVVV_YmmReg, YmmReg2_m256 ); - ZmmReg1 = zext(tmp); + fmadd132(YmmReg1[ 0,32], YmmReg1[ 0,32], vexVVVV_YmmReg[ 0,32], YmmReg2_m256[ 0,32]); + fmadd132(YmmReg1[ 32,32], YmmReg1[ 32,32], vexVVVV_YmmReg[ 32,32], YmmReg2_m256[ 32,32]); + fmadd132(YmmReg1[ 64,32], YmmReg1[ 64,32], vexVVVV_YmmReg[ 64,32], YmmReg2_m256[ 64,32]); + fmadd132(YmmReg1[ 96,32], YmmReg1[ 96,32], vexVVVV_YmmReg[ 96,32], YmmReg2_m256[ 96,32]); + fmadd132(YmmReg1[128,32], YmmReg1[128,32], vexVVVV_YmmReg[128,32], YmmReg2_m256[128,32]); + fmadd132(YmmReg1[160,32], YmmReg1[160,32], vexVVVV_YmmReg[160,32], YmmReg2_m256[160,32]); + fmadd132(YmmReg1[192,32], YmmReg1[192,32], vexVVVV_YmmReg[192,32], YmmReg2_m256[192,32]); + fmadd132(YmmReg1[224,32], YmmReg1[224,32], vexVVVV_YmmReg[224,32], YmmReg2_m256[224,32]); + ZmmReg1 = zext(YmmReg1); } -# VFIXUPIMMSS 5-127 PAGE 1951 LINE 101584 :VFMADD213PS YmmReg1, vexVVVV_YmmReg, YmmReg2_m256 is $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & vexVVVV_YmmReg; byte=0xA8; (YmmReg1 & ZmmReg1) ... & YmmReg2_m256 { - local tmp:16 = vfmadd213ps_fma( YmmReg1, vexVVVV_YmmReg, YmmReg2_m256 ); - ZmmReg1 = zext(tmp); + fmadd213(YmmReg1[ 0,32], YmmReg1[ 0,32], vexVVVV_YmmReg[ 0,32], YmmReg2_m256[ 0,32]); + fmadd213(YmmReg1[ 32,32], YmmReg1[ 32,32], vexVVVV_YmmReg[ 32,32], YmmReg2_m256[ 32,32]); + fmadd213(YmmReg1[ 64,32], YmmReg1[ 64,32], vexVVVV_YmmReg[ 64,32], YmmReg2_m256[ 64,32]); + fmadd213(YmmReg1[ 96,32], YmmReg1[ 96,32], vexVVVV_YmmReg[ 96,32], YmmReg2_m256[ 96,32]); + fmadd213(YmmReg1[128,32], YmmReg1[128,32], vexVVVV_YmmReg[128,32], YmmReg2_m256[128,32]); + fmadd213(YmmReg1[160,32], YmmReg1[160,32], vexVVVV_YmmReg[160,32], YmmReg2_m256[160,32]); + fmadd213(YmmReg1[192,32], YmmReg1[192,32], vexVVVV_YmmReg[192,32], YmmReg2_m256[192,32]); + fmadd213(YmmReg1[224,32], YmmReg1[224,32], vexVVVV_YmmReg[224,32], YmmReg2_m256[224,32]); + ZmmReg1 = zext(YmmReg1); } -# VFIXUPIMMSS 5-127 PAGE 1951 LINE 101587 -# WARNING: did not recognize VEX field 0 for "VFMADD231PS ymm1, ymm2, ymm3/m256" -:VFMADD231PS YmmReg1, vexVVVV_YmmReg, YmmReg2_m256 is $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & vexVVVV_YmmReg; byte=0xB8; (YmmReg1 & ZmmReg1) ... & YmmReg2_m256 +:VFMADD231PS YmmReg1, vexVVVV_YmmReg, YmmReg2_m256 is $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & vexVVVV_YmmReg; byte=0xB8; (YmmReg1 & ZmmReg1) ... & YmmReg2_m256 { - local tmp:16 = vfmadd231ps_fma( YmmReg1, vexVVVV_YmmReg, YmmReg2_m256 ); - ZmmReg1 = zext(tmp); + fmadd231(YmmReg1[ 0,32], YmmReg1[ 0,32], vexVVVV_YmmReg[ 0,32], YmmReg2_m256[ 0,32]); + fmadd231(YmmReg1[ 32,32], YmmReg1[ 32,32], vexVVVV_YmmReg[ 32,32], YmmReg2_m256[ 32,32]); + fmadd231(YmmReg1[ 64,32], YmmReg1[ 64,32], vexVVVV_YmmReg[ 64,32], YmmReg2_m256[ 64,32]); + fmadd231(YmmReg1[ 96,32], YmmReg1[ 96,32], vexVVVV_YmmReg[ 96,32], YmmReg2_m256[ 96,32]); + fmadd231(YmmReg1[128,32], YmmReg1[128,32], vexVVVV_YmmReg[128,32], YmmReg2_m256[128,32]); + fmadd231(YmmReg1[160,32], YmmReg1[160,32], vexVVVV_YmmReg[160,32], YmmReg2_m256[160,32]); + fmadd231(YmmReg1[192,32], YmmReg1[192,32], vexVVVV_YmmReg[192,32], YmmReg2_m256[192,32]); + fmadd231(YmmReg1[224,32], YmmReg1[224,32], vexVVVV_YmmReg[224,32], YmmReg2_m256[224,32]); + ZmmReg1 = zext(YmmReg1); } -# VFMADD132PS/VFMADD213PS/VFMADD231PS 5-134 PAGE 1958 LINE 101931 -define pcodeop vfmadd132sd_fma ; +# VFMADD132SD/VFMADD213SD/VFMADD231SD :VFMADD132SD XmmReg1, vexVVVV_XmmReg, XmmReg2_m64 is $(VEX_LIG) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & vexVVVV_XmmReg; byte=0x99; (XmmReg1 & ZmmReg1) ... & XmmReg2_m64 { - local tmp:16 = vfmadd132sd_fma( XmmReg1, vexVVVV_XmmReg, XmmReg2_m64 ); - ZmmReg1 = zext(tmp); + fmadd132(XmmReg1[ 0,64],XmmReg1[ 0,64],vexVVVV_XmmReg[ 0,64],XmmReg2_m64[ 0,64]); + # XmmReg1[64,64] = XmmReg1[64,64]; + ZmmReg1 = zext(XmmReg1); } -# VFMADD132PS/VFMADD213PS/VFMADD231PS 5-134 PAGE 1958 LINE 101934 -define pcodeop vfmadd213sd_fma ; :VFMADD213SD XmmReg1, vexVVVV_XmmReg, XmmReg2_m64 is $(VEX_LIG) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & vexVVVV_XmmReg; byte=0xA9; (XmmReg1 & ZmmReg1) ... & XmmReg2_m64 { - local tmp:16 = vfmadd213sd_fma( XmmReg1, vexVVVV_XmmReg, XmmReg2_m64 ); - ZmmReg1 = zext(tmp); + fmadd213(XmmReg1[ 0,64],XmmReg1[ 0,64],vexVVVV_XmmReg[ 0,64],XmmReg2_m64[ 0,64]); + # XmmReg1[64,64] = XmmReg1[64,64]; + ZmmReg1 = zext(XmmReg1); } -# VFMADD132PS/VFMADD213PS/VFMADD231PS 5-134 PAGE 1958 LINE 101937 -define pcodeop vfmadd231sd_fma ; :VFMADD231SD XmmReg1, vexVVVV_XmmReg, XmmReg2_m64 is $(VEX_LIG) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & vexVVVV_XmmReg; byte=0xB9; (XmmReg1 & ZmmReg1) ... & XmmReg2_m64 { - local tmp:16 = vfmadd231sd_fma( XmmReg1, vexVVVV_XmmReg, XmmReg2_m64 ); - ZmmReg1 = zext(tmp); + fmadd231(XmmReg1[ 0,64],XmmReg1[ 0,64],vexVVVV_XmmReg[ 0,64],XmmReg2_m64[ 0,64]); + # XmmReg1[64,64] = XmmReg1[64,64]; + ZmmReg1 = zext(XmmReg1); } -# VFMADD132SS/VFMADD213SS/VFMADD231SS 5-137 PAGE 1961 LINE 102099 -define pcodeop vfmadd132ss_fma ; +# VFMADD132SS/VFMADD213SS/VFMADD231SS :VFMADD132SS XmmReg1, vexVVVV_XmmReg, XmmReg2_m32 is $(VEX_LIG) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & vexVVVV_XmmReg; byte=0x99; (XmmReg1 & ZmmReg1) ... & XmmReg2_m32 { - local tmp:16 = vfmadd132ss_fma( XmmReg1, vexVVVV_XmmReg, XmmReg2_m32 ); - ZmmReg1 = zext(tmp); + fmadd132(XmmReg1[ 0,32], XmmReg1[ 0,32], vexVVVV_XmmReg[ 0,32], XmmReg2_m32[ 0,32]); + # XmmReg1[32,96] = XmmReg1[32,96]; + ZmmReg1 = zext(XmmReg1); } -# VFMADD132SS/VFMADD213SS/VFMADD231SS 5-137 PAGE 1961 LINE 102102 -define pcodeop vfmadd213ss_fma ; :VFMADD213SS XmmReg1, vexVVVV_XmmReg, XmmReg2_m32 is $(VEX_LIG) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & vexVVVV_XmmReg; byte=0xA9; (XmmReg1 & ZmmReg1) ... & XmmReg2_m32 { - local tmp:16 = vfmadd213ss_fma( XmmReg1, vexVVVV_XmmReg, XmmReg2_m32 ); - ZmmReg1 = zext(tmp); + fmadd213(XmmReg1[ 0,32], XmmReg1[ 0,32], vexVVVV_XmmReg[ 0,32], XmmReg2_m32[ 0,32]); + # XmmReg1[32,96] = XmmReg1[32,96]; + ZmmReg1 = zext(XmmReg1); } -# VFMADD132SS/VFMADD213SS/VFMADD231SS 5-137 PAGE 1961 LINE 102105 -define pcodeop vfmadd231ss_fma ; :VFMADD231SS XmmReg1, vexVVVV_XmmReg, XmmReg2_m32 is $(VEX_LIG) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & vexVVVV_XmmReg; byte=0xB9; (XmmReg1 & ZmmReg1) ... & XmmReg2_m32 { - local tmp:16 = vfmadd231ss_fma( XmmReg1, vexVVVV_XmmReg, XmmReg2_m32 ); - ZmmReg1 = zext(tmp); + fmadd231(XmmReg1[ 0,32], XmmReg1[ 0,32], vexVVVV_XmmReg[ 0,32], XmmReg2_m32[ 0,32]); + # XmmReg1[32,96] = XmmReg1[32,96]; + ZmmReg1 = zext(XmmReg1); } -# VFMADDSUB132PD/VFMADDSUB213PD/VFMADDSUB231PD 5-140 PAGE 1964 LINE 102272 -define pcodeop vfmaddsub132pd_fma ; +# VFMADDSUB132PD/VFMADDSUB213PD/VFMADDSUB231PD :VFMADDSUB132PD XmmReg1, vexVVVV_XmmReg, XmmReg2_m128 is $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & vexVVVV_XmmReg; byte=0x96; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128 { - local tmp:16 = vfmaddsub132pd_fma( XmmReg1, vexVVVV_XmmReg, XmmReg2_m128 ); - ZmmReg1 = zext(tmp); + fmsub132(XmmReg1[ 0,64],XmmReg1[ 0,64],vexVVVV_XmmReg[ 0,64],XmmReg2_m128[ 0,64]); + fmadd132(XmmReg1[64,64],XmmReg1[64,64],vexVVVV_XmmReg[64,64],XmmReg2_m128[64,64]); + ZmmReg1 = zext(XmmReg1); } -# VFMADDSUB132PD/VFMADDSUB213PD/VFMADDSUB231PD 5-140 PAGE 1964 LINE 102275 -define pcodeop vfmaddsub213pd_fma ; :VFMADDSUB213PD XmmReg1, vexVVVV_XmmReg, XmmReg2_m128 is $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & vexVVVV_XmmReg; byte=0xA6; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128 { - local tmp:16 = vfmaddsub213pd_fma( XmmReg1, vexVVVV_XmmReg, XmmReg2_m128 ); - ZmmReg1 = zext(tmp); + fmsub213(XmmReg1[ 0,64],XmmReg1[ 0,64],vexVVVV_XmmReg[ 0,64],XmmReg2_m128[ 0,64]); + fmadd213(XmmReg1[64,64],XmmReg1[64,64],vexVVVV_XmmReg[64,64],XmmReg2_m128[64,64]); + ZmmReg1 = zext(XmmReg1); } -# VFMADDSUB132PD/VFMADDSUB213PD/VFMADDSUB231PD 5-140 PAGE 1964 LINE 102278 -define pcodeop vfmaddsub231pd_fma ; :VFMADDSUB231PD XmmReg1, vexVVVV_XmmReg, XmmReg2_m128 is $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & vexVVVV_XmmReg; byte=0xB6; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128 { - local tmp:16 = vfmaddsub231pd_fma( XmmReg1, vexVVVV_XmmReg, XmmReg2_m128 ); - ZmmReg1 = zext(tmp); + fmsub231(XmmReg1[ 0,64],XmmReg1[ 0,64],vexVVVV_XmmReg[ 0,64],XmmReg2_m128[ 0,64]); + fmadd231(XmmReg1[64,64],XmmReg1[64,64],vexVVVV_XmmReg[64,64],XmmReg2_m128[64,64]); + ZmmReg1 = zext(XmmReg1); } -# VFMADDSUB132PD/VFMADDSUB213PD/VFMADDSUB231PD 5-140 PAGE 1964 LINE 102281 :VFMADDSUB132PD YmmReg1, vexVVVV_YmmReg, YmmReg2_m256 is $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & vexVVVV_YmmReg; byte=0x96; (YmmReg1 & ZmmReg1) ... & YmmReg2_m256 { - local tmp:16 = vfmaddsub132pd_fma( YmmReg1, vexVVVV_YmmReg, YmmReg2_m256 ); - ZmmReg1 = zext(tmp); + fmsub132(YmmReg1[ 0,64],YmmReg1[ 0,64],vexVVVV_YmmReg[ 0,64],YmmReg2_m256[ 0,64]); + fmadd132(YmmReg1[ 64,64],YmmReg1[ 64,64],vexVVVV_YmmReg[ 64,64],YmmReg2_m256[ 64,64]); + fmsub132(YmmReg1[128,64],YmmReg1[128,64],vexVVVV_YmmReg[128,64],YmmReg2_m256[128,64]); + fmadd132(YmmReg1[192,64],YmmReg1[192,64],vexVVVV_YmmReg[192,64],YmmReg2_m256[192,64]); + ZmmReg1 = zext(YmmReg1); } -# VFMADDSUB132PD/VFMADDSUB213PD/VFMADDSUB231PD 5-140 PAGE 1964 LINE 102284 :VFMADDSUB213PD YmmReg1, vexVVVV_YmmReg, YmmReg2_m256 is $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & vexVVVV_YmmReg; byte=0xA6; (YmmReg1 & ZmmReg1) ... & YmmReg2_m256 { - local tmp:16 = vfmaddsub213pd_fma( YmmReg1, vexVVVV_YmmReg, YmmReg2_m256 ); - ZmmReg1 = zext(tmp); + fmsub213(YmmReg1[ 0,64],YmmReg1[ 0,64],vexVVVV_YmmReg[ 0,64],YmmReg2_m256[ 0,64]); + fmadd213(YmmReg1[ 64,64],YmmReg1[ 64,64],vexVVVV_YmmReg[ 64,64],YmmReg2_m256[ 64,64]); + fmsub213(YmmReg1[128,64],YmmReg1[128,64],vexVVVV_YmmReg[128,64],YmmReg2_m256[128,64]); + fmadd213(YmmReg1[192,64],YmmReg1[192,64],vexVVVV_YmmReg[192,64],YmmReg2_m256[192,64]); + ZmmReg1 = zext(YmmReg1); } -# VFMADDSUB132PD/VFMADDSUB213PD/VFMADDSUB231PD 5-140 PAGE 1964 LINE 102287 :VFMADDSUB231PD YmmReg1, vexVVVV_YmmReg, YmmReg2_m256 is $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & vexVVVV_YmmReg; byte=0xB6; (YmmReg1 & ZmmReg1) ... & YmmReg2_m256 { - local tmp:16 = vfmaddsub231pd_fma( YmmReg1, vexVVVV_YmmReg, YmmReg2_m256 ); - ZmmReg1 = zext(tmp); + fmsub231(YmmReg1[ 0,64],YmmReg1[ 0,64],vexVVVV_YmmReg[ 0,64],YmmReg2_m256[ 0,64]); + fmadd231(YmmReg1[ 64,64],YmmReg1[ 64,64],vexVVVV_YmmReg[ 64,64],YmmReg2_m256[ 64,64]); + fmsub231(YmmReg1[128,64],YmmReg1[128,64],vexVVVV_YmmReg[128,64],YmmReg2_m256[128,64]); + fmadd231(YmmReg1[192,64],YmmReg1[192,64],vexVVVV_YmmReg[192,64],YmmReg2_m256[192,64]); + ZmmReg1 = zext(YmmReg1); } -# VFMADD132SS/VFMADD213SS/VFMADD231SS 5-150 PAGE 1974 LINE 102711 -define pcodeop vfmaddsub132ps_fma ; +# VFMADDSUB132PS/VFMADDSUB213PS/VFMADDSUB231PS :VFMADDSUB132PS XmmReg1, vexVVVV_XmmReg, XmmReg2_m128 is $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & vexVVVV_XmmReg; byte=0x96; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128 { - local tmp:16 = vfmaddsub132ps_fma( XmmReg1, vexVVVV_XmmReg, XmmReg2_m128 ); - ZmmReg1 = zext(tmp); + fmsub132(XmmReg1[ 0,32],XmmReg1[ 0,32],vexVVVV_XmmReg[ 0,32],XmmReg2_m128[ 0,32]); + fmadd132(XmmReg1[32,32],XmmReg1[32,32],vexVVVV_XmmReg[32,32],XmmReg2_m128[32,32]); + fmsub132(XmmReg1[64,32],XmmReg1[64,32],vexVVVV_XmmReg[64,32],XmmReg2_m128[64,32]); + fmadd132(XmmReg1[96,32],XmmReg1[96,32],vexVVVV_XmmReg[96,32],XmmReg2_m128[96,32]); + ZmmReg1 = zext(XmmReg1); } -# VFMADD132SS/VFMADD213SS/VFMADD231SS 5-150 PAGE 1974 LINE 102714 -define pcodeop vfmaddsub213ps_fma ; :VFMADDSUB213PS XmmReg1, vexVVVV_XmmReg, XmmReg2_m128 is $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & vexVVVV_XmmReg; byte=0xA6; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128 { - local tmp:16 = vfmaddsub213ps_fma( XmmReg1, vexVVVV_XmmReg, XmmReg2_m128 ); - ZmmReg1 = zext(tmp); + fmsub213(XmmReg1[ 0,32],XmmReg1[ 0,32],vexVVVV_XmmReg[ 0,32],XmmReg2_m128[ 0,32]); + fmadd213(XmmReg1[32,32],XmmReg1[32,32],vexVVVV_XmmReg[32,32],XmmReg2_m128[32,32]); + fmsub213(XmmReg1[64,32],XmmReg1[64,32],vexVVVV_XmmReg[64,32],XmmReg2_m128[64,32]); + fmadd213(XmmReg1[96,32],XmmReg1[96,32],vexVVVV_XmmReg[96,32],XmmReg2_m128[96,32]); + ZmmReg1 = zext(XmmReg1); } -# VFMADD132SS/VFMADD213SS/VFMADD231SS 5-150 PAGE 1974 LINE 102717 -define pcodeop vfmaddsub231ps_fma ; :VFMADDSUB231PS XmmReg1, vexVVVV_XmmReg, XmmReg2_m128 is $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & vexVVVV_XmmReg; byte=0xB6; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128 { - local tmp:16 = vfmaddsub231ps_fma( XmmReg1, vexVVVV_XmmReg, XmmReg2_m128 ); - ZmmReg1 = zext(tmp); + fmsub231(XmmReg1[ 0,32],XmmReg1[ 0,32],vexVVVV_XmmReg[ 0,32],XmmReg2_m128[ 0,32]); + fmadd231(XmmReg1[32,32],XmmReg1[32,32],vexVVVV_XmmReg[32,32],XmmReg2_m128[32,32]); + fmsub231(XmmReg1[64,32],XmmReg1[64,32],vexVVVV_XmmReg[64,32],XmmReg2_m128[64,32]); + fmadd231(XmmReg1[96,32],XmmReg1[96,32],vexVVVV_XmmReg[96,32],XmmReg2_m128[96,32]); + ZmmReg1 = zext(XmmReg1); } -# VFMADD132SS/VFMADD213SS/VFMADD231SS 5-150 PAGE 1974 LINE 102720 :VFMADDSUB132PS YmmReg1, vexVVVV_YmmReg, YmmReg2_m256 is $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & vexVVVV_YmmReg; byte=0x96; (YmmReg1 & ZmmReg1) ... & YmmReg2_m256 { - local tmp:16 = vfmaddsub132ps_fma( YmmReg1, vexVVVV_YmmReg, YmmReg2_m256 ); - ZmmReg1 = zext(tmp); + fmsub132(YmmReg1[ 0,32], YmmReg1[ 0,32], vexVVVV_YmmReg[ 0,32], YmmReg2_m256[ 0,32]); + fmadd132(YmmReg1[ 32,32], YmmReg1[ 32,32], vexVVVV_YmmReg[ 32,32], YmmReg2_m256[ 32,32]); + fmsub132(YmmReg1[ 64,32], YmmReg1[ 64,32], vexVVVV_YmmReg[ 64,32], YmmReg2_m256[ 64,32]); + fmadd132(YmmReg1[ 96,32], YmmReg1[ 96,32], vexVVVV_YmmReg[ 96,32], YmmReg2_m256[ 96,32]); + fmsub132(YmmReg1[128,32], YmmReg1[128,32], vexVVVV_YmmReg[128,32], YmmReg2_m256[128,32]); + fmadd132(YmmReg1[160,32], YmmReg1[160,32], vexVVVV_YmmReg[160,32], YmmReg2_m256[160,32]); + fmsub132(YmmReg1[192,32], YmmReg1[192,32], vexVVVV_YmmReg[192,32], YmmReg2_m256[192,32]); + fmadd132(YmmReg1[224,32], YmmReg1[224,32], vexVVVV_YmmReg[224,32], YmmReg2_m256[224,32]); + ZmmReg1 = zext(YmmReg1); } -# VFMADD132SS/VFMADD213SS/VFMADD231SS 5-150 PAGE 1974 LINE 102723 :VFMADDSUB213PS YmmReg1, vexVVVV_YmmReg, YmmReg2_m256 is $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & vexVVVV_YmmReg; byte=0xA6; (YmmReg1 & ZmmReg1) ... & YmmReg2_m256 { - local tmp:16 = vfmaddsub213ps_fma( YmmReg1, vexVVVV_YmmReg, YmmReg2_m256 ); - ZmmReg1 = zext(tmp); + fmsub213(YmmReg1[ 0,32], YmmReg1[ 0,32], vexVVVV_YmmReg[ 0,32], YmmReg2_m256[ 0,32]); + fmadd213(YmmReg1[ 32,32], YmmReg1[ 32,32], vexVVVV_YmmReg[ 32,32], YmmReg2_m256[ 32,32]); + fmsub213(YmmReg1[ 64,32], YmmReg1[ 64,32], vexVVVV_YmmReg[ 64,32], YmmReg2_m256[ 64,32]); + fmadd213(YmmReg1[ 96,32], YmmReg1[ 96,32], vexVVVV_YmmReg[ 96,32], YmmReg2_m256[ 96,32]); + fmsub213(YmmReg1[128,32], YmmReg1[128,32], vexVVVV_YmmReg[128,32], YmmReg2_m256[128,32]); + fmadd213(YmmReg1[160,32], YmmReg1[160,32], vexVVVV_YmmReg[160,32], YmmReg2_m256[160,32]); + fmsub213(YmmReg1[192,32], YmmReg1[192,32], vexVVVV_YmmReg[192,32], YmmReg2_m256[192,32]); + fmadd213(YmmReg1[224,32], YmmReg1[224,32], vexVVVV_YmmReg[224,32], YmmReg2_m256[224,32]); + ZmmReg1 = zext(YmmReg1); } -# VFMADD132SS/VFMADD213SS/VFMADD231SS 5-150 PAGE 1974 LINE 102726 :VFMADDSUB231PS YmmReg1, vexVVVV_YmmReg, YmmReg2_m256 is $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & vexVVVV_YmmReg; byte=0xB6; (YmmReg1 & ZmmReg1) ... & YmmReg2_m256 { - local tmp:16 = vfmaddsub231ps_fma( YmmReg1, vexVVVV_YmmReg, YmmReg2_m256 ); - ZmmReg1 = zext(tmp); + fmsub231(YmmReg1[ 0,32], YmmReg1[ 0,32], vexVVVV_YmmReg[ 0,32], YmmReg2_m256[ 0,32]); + fmadd231(YmmReg1[ 32,32], YmmReg1[ 32,32], vexVVVV_YmmReg[ 32,32], YmmReg2_m256[ 32,32]); + fmsub231(YmmReg1[ 64,32], YmmReg1[ 64,32], vexVVVV_YmmReg[ 64,32], YmmReg2_m256[ 64,32]); + fmadd231(YmmReg1[ 96,32], YmmReg1[ 96,32], vexVVVV_YmmReg[ 96,32], YmmReg2_m256[ 96,32]); + fmsub231(YmmReg1[128,32], YmmReg1[128,32], vexVVVV_YmmReg[128,32], YmmReg2_m256[128,32]); + fmadd231(YmmReg1[160,32], YmmReg1[160,32], vexVVVV_YmmReg[160,32], YmmReg2_m256[160,32]); + fmsub231(YmmReg1[192,32], YmmReg1[192,32], vexVVVV_YmmReg[192,32], YmmReg2_m256[192,32]); + fmadd231(YmmReg1[224,32], YmmReg1[224,32], vexVVVV_YmmReg[224,32], YmmReg2_m256[224,32]); + ZmmReg1 = zext(YmmReg1); } -# VFMSUBADD132PD/VFMSUBADD213PD/VFMSUBADD231PD 5-159 PAGE 1983 LINE 103141 -define pcodeop vfmsubadd132pd_fma ; -:VFMSUBADD132PD XmmReg1, vexVVVV_XmmReg, XmmReg2_m128 is $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & vexVVVV_XmmReg; byte=0x97; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128 +# VFMSUB132PD/VFMSUB213PD/VFMSUB231PD +:VFMSUB132PD XmmReg1, vexVVVV_XmmReg, XmmReg2_m128 is $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & vexVVVV_XmmReg; byte=0x9A; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128 { - local tmp:16 = vfmsubadd132pd_fma( XmmReg1, vexVVVV_XmmReg, XmmReg2_m128 ); - ZmmReg1 = zext(tmp); + fmsub132(XmmReg1[ 0,64],XmmReg1[ 0,64],vexVVVV_XmmReg[ 0,64],XmmReg2_m128[ 0,64]); + fmsub132(XmmReg1[64,64],XmmReg1[64,64],vexVVVV_XmmReg[64,64],XmmReg2_m128[64,64]); + ZmmReg1 = zext(XmmReg1); } -# VFMSUBADD132PD/VFMSUBADD213PD/VFMSUBADD231PD 5-159 PAGE 1983 LINE 103144 -define pcodeop vfmsubadd213pd_fma ; -:VFMSUBADD213PD XmmReg1, vexVVVV_XmmReg, XmmReg2_m128 is $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & vexVVVV_XmmReg; byte=0xA7; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128 +# VFMSUB132PD/VFMSUB213PD/VFMSUB231PD +:VFMSUB213PD XmmReg1, vexVVVV_XmmReg, XmmReg2_m128 is $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & vexVVVV_XmmReg; byte=0xAA; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128 { - local tmp:16 = vfmsubadd213pd_fma( XmmReg1, vexVVVV_XmmReg, XmmReg2_m128 ); - ZmmReg1 = zext(tmp); + fmsub213(XmmReg1[ 0,64],XmmReg1[ 0,64],vexVVVV_XmmReg[ 0,64],XmmReg2_m128[ 0,64]); + fmsub213(XmmReg1[64,64],XmmReg1[64,64],vexVVVV_XmmReg[64,64],XmmReg2_m128[64,64]); + ZmmReg1 = zext(XmmReg1); } -# VFMSUBADD132PD/VFMSUBADD213PD/VFMSUBADD231PD 5-159 PAGE 1983 LINE 103147 -define pcodeop vfmsubadd231pd_fma ; -:VFMSUBADD231PD XmmReg1, vexVVVV_XmmReg, XmmReg2_m128 is $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & vexVVVV_XmmReg; byte=0xB7; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128 +# VFMSUB132PD/VFMSUB213PD/VFMSUB231PD +:VFMSUB231PD XmmReg1, vexVVVV_XmmReg, XmmReg2_m128 is $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & vexVVVV_XmmReg; byte=0xBA; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128 { - local tmp:16 = vfmsubadd231pd_fma( XmmReg1, vexVVVV_XmmReg, XmmReg2_m128 ); - ZmmReg1 = zext(tmp); + fmsub231(XmmReg1[ 0,64],XmmReg1[ 0,64],vexVVVV_XmmReg[ 0,64],XmmReg2_m128[ 0,64]); + fmsub231(XmmReg1[64,64],XmmReg1[64,64],vexVVVV_XmmReg[64,64],XmmReg2_m128[64,64]); + ZmmReg1 = zext(XmmReg1); } -# VFMSUBADD132PD/VFMSUBADD213PD/VFMSUBADD231PD 5-159 PAGE 1983 LINE 103150 -:VFMSUBADD132PD YmmReg1, vexVVVV_YmmReg, YmmReg2_m256 is $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & vexVVVV_YmmReg; byte=0x97; (YmmReg1 & ZmmReg1) ... & YmmReg2_m256 +# VFMSUB132PD/VFMSUB213PD/VFMSUB231PD +:VFMSUB132PD YmmReg1, vexVVVV_YmmReg, YmmReg2_m256 is $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & vexVVVV_YmmReg; byte=0x9A; (YmmReg1 & ZmmReg1) ... & YmmReg2_m256 { - local tmp:16 = vfmsubadd132pd_fma( YmmReg1, vexVVVV_YmmReg, YmmReg2_m256 ); - ZmmReg1 = zext(tmp); + fmsub132(YmmReg1[ 0,64], YmmReg1[ 0,64], vexVVVV_YmmReg[ 0,64], YmmReg2_m256[ 0,64]); + fmsub132(YmmReg1[ 64,64], YmmReg1[ 64,64], vexVVVV_YmmReg[ 64,64], YmmReg2_m256[ 64,64]); + fmsub132(YmmReg1[128,64], YmmReg1[128,64], vexVVVV_YmmReg[128,64], YmmReg2_m256[128,64]); + fmsub132(YmmReg1[192,64], YmmReg1[192,64], vexVVVV_YmmReg[192,64], YmmReg2_m256[192,64]); + ZmmReg1 = zext(YmmReg1); } -# VFMSUBADD132PD/VFMSUBADD213PD/VFMSUBADD231PD 5-159 PAGE 1983 LINE 103153 -:VFMSUBADD213PD YmmReg1, vexVVVV_YmmReg, YmmReg2_m256 is $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & vexVVVV_YmmReg; byte=0xA7; (YmmReg1 & ZmmReg1) ... & YmmReg2_m256 +# VFMSUB132PD/VFMSUB213PD/VFMSUB231PD +:VFMSUB213PD YmmReg1, vexVVVV_YmmReg, YmmReg2_m256 is $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & vexVVVV_YmmReg; byte=0xAA; (YmmReg1 & ZmmReg1) ... & YmmReg2_m256 { - local tmp:16 = vfmsubadd213pd_fma( YmmReg1, vexVVVV_YmmReg, YmmReg2_m256 ); - ZmmReg1 = zext(tmp); + fmsub213(YmmReg1[ 0,64], YmmReg1[ 0,64], vexVVVV_YmmReg[ 0,64], YmmReg2_m256[ 0,64]); + fmsub213(YmmReg1[ 64,64], YmmReg1[ 64,64], vexVVVV_YmmReg[ 64,64], YmmReg2_m256[ 64,64]); + fmsub213(YmmReg1[128,64], YmmReg1[128,64], vexVVVV_YmmReg[128,64], YmmReg2_m256[128,64]); + fmsub213(YmmReg1[192,64], YmmReg1[192,64], vexVVVV_YmmReg[192,64], YmmReg2_m256[192,64]); + ZmmReg1 = zext(YmmReg1); } -# VFMSUBADD132PD/VFMSUBADD213PD/VFMSUBADD231PD 5-159 PAGE 1983 LINE 103156 -:VFMSUBADD231PD YmmReg1, vexVVVV_YmmReg, YmmReg2_m256 is $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & vexVVVV_YmmReg; byte=0xB7; (YmmReg1 & ZmmReg1) ... & YmmReg2_m256 +# VFMSUB132PD/VFMSUB213PD/VFMSUB231PD +:VFMSUB231PD YmmReg1, vexVVVV_YmmReg, YmmReg2_m256 is $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & vexVVVV_YmmReg; byte=0xBA; (YmmReg1 & ZmmReg1) ... & YmmReg2_m256 { - local tmp:16 = vfmsubadd231pd_fma( YmmReg1, vexVVVV_YmmReg, YmmReg2_m256 ); - ZmmReg1 = zext(tmp); + fmsub231(YmmReg1[ 0,64], YmmReg1[ 0,64], vexVVVV_YmmReg[ 0,64], YmmReg2_m256[ 0,64]); + fmsub231(YmmReg1[ 64,64], YmmReg1[ 64,64], vexVVVV_YmmReg[ 64,64], YmmReg2_m256[ 64,64]); + fmsub231(YmmReg1[128,64], YmmReg1[128,64], vexVVVV_YmmReg[128,64], YmmReg2_m256[128,64]); + fmsub231(YmmReg1[192,64], YmmReg1[192,64], vexVVVV_YmmReg[192,64], YmmReg2_m256[192,64]); + ZmmReg1 = zext(YmmReg1); } -# VFMSUBADD132PS/VFMSUBADD213PS/VFMSUBADD231PS 5-169 PAGE 1993 LINE 103581 -define pcodeop vfmsubadd132ps_fma ; -:VFMSUBADD132PS XmmReg1, vexVVVV_XmmReg, XmmReg2_m128 is $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & vexVVVV_XmmReg; byte=0x97; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128 +# VFMSUB132PS/VFMSUB213PS/VFMSUB231PS +:VFMSUB132PS XmmReg1, vexVVVV_XmmReg, XmmReg2_m128 is $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & vexVVVV_XmmReg; byte=0x9A; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128 { - local tmp:16 = vfmsubadd132ps_fma( XmmReg1, vexVVVV_XmmReg, XmmReg2_m128 ); - ZmmReg1 = zext(tmp); + fmsub132(XmmReg1[ 0,32], XmmReg1[ 0,32], vexVVVV_XmmReg[ 0,32], XmmReg2_m128[ 0,32]); + fmsub132(XmmReg1[32,32], XmmReg1[32,32], vexVVVV_XmmReg[32,32], XmmReg2_m128[32,32]); + fmsub132(XmmReg1[64,32], XmmReg1[64,32], vexVVVV_XmmReg[64,32], XmmReg2_m128[64,32]); + fmsub132(XmmReg1[96,32], XmmReg1[96,32], vexVVVV_XmmReg[96,32], XmmReg2_m128[96,32]); + ZmmReg1 = zext(XmmReg1); } -# VFMSUBADD132PS/VFMSUBADD213PS/VFMSUBADD231PS 5-169 PAGE 1993 LINE 103584 -define pcodeop vfmsubadd213ps_fma ; -:VFMSUBADD213PS XmmReg1, vexVVVV_XmmReg, XmmReg2_m128 is $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & vexVVVV_XmmReg; byte=0xA7; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128 +# VFMSUB132PS/VFMSUB213PS/VFMSUB231PS +:VFMSUB213PS XmmReg1, vexVVVV_XmmReg, XmmReg2_m128 is $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & vexVVVV_XmmReg; byte=0xAA; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128 { - local tmp:16 = vfmsubadd213ps_fma( XmmReg1, vexVVVV_XmmReg, XmmReg2_m128 ); - ZmmReg1 = zext(tmp); + fmsub213(XmmReg1[ 0,32], XmmReg1[ 0,32], vexVVVV_XmmReg[ 0,32], XmmReg2_m128[ 0,32]); + fmsub213(XmmReg1[32,32], XmmReg1[32,32], vexVVVV_XmmReg[32,32], XmmReg2_m128[32,32]); + fmsub213(XmmReg1[64,32], XmmReg1[64,32], vexVVVV_XmmReg[64,32], XmmReg2_m128[64,32]); + fmsub213(XmmReg1[96,32], XmmReg1[96,32], vexVVVV_XmmReg[96,32], XmmReg2_m128[96,32]); + ZmmReg1 = zext(XmmReg1); } -# VFMSUBADD132PS/VFMSUBADD213PS/VFMSUBADD231PS 5-169 PAGE 1993 LINE 103587 -define pcodeop vfmsubadd231ps_fma ; -:VFMSUBADD231PS XmmReg1, vexVVVV_XmmReg, XmmReg2_m128 is $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & vexVVVV_XmmReg; byte=0xB7; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128 +# VFMSUB132PS/VFMSUB213PS/VFMSUB231PS +:VFMSUB231PS XmmReg1, vexVVVV_XmmReg, XmmReg2_m128 is $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & vexVVVV_XmmReg; byte=0xBA; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128 { - local tmp:16 = vfmsubadd231ps_fma( XmmReg1, vexVVVV_XmmReg, XmmReg2_m128 ); - ZmmReg1 = zext(tmp); + fmsub231(XmmReg1[ 0,32], XmmReg1[ 0,32], vexVVVV_XmmReg[ 0,32], XmmReg2_m128[ 0,32]); + fmsub231(XmmReg1[32,32], XmmReg1[32,32], vexVVVV_XmmReg[32,32], XmmReg2_m128[32,32]); + fmsub231(XmmReg1[64,32], XmmReg1[64,32], vexVVVV_XmmReg[64,32], XmmReg2_m128[64,32]); + fmsub231(XmmReg1[96,32], XmmReg1[96,32], vexVVVV_XmmReg[96,32], XmmReg2_m128[96,32]); + ZmmReg1 = zext(XmmReg1); } -# VFMSUBADD132PS/VFMSUBADD213PS/VFMSUBADD231PS 5-169 PAGE 1993 LINE 103590 -:VFMSUBADD132PS YmmReg1, vexVVVV_YmmReg, YmmReg2_m256 is $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & vexVVVV_YmmReg; byte=0x97; (YmmReg1 & ZmmReg1) ... & YmmReg2_m256 +# VFMSUB132PS/VFMSUB213PS/VFMSUB231PS +:VFMSUB132PS YmmReg1, vexVVVV_YmmReg, YmmReg2_m256 is $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & vexVVVV_YmmReg; byte=0x9A; (YmmReg1 & ZmmReg1) ... & YmmReg2_m256 { - local tmp:16 = vfmsubadd132ps_fma( YmmReg1, vexVVVV_YmmReg, YmmReg2_m256 ); - ZmmReg1 = zext(tmp); + fmsub132(YmmReg1[ 0,32], YmmReg1[ 0,32], vexVVVV_YmmReg[ 0,32], YmmReg2_m256[ 0,32]); + fmsub132(YmmReg1[ 32,32], YmmReg1[ 32,32], vexVVVV_YmmReg[ 32,32], YmmReg2_m256[ 32,32]); + fmsub132(YmmReg1[ 64,32], YmmReg1[ 64,32], vexVVVV_YmmReg[ 64,32], YmmReg2_m256[ 64,32]); + fmsub132(YmmReg1[ 96,32], YmmReg1[ 96,32], vexVVVV_YmmReg[ 96,32], YmmReg2_m256[ 96,32]); + fmsub132(YmmReg1[128,32], YmmReg1[128,32], vexVVVV_YmmReg[128,32], YmmReg2_m256[128,32]); + fmsub132(YmmReg1[160,32], YmmReg1[160,32], vexVVVV_YmmReg[160,32], YmmReg2_m256[160,32]); + fmsub132(YmmReg1[192,32], YmmReg1[192,32], vexVVVV_YmmReg[192,32], YmmReg2_m256[192,32]); + fmsub132(YmmReg1[224,32], YmmReg1[224,32], vexVVVV_YmmReg[224,32], YmmReg2_m256[224,32]); + ZmmReg1 = zext(YmmReg1); } -# VFMSUBADD132PS/VFMSUBADD213PS/VFMSUBADD231PS 5-169 PAGE 1993 LINE 103593 -:VFMSUBADD213PS YmmReg1, vexVVVV_YmmReg, YmmReg2_m256 is $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & vexVVVV_YmmReg; byte=0xA7; (YmmReg1 & ZmmReg1) ... & YmmReg2_m256 +# VFMSUB132PS/VFMSUB213PS/VFMSUB231PS +:VFMSUB213PS YmmReg1, vexVVVV_YmmReg, YmmReg2_m256 is $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & vexVVVV_YmmReg; byte=0xAA; (YmmReg1 & ZmmReg1) ... & YmmReg2_m256 { - local tmp:16 = vfmsubadd213ps_fma( YmmReg1, vexVVVV_YmmReg, YmmReg2_m256 ); - ZmmReg1 = zext(tmp); + fmsub213(YmmReg1[ 0,32], YmmReg1[ 0,32], vexVVVV_YmmReg[ 0,32], YmmReg2_m256[ 0,32]); + fmsub213(YmmReg1[ 32,32], YmmReg1[ 32,32], vexVVVV_YmmReg[ 32,32], YmmReg2_m256[ 32,32]); + fmsub213(YmmReg1[ 64,32], YmmReg1[ 64,32], vexVVVV_YmmReg[ 64,32], YmmReg2_m256[ 64,32]); + fmsub213(YmmReg1[ 96,32], YmmReg1[ 96,32], vexVVVV_YmmReg[ 96,32], YmmReg2_m256[ 96,32]); + fmsub213(YmmReg1[128,32], YmmReg1[128,32], vexVVVV_YmmReg[128,32], YmmReg2_m256[128,32]); + fmsub213(YmmReg1[160,32], YmmReg1[160,32], vexVVVV_YmmReg[160,32], YmmReg2_m256[160,32]); + fmsub213(YmmReg1[192,32], YmmReg1[192,32], vexVVVV_YmmReg[192,32], YmmReg2_m256[192,32]); + fmsub213(YmmReg1[224,32], YmmReg1[224,32], vexVVVV_YmmReg[224,32], YmmReg2_m256[224,32]); + ZmmReg1 = zext(YmmReg1); } -# VFMSUBADD132PS/VFMSUBADD213PS/VFMSUBADD231PS 5-169 PAGE 1993 LINE 103596 -:VFMSUBADD231PS YmmReg1, vexVVVV_YmmReg, YmmReg2_m256 is $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & vexVVVV_YmmReg; byte=0xB7; (YmmReg1 & ZmmReg1) ... & YmmReg2_m256 +# VFMSUB132PS/VFMSUB213PS/VFMSUB231PS +:VFMSUB231PS YmmReg1, vexVVVV_YmmReg, YmmReg2_m256 is $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & vexVVVV_YmmReg; byte=0xBA; (YmmReg1 & ZmmReg1) ... & YmmReg2_m256 { - local tmp:16 = vfmsubadd231ps_fma( YmmReg1, vexVVVV_YmmReg, YmmReg2_m256 ); - ZmmReg1 = zext(tmp); + fmsub231(YmmReg1[ 0,32], YmmReg1[ 0,32], vexVVVV_YmmReg[ 0,32], YmmReg2_m256[ 0,32]); + fmsub231(YmmReg1[ 32,32], YmmReg1[ 32,32], vexVVVV_YmmReg[ 32,32], YmmReg2_m256[ 32,32]); + fmsub231(YmmReg1[ 64,32], YmmReg1[ 64,32], vexVVVV_YmmReg[ 64,32], YmmReg2_m256[ 64,32]); + fmsub231(YmmReg1[ 96,32], YmmReg1[ 96,32], vexVVVV_YmmReg[ 96,32], YmmReg2_m256[ 96,32]); + fmsub231(YmmReg1[128,32], YmmReg1[128,32], vexVVVV_YmmReg[128,32], YmmReg2_m256[128,32]); + fmsub231(YmmReg1[160,32], YmmReg1[160,32], vexVVVV_YmmReg[160,32], YmmReg2_m256[160,32]); + fmsub231(YmmReg1[192,32], YmmReg1[192,32], vexVVVV_YmmReg[192,32], YmmReg2_m256[192,32]); + fmsub231(YmmReg1[224,32], YmmReg1[224,32], vexVVVV_YmmReg[224,32], YmmReg2_m256[224,32]); + ZmmReg1 = zext(YmmReg1); } -# VFMSUB132PD/VFMSUB213PD/VFMSUB231PD 5-179 PAGE 2003 LINE 104019 -define pcodeop vfmsub132pd_fma ; -:VFMSUB132PD XmmReg1, vexVVVV_XmmReg, XmmReg2_m128 is $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & vexVVVV_XmmReg; byte=0x9A; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128 +# VFMSUB132SD/VFMSUB213SD/VFMSUB231SD +:VFMSUB132SD XmmReg1, vexVVVV_XmmReg, XmmReg2_m64 is $(VEX_LIG) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & vexVVVV_XmmReg; byte=0x9B; (XmmReg1 & ZmmReg1) ... & XmmReg2_m64 { - local tmp:16 = vfmsub132pd_fma( XmmReg1, vexVVVV_XmmReg, XmmReg2_m128 ); - ZmmReg1 = zext(tmp); + fmsub132(XmmReg1[ 0,64],XmmReg1[ 0,64],vexVVVV_XmmReg[ 0,64],XmmReg2_m64[ 0,64]); + # XmmReg1[64,64] = XmmReg1[64,64]; + ZmmReg1 = zext(XmmReg1); } -# VFMSUB132PD/VFMSUB213PD/VFMSUB231PD 5-179 PAGE 2003 LINE 104022 -define pcodeop vfmsub213pd_fma ; -:VFMSUB213PD XmmReg1, vexVVVV_XmmReg, XmmReg2_m128 is $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & vexVVVV_XmmReg; byte=0xAA; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128 +# VFMSUB132SD/VFMSUB213SD/VFMSUB231SD +:VFMSUB213SD XmmReg1, vexVVVV_XmmReg, XmmReg2_m64 is $(VEX_LIG) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & vexVVVV_XmmReg; byte=0xAB; (XmmReg1 & ZmmReg1) ... & XmmReg2_m64 { - local tmp:16 = vfmsub213pd_fma( XmmReg1, vexVVVV_XmmReg, XmmReg2_m128 ); - ZmmReg1 = zext(tmp); + fmsub213(XmmReg1[ 0,64],XmmReg1[ 0,64],vexVVVV_XmmReg[ 0,64],XmmReg2_m64[ 0,64]); + # XmmReg1[64,64] = XmmReg1[64,64]; + ZmmReg1 = zext(XmmReg1); } -# VFMSUB132PD/VFMSUB213PD/VFMSUB231PD 5-179 PAGE 2003 LINE 104025 -define pcodeop vfmsub231pd_fma ; -:VFMSUB231PD XmmReg1, vexVVVV_XmmReg, XmmReg2_m128 is $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & vexVVVV_XmmReg; byte=0xBA; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128 +# VFMSUB132SD/VFMSUB213SD/VFMSUB231SD +:VFMSUB231SD XmmReg1, vexVVVV_XmmReg, XmmReg2_m64 is $(VEX_LIG) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & vexVVVV_XmmReg; byte=0xBB; (XmmReg1 & ZmmReg1) ... & XmmReg2_m64 { - local tmp:16 = vfmsub231pd_fma( XmmReg1, vexVVVV_XmmReg, XmmReg2_m128 ); - ZmmReg1 = zext(tmp); + fmsub231(XmmReg1[ 0,64],XmmReg1[ 0,64],vexVVVV_XmmReg[ 0,64],XmmReg2_m64[ 0,64]); + # XmmReg1[64,64] = XmmReg1[64,64]; + ZmmReg1 = zext(XmmReg1); } -# VFMSUB132PD/VFMSUB213PD/VFMSUB231PD 5-179 PAGE 2003 LINE 104028 -:VFMSUB132PD YmmReg1, vexVVVV_YmmReg, YmmReg2_m256 is $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & vexVVVV_YmmReg; byte=0x9A; (YmmReg1 & ZmmReg1) ... & YmmReg2_m256 +# VFMSUB132SS/VFMSUB213SS/VFMSUB231SS +:VFMSUB132SS XmmReg1, vexVVVV_XmmReg, XmmReg2_m32 is $(VEX_LIG) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & vexVVVV_XmmReg; byte=0x9B; (XmmReg1 & ZmmReg1) ... & XmmReg2_m32 { - local tmp:16 = vfmsub132pd_fma( YmmReg1, vexVVVV_YmmReg, YmmReg2_m256 ); - ZmmReg1 = zext(tmp); + fmsub132(XmmReg1[ 0,32], XmmReg1[ 0,32], vexVVVV_XmmReg[ 0,32], XmmReg2_m32[ 0,32]); + # XmmReg1[32,96] = XmmReg1[32,96]; + ZmmReg1 = zext(XmmReg1); } -# VFMSUB132PD/VFMSUB213PD/VFMSUB231PD 5-179 PAGE 2003 LINE 104031 -:VFMSUB213PD YmmReg1, vexVVVV_YmmReg, YmmReg2_m256 is $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & vexVVVV_YmmReg; byte=0xAA; (YmmReg1 & ZmmReg1) ... & YmmReg2_m256 +# VFMSUB132SS/VFMSUB213SS/VFMSUB231SS +:VFMSUB213SS XmmReg1, vexVVVV_XmmReg, XmmReg2_m32 is $(VEX_LIG) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & vexVVVV_XmmReg; byte=0xAB; (XmmReg1 & ZmmReg1) ... & XmmReg2_m32 { - local tmp:16 = vfmsub213pd_fma( YmmReg1, vexVVVV_YmmReg, YmmReg2_m256 ); - ZmmReg1 = zext(tmp); + fmsub213(XmmReg1[ 0,32], XmmReg1[ 0,32], vexVVVV_XmmReg[ 0,32], XmmReg2_m32[ 0,32]); + # XmmReg1[32,96] = XmmReg1[32,96]; + ZmmReg1 = zext(XmmReg1); } -# VFMSUB132PD/VFMSUB213PD/VFMSUB231PD 5-179 PAGE 2003 LINE 104034 -:VFMSUB231PD YmmReg1, vexVVVV_YmmReg, YmmReg2_m256 is $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & vexVVVV_YmmReg; byte=0xBA; (YmmReg1 & ZmmReg1) ... & YmmReg2_m256 +# VFMSUB132SS/VFMSUB213SS/VFMSUB231SS +:VFMSUB231SS XmmReg1, vexVVVV_XmmReg, XmmReg2_m32 is $(VEX_LIG) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & vexVVVV_XmmReg; byte=0xBB; (XmmReg1 & ZmmReg1) ... & XmmReg2_m32 { - local tmp:16 = vfmsub231pd_fma( YmmReg1, vexVVVV_YmmReg, YmmReg2_m256 ); - ZmmReg1 = zext(tmp); + fmsub231(XmmReg1[ 0,32], XmmReg1[ 0,32], vexVVVV_XmmReg[ 0,32], XmmReg2_m32[ 0,32]); + # XmmReg1[32,96] = XmmReg1[32,96]; + ZmmReg1 = zext(XmmReg1); } -# VFMSUB132PS/VFMSUB213PS/VFMSUB231PS 5-186 PAGE 2010 LINE 104379 -define pcodeop vfmsub132ps_fma ; -:VFMSUB132PS XmmReg1, vexVVVV_XmmReg, XmmReg2_m128 is $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & vexVVVV_XmmReg; byte=0x9A; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128 +# VFMSUBADD132PD/VFMSUBADD213PD/VFMSUBADD231PD +:VFMSUBADD132PD XmmReg1, vexVVVV_XmmReg, XmmReg2_m128 is $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & vexVVVV_XmmReg; byte=0x97; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128 { - local tmp:16 = vfmsub132ps_fma( XmmReg1, vexVVVV_XmmReg, XmmReg2_m128 ); - ZmmReg1 = zext(tmp); + fmadd132(XmmReg1[ 0,64],XmmReg1[ 0,64],vexVVVV_XmmReg[ 0,64],XmmReg2_m128[ 0,64]); + fmsub132(XmmReg1[64,64],XmmReg1[64,64],vexVVVV_XmmReg[64,64],XmmReg2_m128[64,64]); + ZmmReg1 = zext(XmmReg1); } -# VFMSUB132PS/VFMSUB213PS/VFMSUB231PS 5-186 PAGE 2010 LINE 104382 -define pcodeop vfmsub213ps_fma ; -:VFMSUB213PS XmmReg1, vexVVVV_XmmReg, XmmReg2_m128 is $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & vexVVVV_XmmReg; byte=0xAA; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128 +:VFMSUBADD213PD XmmReg1, vexVVVV_XmmReg, XmmReg2_m128 is $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & vexVVVV_XmmReg; byte=0xA7; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128 { - local tmp:16 = vfmsub213ps_fma( XmmReg1, vexVVVV_XmmReg, XmmReg2_m128 ); - ZmmReg1 = zext(tmp); + fmadd213(XmmReg1[ 0,64],XmmReg1[ 0,64],vexVVVV_XmmReg[ 0,64],XmmReg2_m128[ 0,64]); + fmsub213(XmmReg1[64,64],XmmReg1[64,64],vexVVVV_XmmReg[64,64],XmmReg2_m128[64,64]); + ZmmReg1 = zext(XmmReg1); } -# VFMSUB132PS/VFMSUB213PS/VFMSUB231PS 5-186 PAGE 2010 LINE 104385 -define pcodeop vfmsub231ps_fma ; -:VFMSUB231PS XmmReg1, vexVVVV_XmmReg, XmmReg2_m128 is $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & vexVVVV_XmmReg; byte=0xBA; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128 +:VFMSUBADD231PD XmmReg1, vexVVVV_XmmReg, XmmReg2_m128 is $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & vexVVVV_XmmReg; byte=0xB7; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128 { - local tmp:16 = vfmsub231ps_fma( XmmReg1, vexVVVV_XmmReg, XmmReg2_m128 ); - ZmmReg1 = zext(tmp); + fmadd231(XmmReg1[ 0,64],XmmReg1[ 0,64],vexVVVV_XmmReg[ 0,64],XmmReg2_m128[ 0,64]); + fmsub231(XmmReg1[64,64],XmmReg1[64,64],vexVVVV_XmmReg[64,64],XmmReg2_m128[64,64]); + ZmmReg1 = zext(XmmReg1); } -# VFMSUB132PS/VFMSUB213PS/VFMSUB231PS 5-186 PAGE 2010 LINE 104388 -:VFMSUB132PS YmmReg1, vexVVVV_YmmReg, YmmReg2_m256 is $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & vexVVVV_YmmReg; byte=0x9A; (YmmReg1 & ZmmReg1) ... & YmmReg2_m256 +:VFMSUBADD132PD YmmReg1, vexVVVV_YmmReg, YmmReg2_m256 is $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & vexVVVV_YmmReg; byte=0x97; (YmmReg1 & ZmmReg1) ... & YmmReg2_m256 { - local tmp:16 = vfmsub132ps_fma( YmmReg1, vexVVVV_YmmReg, YmmReg2_m256 ); - ZmmReg1 = zext(tmp); + fmadd132(YmmReg1[ 0,64],YmmReg1[ 0,64],vexVVVV_YmmReg[ 0,64],YmmReg2_m256[ 0,64]); + fmsub132(YmmReg1[ 64,64],YmmReg1[ 64,64],vexVVVV_YmmReg[ 64,64],YmmReg2_m256[ 64,64]); + fmadd132(YmmReg1[128,64],YmmReg1[128,64],vexVVVV_YmmReg[128,64],YmmReg2_m256[128,64]); + fmsub132(YmmReg1[192,64],YmmReg1[192,64],vexVVVV_YmmReg[192,64],YmmReg2_m256[192,64]); + ZmmReg1 = zext(YmmReg1); } -# VFMSUB132PS/VFMSUB213PS/VFMSUB231PS 5-186 PAGE 2010 LINE 104391 -:VFMSUB213PS YmmReg1, vexVVVV_YmmReg, YmmReg2_m256 is $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & vexVVVV_YmmReg; byte=0xAA; (YmmReg1 & ZmmReg1) ... & YmmReg2_m256 +:VFMSUBADD213PD YmmReg1, vexVVVV_YmmReg, YmmReg2_m256 is $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & vexVVVV_YmmReg; byte=0xA7; (YmmReg1 & ZmmReg1) ... & YmmReg2_m256 { - local tmp:16 = vfmsub213ps_fma( YmmReg1, vexVVVV_YmmReg, YmmReg2_m256 ); - ZmmReg1 = zext(tmp); + fmadd213(YmmReg1[ 0,64],YmmReg1[ 0,64],vexVVVV_YmmReg[ 0,64],YmmReg2_m256[ 0,64]); + fmsub213(YmmReg1[ 64,64],YmmReg1[ 64,64],vexVVVV_YmmReg[ 64,64],YmmReg2_m256[ 64,64]); + fmadd213(YmmReg1[128,64],YmmReg1[128,64],vexVVVV_YmmReg[128,64],YmmReg2_m256[128,64]); + fmsub213(YmmReg1[192,64],YmmReg1[192,64],vexVVVV_YmmReg[192,64],YmmReg2_m256[192,64]); + ZmmReg1 = zext(YmmReg1); } -# VFMSUB132PS/VFMSUB213PS/VFMSUB231PS 5-186 PAGE 2010 LINE 104394 -# WARNING: did not recognize VEX field 0 for "VFMSUB231PS ymm1, ymm2, ymm3/m256" -:VFMSUB231PS YmmReg1, vexVVVV_YmmReg, YmmReg2_m256 is $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & vexVVVV_YmmReg; byte=0xBA; (YmmReg1 & ZmmReg1) ... & YmmReg2_m256 +:VFMSUBADD231PD YmmReg1, vexVVVV_YmmReg, YmmReg2_m256 is $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & vexVVVV_YmmReg; byte=0xB7; (YmmReg1 & ZmmReg1) ... & YmmReg2_m256 { - local tmp:16 = vfmsub231ps_fma( YmmReg1, vexVVVV_YmmReg, YmmReg2_m256 ); - ZmmReg1 = zext(tmp); + fmadd231(YmmReg1[ 0,64],YmmReg1[ 0,64],vexVVVV_YmmReg[ 0,64],YmmReg2_m256[ 0,64]); + fmsub231(YmmReg1[ 64,64],YmmReg1[ 64,64],vexVVVV_YmmReg[ 64,64],YmmReg2_m256[ 64,64]); + fmadd231(YmmReg1[128,64],YmmReg1[128,64],vexVVVV_YmmReg[128,64],YmmReg2_m256[128,64]); + fmsub231(YmmReg1[192,64],YmmReg1[192,64],vexVVVV_YmmReg[192,64],YmmReg2_m256[192,64]); + ZmmReg1 = zext(YmmReg1); } -# VFMSUB132SD/VFMSUB213SD/VFMSUB231SD 5-193 PAGE 2017 LINE 104738 -define pcodeop vfmsub132sd_fma ; -:VFMSUB132SD XmmReg1, vexVVVV_XmmReg, XmmReg2_m64 is $(VEX_LIG) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & vexVVVV_XmmReg; byte=0x9B; (XmmReg1 & ZmmReg1) ... & XmmReg2_m64 +# VFMSUBADD132PS/VFMSUBADD213PS/VFMSUBADD231PS +:VFMSUBADD132PS XmmReg1, vexVVVV_XmmReg, XmmReg2_m128 is $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & vexVVVV_XmmReg; byte=0x97; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128 { - local tmp:16 = vfmsub132sd_fma( XmmReg1, vexVVVV_XmmReg, XmmReg2_m64 ); - ZmmReg1 = zext(tmp); + fmadd132(XmmReg1[ 0,32],XmmReg1[ 0,32],vexVVVV_XmmReg[ 0,32],XmmReg2_m128[ 0,32]); + fmsub132(XmmReg1[32,32],XmmReg1[32,32],vexVVVV_XmmReg[32,32],XmmReg2_m128[32,32]); + fmadd132(XmmReg1[64,32],XmmReg1[64,32],vexVVVV_XmmReg[64,32],XmmReg2_m128[64,32]); + fmsub132(XmmReg1[96,32],XmmReg1[96,32],vexVVVV_XmmReg[96,32],XmmReg2_m128[96,32]); + ZmmReg1 = zext(XmmReg1); } -# VFMSUB132SD/VFMSUB213SD/VFMSUB231SD 5-193 PAGE 2017 LINE 104741 -define pcodeop vfmsub213sd_fma ; -:VFMSUB213SD XmmReg1, vexVVVV_XmmReg, XmmReg2_m64 is $(VEX_LIG) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & vexVVVV_XmmReg; byte=0xAB; (XmmReg1 & ZmmReg1) ... & XmmReg2_m64 +:VFMSUBADD213PS XmmReg1, vexVVVV_XmmReg, XmmReg2_m128 is $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & vexVVVV_XmmReg; byte=0xA7; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128 { - local tmp:16 = vfmsub213sd_fma( XmmReg1, vexVVVV_XmmReg, XmmReg2_m64 ); - ZmmReg1 = zext(tmp); + fmadd213(XmmReg1[ 0,32],XmmReg1[ 0,32],vexVVVV_XmmReg[ 0,32],XmmReg2_m128[ 0,32]); + fmsub213(XmmReg1[32,32],XmmReg1[32,32],vexVVVV_XmmReg[32,32],XmmReg2_m128[32,32]); + fmadd213(XmmReg1[64,32],XmmReg1[64,32],vexVVVV_XmmReg[64,32],XmmReg2_m128[64,32]); + fmsub213(XmmReg1[96,32],XmmReg1[96,32],vexVVVV_XmmReg[96,32],XmmReg2_m128[96,32]); + ZmmReg1 = zext(XmmReg1); } -# VFMSUB132SD/VFMSUB213SD/VFMSUB231SD 5-193 PAGE 2017 LINE 104744 -define pcodeop vfmsub231sd_fma ; -:VFMSUB231SD XmmReg1, vexVVVV_XmmReg, XmmReg2_m64 is $(VEX_LIG) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & vexVVVV_XmmReg; byte=0xBB; (XmmReg1 & ZmmReg1) ... & XmmReg2_m64 +:VFMSUBADD231PS XmmReg1, vexVVVV_XmmReg, XmmReg2_m128 is $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & vexVVVV_XmmReg; byte=0xB7; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128 { - local tmp:16 = vfmsub231sd_fma( XmmReg1, vexVVVV_XmmReg, XmmReg2_m64 ); - ZmmReg1 = zext(tmp); + fmadd231(XmmReg1[ 0,32],XmmReg1[ 0,32],vexVVVV_XmmReg[ 0,32],XmmReg2_m128[ 0,32]); + fmsub231(XmmReg1[32,32],XmmReg1[32,32],vexVVVV_XmmReg[32,32],XmmReg2_m128[32,32]); + fmadd231(XmmReg1[64,32],XmmReg1[64,32],vexVVVV_XmmReg[64,32],XmmReg2_m128[64,32]); + fmsub231(XmmReg1[96,32],XmmReg1[96,32],vexVVVV_XmmReg[96,32],XmmReg2_m128[96,32]); + ZmmReg1 = zext(XmmReg1); } -# VFMSUB132SS/VFMSUB213SS/VFMSUB231SS 5-196 PAGE 2020 LINE 104913 -define pcodeop vfmsub132ss_fma ; -:VFMSUB132SS XmmReg1, vexVVVV_XmmReg, XmmReg2_m32 is $(VEX_LIG) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & vexVVVV_XmmReg; byte=0x9B; (XmmReg1 & ZmmReg1) ... & XmmReg2_m32 +:VFMSUBADD132PS YmmReg1, vexVVVV_YmmReg, YmmReg2_m256 is $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & vexVVVV_YmmReg; byte=0x97; (YmmReg1 & ZmmReg1) ... & YmmReg2_m256 { - local tmp:16 = vfmsub132ss_fma( XmmReg1, vexVVVV_XmmReg, XmmReg2_m32 ); - ZmmReg1 = zext(tmp); + fmadd132(YmmReg1[ 0,32], YmmReg1[ 0,32], vexVVVV_YmmReg[ 0,32], YmmReg2_m256[ 0,32]); + fmsub132(YmmReg1[ 32,32], YmmReg1[ 32,32], vexVVVV_YmmReg[ 32,32], YmmReg2_m256[ 32,32]); + fmadd132(YmmReg1[ 64,32], YmmReg1[ 64,32], vexVVVV_YmmReg[ 64,32], YmmReg2_m256[ 64,32]); + fmsub132(YmmReg1[ 96,32], YmmReg1[ 96,32], vexVVVV_YmmReg[ 96,32], YmmReg2_m256[ 96,32]); + fmadd132(YmmReg1[128,32], YmmReg1[128,32], vexVVVV_YmmReg[128,32], YmmReg2_m256[128,32]); + fmsub132(YmmReg1[160,32], YmmReg1[160,32], vexVVVV_YmmReg[160,32], YmmReg2_m256[160,32]); + fmadd132(YmmReg1[192,32], YmmReg1[192,32], vexVVVV_YmmReg[192,32], YmmReg2_m256[192,32]); + fmsub132(YmmReg1[224,32], YmmReg1[224,32], vexVVVV_YmmReg[224,32], YmmReg2_m256[224,32]); + ZmmReg1 = zext(YmmReg1); } -# VFMSUB132SS/VFMSUB213SS/VFMSUB231SS 5-196 PAGE 2020 LINE 104916 -define pcodeop vfmsub213ss_fma ; -:VFMSUB213SS XmmReg1, vexVVVV_XmmReg, XmmReg2_m32 is $(VEX_LIG) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & vexVVVV_XmmReg; byte=0xAB; (XmmReg1 & ZmmReg1) ... & XmmReg2_m32 +:VFMSUBADD213PS YmmReg1, vexVVVV_YmmReg, YmmReg2_m256 is $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & vexVVVV_YmmReg; byte=0xA7; (YmmReg1 & ZmmReg1) ... & YmmReg2_m256 { - local tmp:16 = vfmsub213ss_fma( XmmReg1, vexVVVV_XmmReg, XmmReg2_m32 ); - ZmmReg1 = zext(tmp); + fmadd213(YmmReg1[ 0,32], YmmReg1[ 0,32], vexVVVV_YmmReg[ 0,32], YmmReg2_m256[ 0,32]); + fmsub213(YmmReg1[ 32,32], YmmReg1[ 32,32], vexVVVV_YmmReg[ 32,32], YmmReg2_m256[ 32,32]); + fmadd213(YmmReg1[ 64,32], YmmReg1[ 64,32], vexVVVV_YmmReg[ 64,32], YmmReg2_m256[ 64,32]); + fmsub213(YmmReg1[ 96,32], YmmReg1[ 96,32], vexVVVV_YmmReg[ 96,32], YmmReg2_m256[ 96,32]); + fmadd213(YmmReg1[128,32], YmmReg1[128,32], vexVVVV_YmmReg[128,32], YmmReg2_m256[128,32]); + fmsub213(YmmReg1[160,32], YmmReg1[160,32], vexVVVV_YmmReg[160,32], YmmReg2_m256[160,32]); + fmadd213(YmmReg1[192,32], YmmReg1[192,32], vexVVVV_YmmReg[192,32], YmmReg2_m256[192,32]); + fmsub213(YmmReg1[224,32], YmmReg1[224,32], vexVVVV_YmmReg[224,32], YmmReg2_m256[224,32]); + ZmmReg1 = zext(YmmReg1); } -# VFMSUB132SS/VFMSUB213SS/VFMSUB231SS 5-196 PAGE 2020 LINE 104919 -define pcodeop vfmsub231ss_fma ; -:VFMSUB231SS XmmReg1, vexVVVV_XmmReg, XmmReg2_m32 is $(VEX_LIG) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & vexVVVV_XmmReg; byte=0xBB; (XmmReg1 & ZmmReg1) ... & XmmReg2_m32 +:VFMSUBADD231PS YmmReg1, vexVVVV_YmmReg, YmmReg2_m256 is $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & vexVVVV_YmmReg; byte=0xB7; (YmmReg1 & ZmmReg1) ... & YmmReg2_m256 { - local tmp:16 = vfmsub231ss_fma( XmmReg1, vexVVVV_XmmReg, XmmReg2_m32 ); - ZmmReg1 = zext(tmp); + fmadd231(YmmReg1[ 0,32], YmmReg1[ 0,32], vexVVVV_YmmReg[ 0,32], YmmReg2_m256[ 0,32]); + fmsub231(YmmReg1[ 32,32], YmmReg1[ 32,32], vexVVVV_YmmReg[ 32,32], YmmReg2_m256[ 32,32]); + fmadd231(YmmReg1[ 64,32], YmmReg1[ 64,32], vexVVVV_YmmReg[ 64,32], YmmReg2_m256[ 64,32]); + fmsub231(YmmReg1[ 96,32], YmmReg1[ 96,32], vexVVVV_YmmReg[ 96,32], YmmReg2_m256[ 96,32]); + fmadd231(YmmReg1[128,32], YmmReg1[128,32], vexVVVV_YmmReg[128,32], YmmReg2_m256[128,32]); + fmsub231(YmmReg1[160,32], YmmReg1[160,32], vexVVVV_YmmReg[160,32], YmmReg2_m256[160,32]); + fmadd231(YmmReg1[192,32], YmmReg1[192,32], vexVVVV_YmmReg[192,32], YmmReg2_m256[192,32]); + fmsub231(YmmReg1[224,32], YmmReg1[224,32], vexVVVV_YmmReg[224,32], YmmReg2_m256[224,32]); + ZmmReg1 = zext(YmmReg1); } -# VFNMADD132PD/VFNMADD213PD/VFNMADD231PD 5-199 PAGE 2023 LINE 105088 -define pcodeop vfnmadd132pd_fma ; +# VFNMADD132PD/VFNMADD213PD/VFNMADD231PD :VFNMADD132PD XmmReg1, vexVVVV_XmmReg, XmmReg2_m128 is $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & vexVVVV_XmmReg; byte=0x9C; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128 { - local tmp:16 = vfnmadd132pd_fma( XmmReg1, vexVVVV_XmmReg, XmmReg2_m128 ); - ZmmReg1 = zext(tmp); + fnmadd132(XmmReg1[ 0,64],XmmReg1[ 0,64],vexVVVV_XmmReg[ 0,64],XmmReg2_m128[ 0,64]); + fnmadd132(XmmReg1[64,64],XmmReg1[64,64],vexVVVV_XmmReg[64,64],XmmReg2_m128[64,64]); + ZmmReg1 = zext(XmmReg1); } -# VFNMADD132PD/VFNMADD213PD/VFNMADD231PD 5-199 PAGE 2023 LINE 105091 -define pcodeop vfnmadd213pd_fma ; +# VFNMADD132PD/VFNMADD213PD/VFNMADD231PD :VFNMADD213PD XmmReg1, vexVVVV_XmmReg, XmmReg2_m128 is $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & vexVVVV_XmmReg; byte=0xAC; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128 { - local tmp:16 = vfnmadd213pd_fma( XmmReg1, vexVVVV_XmmReg, XmmReg2_m128 ); - ZmmReg1 = zext(tmp); + fnmadd213(XmmReg1[ 0,64],XmmReg1[ 0,64],vexVVVV_XmmReg[ 0,64],XmmReg2_m128[ 0,64]); + fnmadd213(XmmReg1[64,64],XmmReg1[64,64],vexVVVV_XmmReg[64,64],XmmReg2_m128[64,64]); + ZmmReg1 = zext(XmmReg1); } -# VFNMADD132PD/VFNMADD213PD/VFNMADD231PD 5-199 PAGE 2023 LINE 105094 -define pcodeop vfnmadd231pd_fma ; +# VFNMADD132PD/VFNMADD213PD/VFNMADD231PD :VFNMADD231PD XmmReg1, vexVVVV_XmmReg, XmmReg2_m128 is $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & vexVVVV_XmmReg; byte=0xBC; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128 { - local tmp:16 = vfnmadd231pd_fma( XmmReg1, vexVVVV_XmmReg, XmmReg2_m128 ); - ZmmReg1 = zext(tmp); + fnmadd231(XmmReg1[ 0,64],XmmReg1[ 0,64],vexVVVV_XmmReg[ 0,64],XmmReg2_m128[ 0,64]); + fnmadd231(XmmReg1[64,64],XmmReg1[64,64],vexVVVV_XmmReg[64,64],XmmReg2_m128[64,64]); + ZmmReg1 = zext(XmmReg1); } -# VFNMADD132PD/VFNMADD213PD/VFNMADD231PD 5-199 PAGE 2023 LINE 105097 +# VFNMADD132PD/VFNMADD213PD/VFNMADD231PD :VFNMADD132PD YmmReg1, vexVVVV_YmmReg, YmmReg2_m256 is $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & vexVVVV_YmmReg; byte=0x9C; (YmmReg1 & ZmmReg1) ... & YmmReg2_m256 { - local tmp:16 = vfnmadd132pd_fma( YmmReg1, vexVVVV_YmmReg, YmmReg2_m256 ); - ZmmReg1 = zext(tmp); + fnmadd132(YmmReg1[ 0,64], YmmReg1[ 0,64], vexVVVV_YmmReg[ 0,64], YmmReg2_m256[ 0,64]); + fnmadd132(YmmReg1[ 64,64], YmmReg1[ 64,64], vexVVVV_YmmReg[ 64,64], YmmReg2_m256[ 64,64]); + fnmadd132(YmmReg1[128,64], YmmReg1[128,64], vexVVVV_YmmReg[128,64], YmmReg2_m256[128,64]); + fnmadd132(YmmReg1[192,64], YmmReg1[192,64], vexVVVV_YmmReg[192,64], YmmReg2_m256[192,64]); + ZmmReg1 = zext(YmmReg1); } -# VFNMADD132PD/VFNMADD213PD/VFNMADD231PD 5-199 PAGE 2023 LINE 105100 +# VFNMADD132PD/VFNMADD213PD/VFNMADD231PD :VFNMADD213PD YmmReg1, vexVVVV_YmmReg, YmmReg2_m256 is $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & vexVVVV_YmmReg; byte=0xAC; (YmmReg1 & ZmmReg1) ... & YmmReg2_m256 { - local tmp:16 = vfnmadd213pd_fma( YmmReg1, vexVVVV_YmmReg, YmmReg2_m256 ); - ZmmReg1 = zext(tmp); + fnmadd213(YmmReg1[ 0,64], YmmReg1[ 0,64], vexVVVV_YmmReg[ 0,64], YmmReg2_m256[ 0,64]); + fnmadd213(YmmReg1[ 64,64], YmmReg1[ 64,64], vexVVVV_YmmReg[ 64,64], YmmReg2_m256[ 64,64]); + fnmadd213(YmmReg1[128,64], YmmReg1[128,64], vexVVVV_YmmReg[128,64], YmmReg2_m256[128,64]); + fnmadd213(YmmReg1[192,64], YmmReg1[192,64], vexVVVV_YmmReg[192,64], YmmReg2_m256[192,64]); + ZmmReg1 = zext(YmmReg1); } -# VFNMADD132PD/VFNMADD213PD/VFNMADD231PD 5-199 PAGE 2023 LINE 105103 +# VFNMADD132PD/VFNMADD213PD/VFNMADD231PD :VFNMADD231PD YmmReg1, vexVVVV_YmmReg, YmmReg2_m256 is $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & vexVVVV_YmmReg; byte=0xBC; (YmmReg1 & ZmmReg1) ... & YmmReg2_m256 { - local tmp:16 = vfnmadd231pd_fma( YmmReg1, vexVVVV_YmmReg, YmmReg2_m256 ); - ZmmReg1 = zext(tmp); + fnmadd231(YmmReg1[ 0,64], YmmReg1[ 0,64], vexVVVV_YmmReg[ 0,64], YmmReg2_m256[ 0,64]); + fnmadd231(YmmReg1[ 64,64], YmmReg1[ 64,64], vexVVVV_YmmReg[ 64,64], YmmReg2_m256[ 64,64]); + fnmadd231(YmmReg1[128,64], YmmReg1[128,64], vexVVVV_YmmReg[128,64], YmmReg2_m256[128,64]); + fnmadd231(YmmReg1[192,64], YmmReg1[192,64], vexVVVV_YmmReg[192,64], YmmReg2_m256[192,64]); + ZmmReg1 = zext(YmmReg1); } -# VFNMADD132PS/VFNMADD213PS/VFNMADD231PS 5-206 PAGE 2030 LINE 105447 -define pcodeop vfnmadd132ps_fma ; +# VFNMADD132PS/VFNMADD213PS/VFNMADD231PS :VFNMADD132PS XmmReg1, vexVVVV_XmmReg, XmmReg2_m128 is $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & vexVVVV_XmmReg; byte=0x9C; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128 { - local tmp:16 = vfnmadd132ps_fma( XmmReg1, vexVVVV_XmmReg, XmmReg2_m128 ); - ZmmReg1 = zext(tmp); + fnmadd132(XmmReg1[ 0,32], XmmReg1[ 0,32], vexVVVV_XmmReg[ 0,32], XmmReg2_m128[ 0,32]); + fnmadd132(XmmReg1[32,32], XmmReg1[32,32], vexVVVV_XmmReg[32,32], XmmReg2_m128[32,32]); + fnmadd132(XmmReg1[64,32], XmmReg1[64,32], vexVVVV_XmmReg[64,32], XmmReg2_m128[64,32]); + fnmadd132(XmmReg1[96,32], XmmReg1[96,32], vexVVVV_XmmReg[96,32], XmmReg2_m128[96,32]); + ZmmReg1 = zext(XmmReg1); } -# VFNMADD132PS/VFNMADD213PS/VFNMADD231PS 5-206 PAGE 2030 LINE 105450 -define pcodeop vfnmadd213ps_fma ; +# VFNMADD132PS/VFNMADD213PS/VFNMADD231PS :VFNMADD213PS XmmReg1, vexVVVV_XmmReg, XmmReg2_m128 is $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & vexVVVV_XmmReg; byte=0xAC; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128 { - local tmp:16 = vfnmadd213ps_fma( XmmReg1, vexVVVV_XmmReg, XmmReg2_m128 ); - ZmmReg1 = zext(tmp); + fnmadd213(XmmReg1[ 0,32], XmmReg1[ 0,32], vexVVVV_XmmReg[ 0,32], XmmReg2_m128[ 0,32]); + fnmadd213(XmmReg1[32,32], XmmReg1[32,32], vexVVVV_XmmReg[32,32], XmmReg2_m128[32,32]); + fnmadd213(XmmReg1[64,32], XmmReg1[64,32], vexVVVV_XmmReg[64,32], XmmReg2_m128[64,32]); + fnmadd213(XmmReg1[96,32], XmmReg1[96,32], vexVVVV_XmmReg[96,32], XmmReg2_m128[96,32]); + ZmmReg1 = zext(XmmReg1); } -# VFNMADD132PS/VFNMADD213PS/VFNMADD231PS 5-206 PAGE 2030 LINE 105453 -define pcodeop vfnmadd231ps_fma ; +# VFNMADD132PS/VFNMADD213PS/VFNMADD231PS :VFNMADD231PS XmmReg1, vexVVVV_XmmReg, XmmReg2_m128 is $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & vexVVVV_XmmReg; byte=0xBC; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128 { - local tmp:16 = vfnmadd231ps_fma( XmmReg1, vexVVVV_XmmReg, XmmReg2_m128 ); - ZmmReg1 = zext(tmp); + fnmadd231(XmmReg1[ 0,32], XmmReg1[ 0,32], vexVVVV_XmmReg[ 0,32], XmmReg2_m128[ 0,32]); + fnmadd231(XmmReg1[32,32], XmmReg1[32,32], vexVVVV_XmmReg[32,32], XmmReg2_m128[32,32]); + fnmadd231(XmmReg1[64,32], XmmReg1[64,32], vexVVVV_XmmReg[64,32], XmmReg2_m128[64,32]); + fnmadd231(XmmReg1[96,32], XmmReg1[96,32], vexVVVV_XmmReg[96,32], XmmReg2_m128[96,32]); + ZmmReg1 = zext(XmmReg1); } -# VFNMADD132PS/VFNMADD213PS/VFNMADD231PS 5-206 PAGE 2030 LINE 105456 +# VFNMADD132PS/VFNMADD213PS/VFNMADD231PS :VFNMADD132PS YmmReg1, vexVVVV_YmmReg, YmmReg2_m256 is $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & vexVVVV_YmmReg; byte=0x9C; (YmmReg1 & ZmmReg1) ... & YmmReg2_m256 { - local tmp:16 = vfnmadd132ps_fma( YmmReg1, vexVVVV_YmmReg, YmmReg2_m256 ); - ZmmReg1 = zext(tmp); + fnmadd132(YmmReg1[ 0,32], YmmReg1[ 0,32], vexVVVV_YmmReg[ 0,32], YmmReg2_m256[ 0,32]); + fnmadd132(YmmReg1[ 32,32], YmmReg1[ 32,32], vexVVVV_YmmReg[ 32,32], YmmReg2_m256[ 32,32]); + fnmadd132(YmmReg1[ 64,32], YmmReg1[ 64,32], vexVVVV_YmmReg[ 64,32], YmmReg2_m256[ 64,32]); + fnmadd132(YmmReg1[ 96,32], YmmReg1[ 96,32], vexVVVV_YmmReg[ 96,32], YmmReg2_m256[ 96,32]); + fnmadd132(YmmReg1[128,32], YmmReg1[128,32], vexVVVV_YmmReg[128,32], YmmReg2_m256[128,32]); + fnmadd132(YmmReg1[160,32], YmmReg1[160,32], vexVVVV_YmmReg[160,32], YmmReg2_m256[160,32]); + fnmadd132(YmmReg1[192,32], YmmReg1[192,32], vexVVVV_YmmReg[192,32], YmmReg2_m256[192,32]); + fnmadd132(YmmReg1[224,32], YmmReg1[224,32], vexVVVV_YmmReg[224,32], YmmReg2_m256[224,32]); + ZmmReg1 = zext(YmmReg1); } -# VFNMADD132PS/VFNMADD213PS/VFNMADD231PS 5-206 PAGE 2030 LINE 105459 +# VFNMADD132PS/VFNMADD213PS/VFNMADD231PS 5-206 :VFNMADD213PS YmmReg1, vexVVVV_YmmReg, YmmReg2_m256 is $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & vexVVVV_YmmReg; byte=0xAC; (YmmReg1 & ZmmReg1) ... & YmmReg2_m256 { - local tmp:16 = vfnmadd213ps_fma( YmmReg1, vexVVVV_YmmReg, YmmReg2_m256 ); - ZmmReg1 = zext(tmp); + fnmadd213(YmmReg1[ 0,32], YmmReg1[ 0,32], vexVVVV_YmmReg[ 0,32], YmmReg2_m256[ 0,32]); + fnmadd213(YmmReg1[ 32,32], YmmReg1[ 32,32], vexVVVV_YmmReg[ 32,32], YmmReg2_m256[ 32,32]); + fnmadd213(YmmReg1[ 64,32], YmmReg1[ 64,32], vexVVVV_YmmReg[ 64,32], YmmReg2_m256[ 64,32]); + fnmadd213(YmmReg1[ 96,32], YmmReg1[ 96,32], vexVVVV_YmmReg[ 96,32], YmmReg2_m256[ 96,32]); + fnmadd213(YmmReg1[128,32], YmmReg1[128,32], vexVVVV_YmmReg[128,32], YmmReg2_m256[128,32]); + fnmadd213(YmmReg1[160,32], YmmReg1[160,32], vexVVVV_YmmReg[160,32], YmmReg2_m256[160,32]); + fnmadd213(YmmReg1[192,32], YmmReg1[192,32], vexVVVV_YmmReg[192,32], YmmReg2_m256[192,32]); + fnmadd213(YmmReg1[224,32], YmmReg1[224,32], vexVVVV_YmmReg[224,32], YmmReg2_m256[224,32]); + ZmmReg1 = zext(YmmReg1); } -# VFNMADD132PS/VFNMADD213PS/VFNMADD231PS 5-206 PAGE 2030 LINE 105462 -# WARNING: did not recognize VEX field 0 for "VFNMADD231PS ymm1, ymm2, ymm3/m256" -:VFNMADD231PS YmmReg1, vexVVVV_YmmReg, YmmReg2_m256 is $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & vexVVVV_YmmReg; byte=0xBC; (YmmReg1 & ZmmReg1) ... & YmmReg2_m256 +# VFNMADD132PS/VFNMADD213PS/VFNMADD231PS +:VFNMADD231PS YmmReg1, vexVVVV_YmmReg, YmmReg2_m256 is $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & vexVVVV_YmmReg; byte=0xBC; (YmmReg1 & ZmmReg1) ... & YmmReg2_m256 { - local tmp:16 = vfnmadd231ps_fma( YmmReg1, vexVVVV_YmmReg, YmmReg2_m256 ); - ZmmReg1 = zext(tmp); + fnmadd231(YmmReg1[ 0,32], YmmReg1[ 0,32], vexVVVV_YmmReg[ 0,32], YmmReg2_m256[ 0,32]); + fnmadd231(YmmReg1[ 32,32], YmmReg1[ 32,32], vexVVVV_YmmReg[ 32,32], YmmReg2_m256[ 32,32]); + fnmadd231(YmmReg1[ 64,32], YmmReg1[ 64,32], vexVVVV_YmmReg[ 64,32], YmmReg2_m256[ 64,32]); + fnmadd231(YmmReg1[ 96,32], YmmReg1[ 96,32], vexVVVV_YmmReg[ 96,32], YmmReg2_m256[ 96,32]); + fnmadd231(YmmReg1[128,32], YmmReg1[128,32], vexVVVV_YmmReg[128,32], YmmReg2_m256[128,32]); + fnmadd231(YmmReg1[160,32], YmmReg1[160,32], vexVVVV_YmmReg[160,32], YmmReg2_m256[160,32]); + fnmadd231(YmmReg1[192,32], YmmReg1[192,32], vexVVVV_YmmReg[192,32], YmmReg2_m256[192,32]); + fnmadd231(YmmReg1[224,32], YmmReg1[224,32], vexVVVV_YmmReg[224,32], YmmReg2_m256[224,32]); + ZmmReg1 = zext(YmmReg1); } -# VFNMADD132SD/VFNMADD213SD/VFNMADD231SD 5-212 PAGE 2036 LINE 105794 -define pcodeop vfnmadd132sd_fma ; +# VFNMADD132SD/VFNMADD213SD/VFNMADD231SD :VFNMADD132SD XmmReg1, vexVVVV_XmmReg, XmmReg2_m64 is $(VEX_LIG) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & vexVVVV_XmmReg; byte=0x9D; (XmmReg1 & ZmmReg1) ... & XmmReg2_m64 { - local tmp:16 = vfnmadd132sd_fma( XmmReg1, vexVVVV_XmmReg, XmmReg2_m64 ); - ZmmReg1 = zext(tmp); + fnmadd132(XmmReg1[ 0,64],XmmReg1[ 0,64],vexVVVV_XmmReg[ 0,64],XmmReg2_m64[ 0,64]); + # XmmReg1[64,64] = XmmReg1[64,64]; + ZmmReg1 = zext(XmmReg1); } -# VFNMADD132SD/VFNMADD213SD/VFNMADD231SD 5-212 PAGE 2036 LINE 105797 -define pcodeop vfnmadd213sd_fma ; +# VFNMADD132SD/VFNMADD213SD/VFNMADD231SD :VFNMADD213SD XmmReg1, vexVVVV_XmmReg, XmmReg2_m64 is $(VEX_LIG) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & vexVVVV_XmmReg; byte=0xAD; (XmmReg1 & ZmmReg1) ... & XmmReg2_m64 { - local tmp:16 = vfnmadd213sd_fma( XmmReg1, vexVVVV_XmmReg, XmmReg2_m64 ); - ZmmReg1 = zext(tmp); + fnmadd213(XmmReg1[ 0,64],XmmReg1[ 0,64],vexVVVV_XmmReg[ 0,64],XmmReg2_m64[ 0,64]); + # XmmReg1[64,64] = XmmReg1[64,64]; + ZmmReg1 = zext(XmmReg1); } -# VFNMADD132SD/VFNMADD213SD/VFNMADD231SD 5-212 PAGE 2036 LINE 105800 -define pcodeop vfnmadd231sd_fma ; +# VFNMADD132SD/VFNMADD213SD/VFNMADD231SD :VFNMADD231SD XmmReg1, vexVVVV_XmmReg, XmmReg2_m64 is $(VEX_LIG) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & vexVVVV_XmmReg; byte=0xBD; (XmmReg1 & ZmmReg1) ... & XmmReg2_m64 { - local tmp:16 = vfnmadd231sd_fma( XmmReg1, vexVVVV_XmmReg, XmmReg2_m64 ); - ZmmReg1 = zext(tmp); + fnmadd231(XmmReg1[ 0,64],XmmReg1[ 0,64],vexVVVV_XmmReg[ 0,64],XmmReg2_m64[ 0,64]); + # XmmReg1[64,64] = XmmReg1[64,64]; + ZmmReg1 = zext(XmmReg1); } -# VFNMADD132SS/VFNMADD213SS/VFNMADD231SS 5-215 PAGE 2039 LINE 105966 -define pcodeop vfnmadd132ss_fma ; +# VFNMADD132SS/VFNMADD213SS/VFNMADD231SS :VFNMADD132SS XmmReg1, vexVVVV_XmmReg, XmmReg2_m32 is $(VEX_LIG) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & vexVVVV_XmmReg; byte=0x9D; (XmmReg1 & ZmmReg1) ... & XmmReg2_m32 { - local tmp:16 = vfnmadd132ss_fma( XmmReg1, vexVVVV_XmmReg, XmmReg2_m32 ); - ZmmReg1 = zext(tmp); + fnmadd132(XmmReg1[ 0,32], XmmReg1[ 0,32], vexVVVV_XmmReg[ 0,32], XmmReg2_m32[ 0,32]); + # XmmReg1[32,96] = XmmReg1[32,96]; + ZmmReg1 = zext(XmmReg1); } -# VFNMADD132SS/VFNMADD213SS/VFNMADD231SS 5-215 PAGE 2039 LINE 105969 -define pcodeop vfnmadd213ss_fma ; +# VFNMADD132SS/VFNMADD213SS/VFNMADD231SS :VFNMADD213SS XmmReg1, vexVVVV_XmmReg, XmmReg2_m32 is $(VEX_LIG) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & vexVVVV_XmmReg; byte=0xAD; (XmmReg1 & ZmmReg1) ... & XmmReg2_m32 { - local tmp:16 = vfnmadd213ss_fma( XmmReg1, vexVVVV_XmmReg, XmmReg2_m32 ); - ZmmReg1 = zext(tmp); + fnmadd213(XmmReg1[ 0,32], XmmReg1[ 0,32], vexVVVV_XmmReg[ 0,32], XmmReg2_m32[ 0,32]); + # XmmReg1[32,96] = XmmReg1[32,96]; + ZmmReg1 = zext(XmmReg1); } -# VFNMADD132SS/VFNMADD213SS/VFNMADD231SS 5-215 PAGE 2039 LINE 105972 -define pcodeop vfnmadd231ss_fma ; +# VFNMADD132SS/VFNMADD213SS/VFNMADD231SS :VFNMADD231SS XmmReg1, vexVVVV_XmmReg, XmmReg2_m32 is $(VEX_LIG) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & vexVVVV_XmmReg; byte=0xBD; (XmmReg1 & ZmmReg1) ... & XmmReg2_m32 { - local tmp:16 = vfnmadd231ss_fma( XmmReg1, vexVVVV_XmmReg, XmmReg2_m32 ); - ZmmReg1 = zext(tmp); + fnmadd231(XmmReg1[ 0,32], XmmReg1[ 0,32], vexVVVV_XmmReg[ 0,32], XmmReg2_m32[ 0,32]); + # XmmReg1[32,96] = XmmReg1[32,96]; + ZmmReg1 = zext(XmmReg1); } -# VFNMSUB132PD/VFNMSUB213PD/VFNMSUB231PD 5-218 PAGE 2042 LINE 106138 -define pcodeop vfnmsub132pd_fma ; +# VFNMSUB132PD/VFNMSUB213PD/VFNMSUB231PD :VFNMSUB132PD XmmReg1, vexVVVV_XmmReg, XmmReg2_m128 is $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & vexVVVV_XmmReg; byte=0x9E; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128 { - local tmp:16 = vfnmsub132pd_fma( XmmReg1, vexVVVV_XmmReg, XmmReg2_m128 ); - ZmmReg1 = zext(tmp); + fnmsub132(XmmReg1[ 0,64],XmmReg1[ 0,64],vexVVVV_XmmReg[ 0,64],XmmReg2_m128[ 0,64]); + fnmsub132(XmmReg1[64,64],XmmReg1[64,64],vexVVVV_XmmReg[64,64],XmmReg2_m128[64,64]); + ZmmReg1 = zext(XmmReg1); } -# VFNMSUB132PD/VFNMSUB213PD/VFNMSUB231PD 5-218 PAGE 2042 LINE 106141 -define pcodeop vfnmsub213pd_fma ; +# VFNMSUB132PD/VFNMSUB213PD/VFNMSUB231PD :VFNMSUB213PD XmmReg1, vexVVVV_XmmReg, XmmReg2_m128 is $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & vexVVVV_XmmReg; byte=0xAE; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128 { - local tmp:16 = vfnmsub213pd_fma( XmmReg1, vexVVVV_XmmReg, XmmReg2_m128 ); - ZmmReg1 = zext(tmp); + fnmsub213(XmmReg1[ 0,64],XmmReg1[ 0,64],vexVVVV_XmmReg[ 0,64],XmmReg2_m128[ 0,64]); + fnmsub213(XmmReg1[64,64],XmmReg1[64,64],vexVVVV_XmmReg[64,64],XmmReg2_m128[64,64]); + ZmmReg1 = zext(XmmReg1); } -# VFNMSUB132PD/VFNMSUB213PD/VFNMSUB231PD 5-218 PAGE 2042 LINE 106144 -define pcodeop vfnmsub231pd_fma ; +# VFNMSUB132PD/VFNMSUB213PD/VFNMSUB231PD :VFNMSUB231PD XmmReg1, vexVVVV_XmmReg, XmmReg2_m128 is $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & vexVVVV_XmmReg; byte=0xBE; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128 { - local tmp:16 = vfnmsub231pd_fma( XmmReg1, vexVVVV_XmmReg, XmmReg2_m128 ); - ZmmReg1 = zext(tmp); + fnmsub231(XmmReg1[ 0,64],XmmReg1[ 0,64],vexVVVV_XmmReg[ 0,64],XmmReg2_m128[ 0,64]); + fnmsub231(XmmReg1[64,64],XmmReg1[64,64],vexVVVV_XmmReg[64,64],XmmReg2_m128[64,64]); + ZmmReg1 = zext(XmmReg1); } -# VFNMSUB132PD/VFNMSUB213PD/VFNMSUB231PD 5-218 PAGE 2042 LINE 106147 +# VFNMSUB132PD/VFNMSUB213PD/VFNMSUB231PD :VFNMSUB132PD YmmReg1, vexVVVV_YmmReg, YmmReg2_m256 is $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & vexVVVV_YmmReg; byte=0x9E; (YmmReg1 & ZmmReg1) ... & YmmReg2_m256 { - local tmp:16 = vfnmsub132pd_fma( YmmReg1, vexVVVV_YmmReg, YmmReg2_m256 ); - ZmmReg1 = zext(tmp); + fnmsub132(YmmReg1[ 0,64], YmmReg1[ 0,64], vexVVVV_YmmReg[ 0,64], YmmReg2_m256[ 0,64]); + fnmsub132(YmmReg1[ 64,64], YmmReg1[ 64,64], vexVVVV_YmmReg[ 64,64], YmmReg2_m256[ 64,64]); + fnmsub132(YmmReg1[128,64], YmmReg1[128,64], vexVVVV_YmmReg[128,64], YmmReg2_m256[128,64]); + fnmsub132(YmmReg1[192,64], YmmReg1[192,64], vexVVVV_YmmReg[192,64], YmmReg2_m256[192,64]); + ZmmReg1 = zext(YmmReg1); } -# VFNMSUB132PD/VFNMSUB213PD/VFNMSUB231PD 5-218 PAGE 2042 LINE 106150 +# VFNMSUB132PD/VFNMSUB213PD/VFNMSUB231PD :VFNMSUB213PD YmmReg1, vexVVVV_YmmReg, YmmReg2_m256 is $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & vexVVVV_YmmReg; byte=0xAE; (YmmReg1 & ZmmReg1) ... & YmmReg2_m256 { - local tmp:16 = vfnmsub213pd_fma( YmmReg1, vexVVVV_YmmReg, YmmReg2_m256 ); - ZmmReg1 = zext(tmp); + fnmsub213(YmmReg1[ 0,64], YmmReg1[ 0,64], vexVVVV_YmmReg[ 0,64], YmmReg2_m256[ 0,64]); + fnmsub213(YmmReg1[ 64,64], YmmReg1[ 64,64], vexVVVV_YmmReg[ 64,64], YmmReg2_m256[ 64,64]); + fnmsub213(YmmReg1[128,64], YmmReg1[128,64], vexVVVV_YmmReg[128,64], YmmReg2_m256[128,64]); + fnmsub213(YmmReg1[192,64], YmmReg1[192,64], vexVVVV_YmmReg[192,64], YmmReg2_m256[192,64]); + ZmmReg1 = zext(YmmReg1); } -# VFNMSUB132PD/VFNMSUB213PD/VFNMSUB231PD 5-218 PAGE 2042 LINE 106153 +# VFNMSUB132PD/VFNMSUB213PD/VFNMSUB231PD :VFNMSUB231PD YmmReg1, vexVVVV_YmmReg, YmmReg2_m256 is $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & vexVVVV_YmmReg; byte=0xBE; (YmmReg1 & ZmmReg1) ... & YmmReg2_m256 { - local tmp:16 = vfnmsub231pd_fma( YmmReg1, vexVVVV_YmmReg, YmmReg2_m256 ); - ZmmReg1 = zext(tmp); + fnmsub231(YmmReg1[ 0,64], YmmReg1[ 0,64], vexVVVV_YmmReg[ 0,64], YmmReg2_m256[ 0,64]); + fnmsub231(YmmReg1[ 64,64], YmmReg1[ 64,64], vexVVVV_YmmReg[ 64,64], YmmReg2_m256[ 64,64]); + fnmsub231(YmmReg1[128,64], YmmReg1[128,64], vexVVVV_YmmReg[128,64], YmmReg2_m256[128,64]); + fnmsub231(YmmReg1[192,64], YmmReg1[192,64], vexVVVV_YmmReg[192,64], YmmReg2_m256[192,64]); + ZmmReg1 = zext(YmmReg1); } -# VFNMSUB132PS/VFNMSUB213PS/VFNMSUB231PS 5-224 PAGE 2048 LINE 106487 -define pcodeop vfnmsub132ps_fma ; +# VFNMSUB132PS/VFNMSUB213PS/VFNMSUB231PS :VFNMSUB132PS XmmReg1, vexVVVV_XmmReg, XmmReg2_m128 is $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & vexVVVV_XmmReg; byte=0x9E; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128 { - local tmp:16 = vfnmsub132ps_fma( XmmReg1, vexVVVV_XmmReg, XmmReg2_m128 ); - ZmmReg1 = zext(tmp); + fnmsub132(XmmReg1[ 0,32], XmmReg1[ 0,32], vexVVVV_XmmReg[ 0,32], XmmReg2_m128[ 0,32]); + fnmsub132(XmmReg1[32,32], XmmReg1[32,32], vexVVVV_XmmReg[32,32], XmmReg2_m128[32,32]); + fnmsub132(XmmReg1[64,32], XmmReg1[64,32], vexVVVV_XmmReg[64,32], XmmReg2_m128[64,32]); + fnmsub132(XmmReg1[96,32], XmmReg1[96,32], vexVVVV_XmmReg[96,32], XmmReg2_m128[96,32]); + ZmmReg1 = zext(XmmReg1); } -# VFNMSUB132PS/VFNMSUB213PS/VFNMSUB231PS 5-224 PAGE 2048 LINE 106490 -define pcodeop vfnmsub213ps_fma ; +# VFNMSUB132PS/VFNMSUB213PS/VFNMSUB231PS :VFNMSUB213PS XmmReg1, vexVVVV_XmmReg, XmmReg2_m128 is $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & vexVVVV_XmmReg; byte=0xAE; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128 { - local tmp:16 = vfnmsub213ps_fma( XmmReg1, vexVVVV_XmmReg, XmmReg2_m128 ); - ZmmReg1 = zext(tmp); + fnmsub213(XmmReg1[ 0,32], XmmReg1[ 0,32], vexVVVV_XmmReg[ 0,32], XmmReg2_m128[ 0,32]); + fnmsub213(XmmReg1[32,32], XmmReg1[32,32], vexVVVV_XmmReg[32,32], XmmReg2_m128[32,32]); + fnmsub213(XmmReg1[64,32], XmmReg1[64,32], vexVVVV_XmmReg[64,32], XmmReg2_m128[64,32]); + fnmsub213(XmmReg1[96,32], XmmReg1[96,32], vexVVVV_XmmReg[96,32], XmmReg2_m128[96,32]); + ZmmReg1 = zext(XmmReg1); } -# VFNMSUB132PS/VFNMSUB213PS/VFNMSUB231PS 5-224 PAGE 2048 LINE 106493 -define pcodeop vfnmsub231ps_fma ; +# VFNMSUB132PS/VFNMSUB213PS/VFNMSUB231PS :VFNMSUB231PS XmmReg1, vexVVVV_XmmReg, XmmReg2_m128 is $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & vexVVVV_XmmReg; byte=0xBE; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128 { - local tmp:16 = vfnmsub231ps_fma( XmmReg1, vexVVVV_XmmReg, XmmReg2_m128 ); - ZmmReg1 = zext(tmp); + fnmsub231(XmmReg1[ 0,32], XmmReg1[ 0,32], vexVVVV_XmmReg[ 0,32], XmmReg2_m128[ 0,32]); + fnmsub231(XmmReg1[32,32], XmmReg1[32,32], vexVVVV_XmmReg[32,32], XmmReg2_m128[32,32]); + fnmsub231(XmmReg1[64,32], XmmReg1[64,32], vexVVVV_XmmReg[64,32], XmmReg2_m128[64,32]); + fnmsub231(XmmReg1[96,32], XmmReg1[96,32], vexVVVV_XmmReg[96,32], XmmReg2_m128[96,32]); + ZmmReg1 = zext(XmmReg1); } -# VFNMSUB132PS/VFNMSUB213PS/VFNMSUB231PS 5-224 PAGE 2048 LINE 106496 +# VFNMSUB132PS/VFNMSUB213PS/VFNMSUB231PS :VFNMSUB132PS YmmReg1, vexVVVV_YmmReg, YmmReg2_m256 is $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & vexVVVV_YmmReg; byte=0x9E; (YmmReg1 & ZmmReg1) ... & YmmReg2_m256 { - local tmp:16 = vfnmsub132ps_fma( YmmReg1, vexVVVV_YmmReg, YmmReg2_m256 ); - ZmmReg1 = zext(tmp); + fnmsub132(YmmReg1[ 0,32], YmmReg1[ 0,32], vexVVVV_YmmReg[ 0,32], YmmReg2_m256[ 0,32]); + fnmsub132(YmmReg1[ 32,32], YmmReg1[ 32,32], vexVVVV_YmmReg[ 32,32], YmmReg2_m256[ 32,32]); + fnmsub132(YmmReg1[ 64,32], YmmReg1[ 64,32], vexVVVV_YmmReg[ 64,32], YmmReg2_m256[ 64,32]); + fnmsub132(YmmReg1[ 96,32], YmmReg1[ 96,32], vexVVVV_YmmReg[ 96,32], YmmReg2_m256[ 96,32]); + fnmsub132(YmmReg1[128,32], YmmReg1[128,32], vexVVVV_YmmReg[128,32], YmmReg2_m256[128,32]); + fnmsub132(YmmReg1[160,32], YmmReg1[160,32], vexVVVV_YmmReg[160,32], YmmReg2_m256[160,32]); + fnmsub132(YmmReg1[192,32], YmmReg1[192,32], vexVVVV_YmmReg[192,32], YmmReg2_m256[192,32]); + fnmsub132(YmmReg1[224,32], YmmReg1[224,32], vexVVVV_YmmReg[224,32], YmmReg2_m256[224,32]); + ZmmReg1 = zext(YmmReg1); } -# VFNMSUB132PS/VFNMSUB213PS/VFNMSUB231PS 5-224 PAGE 2048 LINE 106499 +# VFNMSUB132PS/VFNMSUB213PS/VFNMSUB231PS :VFNMSUB213PS YmmReg1, vexVVVV_YmmReg, YmmReg2_m256 is $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & vexVVVV_YmmReg; byte=0xAE; (YmmReg1 & ZmmReg1) ... & YmmReg2_m256 { - local tmp:16 = vfnmsub213ps_fma( YmmReg1, vexVVVV_YmmReg, YmmReg2_m256 ); - ZmmReg1 = zext(tmp); + fnmsub213(YmmReg1[ 0,32], YmmReg1[ 0,32], vexVVVV_YmmReg[ 0,32], YmmReg2_m256[ 0,32]); + fnmsub213(YmmReg1[ 32,32], YmmReg1[ 32,32], vexVVVV_YmmReg[ 32,32], YmmReg2_m256[ 32,32]); + fnmsub213(YmmReg1[ 64,32], YmmReg1[ 64,32], vexVVVV_YmmReg[ 64,32], YmmReg2_m256[ 64,32]); + fnmsub213(YmmReg1[ 96,32], YmmReg1[ 96,32], vexVVVV_YmmReg[ 96,32], YmmReg2_m256[ 96,32]); + fnmsub213(YmmReg1[128,32], YmmReg1[128,32], vexVVVV_YmmReg[128,32], YmmReg2_m256[128,32]); + fnmsub213(YmmReg1[160,32], YmmReg1[160,32], vexVVVV_YmmReg[160,32], YmmReg2_m256[160,32]); + fnmsub213(YmmReg1[192,32], YmmReg1[192,32], vexVVVV_YmmReg[192,32], YmmReg2_m256[192,32]); + fnmsub213(YmmReg1[224,32], YmmReg1[224,32], vexVVVV_YmmReg[224,32], YmmReg2_m256[224,32]); + ZmmReg1 = zext(YmmReg1); } -# VFNMSUB132PS/VFNMSUB213PS/VFNMSUB231PS 5-224 PAGE 2048 LINE 106502 -# WARNING: did not recognize VEX field 0 for "VFNMSUB231PS ymm1, ymm2, ymm3/m256" -:VFNMSUB231PS YmmReg1, vexVVVV_YmmReg, YmmReg2_m256 is $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & vexVVVV_YmmReg; byte=0xBE; (YmmReg1 & ZmmReg1) ... & YmmReg2_m256 +# VFNMSUB132PS/VFNMSUB213PS/VFNMSUB231PS +:VFNMSUB231PS YmmReg1, vexVVVV_YmmReg, YmmReg2_m256 is $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & vexVVVV_YmmReg; byte=0xBE; (YmmReg1 & ZmmReg1) ... & YmmReg2_m256 { - local tmp:16 = vfnmsub231ps_fma( YmmReg1, vexVVVV_YmmReg, YmmReg2_m256 ); - ZmmReg1 = zext(tmp); + fnmsub231(YmmReg1[ 0,32], YmmReg1[ 0,32], vexVVVV_YmmReg[ 0,32], YmmReg2_m256[ 0,32]); + fnmsub231(YmmReg1[ 32,32], YmmReg1[ 32,32], vexVVVV_YmmReg[ 32,32], YmmReg2_m256[ 32,32]); + fnmsub231(YmmReg1[ 64,32], YmmReg1[ 64,32], vexVVVV_YmmReg[ 64,32], YmmReg2_m256[ 64,32]); + fnmsub231(YmmReg1[ 96,32], YmmReg1[ 96,32], vexVVVV_YmmReg[ 96,32], YmmReg2_m256[ 96,32]); + fnmsub231(YmmReg1[128,32], YmmReg1[128,32], vexVVVV_YmmReg[128,32], YmmReg2_m256[128,32]); + fnmsub231(YmmReg1[160,32], YmmReg1[160,32], vexVVVV_YmmReg[160,32], YmmReg2_m256[160,32]); + fnmsub231(YmmReg1[192,32], YmmReg1[192,32], vexVVVV_YmmReg[192,32], YmmReg2_m256[192,32]); + fnmsub231(YmmReg1[224,32], YmmReg1[224,32], vexVVVV_YmmReg[224,32], YmmReg2_m256[224,32]); + ZmmReg1 = zext(YmmReg1); } -# VFNMSUB132SD/VFNMSUB213SD/VFNMSUB231SD 5-230 PAGE 2054 LINE 106832 -define pcodeop vfnmsub132sd_fma ; +# VFNMSUB132SD/VFNMSUB213SD/VFNMSUB231SD :VFNMSUB132SD XmmReg1, vexVVVV_XmmReg, XmmReg2_m64 is $(VEX_LIG) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & vexVVVV_XmmReg; byte=0x9F; (XmmReg1 & ZmmReg1) ... & XmmReg2_m64 { - local tmp:16 = vfnmsub132sd_fma( XmmReg1, vexVVVV_XmmReg, XmmReg2_m64 ); - ZmmReg1 = zext(tmp); + fnmsub132(XmmReg1[ 0,64],XmmReg1[ 0,64],vexVVVV_XmmReg[ 0,64],XmmReg2_m64[ 0,64]); + # XmmReg1[64,64] = XmmReg1[64,64]; + ZmmReg1 = zext(XmmReg1); } -# VFNMSUB132SD/VFNMSUB213SD/VFNMSUB231SD 5-230 PAGE 2054 LINE 106835 -define pcodeop vfnmsub213sd_fma ; +# VFNMSUB132SD/VFNMSUB213SD/VFNMSUB231SD :VFNMSUB213SD XmmReg1, vexVVVV_XmmReg, XmmReg2_m64 is $(VEX_LIG) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & vexVVVV_XmmReg; byte=0xAF; (XmmReg1 & ZmmReg1) ... & XmmReg2_m64 { - local tmp:16 = vfnmsub213sd_fma( XmmReg1, vexVVVV_XmmReg, XmmReg2_m64 ); - ZmmReg1 = zext(tmp); + fnmsub213(XmmReg1[ 0,64],XmmReg1[ 0,64],vexVVVV_XmmReg[ 0,64],XmmReg2_m64[ 0,64]); + # XmmReg1[64,64] = XmmReg1[64,64]; + ZmmReg1 = zext(XmmReg1); } -# VFNMSUB132SD/VFNMSUB213SD/VFNMSUB231SD 5-230 PAGE 2054 LINE 106838 -define pcodeop vfnmsub231sd_fma ; +# VFNMSUB132SD/VFNMSUB213SD/VFNMSUB231SD :VFNMSUB231SD XmmReg1, vexVVVV_XmmReg, XmmReg2_m64 is $(VEX_LIG) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & vexVVVV_XmmReg; byte=0xBF; (XmmReg1 & ZmmReg1) ... & XmmReg2_m64 { - local tmp:16 = vfnmsub231sd_fma( XmmReg1, vexVVVV_XmmReg, XmmReg2_m64 ); - ZmmReg1 = zext(tmp); + fnmsub231(XmmReg1[ 0,64],XmmReg1[ 0,64],vexVVVV_XmmReg[ 0,64],XmmReg2_m64[ 0,64]); + # XmmReg1[64,64] = XmmReg1[64,64]; + ZmmReg1 = zext(XmmReg1); } -# VFNMSUB132SS/VFNMSUB213SS/VFNMSUB231SS 5-233 PAGE 2057 LINE 107004 -define pcodeop vfnmsub132ss_fma ; +# VFNMSUB132SS/VFNMSUB213SS/VFNMSUB231SS :VFNMSUB132SS XmmReg1, vexVVVV_XmmReg, XmmReg2_m32 is $(VEX_LIG) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & vexVVVV_XmmReg; byte=0x9F; (XmmReg1 & ZmmReg1) ... & XmmReg2_m32 { - local tmp:16 = vfnmsub132ss_fma( XmmReg1, vexVVVV_XmmReg, XmmReg2_m32 ); - ZmmReg1 = zext(tmp); + fnmsub132(XmmReg1[ 0,32], XmmReg1[ 0,32], vexVVVV_XmmReg[ 0,32], XmmReg2_m32[ 0,32]); + # XmmReg1[32,96] = XmmReg1[32,96]; + ZmmReg1 = zext(XmmReg1); } -# VFNMSUB132SS/VFNMSUB213SS/VFNMSUB231SS 5-233 PAGE 2057 LINE 107007 -define pcodeop vfnmsub213ss_fma ; +# VFNMSUB132SS/VFNMSUB213SS/VFNMSUB231SS :VFNMSUB213SS XmmReg1, vexVVVV_XmmReg, XmmReg2_m32 is $(VEX_LIG) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & vexVVVV_XmmReg; byte=0xAF; (XmmReg1 & ZmmReg1) ... & XmmReg2_m32 { - local tmp:16 = vfnmsub213ss_fma( XmmReg1, vexVVVV_XmmReg, XmmReg2_m32 ); - ZmmReg1 = zext(tmp); + fnmsub213(XmmReg1[ 0,32], XmmReg1[ 0,32], vexVVVV_XmmReg[ 0,32], XmmReg2_m32[ 0,32]); + # XmmReg1[32,96] = XmmReg1[32,96]; + ZmmReg1 = zext(XmmReg1); } -# VFNMSUB132SS/VFNMSUB213SS/VFNMSUB231SS 5-233 PAGE 2057 LINE 107010 -define pcodeop vfnmsub231ss_fma ; +# VFNMSUB132SS/VFNMSUB213SS/VFNMSUB231SS :VFNMSUB231SS XmmReg1, vexVVVV_XmmReg, XmmReg2_m32 is $(VEX_LIG) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & vexVVVV_XmmReg; byte=0xBF; (XmmReg1 & ZmmReg1) ... & XmmReg2_m32 { - local tmp:16 = vfnmsub231ss_fma( XmmReg1, vexVVVV_XmmReg, XmmReg2_m32 ); - ZmmReg1 = zext(tmp); + fnmsub231(XmmReg1[ 0,32], XmmReg1[ 0,32], vexVVVV_XmmReg[ 0,32], XmmReg2_m32[ 0,32]); + # XmmReg1[32,96] = XmmReg1[32,96]; + ZmmReg1 = zext(XmmReg1); } diff --git a/pypcode/processors/x86/data/languages/gfni.sinc b/pypcode/processors/x86/data/languages/gfni.sinc new file mode 100644 index 0000000..469187f --- /dev/null +++ b/pypcode/processors/x86/data/languages/gfni.sinc @@ -0,0 +1,193 @@ +#66 0F3A CF /r /ib +#GF2P8AFFINEINVQB xmm1, +#xmm2/m128, imm8 A V/V +#GFNI Computes inverse affine transformation in the finite field GF(2^8). +define pcodeop gf2p8affineinvqb; +:GF2P8AFFINEINVQB XmmReg1, XmmReg2_m128, imm8 is vexMode=0 & $(PRE_66) & byte=0x0F; byte=0x3A; byte=0xCF; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128; imm8 +[ evexD8Type = 0; evexTType = 0; ] # (TupleType Full) +{ + XmmReg1 = gf2p8affineinvqb(XmmReg2_m128, XmmReg1, imm8:1 ); + ZmmReg1 = zext(XmmReg1); +} + +#VEX.128.66.0F3A.W1 CF /r /ib +#VGF2P8AFFINEINVQB xmm1, xmm2, +#xmm3/m128, imm8 B V/V +#AVX GFNI Computes inverse affine transformation in the finite field GF(2^8). +define pcodeop vgf2p8affineinvqb_avx; +:VGF2P8AFFINEINVQB XmmReg1, vexVVVV_XmmReg, XmmReg2_m128, imm8 is $(VEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W1) & vexVVVV_XmmReg; byte=0xCF; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128; imm8 +[ evexD8Type = 0; evexTType = 0; ] # (TupleType Full) +{ + XmmReg1 = vgf2p8affineinvqb_avx( vexVVVV_XmmReg, XmmReg2_m128, imm8:1 ); + ZmmReg1 = zext(XmmReg1); +} +#VEX.256.66.0F3A.W1 CF /r /ib +#VGF2P8AFFINEINVQB ymm1, ymm2, +#ymm3/m256, imm8 B V/V AVX +#GFNI Computes inverse affine transformation in the finite field GF(2^8). +:VGF2P8AFFINEINVQB YmmReg1, vexVVVV_YmmReg, YmmReg2_m256, imm8 is $(VEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W1) & vexVVVV_YmmReg; byte=0xCF; (YmmReg1 & ZmmReg1) ... & YmmReg2_m256; imm8 +[ evexD8Type = 0; evexTType = 0; ] # (TupleType Full) +{ + YmmReg1 = vgf2p8affineinvqb_avx( vexVVVV_YmmReg, YmmReg2_m256, imm8:1 ); + ZmmReg1 = zext(YmmReg1); +} + +# GF2P8AFFINEINVQB 3-476 PAGE 1046 LINE 56498 +define pcodeop vgf2p8affineinvqb_avx512vl ; +:VGF2P8AFFINEINVQB XmmReg1 XmmOpMask8, evexV5_XmmReg, XmmReg2_m128_m64bcst, imm8 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W1) & XmmOpMask8 & evexV5_XmmReg; byte=0xCF; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128_m64bcst; imm8 +[ evexD8Type = 0; evexTType = 0; ] # (TupleType Full) +{ + XmmResult = vgf2p8affineinvqb_avx512vl( evexV5_XmmReg, XmmReg2_m128_m64bcst, imm8:1 ); + XmmMask = XmmReg1; + build XmmOpMask8; + ZmmReg1 = zext(XmmResult); +} + +# GF2P8AFFINEINVQB 3-476 PAGE 1046 LINE 56501 +:VGF2P8AFFINEINVQB YmmReg1 YmmOpMask8, evexV5_YmmReg, YmmReg2_m256_m64bcst, imm8 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W1) & YmmOpMask8 & evexV5_YmmReg; byte=0xCF; (YmmReg1 & ZmmReg1) ... & YmmReg2_m256_m64bcst; imm8 +[ evexD8Type = 0; evexTType = 0; ] # (TupleType Full) +{ + YmmResult = vgf2p8affineinvqb_avx512vl( evexV5_YmmReg, YmmReg2_m256_m64bcst, imm8:1 ); + YmmMask = YmmReg1; + build YmmOpMask8; + ZmmReg1 = zext(YmmResult); +} + +# GF2P8AFFINEINVQB 3-476 PAGE 1046 LINE 56504 +define pcodeop vgf2p8affineinvqb_avx512f ; +:VGF2P8AFFINEINVQB ZmmReg1 ZmmOpMask8, evexV5_ZmmReg, ZmmReg2_m512_m64bcst, imm8 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W1) & ZmmOpMask8 & evexV5_ZmmReg; byte=0xCF; ZmmReg1 ... & ZmmReg2_m512_m64bcst; imm8 +[ evexD8Type = 0; evexTType = 0; ] # (TupleType Full) +{ + ZmmResult = vgf2p8affineinvqb_avx512f( evexV5_ZmmReg, ZmmReg2_m512_m64bcst, imm8:1 ); + ZmmMask = ZmmReg1; + build ZmmOpMask8; + ZmmReg1 = ZmmResult; +} + +#66 0F3A CE /r /ib +#GF2P8AFFINEQB xmm1, xmm2/m128, imm8 A V/V GFNI +#Computes affine transformation in the finite field GF(2^8). +define pcodeop gf2p8affineqb; +:GF2P8AFFINEQB XmmReg1, XmmReg2_m128, imm8 is vexMode=0 & $(PRE_66) & byte=0x0F; byte=0x3A; byte=0xCE; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128; imm8 +[ evexD8Type = 0; evexTType = 0; ] # (TupleType Full) +{ + XmmReg1 = gf2p8affineqb(XmmReg2_m128, XmmReg1, imm8:1 ); + ZmmReg1 = zext(XmmReg1); +} + +#VEX.128.66.0F3A.W1 CE /r /ib +#VGF2P8AFFINEQB xmm1, xmm2, xmm3/m128, imm8 B V/V AVX +#GFNI Computes affine transformation in the finite field GF(2^8). +define pcodeop vgf2p8affineqb_avx; +:VGF2P8AFFINEQB XmmReg1, vexVVVV_XmmReg, XmmReg2_m128, imm8 is $(VEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W1) & vexVVVV_XmmReg; byte=0xCE; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128; imm8 +[ evexD8Type = 0; evexTType = 0; ] # (TupleType Full) +{ + XmmReg1 = vgf2p8affineqb_avx( vexVVVV_XmmReg, XmmReg2_m128, imm8:1 ); + ZmmReg1 = zext(XmmReg1); +} + +#VEX.256.66.0F3A.W1 CE /r /ib +#VGF2P8AFFINEQB ymm1, ymm2, ymm3/m256, imm8 B V/V AVX +#GFNI Computes affine transformation in the finite field GF(2^8). +:VGF2P8AFFINEQB YmmReg1, vexVVVV_YmmReg, YmmReg2_m256, imm8 is $(VEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W1) & vexVVVV_YmmReg; byte=0xCE; (YmmReg1 & ZmmReg1) ... & YmmReg2_m256; imm8 +[ evexD8Type = 0; evexTType = 0; ] # (TupleType Full) +{ + YmmReg1 = vgf2p8affineqb_avx( vexVVVV_YmmReg, YmmReg2_m256, imm8:1 ); + ZmmReg1 = zext(YmmReg1); +} + +# GF2P8AFFINEQB 3-479 PAGE 1049 LINE 56642 +define pcodeop vgf2p8affineqb_avx512vl ; +:VGF2P8AFFINEQB XmmReg1 XmmOpMask8, evexV5_XmmReg, XmmReg2_m128_m64bcst, imm8 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W1) & XmmOpMask8 & evexV5_XmmReg; byte=0xCE; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128_m64bcst; imm8 +[ evexD8Type = 0; evexTType = 0; ] # (TupleType Full) +{ + XmmResult = vgf2p8affineqb_avx512vl( evexV5_XmmReg, XmmReg2_m128_m64bcst, imm8:1 ); + XmmMask = XmmReg1; + build XmmOpMask8; + ZmmReg1 = zext(XmmResult); +} + +# GF2P8AFFINEQB 3-479 PAGE 1049 LINE 56645 +:VGF2P8AFFINEQB YmmReg1 YmmOpMask8, evexV5_YmmReg, YmmReg2_m256_m64bcst, imm8 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W1) & YmmOpMask8 & evexV5_YmmReg; byte=0xCE; (YmmReg1 & ZmmReg1) ... & YmmReg2_m256_m64bcst; imm8 +[ evexD8Type = 0; evexTType = 0; ] # (TupleType Full) +{ + YmmResult = vgf2p8affineqb_avx512vl( evexV5_YmmReg, YmmReg2_m256_m64bcst, imm8:1 ); + YmmMask = YmmReg1; + build YmmOpMask8; + ZmmReg1 = zext(YmmResult); +} + +# GF2P8AFFINEQB 3-479 PAGE 1049 LINE 56648 +define pcodeop vgf2p8affineqb_avx512f ; +:VGF2P8AFFINEQB ZmmReg1 ZmmOpMask8, evexV5_ZmmReg, ZmmReg2_m512_m64bcst, imm8 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W1) & ZmmOpMask8 & evexV5_ZmmReg; byte=0xCE; ZmmReg1 ... & ZmmReg2_m512_m64bcst; imm8 +[ evexD8Type = 0; evexTType = 0; ] # (TupleType Full) +{ + ZmmResult = vgf2p8affineqb_avx512f( evexV5_ZmmReg, ZmmReg2_m512_m64bcst, imm8:1 ); + ZmmMask = ZmmReg1; + build ZmmOpMask8; + ZmmReg1 = ZmmResult; +} + +#66 0F38 CF /r +#GF2P8MULB xmm1, xmm2/m128 A V/V +#GFNI Multiplies elements in the finite field GF(2^8). +define pcodeop gf2p8mulb; +:GF2P8MULB XmmReg1, XmmReg2_m128, imm8 is vexMode=0 & $(PRE_66) & byte=0x0F; byte=0x38; byte=0xCF; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128; imm8 +[ evexD8Type = 0; evexTType = 0; ] # (TupleType Full) +{ + XmmReg1 = gf2p8mulb(XmmReg2_m128, XmmReg1, imm8:1 ); + ZmmReg1 = zext(XmmReg1); +} + +#VEX.128.66.0F38.W0 CF /r +#VGF2P8MULB xmm1, xmm2, xmm3/m128 B V/V AVX +#GFNI Multiplies elements in the finite field GF(2^8). +define pcodeop vgf2p8mulb_avx; +:VGF2P8MULB XmmReg1, vexVVVV_XmmReg, XmmReg2_m128, imm8 is $(VEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & vexVVVV_XmmReg; byte=0xCF; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128; imm8 +[ evexD8Type = 0; evexTType = 0; ] # (TupleType Full) +{ + XmmReg1 = vgf2p8affineqb_avx( vexVVVV_XmmReg, XmmReg2_m128, imm8:1 ); + ZmmReg1 = zext(XmmReg1); +} + +#VEX.256.66.0F38.W0 CF /r +#VGF2P8MULB ymm1, ymm2, ymm3/m256 B V/V AVX +#GFNI Multiplies elements in the finite field GF(2^8). +:VGF2P8MULB YmmReg1, vexVVVV_YmmReg, YmmReg2_m256, imm8 is $(VEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & vexVVVV_YmmReg; byte=0xCF; (YmmReg1 & ZmmReg1) ... & YmmReg2_m256; imm8 +[ evexD8Type = 0; evexTType = 0; ] # (TupleType Full) +{ + YmmReg1 = vgf2p8mulb_avx( vexVVVV_YmmReg, YmmReg2_m256, imm8:1 ); + ZmmReg1 = zext(YmmReg1); +} + +# GF2P8MULB 3-481 PAGE 1051 LINE 56754 +define pcodeop vgf2p8mulb_avx512vl ; +:VGF2P8MULB XmmReg1 XmmOpMask8, evexV5_XmmReg, XmmReg2_m128 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & XmmOpMask8 & evexV5_XmmReg; byte=0xCF; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128 +[ evexD8Type = 1; evexTType = 0; ] # (TupleType Full Mem) +{ + XmmResult = vgf2p8mulb_avx512vl( evexV5_XmmReg, XmmReg2_m128 ); + XmmMask = XmmReg1; + build XmmOpMask8; + ZmmReg1 = zext(XmmResult); +} + +# GF2P8MULB 3-481 PAGE 1051 LINE 56757 +:VGF2P8MULB YmmReg1 YmmOpMask8, evexV5_YmmReg, YmmReg2_m256 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & YmmOpMask8 & evexV5_YmmReg; byte=0xCF; (YmmReg1 & ZmmReg1) ... & YmmReg2_m256 +[ evexD8Type = 1; evexTType = 0; ] # (TupleType Full Mem) +{ + YmmResult = vgf2p8mulb_avx512vl( evexV5_YmmReg, YmmReg2_m256 ); + YmmMask = YmmReg1; + build YmmOpMask8; + ZmmReg1 = zext(YmmResult); +} + +# GF2P8MULB 3-481 PAGE 1051 LINE 56760 +define pcodeop vgf2p8mulb_avx512f ; +:VGF2P8MULB ZmmReg1 ZmmOpMask8, evexV5_ZmmReg, ZmmReg2_m512 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & ZmmOpMask8 & evexV5_ZmmReg; byte=0xCF; ZmmReg1 ... & ZmmReg2_m512 +[ evexD8Type = 1; evexTType = 0; ] # (TupleType Full Mem) +{ + ZmmResult = vgf2p8mulb_avx512f( evexV5_ZmmReg, ZmmReg2_m512 ); + ZmmMask = ZmmReg1; + build ZmmOpMask8; + ZmmReg1 = ZmmResult; +} \ No newline at end of file diff --git a/pypcode/processors/x86/data/languages/ia.sinc b/pypcode/processors/x86/data/languages/ia.sinc index d216d90..fad8c59 100644 --- a/pypcode/processors/x86/data/languages/ia.sinc +++ b/pypcode/processors/x86/data/languages/ia.sinc @@ -479,6 +479,7 @@ define context contextreg # For example: CRC32 r32, r16 -- 66 F2 OF 38 F1 C8 @define PRE_NO "mandover=0" +@define PRE_NOFX "(mandover=0 | prefix_66=1)" @define PRE_66 "prefix_66=1" @define PRE_F3 "prefix_f3=1" @define PRE_F2 "prefix_f2=1" @@ -865,28 +866,28 @@ XmmReg1: xmmreg1 is rexRprefix=0 & xmmreg1 { export XmmReg1: xmmreg1_x is rexRprefix=1 & xmmreg1_x { export xmmreg1_x; } XmmReg1: xmmreg1_r is rexRprefix=0 & evexRp=1 & xmmreg1_r { export xmmreg1_r; } XmmReg1: xmmreg1_rx is rexRprefix=1 & evexRp=1 & xmmreg1_rx { export xmmreg1_rx; } -XmmReg2: xmmreg2 is rexBprefix=0 & xmmreg2 { export xmmreg2; } -XmmReg2: xmmreg2_b is rexBprefix=1 & xmmreg2_b { export xmmreg2_b; } -XmmReg2: xmmreg2_x is rexBprefix=0 & rexXprefix=1 & xmmreg2_x { export xmmreg2_x; } -XmmReg2: xmmreg2_bx is rexBprefix=1 & rexXprefix=1 & xmmreg2_bx { export xmmreg2_bx; } +XmmReg2: xmmreg2 is rexBprefix=0 & xmmreg2 { export xmmreg2; } +XmmReg2: xmmreg2_b is rexBprefix=1 & xmmreg2_b { export xmmreg2_b; } +XmmReg2: xmmreg2_x is vexMode=2 & rexBprefix=0 & rexXprefix=1 & xmmreg2_x { export xmmreg2_x; } +XmmReg2: xmmreg2_bx is vexMode=2 & rexBprefix=1 & rexXprefix=1 & xmmreg2_bx { export xmmreg2_bx; } -YmmReg1: ymmreg1 is rexRprefix=0 & ymmreg1 { export ymmreg1; } -YmmReg1: ymmreg1_x is rexRprefix=1 & ymmreg1_x { export ymmreg1_x; } +YmmReg1: ymmreg1 is rexRprefix=0 & ymmreg1 { export ymmreg1; } +YmmReg1: ymmreg1_x is rexRprefix=1 & ymmreg1_x { export ymmreg1_x; } YmmReg1: ymmreg1_r is rexRprefix=0 & evexRp=1 & ymmreg1_r { export ymmreg1_r; } YmmReg1: ymmreg1_rx is rexRprefix=1 & evexRp=1 & ymmreg1_rx { export ymmreg1_rx; } -YmmReg2: ymmreg2 is rexBprefix=0 & ymmreg2 { export ymmreg2; } -YmmReg2: ymmreg2_b is rexBprefix=1 & ymmreg2_b { export ymmreg2_b; } -YmmReg2: ymmreg2_x is rexBprefix=0 & rexXprefix=1 & ymmreg2_x { export ymmreg2_x; } -YmmReg2: ymmreg2_bx is rexBprefix=1 & rexXprefix=1 & ymmreg2_bx { export ymmreg2_bx; } +YmmReg2: ymmreg2 is rexBprefix=0 & ymmreg2 { export ymmreg2; } +YmmReg2: ymmreg2_b is rexBprefix=1 & ymmreg2_b { export ymmreg2_b; } +YmmReg2: ymmreg2_x is vexMode=2 & rexBprefix=0 & rexXprefix=1 & ymmreg2_x { export ymmreg2_x; } +YmmReg2: ymmreg2_bx is vexMode=2 & rexBprefix=1 & rexXprefix=1 & ymmreg2_bx { export ymmreg2_bx; } -ZmmReg1: zmmreg1 is rexRprefix=0 & zmmreg1 { export zmmreg1; } -ZmmReg1: zmmreg1_x is rexRprefix=1 & zmmreg1_x { export zmmreg1_x; } +ZmmReg1: zmmreg1 is rexRprefix=0 & zmmreg1 { export zmmreg1; } +ZmmReg1: zmmreg1_x is rexRprefix=1 & zmmreg1_x { export zmmreg1_x; } ZmmReg1: zmmreg1_r is rexRprefix=0 & evexRp=1 & zmmreg1_r { export zmmreg1_r; } ZmmReg1: zmmreg1_rx is rexRprefix=1 & evexRp=1 & zmmreg1_rx { export zmmreg1_rx; } -ZmmReg2: zmmreg2 is rexBprefix=0 & zmmreg2 { export zmmreg2; } -ZmmReg2: zmmreg2_b is rexBprefix=1 & zmmreg2_b { export zmmreg2_b; } -ZmmReg2: zmmreg2_x is rexBprefix=0 & rexXprefix=1 & zmmreg2_x { export zmmreg2_x; } -ZmmReg2: zmmreg2_bx is rexBprefix=1 & rexXprefix=1 & zmmreg2_bx { export zmmreg2_bx; } +ZmmReg2: zmmreg2 is rexBprefix=0 & zmmreg2 { export zmmreg2; } +ZmmReg2: zmmreg2_b is rexBprefix=1 & zmmreg2_b { export zmmreg2_b; } +ZmmReg2: zmmreg2_x is vexMode=2 & rexBprefix=0 & rexXprefix=1 & zmmreg2_x { export zmmreg2_x; } +ZmmReg2: zmmreg2_bx is vexMode=2 & rexBprefix=1 & rexXprefix=1 & zmmreg2_bx { export zmmreg2_bx; } Xmm_vsib: xmm_vsib is rexXprefix=0 & xmm_vsib { export xmm_vsib; } Xmm_vsib: xmm_vsib_x is rexXprefix=1 & xmm_vsib_x { export xmm_vsib_x; } @@ -1025,6 +1026,7 @@ usimm8_64: val is imm8 & imm8_7=1 [ val = 0xffffffffffffff00 | imm8; ] { export # RIP/EIP relative address - NOTE: export of size 0 is intentional so it may be adjusted pcRelSimm32: addr is simm32 [ addr=inst_next+simm32; ] { export addr; } +pcRelSimm32_32: addr is simm32 [ addr=(inst_next+simm32) & 0xffffffff; ] { export addr; } # 16-bit addressing modes (the offset portion) addr16: [BX + SI] is mod=0 & r_m=0 & BX & SI { local tmp=BX+SI; export tmp; } @@ -1072,9 +1074,8 @@ addr32: [Base + imm32] is mod=2 & r_m=4; index=4 & Base; imm32 { local addr32: [Base + Index*ss] is mod=2 & r_m=4; Index & Base & ss; imm32=0 { local tmp=Base+Index*ss; export tmp; } addr32: [Base] is mod=2 & r_m=4; index=4 & Base; imm32=0 { export Base; } @ifdef IA64 -addr32: [pcRelSimm32] is bit64=1 & mod=0 & r_m=4; index=4 & base=5; pcRelSimm32 { export *[const]:4 pcRelSimm32; } -Addr32_64: [pcRelSimm32] is mod=0 & r_m=5; pcRelSimm32 { export *[const]:8 pcRelSimm32; } +Addr32_64: [pcRelSimm32_32] is mod=0 & r_m=5; pcRelSimm32_32 { export *[const]:8 pcRelSimm32_32; } Addr32_64: [imm32] is mod=0 & r_m=4; index=4 & base=5; imm32 { export *[const]:8 imm32; } Addr32_64: addr32 is addr32 { tmp:8 = sext(addr32); export tmp; } @@ -1502,12 +1503,14 @@ check_Rmr32_dest: is rexBprefix=0 & r32 & r64 { r64 = zext(r32); } check_Rmr32_dest: is rexBprefix=1 & r32_x & r64_x { r64_x = zext(r32_x); } check_rm32_dest: is mod=3 & check_Rmr32_dest { build check_Rmr32_dest; } check_EAX_dest: is epsilon { RAX = zext(EAX); } +check_ECX_dest: is epsilon { RCX = zext(ECX); } check_EDX_dest: is epsilon { RDX = zext(EDX); } check_vexVVVV_r32_dest: is bit64=1 & vexVVVV_r64 & vexVVVV_r32 { vexVVVV_r64 = zext(vexVVVV_r32);} @else check_Reg32_dest: is epsilon { } check_Rmr32_dest: is epsilon { } check_EAX_dest: is epsilon { } +check_ECX_dest: is epsilon { } check_EDX_dest: is epsilon { } check_vexVVVV_r32_dest: is epsilon { } @endif @@ -2187,68 +2190,33 @@ macro multflags(highhalf) { } macro rolflags(result,count) { - - local notzero = (count != 0); - local newCF = ((result & 1) != 0); - CF = (!notzero & CF) | (notzero & newCF); - - local one = (count == 1); - local newOF = CF ^ (result s< 0); - OF = (!one & OF) | (one & newOF); + conditionalAssign(CF, count==0, CF, (result & 1) != 0); + conditionalAssign(OF, count==1, CF ^ (result s< 0), OF); } macro rorflags(result,count) { - - local notzero = (count != 0); - local newCF = (result s< 0); - CF = (!notzero & CF) | (notzero & newCF); - - local one = (count == 1); - local newOF = (result s< 0) ^ ((result << 1) s< 0); - OF = (!one & OF) | (one & newOF); + conditionalAssign(CF, count==0, CF, (result s< 0)); + conditionalAssign(OF, count==1, CF ^ ((result << 1) s< 0), OF); } macro shlflags(op1,result,count) { # works for shld also - - local notzero = (count != 0); - local newCF = ( (op1 << (count - 1)) s< 0 ); - CF = (!notzero & CF) | (notzero & newCF); - - local one = (count == 1); - local newOF = CF ^ (result s< 0); - OF = (!one & OF) | (one & newOF); + conditionalAssign(CF, count==0, CF, (op1 << (count - 1)) s< 0); + conditionalAssign(OF, count==1, CF ^ (result s< 0), OF); } macro sarflags(op1,result,count) { - - local notzero = (count != 0); - local newCF = ( ( (op1 s>> (count - 1)) & 1 ) != 0 ); - CF = (!notzero & CF) | (notzero & newCF); - - local one = (count == 1); - OF = (!one & OF); + conditionalAssign(CF, count==0, CF, ( (op1 s>> (count - 1)) & 1 ) != 0 ); + conditionalAssign(OF, count==1, 0, OF); } macro shrflags(op1,result,count) { - - local notzero = (count != 0); - local newCF = ( ( (op1 >> (count - 1)) & 1 ) != 0 ); - CF = (!notzero & CF) | (notzero & newCF); - - local one = (count == 1); - local newOF = (op1 s< 0); - OF = (!one & OF) | (one & newOF); + conditionalAssign(CF, count==0, CF, ( (op1 >> (count - 1)) & 1 ) != 0 ); + conditionalAssign(OF, count==1, 0, (op1 s< 0)); } macro shrdflags(op1,result,count) { - - local notzero = (count != 0); - local newCF = ( ( (op1 >> (count - 1)) & 1 ) != 0 ); - CF = (!notzero & CF) | (notzero & newCF); - - local one = (count == 1); - local newOF = ((op1 s< 0) ^ (result s< 0)); - OF = (!one & OF) | (one & newOF); + conditionalAssign(CF, count==0, CF, ( (op1 >> (count - 1)) & 1 ) != 0 ); + conditionalAssign(OF, count==1, 0, ((op1 s< 0) ^ (result s< 0))); } macro fdec() { @@ -2418,6 +2386,7 @@ macro fucompe(val1, val2) { @define VEX_MAP4 "vexMMMMM=4" @define VEX_MAP5 "vexMMMMM=5" @define VEX_MAP6 "vexMMMMM=6" +@define VEX_MAP7 "vexMMMMM=7" # Specification is "WIG", "W0", or "W1". @define VEX_WIG "rexWprefix" @@ -2623,7 +2592,7 @@ with : lockprefx=0 { #ARPL is not encodable in 64-bit mode :ARPL rm16,Reg16 is $(LONGMODE_OFF) & vexMode=0 & bit64=0 & byte=0x63; rm16 & Reg16 ... { local rpldest=rm16&3; local rplsrc=Reg16&3; local rpldiff=rplsrc-rpldest; - ZF = rpldiff s> 0; rm16 = rm16 + (zext(CF) * rpldiff); } + ZF = rpldiff s> 0; rm16 = rm16 + (zext(ZF) * rpldiff); } :BOUND Reg16,m16 is $(LONGMODE_OFF) & vexMode=0 & bit64=0 & opsize=0 & byte=0x62; m16 & Reg16 ... { } :BOUND Reg32,m32 is $(LONGMODE_OFF) & vexMode=0 & bit64=0 & opsize=1 & byte=0x62; m32 & Reg32 ... { } @@ -3012,12 +2981,17 @@ with : lockprefx=0 { :CQO is $(LONGMODE_ON) & vexMode=0 & opsize=2 & byte=0x99 { tmp:16 = sext(RAX); RDX = tmp(8); } @endif +define pcodeop cldemote; +:CLDEMOTE m8 is vexMode=0 & $(PRE_NO) & byte=0x0F; byte=0x1C; reg_opcode=0 ... & m8 { + cldemote(m8); +} + define pcodeop clflush; :CLFLUSH m8 is vexMode=0 & mandover=0 & byte=0x0F; byte=0xAE; ( mod != 0b11 & reg_opcode=7 ) ... & m8 { clflush(m8); } -:CLAC is vexMode=0 & byte=0x0F; byte=0x01; byte=0xCA { AC = 0; } +:CLAC is $(PRE_NO) & vexMode=0 & byte=0x0F; byte=0x01; byte=0xCA { AC = 0; } :CLC is vexMode=0 & byte=0xf8 { CF = 0; } :CLD is vexMode=0 & byte=0xfc { DF = 0; } @@ -3258,20 +3232,28 @@ define pcodeop cpuid_brand_part3_info; } -:DAA is vexMode=0 & bit64=0 & byte=0x27 { local car = ((AL & 0xf) > 9) | AF; +:DAA is vexMode=0 & bit64=0 & byte=0x27 { local oldAL = AL; + local oldCF = CF; + CF = 0; + local car = ((AL & 0xf) > 9) | AF; AL = AL + 6 * car; - CF = CF | car * carry(AL,6); AF = car; - car = ((AL & 0xf0) > 0x90) | CF; + # CF set if car, but immediately overwritten by second if-else pair regardless + car = (oldAL > 0x99) | oldCF; AL = AL + 0x60 * car; - CF = car; } -:DAS is vexMode=0 & bit64=0 & byte=0x2f { local car = ((AL & 0xf) > 9) | AF; + CF = car; + resultflags(AL); } +:DAS is vexMode=0 & bit64=0 & byte=0x2f { local oldAL = AL; + local oldCF = CF; + CF = 0; + local car = ((AL & 0xf) > 9) | AF; + CF = oldCF | (AL < 6); # borrow from AL - 6 AL = AL - 6 * car; - CF = CF | car * (AL < 6); AF = car; - car = (AL > 0x9f) | CF; + car = (oldAL > 0x99) | oldCF; AL = AL - 0x60 * car; - CF = car; } + CF = car; + resultflags(AL); } # See 'lockable.sinc' for memory destination, lockable variants :DEC Rmr8 is vexMode=0 & byte=0xfe; mod=3 & Rmr8 & reg_opcode=1 { OF = sborrow(Rmr8,1); Rmr8 = Rmr8 - 1; resultflags( Rmr8); } @@ -3312,6 +3294,23 @@ define pcodeop cpuid_brand_part3_info; RDX = rem:8; } @endif +define pcodeop enqcmd; +define pcodeop enqcmds; +macro enqcmdFlags() { + OF = 0; + SF = 0; + AF = 0; + CF = 0; + PF = 0; +} +:ENQCMD Reg32, m512 is $(PRE_F2) & opsize=1 & byte=0x0F; byte=0x38; byte=0xF8; (mod!=3 & Reg32) ... & m512 { ZF = enqcmd(Reg32, m512); enqcmdFlags(); } +:ENQCMDS Reg32, m512 is $(PRE_F3) & opsize=1 & byte=0x0F; byte=0x38; byte=0xF8; (mod!=3 & Reg32) ... & m512 { ZF = enqcmds(Reg32, m512); enqcmdFlags(); } +@ifdef IA64 +:ENQCMD Reg64, m512 is $(LONGMODE_ON) & $(PRE_F2) & opsize=2 & byte=0x0F; byte=0x38; byte=0xF8; (mod!=3 & Reg64) ... & m512 { ZF = enqcmd(Reg64, m512); enqcmdFlags(); } +:ENQCMDS Reg64, m512 is $(LONGMODE_ON) & $(PRE_F3) & opsize=2 & byte=0x0F; byte=0x38; byte=0xF8; (mod!=3 & Reg64) ... & m512 { ZF = enqcmds(Reg64, m512); enqcmdFlags(); } +@endif + + enterFrames: low5 is low5 { tmp:1 = low5; export tmp; } :ENTER imm16,enterFrames is $(LONGMODE_OFF) & vexMode=0 & addrsize=1 & opsize=1 & byte=0xc8; imm16; enterFrames & low5=0x00 { @@ -3544,7 +3543,39 @@ enterFrames: low5 is low5 { tmp:1 = low5; export tmp; } } @endif +#### +#### FRED instructions +#### + +@ifdef IA64 +define pcodeop eretu; +define pcodeop erets; +define pcodeop lkgs; + +:ERETU is $(PRE_F3) & byte=0x0F; byte=0x01; byte=0xCA { + eretu(); + pop88(RIP); + tmp:8=0; pop88(tmp); CS=tmp(0)|0x3; + pop88(rflags); + pop88(RSP); + pop88(tmp); SS=tmp(0)|0x3; + return [RIP]; +} +:ERETS is $(PRE_F2) & byte=0x0F; byte=0x01; byte=0xCA { + erets(); + pop88(RIP); + tmp:8=0; pop88(tmp); # Not used to load CS + pop88(rflags); + pop88(RSP); + pop88(tmp); # Not used to load SS + return [RIP]; +} + +:LKGS rm16 is $(LONGMODE_ON) & $(PRE_F2) & byte=0x0F; byte=0x00; reg_opcode=6 ... & rm16 { + lkgs(rm16); +} +@endif #def IA64 # Informs the 80287 coprocessor of the switch to protected mode, treated as NOP for 80387 and later. # We used to have a pseudo-op, but as this is a legacy instruction which is now explicitly treated @@ -3553,6 +3584,16 @@ enterFrames: low5 is low5 { tmp:1 = low5; export tmp; } :HLT is vexMode=0 & byte=0xf4 { goto inst_start; } +define pcodeop hreset; +:HRESET imm8 is vexMode=0 & $(PRE_F3) & byte=0x0F; byte=0x3A; byte=0xF0; byte=0xC0; imm8 { EAX = hreset(imm8:1); } + +@ifdef IA64 +# Indirect Branch History Fence. Treated as a NOP outside of 64-bit mode. +# Used to prevent branch history injection, added as a pseudo-op +define pcodeop ibhf; +:IBHF is $(LONGMODE_ON) & $(PRE_F3) & $(REX_W) & byte=0x0F; byte=0x1E; byte=0xF8 { ibhf(); } +@endif + :IDIV rm8 is vexMode=0 & byte=0xf6; rm8 & reg_opcode=7 ... { rm8ext:2 = sext(rm8); local quotient = AX s/ rm8ext; # DE exception if quotient doesn't fit in AL local rem = AX s% rm8ext; @@ -3692,10 +3733,23 @@ enterFrames: low5 is low5 { tmp:1 = low5; export tmp; } :IRETQ is $(LONGMODE_ON) & vexMode=0 & addrsize=2 & opsize=2 & byte=0xcf { pop88(RIP); tmp:8=0; pop88(tmp); CS=tmp(0); pop88(rflags); return [RIP]; } @endif -:J^cc rel8 is vexMode=0 & row=7 & cc; rel8 { if (cc) goto rel8; } -:J^cc rel16 is $(LONGMODE_OFF) & vexMode=0 & opsize=0 & byte=0xf; row=8 & cc; rel16 { if (cc) goto rel16; } -:J^cc rel32 is vexMode=0 & opsize=1 & byte=0xf; row=8 & cc; rel32 { if (cc) goto rel32; } -:J^cc rel32 is vexMode=0 & opsize=2 & byte=0xf; row=8 & cc; rel32 { if (cc) goto rel32; } +# HWNT Branch Not Taken hint (prefix 2E) +# HST Branch Taken hint (prefix 3E) +jccRel8: rel8 is rel8 { export rel8; } +jccRel8: rel8, "bn" is segover=1 & rel8 { export rel8; } +jccRel8: rel8, "bt" is segover=3 & rel8 { export rel8; } +jccRel16: rel16 is rel16 { export rel16; } +jccRel16: rel16, "bn" is segover=1 & rel16 { export rel16; } +jccRel16: rel16, "bt" is segover=3 & rel16 { export rel16; } +jccRel32: rel32 is rel32 { export rel32; } +jccRel32: rel32, "bn" is segover=1 & rel32 { export rel32; } +jccRel32: rel32, "bt" is segover=3 & rel32 { export rel32; } + +:J^cc jccRel8 is vexMode=0 & row=7 & cc; jccRel8 { if (cc) goto jccRel8; } +:J^cc jccRel16 is $(LONGMODE_OFF) & vexMode=0 & opsize=0 & byte=0xf; row=8 & cc; jccRel16 { if (cc) goto jccRel16; } +:J^cc jccRel32 is vexMode=0 & opsize=1 & byte=0xf; row=8 & cc; jccRel32 { if (cc) goto jccRel32; } +:J^cc jccRel32 is vexMode=0 & opsize=2 & byte=0xf; row=8 & cc; jccRel32 { if (cc) goto jccRel32; } + # The following is vexMode=0 & picked up by the line above. rel32 works for both 32 and 64 bit #@ifdef IA64 #:J^cc rel32 is $(LONGMODE_ON) & vexMode=0 & addrsize=2 & byte=0xf; row=8 & cc; rel32 { if (cc) goto rel32; } @@ -3854,7 +3908,7 @@ define pcodeop LocalDescriptorTableRegister; :LODSB^rep^reptail dseSI1 is vexMode=0 & rep & reptail & byte=0xAC & dseSI1 { build rep; build dseSI1; AL=dseSI1; build reptail; } :LODSW^rep^reptail dseSI2 is vexMode=0 & rep & reptail & opsize=0 & byte=0xAD & dseSI2 { build rep; build dseSI2; AX=dseSI2; build reptail; } -:LODSD^rep^reptail dseSI4 is vexMode=0 & rep & reptail & opsize=1 & byte=0xAD & dseSI4 { build rep; build dseSI4; EAX=dseSI4; build reptail; } +:LODSD^rep^reptail dseSI4 is vexMode=0 & rep & reptail & opsize=1 & byte=0xAD & dseSI4 & check_EAX_dest { build rep; build dseSI4; EAX=dseSI4; build check_EAX_dest; build reptail; } @ifdef IA64 :LODSQ^rep^reptail dseSI8 is $(LONGMODE_ON) & vexMode=0 & rep & reptail & opsize=2 & byte=0xAD & dseSI8 { build rep; build dseSI8; RAX=dseSI8; build reptail; } @endif @@ -3885,10 +3939,11 @@ define pcodeop SegmentLimit; ZF = tmp[16,1]; } -:LSL Reg32,rm32 is vexMode=0 & opsize=1 & byte=0xf; byte=0x3; rm32 & Reg32 ... +:LSL Reg32,rm32 is vexMode=0 & opsize=1 & byte=0xf; byte=0x3; rm32 & (Reg32 & check_Reg32_dest) ... { tmp:3 = SegmentLimit(rm32); Reg32 = zext(tmp:2); + build check_Reg32_dest; ZF = tmp[16,1]; } @@ -3948,8 +4003,18 @@ define pcodeop TaskRegister; @ifdef IA64 :MOV Reg64,rm64 is $(LONGMODE_ON) & vexMode=0 & opsize=2 & byte=0x8b; rm64 & Reg64 ... { Reg64 = rm64; } @endif -:MOV rm16,Sreg is vexMode=0 & byte=0x8c; rm16 & Sreg ... { rm16 = Sreg; } -:MOV Sreg,rm16 is vexMode=0 & byte=0x8e; rm16 & Sreg ... { Sreg=rm16; } +:MOV m16,Sreg is vexMode=0 & byte=0x8c; (mod != 3 & Sreg) ... & m16 { m16 = Sreg; } +:MOV Rmr16,Sreg is vexMode=0 & opsize=0 & byte=0x8c; mod=3 & Rmr16 & Sreg { Rmr16 = Sreg; } +:MOV Rmr32,Sreg is vexMode=0 & opsize=1 & byte=0x8c; mod=3 & Rmr32 & check_Rmr32_dest & Sreg { Rmr32 = zext(Sreg); build check_Rmr32_dest; } +@ifdef IA64 +:MOV Rmr64,Sreg is $(LONGMODE_ON) & vexMode=0 & opsize=2 & byte=0x8c; mod=3 & Rmr64 & Sreg { Rmr64 = zext(Sreg); } +@endif +:MOV Sreg,m16 is vexMode=0 & byte=0x8e; (mod != 3 & Sreg) ... & m16 { Sreg = m16; } +:MOV Rmr16,Sreg is vexMode=0 & opsize=0 & byte=0x8e; mod=3 & Rmr16 & Sreg { Sreg = Rmr16; } +:MOV Rmr32,Sreg is vexMode=0 & opsize=1 & byte=0x8e; mod=3 & Rmr32 & Sreg { Sreg = Rmr32(0); } +@ifdef IA64 +:MOV Rmr64,Sreg is $(LONGMODE_ON) & vexMode=0 & opsize=2 & byte=0x8e; mod=3 & Rmr64 & Sreg { Sreg = Rmr64(0); } +@endif :MOV AL,moffs8 is vexMode=0 & byte=0xa0; AL & moffs8 { AL=moffs8; } :MOV AX,moffs16 is vexMode=0 & opsize=0 & byte=0xa1; AX & moffs16 { AX=moffs16; } :MOV EAX,moffs32 is vexMode=0 & opsize=1 & byte=0xa1; EAX & check_EAX_dest & moffs32 { EAX=moffs32; build check_EAX_dest; } @@ -4016,9 +4081,10 @@ define pcodeop TaskRegister; :MOV creg_x, Rmr64 is $(LONGMODE_ON) & vexMode=0 & rexRprefix=1 & byte=0xf; byte=0x22; Rmr64 & creg_x { creg_x=Rmr64; } @endif -:MOV Rmr32, creg is $(LONGMODE_OFF) & vexMode=0 & byte=0xf; byte=0x20; Rmr32 & creg { +:MOV Rmr32, creg is $(LONGMODE_OFF) & vexMode=0 & byte=0xf; byte=0x20; Rmr32 & check_Rmr32_dest & creg { @ifdef IA64 Rmr32 = creg:4; + build check_Rmr32_dest; @else Rmr32 = creg; @endif @@ -4028,9 +4094,10 @@ define pcodeop TaskRegister; :MOV Rmr64, creg_x is $(LONGMODE_ON) & vexMode=0 & rexRprefix=1 & byte=0xf; byte=0x20; Rmr64 & creg_x { Rmr64 = creg_x; } @endif -:MOV Rmr32, debugreg is $(LONGMODE_OFF) & vexMode=0 & byte=0xf; byte=0x21; Rmr32 & debugreg { +:MOV Rmr32, debugreg is $(LONGMODE_OFF) & vexMode=0 & byte=0xf; byte=0x21; Rmr32 & check_Rmr32_dest & debugreg { @ifdef IA64 Rmr32 = debugreg:4; + build check_Rmr32_dest; @else Rmr32 = debugreg; @endif @@ -4058,14 +4125,55 @@ define pcodeop TaskRegister; :MOV testreg, r32 is vexMode=0 & byte=0xf; byte=0x26; r32 & testreg & mod=3 { testreg = r32; } @endif -define pcodeop swap_bytes; -:MOVBE Reg16, m16 is vexMode=0 & opsize=0 & byte=0xf; byte=0x38; byte=0xf0; Reg16 ... & m16 { Reg16 = swap_bytes( m16 ); } -:MOVBE Reg32, m32 is vexMode=0 & opsize=1 & mandover=0 & byte=0xf; byte=0x38; byte=0xf0; Reg32 ... & m32 { Reg32 = swap_bytes( m32 ); } -:MOVBE m16, Reg16 is vexMode=0 & opsize=0 & byte=0xf; byte=0x38; byte=0xf1; Reg16 ... & m16 { m16 = swap_bytes( Reg16 ); } -:MOVBE m32, Reg32 is vexMode=0 & opsize=1 & mandover=0 & byte=0xf; byte=0x38; byte=0xf1; Reg32 ... & m32 { m32 = swap_bytes( Reg32 ); } -@ifdef IA64 -:MOVBE Reg64, m64 is $(LONGMODE_ON) & vexMode=0 & opsize=2 & mandover=0 & byte=0xf; byte=0x38; byte=0xf0; Reg64 ... & m64 { Reg64 = swap_bytes( m64 ); } -:MOVBE m64, Reg64 is $(LONGMODE_ON) & vexMode=0 & opsize=2 & mandover=0 & byte=0xf; byte=0x38; byte=0xf1; Reg64 ... & m64 { m64 = swap_bytes( Reg64 ); } +:MOVBE Reg16, m16 is vexMode=0 & opsize=0 & byte=0xf; byte=0x38; byte=0xf0; Reg16 ... & m16 { local tmp = m16; local dest:2 = 0; dest[0,8] = tmp[8,8]; dest[8,8] = tmp[0,8]; Reg16 = dest; } +:MOVBE m16, Reg16 is vexMode=0 & opsize=0 & byte=0xf; byte=0x38; byte=0xf1; Reg16 ... & m16 { local tmp = Reg16; local dest:2 = 0; dest[0,8] = tmp[8,8]; dest[8,8] = tmp[0,8]; m16 = dest; } +:MOVBE Reg32, m32 is vexMode=0 & opsize=1 & mandover=0 & byte=0xf; byte=0x38; byte=0xf0; (Reg32 & check_Reg32_dest) ... & m32 { + local tmp = m32; + local dest:4 = 0; + dest[0,8] = tmp[24,8]; + dest[8,8] = tmp[16,8]; + dest[16,8] = tmp[8,8]; + dest[24,8] = tmp[0,8]; + Reg32 = dest; + build check_Reg32_dest; +} +:MOVBE m32, Reg32 is vexMode=0 & opsize=1 & mandover=0 & byte=0xf; byte=0x38; byte=0xf1; Reg32 ... & m32 { + local tmp = Reg32; + local dest:4 = 0; + dest[0,8] = tmp[24,8]; + dest[8,8] = tmp[16,8]; + dest[16,8] = tmp[8,8]; + dest[24,8] = tmp[0,8]; + m32 = dest; +} +@ifdef IA64 +:MOVBE Reg64, m64 is $(LONGMODE_ON) & vexMode=0 & opsize=2 & mandover=0 & byte=0xf; byte=0x38; byte=0xf0; Reg64 ... & m64 { + local tmp = m64; + local dest:8 = 0; + dest[0,8] = tmp[56,8]; + dest[8,8] = tmp[48,8]; + dest[16,8] = tmp[40,8]; + dest[24,8] = tmp[32,8]; + dest[32,8] = tmp[24,8]; + dest[40,8] = tmp[16,8]; + dest[48,8] = tmp[8,8]; + dest[56,8] = tmp[0,8]; + Reg64 = dest; +} + +:MOVBE m64, Reg64 is $(LONGMODE_ON) & vexMode=0 & opsize=2 & mandover=0 & byte=0xf; byte=0x38; byte=0xf1; Reg64 ... & m64 { + local tmp = Reg64; + local dest:8 = 0; + dest[0,8] = tmp[56,8]; + dest[8,8] = tmp[48,8]; + dest[16,8] = tmp[40,8]; + dest[24,8] = tmp[32,8]; + dest[32,8] = tmp[24,8]; + dest[40,8] = tmp[16,8]; + dest[48,8] = tmp[8,8]; + dest[56,8] = tmp[0,8]; + m64 = dest; +} @endif @@ -4128,7 +4236,7 @@ define pcodeop swap_bytes; :NEG Rmr64 is $(LONGMODE_ON) & vexMode=0 & opsize=2 & byte=0xf7; mod=3 & Rmr64 & reg_opcode=3 { negflags(Rmr64); Rmr64 = -Rmr64; resultflags(Rmr64); } @endif -:NOP is vexMode=0 & byte=0x90 & (mandover=0 | mandover=4 | mandover=1) & (rexprefix=0 | rexWRXBprefix=8) { } +:NOP is vexMode=0 & byte=0x90 & (mandover=0 | mandover=4 | mandover=1) & (rexprefix=0 | rexWRXBprefix=8 | rexWRXBprefix=0) { } :NOP rm16 is vexMode=0 & mandover & opsize=0 & byte=0x0f; high5=3; rm16 ... { } :NOP rm32 is vexMode=0 & mandover & opsize=1 & byte=0x0f; high5=3; rm32 ... { } :NOP^"/reserved" rm16 is vexMode=0 & mandover & opsize=0 & byte=0x0f; byte=0x18; rm16 & reg_opcode_hb=1 ... { } @@ -4189,6 +4297,19 @@ define pcodeop swap_bytes; :PAUSE is vexMode=0 & opsize=0 & $(PRE_F3) & byte=0x90 { } :PAUSE is vexMode=0 & opsize=1 & $(PRE_F3) & byte=0x90 { } +@ifdef IA64 +define pcodeop pbndkb; +:PBNDKB is $(LONGMODE_ON) & vexMode=0 & $(PRE_NO) & byte=0x0F; byte=0x01; byte=0xC7 { RAX = pbndkb(RBX, RCX); ZF = (RAX != 0); } +@endif + +# leaf function 2 is the only one that uses RCX, and it is only available in 64-bit +# The instruction description mentions RDX, but no leaf functions use RDX +define pcodeop pconfig; +:PCONFIG is $(LONGMODE_OFF) & vexMode=0 & $(PRE_NO) & byte=0x0F; byte=0x01; byte=0xC5 { EAX = pconfig(EAX, EBX); ZF = (EAX != 0); } +@ifdef IA64 +:PCONFIG is $(LONGMODE_ON) & vexMode=0 & $(PRE_NO) & byte=0x0F; byte=0x01; byte=0xC5 { RAX = pconfig(RAX, RBX, RCX); ZF = (RAX != 0); } +@endif + :POP rm16 is $(LONGMODE_OFF) & vexMode=0 & addrsize=0 & opsize=0 & byte=0x8f; rm16 & reg_opcode=0 ... { local val:2 = 0; pop22(val); build rm16; rm16 = val; } :POP rm16 is $(LONGMODE_OFF) & vexMode=0 & addrsize=1 & opsize=0 & byte=0x8f; rm16 & reg_opcode=0 ... { local val:2 = 0; pop42(val); build rm16; rm16 = val; } :POP rm32 is $(LONGMODE_OFF) & vexMode=0 & addrsize=0 & opsize=1 & byte=0x8f; rm32 & reg_opcode=0 ... { local val:4 = 0; pop24(val); build rm32; rm32 = val; } @@ -4326,82 +4447,117 @@ define pcodeop ptwrite; :PUSHFQ is $(LONGMODE_ON) & vexMode=0 & byte=0x9c { packflags(rflags); packeflags(rflags); push88(rflags); } @endif -:RCL rm8,n1 is vexMode=0 & byte=0xD0; rm8 & n1 & reg_opcode=2 ... { local tmpCF = CF; CF = rm8 s< 0; rm8 = (rm8 << 1) | tmpCF; OF = CF ^ (rm8 s< 0); } -:RCL rm8,CL is vexMode=0 & byte=0xD2; CL & rm8 & reg_opcode=2 ... { local cnt=(CL&0x1f)%9; tmp:2=(zext(CF)<<8)|zext(rm8); tmp=(tmp<>(9-cnt));rm8=tmp(0); CF=(tmp&0x100)!=0; } -:RCL rm8,imm8 is vexMode=0 & byte=0xC0; rm8 & reg_opcode=2 ... ; imm8 { local cnt=(imm8&0x1f)%9; tmp:2=(zext(CF)<<8)|zext(rm8); tmp=(tmp<>(9-cnt)); rm8=tmp(0); CF=(tmp&0x100)!=0; } -:RCL rm16,n1 is vexMode=0 & opsize=0 & byte=0xD1; rm16 & n1 & reg_opcode=2 ... { local tmpCF = CF; CF = rm16 s< 0; rm16 = (rm16 << 1) | zext(tmpCF); OF = CF ^ (rm16 s< 0);} -:RCL rm16,CL is vexMode=0 & opsize=0 & byte=0xD3; CL & rm16 & reg_opcode=2 ... {local cnt=(CL&0x1f)%17; tmp:4=(zext(CF)<<16)|zext(rm16); tmp=(tmp<>(17-cnt)); rm16=tmp(0); CF=(tmp&0x10000)!=0; } -:RCL rm16,imm8 is vexMode=0 & opsize=0 & byte=0xC1; rm16 & reg_opcode=2 ... ; imm8 { local cnt=(imm8&0x1f)%17; tmp:4=(zext(CF)<<16)|zext(rm16); tmp=(tmp<>(17-cnt)); rm16=tmp(0); CF=(tmp&0x10000)!=0; } -:RCL rm32,n1 is vexMode=0 & opsize=1 & byte=0xD1; rm32 & n1 & check_rm32_dest ... & reg_opcode=2 ... { local tmpCF=CF; CF=rm32 s< 0; rm32=(rm32<<1)|zext(tmpCF); OF=CF^(rm32 s< 0); build check_rm32_dest; } -:RCL rm32,CL is vexMode=0 & opsize=1 & byte=0xD3; CL & rm32 & check_rm32_dest ... & reg_opcode=2 ... { local cnt=CL&0x1f; tmp:8=(zext(CF)<<32)|zext(rm32); tmp=(tmp<>(33-cnt)); rm32=tmp(0); CF=(tmp&0x100000000)!=0; build check_rm32_dest; } -:RCL rm32,imm8 is vexMode=0 & opsize=1 & byte=0xC1; rm32 & check_rm32_dest ... & reg_opcode=2 ... ; imm8 { local cnt=imm8&0x1f; tmp:8=(zext(CF)<<32)|zext(rm32); tmp=(tmp<>(33-cnt)); rm32=tmp(0); CF=(tmp&0x100000000)!=0; build check_rm32_dest; } -@ifdef IA64 -:RCL rm64,n1 is $(LONGMODE_ON) & vexMode=0 & opsize=2 & byte=0xD1; rm64 & n1 & reg_opcode=2 ... { local tmpCF=CF; CF=rm64 s< 0; rm64=(rm64<<1)|zext(tmpCF); OF=CF^(rm64 s< 0);} - -:RCL rm64,CL is $(LONGMODE_ON) & vexMode=0 & opsize=2 & byte=0xD3; CL & rm64 & reg_opcode=2 ... -{ - local cnt:1=CL&0x3f; - local rm64_copy:8 = rm64; - local CF_copy:1 = CF; - rotated:8 = rm64_copy << cnt; - rotated = rotated | (rm64_copy >> (65 -cnt)); - local CF_bit:8 = zext(CF_copy) << cnt-1; - rotated = rotated | CF_bit; - conditionalAssign(CF, cnt == 0:1, CF_copy, ((1:8<<(64-cnt)) & rm64_copy) != 0); - rm64 = rotated; -} - -:RCL rm64,imm8 is $(LONGMODE_ON) & vexMode=0 & opsize=2 & byte=0xC1; rm64 & reg_opcode=2 ... ; imm8 -{ - local cnt:1=imm8&0x3f; - local rm64_copy:8 = rm64; - local CF_copy:1 = CF; - rotated:8 = rm64_copy << cnt; - rotated = rotated | (rm64_copy >> (65 -cnt)); - local CF_bit:8 = zext(CF_copy) << cnt-1; - rotated = rotated | CF_bit; - conditionalAssign(CF, cnt == 0:1, CF_copy, ((1:8<<(64-cnt)) & rm64_copy) != 0); - rm64 = rotated; -} -@endif - -:RCR rm8,n1 is vexMode=0 & byte=0xD0; rm8 & n1 & reg_opcode=3 ... { local tmpCF=CF; OF=rm8 s< 0; CF=(rm8&1)!=0; rm8=(rm8>>1)|(tmpCF<<7); OF=OF^(rm8 s< 0); } -:RCR rm8,CL is vexMode=0 & byte=0xD2; CL & rm8 & reg_opcode=3 ... { local cnt=(CL&0x1f)%9; tmp:2=(zext(CF)<<8)|zext(rm8); tmp=(tmp>>cnt)|(tmp<<(9-cnt)); rm8=tmp(0); CF=(tmp&0x100)!=0; } -:RCR rm8,imm8 is vexMode=0 & byte=0xC0; rm8 & reg_opcode=3 ... ; imm8 { local cnt=(imm8&0x1f)%9; tmp:2=(zext(CF)<<8)|zext(rm8); tmp=(tmp>>cnt)|(tmp<<(9-cnt)); rm8=tmp(0); CF=(tmp&0x100)!=0; } -:RCR rm16,n1 is vexMode=0 & opsize=0 & byte=0xD1; rm16 & n1 & reg_opcode=3 ... { local tmpCF=CF; OF=rm16 s< 0; CF=(rm16&1)!=0; rm16=(rm16>>1)|(zext(tmpCF)<<15); OF=OF^(rm16 s< 0); } -:RCR rm16,CL is vexMode=0 & opsize=0 & byte=0xD3; CL & rm16 & reg_opcode=3 ... { local cnt=(CL&0x1f)%17; tmp:4=(zext(CF)<<16)|zext(rm16); tmp=(tmp>>cnt)|(tmp<<(17-cnt)); rm16=tmp(0); CF=(tmp&0x10000)!=0; } -:RCR rm16,imm8 is vexMode=0 & opsize=0 & byte=0xC1; rm16 & reg_opcode=3 ... ; imm8 { local cnt=(imm8&0x1f)%17; tmp:4=(zext(CF)<<16)|zext(rm16); tmp=(tmp>>cnt)|(tmp<<(17-cnt)); rm16=tmp(0); CF=(tmp&0x10000)!=0; } -:RCR rm32,n1 is vexMode=0 & opsize=1 & byte=0xD1; rm32 & n1 & check_rm32_dest ... & reg_opcode=3 ... { local tmpCF=CF; OF=rm32 s< 0; CF=(rm32&1)!=0; rm32=(rm32>>1)|(zext(tmpCF)<<31); OF=OF^(rm32 s< 0); build check_rm32_dest; } -:RCR rm32,CL is vexMode=0 & opsize=1 & byte=0xD3; CL & rm32 & check_rm32_dest ... & reg_opcode=3 ... { local cnt=CL&0x1f; tmp:8=(zext(CF)<<32)|zext(rm32); tmp=(tmp>>cnt)|(tmp<<(33-cnt)); rm32=tmp(0); CF=(tmp&0x100000000)!=0; build check_rm32_dest; } -:RCR rm32,imm8 is vexMode=0 & opsize=1 & byte=0xC1; rm32 & check_rm32_dest ... & reg_opcode=3 ... ; imm8 { local cnt=imm8&0x1f; tmp:8=(zext(CF)<<32)|zext(rm32); tmp=(tmp>>cnt)|(tmp<<(33-cnt)); rm32=tmp(0); CF=(tmp&0x100000000)!=0; build check_rm32_dest; } -@ifdef IA64 -:RCR rm64,n1 is $(LONGMODE_ON) & vexMode=0 & opsize=2 & byte=0xD1; rm64 & n1 & reg_opcode=3 ... { local tmpCF=CF; OF=rm64 s< 0; CF=(rm64&1)!=0; rm64=(rm64>>1)|(zext(tmpCF)<<63); OF=OF^(rm64 s< 0); } - -:RCR rm64,CL is $(LONGMODE_ON) & vexMode=0 & opsize=2 & byte=0xD3; CL & rm64 & reg_opcode=3 ... -{ - local cnt:1=CL&0x3f; - local rm64_copy:8 = rm64; - local CF_copy:1 = CF; - rotated:8 = rm64_copy >> cnt; - rotated = rotated | (rm64_copy << (65 -cnt)); - local CF_bit:8 = zext(CF_copy) << 64-cnt; - rotated = rotated | CF_bit; - conditionalAssign(CF, cnt == 0:1, CF_copy, ((1:8<<(cnt-1)) & rm64_copy) != 0); - rm64 = rotated; - } +macro rcl8(dest, rotate_count) { + local cnt:1 = (rotate_count & 0x1f) % 9; + local tmp:2 = (zext(CF) << 8) | zext(dest); + tmp = (tmp << cnt)|(tmp >> (9 - cnt)); + dest = tmp(0); + conditionalAssign(CF, cnt == 0, CF, (tmp & 0x100) != 0); + conditionalAssign(OF, cnt == 1, CF ^ (dest s< 0), OF); +} -:RCR rm64,imm8 is $(LONGMODE_ON) & vexMode=0 & opsize=2 & byte=0xC1; rm64 & reg_opcode=3 ... ; imm8 -{ - local cnt:1=imm8&0x3f; - local rm64_copy:8 = rm64; - local CF_copy:1 = CF; - rotated:8 = rm64_copy >> cnt; - rotated = rotated | (rm64_copy << (65 -cnt)); - local CF_bit:8 = zext(CF_copy) << 64-cnt; - rotated = rotated | CF_bit; - conditionalAssign(CF, cnt == 0:1, CF_copy, ((1:8<<(cnt-1)) & rm64_copy) != 0); - rm64 = rotated; - } +:RCL rm8,n1 is vexMode=0 & byte=0xD0; rm8 & n1 & reg_opcode=2 ... { rcl8(rm8, n1:1); } +:RCL rm8,CL is vexMode=0 & byte=0xD2; CL & rm8 & reg_opcode=2 ... { rcl8(rm8, CL); } +:RCL rm8,imm8 is vexMode=0 & byte=0xC0; rm8 & reg_opcode=2 ... ; imm8 { rcl8(rm8, imm8:1); } + +macro rcl16(dest, rotate_count) { + local cnt = (rotate_count & 0x1f) % 17; + local tmp:4 = (zext(CF) << 16) | zext(dest); + tmp = (tmp << cnt) | (tmp >> (17 - cnt)); + dest = tmp(0); + conditionalAssign(CF, cnt==0, CF, (tmp & 0x10000) != 0); + conditionalAssign(OF, cnt==1, CF ^ (dest s< 0), OF); +} + +:RCL rm16,n1 is vexMode=0 & opsize=0 & byte=0xD1; rm16 & n1 & reg_opcode=2 ... { rcl16(rm16, n1:1); } +:RCL rm16,CL is vexMode=0 & opsize=0 & byte=0xD3; CL & rm16 & reg_opcode=2 ... { rcl16(rm16, CL); } +:RCL rm16,imm8 is vexMode=0 & opsize=0 & byte=0xC1; rm16 & reg_opcode=2 ... ; imm8 { rcl16(rm16, imm8:1); } + + +macro rcl32(dest, rotate_count) { + local cnt = rotate_count & 0x1f; + local tmp:8 = (zext(CF) << 32) | zext(dest); + tmp = (tmp << cnt) | (tmp >> (33 - cnt)); + dest = tmp(0); + conditionalAssign(CF, cnt==0, CF, (tmp&0x100000000)!=0); + conditionalAssign(OF, cnt==1, CF ^ (dest s< 0), OF); +} + +:RCL rm32,n1 is vexMode=0 & opsize=1 & byte=0xD1; rm32 & n1 & check_rm32_dest ... & reg_opcode=2 ... { rcl32(rm32, n1:1); build check_rm32_dest; } +:RCL rm32,CL is vexMode=0 & opsize=1 & byte=0xD3; CL & rm32 & check_rm32_dest ... & reg_opcode=2 ... { rcl32(rm32, CL); build check_rm32_dest; } +:RCL rm32,imm8 is vexMode=0 & opsize=1 & byte=0xC1; rm32 & check_rm32_dest ... & reg_opcode=2 ... ; imm8 { rcl32(rm32, imm8:1); build check_rm32_dest; } + +@ifdef IA64 +macro rcl64(dest, rotate_count) { + local cnt:1 = rotate_count & 0x3f; + local rm64_copy:8 = dest; + local CF_copy:1 = CF; + rotated:8 = rm64_copy << cnt; + rotated = rotated | (rm64_copy >> (65 - cnt)); + local CF_bit:8 = zext(CF_copy) << cnt-1; + rotated = rotated | CF_bit; + dest = rotated; + conditionalAssign(CF, cnt == 0, CF_copy, ((1<<(64-cnt)) & rm64_copy) != 0); + conditionalAssign(OF, cnt==1, CF ^ (dest s< 0), OF); +} + +:RCL rm64,n1 is $(LONGMODE_ON) & vexMode=0 & opsize=2 & byte=0xD1; rm64 & n1 & reg_opcode=2 ... { rcl64(rm64, n1:1); } +:RCL rm64,CL is $(LONGMODE_ON) & vexMode=0 & opsize=2 & byte=0xD3; CL & rm64 & reg_opcode=2 ... { rcl64(rm64, CL); } +:RCL rm64,imm8 is $(LONGMODE_ON) & vexMode=0 & opsize=2 & byte=0xC1; rm64 & reg_opcode=2 ... ; imm8 { rcl64(rm64, imm8:1); } +@endif + +macro rcr8(dest, rotate_count) { + local cnt = (rotate_count & 0x1f) % 9; + conditionalAssign(OF, cnt==1, CF ^ (dest s< 0), OF); + local tmp:2 = (zext(CF) << 8) | zext(dest); tmp = (tmp >> cnt) | (tmp << (9 - cnt)); + dest = tmp(0); + conditionalAssign(CF, cnt == 0, CF, (tmp & 0x100) != 0); +} + +:RCR rm8,n1 is vexMode=0 & byte=0xD0; rm8 & n1 & reg_opcode=3 ... { rcr8(rm8, n1:1); } +:RCR rm8,CL is vexMode=0 & byte=0xD2; CL & rm8 & reg_opcode=3 ... { rcr8(rm8, CL); } +:RCR rm8,imm8 is vexMode=0 & byte=0xC0; rm8 & reg_opcode=3 ... ; imm8 { rcr8(rm8, imm8:1); } + +macro rcr16(dest, rotate_count) { + local cnt=(rotate_count & 0x1f) % 17; + conditionalAssign(OF, cnt==1, CF ^ (dest s< 0), OF); + local tmp:4 = (zext(CF) << 16) | zext(dest); + tmp = (tmp >> cnt) | (tmp << (17 - cnt)); + dest=tmp(0); + conditionalAssign(CF, cnt == 0, CF, (tmp & 0x10000) != 0); +} + +:RCR rm16,n1 is vexMode=0 & opsize=0 & byte=0xD1; rm16 & n1 & reg_opcode=3 ... { rcr16(rm16, n1:1); } +:RCR rm16,CL is vexMode=0 & opsize=0 & byte=0xD3; CL & rm16 & reg_opcode=3 ... { rcr16(rm16, CL); } +:RCR rm16,imm8 is vexMode=0 & opsize=0 & byte=0xC1; rm16 & reg_opcode=3 ... ; imm8 { rcr16(rm16, imm8:1); } + +macro rcr32(dest, rotate_count) { + local cnt = rotate_count & 0x1f; + conditionalAssign(OF, cnt==1, CF ^ (dest s< 0), OF); + local tmp:8 = (zext(CF) << 32) | zext(dest); + tmp = (tmp >> cnt) | (tmp << (33 - cnt)); + dest = tmp(0); + conditionalAssign(CF, cnt == 0, CF, (tmp&0x100000000)!=0); +} + +:RCR rm32,n1 is vexMode=0 & opsize=1 & byte=0xD1; rm32 & n1 & check_rm32_dest ... & reg_opcode=3 ... { rcr32(rm32, n1:1); build check_rm32_dest; } +:RCR rm32,CL is vexMode=0 & opsize=1 & byte=0xD3; CL & rm32 & check_rm32_dest ... & reg_opcode=3 ... { rcr32(rm32, CL); build check_rm32_dest; } +:RCR rm32,imm8 is vexMode=0 & opsize=1 & byte=0xC1; rm32 & check_rm32_dest ... & reg_opcode=3 ... ; imm8 { rcr32(rm32, imm8:1); build check_rm32_dest; } + +@ifdef IA64 +macro rcr64(dest, rotate_count) { + local cnt:1 = rotate_count & 0x3f; + conditionalAssign(OF, cnt==1, CF ^ (dest s< 0), OF); + local tmp:16 = (zext(CF) << 64) | zext(dest); + tmp = (tmp >> cnt) | (tmp << (65 - cnt)); + dest = tmp(0); + local upper:1 = tmp(8) & 0x1; + conditionalAssign(CF, cnt == 0, CF, upper != 0); +} + +:RCR rm64,n1 is $(LONGMODE_ON) & vexMode=0 & opsize=2 & byte=0xD1; rm64 & n1 & reg_opcode=3 ... { rcr64(rm64, n1:1); } +:RCR rm64,CL is $(LONGMODE_ON) & vexMode=0 & opsize=2 & byte=0xD3; CL & rm64 & reg_opcode=3 ... { rcr64(rm64, CL); } +:RCR rm64,imm8 is $(LONGMODE_ON) & vexMode=0 & opsize=2 & byte=0xC1; rm64 & reg_opcode=3 ... ; imm8 { rcr64(rm64, imm8:1); } @endif @ifdef IA64 @@ -4584,6 +4740,10 @@ define pcodeop smm_restore_state; :SCASQ^repe^repetail eseDI8 is $(LONGMODE_ON) & vexMode=0 & repe & repetail & opsize=2 & byte=0xaf & eseDI8 { build repe; build eseDI8; subflags(RAX,eseDI8); local diff=RAX-eseDI8; resultflags(diff); build repetail; } @endif +define pcodeop serialize; +:SERIALIZE is vexMode=0 & $(PRE_NO) & byte=0x0F; byte=0x01; byte=0xE8 { serialize(); } + + :SET^cc rm8 is vexMode=0 & byte=0xf; row=9 & cc; rm8 { rm8 = cc; } # manual is not consistent on operands @@ -4606,7 +4766,7 @@ define pcodeop smm_restore_state; :SHL rm8,n1 is vexMode=0 & byte=0xD0; rm8 & n1 &(reg_opcode=4|reg_opcode=6) ... { CF = rm8 s< 0; rm8 = rm8 << 1; OF = CF ^ (rm8 s< 0); resultflags(rm8); } -:SHL rm8,CL is vexMode=0 & byte=0xD2; CL & rm8 & (reg_opcode=4|reg_opcode=6) ... { local count = CL & 0x1f; local tmp = rm8; rm8 = rm8 << count; +:SHL rm8,CL is vexMode=0 & byte=0xD2; CL & rm8 & (reg_opcode=4|reg_opcode=6) ... { local count = CL & 0x1f; local tmp = rm8; rm8 = rm8 << count; shlflags(tmp, rm8,count); shiftresultflags(rm8,count); } :SHL rm8,imm8 is vexMode=0 & byte=0xC0; rm8 & (reg_opcode=4|reg_opcode=6) ... ; imm8 { local count = imm8 & 0x1f; local tmp = rm8; rm8 = rm8 << count; shlflags(tmp, rm8,count); shiftresultflags(rm8,count); } @@ -4670,23 +4830,23 @@ define pcodeop smm_restore_state; shrdflags(tmp,rm64,count); shiftresultflags(rm64,count); } @endif -:SHR rm8,n1 is vexMode=0 & byte=0xD0; rm8 & n1 & reg_opcode=5 ... { CF = rm8 & 1; OF = 0; rm8 = rm8 >> 1; resultflags(rm8); } -:SHR rm8,CL is vexMode=0 & byte=0xD2; CL & rm8 & reg_opcode=5 ... { local count = CL & 0x1f; local tmp = rm8; rm8 = rm8 >> count; +:SHR rm8,n1 is vexMode=0 & byte=0xD0; rm8 & n1 & reg_opcode=5 ... { CF = rm8 & 1; OF = (rm8 s< 0); rm8 = rm8 >> 1; resultflags(rm8); } +:SHR rm8,CL is vexMode=0 & byte=0xD2; CL & rm8 & reg_opcode=5 ... { local count = CL & 0x1f; local tmp = rm8; rm8 = rm8 >> count; shrflags(tmp, rm8,count); shiftresultflags(rm8,count); } :SHR rm8,imm8 is vexMode=0 & byte=0xC0; rm8 & reg_opcode=5 ... ; imm8 { local count = imm8 & 0x1f; local tmp = rm8; rm8 = rm8 >> count; shrflags(tmp, rm8,count); shiftresultflags(rm8,count); } -:SHR rm16,n1 is vexMode=0 & opsize=0 & byte=0xD1; rm16 & n1 & reg_opcode=5 ... { CF = (rm16 & 1) != 0; OF = 0; rm16 = rm16 >> 1; resultflags(rm16); } +:SHR rm16,n1 is vexMode=0 & opsize=0 & byte=0xD1; rm16 & n1 & reg_opcode=5 ... { CF = (rm16 & 1) != 0; OF = (rm16 s< 0); rm16 = rm16 >> 1; resultflags(rm16); } :SHR rm16,CL is vexMode=0 & opsize=0 & byte=0xD3; CL & rm16 & reg_opcode=5 ... { local count = CL & 0x1f; local tmp = rm16; rm16 = rm16 >> count; shrflags(tmp, rm16,count); shiftresultflags(rm16,count); } :SHR rm16,imm8 is vexMode=0 & opsize=0 & byte=0xC1; rm16 & reg_opcode=5 ... ; imm8 { local count = imm8 & 0x1f; local tmp = rm16; rm16 = rm16 >> count; shrflags(tmp, rm16,count); shiftresultflags(rm16,count); } -:SHR rm32,n1 is vexMode=0 & opsize=1 & byte=0xD1; rm32 & n1 & check_rm32_dest ... & reg_opcode=5 ... { CF = (rm32 & 1) != 0; OF = 0; rm32 = rm32 >> 1; build check_rm32_dest; resultflags(rm32); } +:SHR rm32,n1 is vexMode=0 & opsize=1 & byte=0xD1; rm32 & n1 & check_rm32_dest ... & reg_opcode=5 ... { CF = (rm32 & 1) != 0; OF = (rm32 s< 0); rm32 = rm32 >> 1; build check_rm32_dest; resultflags(rm32); } :SHR rm32,CL is vexMode=0 & opsize=1 & byte=0xD3; CL & rm32 & check_rm32_dest ... & reg_opcode=5 ... { local count = CL & 0x1f; local tmp = rm32; rm32 = rm32 >> count; build check_rm32_dest; shrflags(tmp, rm32,count); shiftresultflags(rm32,count); } :SHR rm32,imm8 is vexMode=0 & opsize=1 & byte=0xC1; rm32 & check_rm32_dest ... & reg_opcode=5 ... ; imm8 { local count = imm8 & 0x1f; local tmp = rm32; rm32 = rm32 >> count; build check_rm32_dest; shrflags(tmp, rm32,count); shiftresultflags(rm32,count); } @ifdef IA64 -:SHR rm64,n1 is $(LONGMODE_ON) & vexMode=0 & opsize=2 & byte=0xD1; rm64 & n1 ®_opcode=5 ... { CF = (rm64 & 1) != 0; OF = 0; rm64 = rm64 >> 1; resultflags(rm64); } +:SHR rm64,n1 is $(LONGMODE_ON) & vexMode=0 & opsize=2 & byte=0xD1; rm64 & n1 ®_opcode=5 ... { CF = (rm64 & 1) != 0; OF = (rm64 s< 0); rm64 = rm64 >> 1; resultflags(rm64); } :SHR rm64,CL is $(LONGMODE_ON) & vexMode=0 & opsize=2 & byte=0xD3; CL & rm64 & reg_opcode=5 ... { local count = CL & 0x3f; local tmp = rm64; rm64 = rm64 >> count; shrflags(tmp, rm64,count); shiftresultflags(rm64,count); } :SHR rm64,imm8 is $(LONGMODE_ON) & vexMode=0 & opsize=2 & byte=0xC1; rm64 & reg_opcode=5 ... ; imm8 { local count = imm8 & 0x3f; local tmp = rm64; rm64 = rm64 >> count; @@ -4797,13 +4957,26 @@ define pcodeop skinit; @endif :SYSENTER is vexMode=0 & byte=0x0f; byte=0x34 { sysenter(); } -:SYSEXIT is vexMode=0 & byte=0x0f; byte=0x35 { sysexit(); +:SYSEXIT is vexMode=0 & opsize=1 & byte=0x0f; byte=0x35 { sysexit(); @ifdef IA64 - RIP=RCX; return [RIP]; + RSP=zext(ECX); RIP=zext(EDX); return [RIP]; +@else + ESP=ECX; EIP=EDX; return [EIP]; @endif } -:SYSCALL is vexMode=0 & byte=0x0f; byte=0x05 { syscall(); } +@ifdef IA64 +:SYSEXIT is $(LONGMODE_ON) & vexMode=0 & opsize=2 & byte=0x0f; byte=0x35 { sysexit(); + RSP=RCX; RIP=RDX; return [RIP]; + } +@endif + +@ifdef IA64 +:SYSCALL is $(LONGMODE_ON) & vexMode=0 & byte=0x0f; byte=0x05 { + RCX = inst_next; R11 = rflags; + syscall(); } +@endif + # returning to 32bit mode loads ECX # returning to 64bit mode loads RCX @@ -4815,7 +4988,7 @@ define pcodeop skinit; :SWAPGS is vexMode=0 & bit64=1 & byte=0x0f; byte=0x01; byte=0xf8 { swapgs(); } -:RDTSCP is vexMode=0 & bit64=1 & byte=0x0f; byte=0x01; byte=0xf9 { rdtscp(); } +:RDTSCP is vexMode=0 & byte=0x0f; byte=0x01; byte=0xf9 { rdtscp(); } :TEST AL,imm8 is vexMode=0 & byte=0xA8; AL & imm8 { logicalflags(); local tmp = AL & imm8; resultflags(tmp); } :TEST AX,imm16 is vexMode=0 & opsize=0; byte=0xA9; AX & imm16 { logicalflags(); local tmp = AX & imm16; resultflags(tmp); } @@ -4841,6 +5014,33 @@ define pcodeop invalidInstructionException; :UD1 Reg32, rm32 is vexMode=0 & byte=0x0f; byte=0xb9; rm32 & Reg32 ... { local target:$(SIZE) = invalidInstructionException(); goto [target]; } :UD2 is vexMode=0 & byte=0xf; byte=0xb { local target:$(SIZE) = invalidInstructionException(); goto [target]; } +define pcodeop umonitor; +:UMONITOR Rmr16 is vexMode=0 & opsize=0 & $(PRE_F3) & byte=0x0F; byte=0xAE; reg_opcode=6 & mod=3 & Rmr16 { + umonitor(Rmr16); +} + +:UMONITOR Rmr32 is vexMode=0 & opsize=1 & $(PRE_F3) & byte=0x0F; byte=0xAE; reg_opcode=6 & mod=3 & Rmr32 { + umonitor(Rmr32); +} + +@ifdef IA64 +:UMONITOR Rmr64 is $(LONGMODE_ON) & vexMode=0 & opsize=2 & $(PRE_F3) & byte=0x0F; byte=0xAE; reg_opcode=6 & mod=3 & Rmr64 { + umonitor(Rmr64); +} +@endif + +define pcodeop umwait; +:UMWAIT Rmr32 is vexMode=0 & $(PRE_F2) & byte=0x0F; byte=0xAE; reg_opcode=6 & mod=3 & Rmr32 { + umwait(Rmr32, EDX, EAX); +} + +define pcodeop tpause; +:TPAUSE Rmr32 is vexMode=0 & $(PRE_66) & byte=0x0F; byte=0xAE; reg_opcode=6 & mod=3 & Rmr32 { + tpause(Rmr32, EDX, EAX); +} + + + define pcodeop verr; define pcodeop verw; :VERR rm16 is vexMode=0 & byte=0xf; byte=0x0; rm16 & reg_opcode=4 ... { ZF = verr(); } @@ -4853,7 +5053,7 @@ define pcodeop verw; @ifdef IA64 :VMLOAD RAX is $(LONGMODE_ON) & vexMode=0 & addrsize=2 & byte=0x0f; byte=0x01; byte=0xda & RAX { vmload(RAX); } @endif -:VMMCALL is vexMode=0 & byte=0x0f; byte=0x01; byte=0xd9 { vmmcall(); } +:VMMCALL is $(PRE_NOFX) & vexMode=0 & byte=0x0f; byte=0x01; byte=0xd9 { vmmcall(); } # Limiting the effective address size to 32 and 64 bit. Surely we're not expecting a 16-bit VM address, are we? :VMRUN EAX is vexMode=0 & addrsize=1 & byte=0x0f; byte=0x01; byte=0xd8 & EAX { vmrun(EAX); } @ifdef IA64 @@ -4864,48 +5064,97 @@ define pcodeop verw; @ifdef IA64 :VMSAVE RAX is $(LONGMODE_ON) & vexMode=0 & addrsize=2 & byte=0x0f; byte=0x01; byte=0xdb & RAX { vmsave(RAX); } @endif -# + +@ifdef IA64 + +define pcodeop rmpFlags; + +# rFLAGS bits OF, ZF, AF, PF and SF are set based on return code +macro rmpFlagSet() { + local result:1 = rmpFlags(EAX); + OF = result[0,1]; + ZF = result[1,1]; + AF = result[2,1]; + PF = result[3,1]; + SF = result[4,1]; +} + +# Exit to VMM +define pcodeop vmgexit; +:VMGEXIT is ($(PRE_F2) | $(PRE_F3)) & vexMode=0 & byte=0x0f; byte=0x01; byte=0xd9 { vmgexit(); } + +# Page Smash +define pcodeop psmash; +:PSMASH is $(LONGMODE_ON) & vexMode=0 & $(PRE_F3) & byte=0x0f; byte=0x01; byte=0xff { EAX = psmash(RAX); rmpFlagSet(); } + +# Validate guest page RMP entry +define pcodeop pvalidate; +:PVALIDATE is $(LONGMODE_ON) & vexMode=0 & $(PRE_F2) & byte=0x0f; byte=0x01; byte=0xff { EAX = pvalidate(RAX, RCX, RDX); rmpFlagSet(); } + +# Adjust RMP permissions for guest page +define pcodeop rmpadjust; +:RMPADJUST is $(LONGMODE_ON) & vexMode=0 & $(PRE_F3) & byte=0x0f; byte=0x01; byte=0xfe { EAX = rmpadjust(RAX, RCX, RDX); rmpFlagSet(); } + +# Read the RMP permission mask for a guest page +define pcodeop rmpquery; +:RMPQUERY is $(LONGMODE_ON) & vexMode=0 & $(PRE_F3) & byte=0x0f; byte=0x01; byte=0xfd { EAX = rmpquery(RAX, RDX); rmpFlagSet(); } + +# Read an RMP entry +define pcodeop rmpread; +:RMPREAD is $(LONGMODE_ON) & vexMode=0 & $(PRE_F2) & byte=0x0f; byte=0x01; byte=0xfd { EAX = rmpread(RAX, RCX); rmpFlagSet(); } + +# Check RMP dirty status +define pcodeop rmpchkd; +:RMPCHKD is $(LONGMODE_ON) & vexMode=0 & $(PRE_F3) & byte=0x0f; byte=0x01; byte=0xfc { local result:1 = rmpchkd(RAX, RCX); ZF = result[1,1]; CF = result[2,1]; } + +# RMP Optimization +define pcodeop rmpopt; +:RMPOPT is $(LONGMODE_ON) & vexMode=0 & $(PRE_F2) & byte=0x0f; byte=0x01; byte=0xfc { CF = rmpopt(RAX, RCX); } + +# Write a new RMP entry +define pcodeop rmpupdate; +:RMPUPDATE is $(LONGMODE_ON) & vexMode=0 & $(PRE_F2) & byte=0x0f; byte=0x01; byte=0xfe { EAX = rmpupdate(RAX, RCX); rmpFlagSet(); } +@endif # # Intel hardware assisted virtualization opcodes + +# All except VMCALL and VMFUNC generate invalid-opcode exceptions if executed in compatibility mode @ifdef IA64 :INVEPT Reg64, m128 is $(LONGMODE_ON) & vexMode=0 & bit64=1 & $(PRE_66) & byte=0x0f; byte=0x38; byte=0x80; Reg64 ... & m128 { invept(Reg64, m128); } -@endif -:INVEPT Reg32, m128 is vexMode=0 & bit64=0 & $(PRE_66) & byte=0x0f; byte=0x38; byte=0x80; Reg32 ... & m128 { invept(Reg32, m128); } -@ifdef IA64 :INVVPID Reg64, m128 is $(LONGMODE_ON) & vexMode=0 & bit64=1 & $(PRE_66) & byte=0x0f; byte=0x38; byte=0x81; Reg64 ... & m128 { invvpid(Reg64, m128); } -@endif -:INVVPID Reg32, m128 is vexMode=0 & bit64=0 & $(PRE_66) & byte=0x0f; byte=0x38; byte=0x81; Reg32 ... & m128 { invvpid(Reg32, m128); } -:VMCALL is vexMode=0 & byte=0x0f; byte=0x01; byte=0xc1 { vmcall(); } -@ifdef IA64 :VMCLEAR m64 is $(LONGMODE_ON) & vexMode=0 & $(PRE_66) & byte=0x0f; byte=0xc7; ( mod != 0b11 & reg_opcode=6 ) ... & m64 { vmclear(m64); } -@endif -#TODO: invokes a VM function specified in EAX -:VMFUNC EAX is vexMode=0 & byte=0x0f; byte=0x01; byte=0xd4 & EAX { vmfunc(EAX); } #TODO: this launches the VM managed by the current VMCS. How is the VMCS expressed for the emulator? For Ghidra analysis? -:VMLAUNCH is vexMode=0 & byte=0x0f; byte=0x01; byte=0xc2 { vmlaunch(); } +:VMLAUNCH is $(LONGMODE_ON) & vexMode=0 & byte=0x0f; byte=0x01; byte=0xc2 { vmlaunch(); } #TODO: this resumes the VM managed by the current VMCS. How is the VMCS expressed for the emulator? For Ghidra analysis? -:VMRESUME is vexMode=0 & byte=0x0f; byte=0x01; byte=0xc3 { vmresume(); } +:VMRESUME is $(LONGMODE_ON) & vexMode=0 & byte=0x0f; byte=0x01; byte=0xc3 { vmresume(); } #TODO: this loads the VMCS pointer from the m64 memory address and makes the VMCS pointer valid; how to express # this for analysis and emulation? -:VMPTRLD m64 is vexMode=0 & byte=0x0f; byte=0xc7; ( mod != 0b11 & reg_opcode=6 ) ... & m64 { vmptrld(m64); } +:VMPTRLD m64 is $(LONGMODE_ON) & vexMode=0 & byte=0x0f; byte=0xc7; ( mod != 0b11 & reg_opcode=6 ) ... & m64 { vmptrld(m64); } #TODO: stores the current VMCS pointer into the specified 64-bit memory address; how to express this for analysis and emulation? -#TODO: note that the Intel manual does not specify m64 (which it does for VMPTRLD, yet it does state that "the operand -# of this instruction is always 64-bits and is always in memory". Is it an error that the "Instruction" entry in the -# box giving the definition does not specify m64? +:VMPTRST m64 is $(LONGMODE_ON) & vexMode=0 & byte=0x0f; byte=0xc7; ( mod != 0b11 & reg_opcode=7 ) ... & m64 { vmptrst(m64); } +:VMREAD rm64, Reg64 is $(LONGMODE_ON) & $(PRE_NO) & vexMode=0 & opsize=2 & byte=0x0f; byte=0x78; rm64 & Reg64 ... { rm64 = vmread(Reg64); } +:VMWRITE Reg64, rm64 is $(LONGMODE_ON) & $(PRE_NO) & vexMode=0 & opsize=2 & byte=0x0f; byte=0x79; rm64 & Reg64 ... { vmwrite(rm64,Reg64); } +:VMXOFF is $(LONGMODE_ON) & vexMode=0 & byte=0x0f; byte=0x01; byte=0xc4 { vmxoff(); } +:VMXON m64 is $(LONGMODE_ON) & vexMode=0 & $(PRE_F3) & byte=0x0f; byte=0xc7; ( mod != 0b11 & reg_opcode=6 ) ... & m64 { vmxon(m64); } +@else +:INVEPT Reg32, m128 is vexMode=0 & bit64=0 & $(PRE_66) & byte=0x0f; byte=0x38; byte=0x80; Reg32 ... & m128 { invept(Reg32, m128); } +:INVVPID Reg32, m128 is vexMode=0 & bit64=0 & $(PRE_66) & byte=0x0f; byte=0x38; byte=0x81; Reg32 ... & m128 { invvpid(Reg32, m128); } +:VMCLEAR m64 is vexMode=0 & $(PRE_66) & byte=0x0f; byte=0xc7; ( mod != 0b11 & reg_opcode=6 ) ... & m64 { vmclear(m64); } +:VMLAUNCH is vexMode=0 & byte=0x0f; byte=0x01; byte=0xc2 { vmlaunch(); } +:VMRESUME is vexMode=0 & byte=0x0f; byte=0x01; byte=0xc3 { vmresume(); } +:VMPTRLD m64 is vexMode=0 & byte=0x0f; byte=0xc7; ( mod != 0b11 & reg_opcode=6 ) ... & m64 { vmptrld(m64); } :VMPTRST m64 is vexMode=0 & byte=0x0f; byte=0xc7; ( mod != 0b11 & reg_opcode=7 ) ... & m64 { vmptrst(m64); } :VMREAD rm32, Reg32 is $(PRE_NO) & vexMode=0 & opsize=1 & byte=0x0f; byte=0x78; rm32 & check_rm32_dest ... & Reg32 ... { rm32 = vmread(Reg32); build check_rm32_dest; } -@ifdef IA64 -:VMREAD rm64, Reg64 is $(LONGMODE_ON) & $(PRE_NO) & vexMode=0 & opsize=2 & byte=0x0f; byte=0x78; rm64 & Reg64 ... { rm64 = vmread(Reg64); } -@endif :VMWRITE Reg32, rm32 is $(PRE_NO) & vexMode=0 & opsize=1 & byte=0x0f; byte=0x79; rm32 & Reg32 ... & check_Reg32_dest ... { vmwrite(rm32,Reg32); build check_Reg32_dest; } -@ifdef IA64 -:VMWRITE Reg64, rm64 is $(LONGMODE_ON) & $(PRE_NO) & vexMode=0 & opsize=2 & byte=0x0f; byte=0x79; rm64 & Reg64 ... { vmwrite(rm64,Reg64); } -@endif :VMXOFF is vexMode=0 & byte=0x0f; byte=0x01; byte=0xc4 { vmxoff(); } -# NB: this opcode is incorrect in the 2005 edition of the Intel manual. Opcode below is taken from the 2008 version. :VMXON m64 is vexMode=0 & $(PRE_F3) & byte=0x0f; byte=0xc7; ( mod != 0b11 & reg_opcode=6 ) ... & m64 { vmxon(m64); } +@endif + +:VMCALL is vexMode=0 & byte=0x0f; byte=0x01; byte=0xc1 { vmcall(); } +#TODO: invokes a VM function specified in EAX +:VMFUNC EAX is vexMode=0 & byte=0x0f; byte=0x01; byte=0xd4 & EAX { vmfunc(EAX); } #END of changes for VMX opcodes :WAIT is vexMode=0 & byte=0x9b { } @@ -4927,8 +5176,25 @@ define pcodeop wrpkru; define pcodeop wrmsr; :WRMSR is vexMode=0 & byte=0xf; byte=0x30 { tmp:8 = (zext(EDX) << 32) | zext(EAX); wrmsr(ECX,tmp); } + +@ifdef IA64 +define pcodeop urdmsr; +define pcodeop uwrmsr; +:URDMSR Rmr64, Reg64 is $(LONGMODE_ON) & vexMode=0 & $(PRE_F2) & byte=0x0F; byte=0x38; byte=0xF8; mod=3 & Reg64 & Rmr64 { Rmr64 = urdmsr(Reg64); } +:URDMSR Rmr64, imm32 is $(LONGMODE_ON) & $(VEX_L128) & $(PRE_F2) & $(VEX_MAP7) & $(VEX_W0) & byte=0xF8; mod=3 & reg_opcode=0 & Rmr64; imm32 { Rmr64 = urdmsr(imm32:4); } +:UWRMSR Reg64, Rmr64 is $(LONGMODE_ON) & vexMode=0 & $(PRE_F3) & byte=0x0F; byte=0x38; byte=0xF8; mod=3 & Reg64 & Rmr64 { Rmr64 = uwrmsr(Reg64, Rmr64); } +:UWRMSR imm32, Rmr64 is $(LONGMODE_ON) & $(VEX_L128) & $(PRE_F3) & $(VEX_MAP7) & $(VEX_W0) & byte=0xF8; mod=3 & reg_opcode=0 & Rmr64; imm32 { uwrmsr(imm32:4, Rmr64); } + +define pcodeop rdmsrlist; +define pcodeop wrmsrlist; +define pcodeop wrmsrns; +:RDMSRLIST is $(LONGMODE_ON) & vexMode=0 & $(PRE_F2) & byte=0x0F; byte=0x01; byte=0xC6 { rdmsrlist(RCX, RDI, RSI); } +:WRMSRLIST is $(LONGMODE_ON) & vexMode=0 & $(PRE_F3) & byte=0x0F; byte=0x01; byte=0xC6 { wrmsrlist(RCX, RDI, RSI); } +:WRMSRNS is $(LONGMODE_ON) & vexMode=0 & $(PRE_NO) & byte=0x0F; byte=0x01; byte=0xC6 { tmp:8 = (zext(EDX) << 32) | zext(EAX); wrmsrns(ECX,tmp); } +@endif + # See 'lockable.sinc' for memory destination, lockable variants -:XADD Rmr8,Reg8 is vexMode=0 & byte=0x0F; byte=0xC0; mod=3 & Rmr8 & Reg8 { addflags( Rmr8,Reg8 ); local tmp = Rmr8 + Reg8; Reg8 = Rmr8; Rmr8 = tmp; resultflags(tmp); } +:XADD Rmr8,Reg8 is vexMode=0 & byte=0x0F; byte=0xC0; mod=3 & Rmr8 & Reg8 { addflags( Rmr8,Reg8 ); local tmp = Rmr8 + Reg8; Reg8 = Rmr8; Rmr8 = tmp; resultflags(tmp); } :XADD Rmr16,Reg16 is vexMode=0 & opsize=0 & byte=0x0F; byte=0xC1; mod=3 & Rmr16 & Reg16 { addflags(Rmr16,Reg16); local tmp = Rmr16 + Reg16; Reg16 = Rmr16; Rmr16 = tmp; resultflags(tmp); } :XADD Rmr32,Reg32 is vexMode=0 & opsize=1 & byte=0x0F; byte=0xC1; mod=3 & Rmr32 & check_Rmr32_dest & Reg32 & check_Reg32_dest { addflags(Rmr32,Reg32); local tmp = Rmr32 + Reg32; Reg32 = Rmr32; Rmr32 = tmp; build check_Rmr32_dest; build check_Reg32_dest; resultflags(tmp); } @ifdef IA64 @@ -4998,8 +5264,9 @@ define pcodeop xend; :XOR Reg64,rm64 is $(LONGMODE_ON) & vexMode=0 & opsize=2 & byte=0x33; rm64 & Reg64 ... { logicalflags(); Reg64 = Reg64 ^ rm64; resultflags(Reg64); } @endif -:XGETBV is vexMode=0 & byte=0x0F; byte=0x01; byte=0xD0 { local tmp = XCR0 >> 32; EDX = tmp:4; EAX = XCR0:4; } -:XSETBV is vexMode=0 & byte=0x0F; byte=0x01; byte=0xD1 { XCR0 = (zext(EDX) << 32) | zext(EAX); } +define pcodeop xinuse; +:XGETBV is vexMode=0 & byte=0x0F; byte=0x01; byte=0xD0 { local test = (ECX == 1); local xiu:8 = xinuse(test); local tXCR0 = (zext(test) * XCR0) + (zext(!test) * (XCR0 & xiu)); local tmp = tXCR0 >> 32; EDX = tmp:4; EAX = tXCR0:4; } +:XSETBV is vexMode=0 & byte=0x0F; byte=0x01; byte=0xD1 { local sel = ECX; XCR0 = (zext(EDX) << 32) | zext(EAX); } define pcodeop xsave; define pcodeop xsave64; @@ -5051,6 +5318,7 @@ define pcodeop xtest; :MFENCE is vexMode=0 & $(PRE_NO) & byte=0x0F; byte=0xAE; mod = 0b11 & reg_opcode=6 & r_m=0 { } :SFENCE is vexMode=0 & $(PRE_NO) & byte=0x0F; byte=0xAE; mod = 0b11 & reg_opcode=7 & r_m=0 { } + # # floating point instructions # @@ -5193,11 +5461,11 @@ define pcodeop to_bcd; ST0 = freg; } -:FCMOVNBE ST0, freg is vexMode=0 & byte=0xDB; frow=13 & fpage=0 & freg & ST0 -{ +:FCMOVNBE ST0, freg is vexMode=0 & byte=0xDB; frow=13 & fpage=0 & freg & ST0 +{ FPUInstructionPointer = inst_start; - if ( CF & ZF ) goto inst_next; - ST0 = freg; + if ( CF | ZF ) goto inst_next; + ST0 = freg; } :FCMOVNU ST0, freg is vexMode=0 & byte=0xDB; frow=13 & fpage=1 & freg & ST0 { @@ -5303,12 +5571,12 @@ define pcodeop fcos; ST0 = fcos(ST0); } -:FDECSTP is vexMode=0 & byte=0xD9; byte=0xF6 -{ +:FDECSTP is vexMode=0 & byte=0xD9; byte=0xF6 +{ FPUInstructionPointer = inst_start; - fdec(); - FPUStatusWord = FPUStatusWord & 0xfeff; - C0 = 0; #Clear C0 + fdec(); + FPUStatusWord = FPUStatusWord & 0xfdff; + C1 = 0; #Clear C1 } # Legacy 8087 instructions. Still valid but treated as NOP instructions. @@ -5732,20 +6000,22 @@ define pcodeop fpatan; fpop(); } -:FPREM is vexMode=0 & byte=0xD9; byte=0xF8 -{ +:FPREM is vexMode=0 & byte=0xD9; byte=0xF8 +{ FPUInstructionPointer = inst_start; - local tmp = ST0 f/ ST1; - tmp = tmp f* ST1; - ST0 = ST0 f- tmp; + local tmp = ST0 f/ ST1; + tmp = trunc(tmp); + tmp = tmp f* ST1; + ST0 = ST0 f- tmp; } -:FPREM1 is vexMode=0 & byte=0xD9; byte=0xF5 -{ +:FPREM1 is vexMode=0 & byte=0xD9; byte=0xF5 +{ FPUInstructionPointer = inst_start; - local tmp = ST0 f/ ST1; - tmp = tmp f* ST1; - ST0 = ST0 f- tmp; + local tmp = ST0 f/ ST1; + tmp = round(tmp); + tmp = tmp f* ST1; + ST0 = ST0 f- tmp; } define pcodeop fptan; @@ -6179,6 +6449,7 @@ define pcodeop _fxrstor64; define pcodeop extract_significand; define pcodeop extract_exponent; +define pcodeop log2; :FXTRACT is vexMode=0 & byte=0xD9; byte=0xF4 { FPUInstructionPointer = inst_start; @@ -6188,20 +6459,20 @@ define pcodeop extract_exponent; fpushv(significand); } -:FYL2X is vexMode=0 & byte=0xD9; byte=0xF1 -{ +:FYL2X is vexMode=0 & byte=0xD9; byte=0xF1 +{ FPUInstructionPointer = inst_start; - local log2st0 = ST0; - ST1 = ST1 f* log2st0; + local log2st0:10 = log2(ST0); + ST1 = ST1 f* log2st0; fpop(); } -:FYL2XP1 is vexMode=0 & byte=0xD9; byte=0xF9 -{ +:FYL2XP1 is vexMode=0 & byte=0xD9; byte=0xF9 +{ FPUInstructionPointer = inst_start; one:4 = 1; tmp:10 = int2float(one); - log2st0:10 = ST0 f+ tmp; - ST1 = ST1 f* log2st0; + log2st0:10 = log2(ST0 f+ tmp); + ST1 = ST1 f* log2st0; fpop(); } @@ -7145,8 +7416,15 @@ define pcodeop divps; define pcodeop lddqu; :LDDQU XmmReg, m128 is vexMode=0 & $(PRE_F2) & byte=0x0F; byte=0xF0; XmmReg ... & m128 { XmmReg = lddqu(XmmReg, m128); } +maskMovDI: seg16^DI is addrsize=0 & seg16 & DI { tmp:$(SIZE) = segment(seg16,DI); export *:16 tmp; } +maskMovDI: segWide^EDI is addrsize=1 & segWide & EDI { tmp:$(SIZE) = zext(EDI); export *:16 tmp; } +maskMovDI: segWide^EDI is addrsize=1 & segWide & highseg=1 & EDI { tmp:$(SIZE) = segWide + zext(EDI); export *:16 tmp; } +@ifdef IA64 +maskMovDI: segWide^RDI is $(LONGMODE_ON) & addrsize=2 & segWide & RDI { tmp:$(SIZE) = RDI; export *:16 tmp; } +maskMovDI: segWide^RDI is $(LONGMODE_ON) & addrsize=2 & segWide & highseg=1 & RDI { tmp:$(SIZE) = segWide + RDI; export *:16 tmp; } +@endif define pcodeop maskmovdqu; -:MASKMOVDQU XmmReg1, XmmReg2 is vexMode=0 & $(PRE_66) & byte=0x0F; byte=0xF7; XmmReg1 & XmmReg2 { XmmReg1 = maskmovdqu(XmmReg1, XmmReg2); } +:MASKMOVDQU XmmReg1, XmmReg2 is vexMode=0 & $(PRE_66) & byte=0x0F; byte=0xF7 & maskMovDI; XmmReg1 & XmmReg2 { maskMovDI = maskmovdqu(XmmReg1, XmmReg2); } define pcodeop maxpd; :MAXPD XmmReg, m128 is vexMode=0 & $(PRE_66) & byte=0x0F; byte=0x5F; XmmReg ... & m128 { XmmReg = maxpd(XmmReg, m128); } @@ -7387,10 +7665,10 @@ define pcodeop movdq2q; :MOVLPS m64, XmmReg is vexMode=0 & mandover=0 & byte=0x0F; byte=0x13; XmmReg ... & m64 { m64 = XmmReg[0,64]; } define pcodeop movmskpd; -:MOVMSKPD Reg32, XmmReg2 is vexMode=0 & $(PRE_66) & byte=0x0F; byte=0x50; XmmReg2 & Reg32 { Reg32 = movmskpd(Reg32, XmmReg2); } +:MOVMSKPD Reg32, XmmReg2 is vexMode=0 & $(PRE_66) & byte=0x0F; byte=0x50; XmmReg2 & Reg32 & check_Reg32_dest { Reg32 = movmskpd(Reg32, XmmReg2); build check_Reg32_dest; } define pcodeop movmskps; -:MOVMSKPS Reg32, XmmReg2 is vexMode=0 & mandover=0 & byte=0x0F; byte=0x50; XmmReg2 & Reg32 { Reg32 = movmskps(Reg32, XmmReg2); } +:MOVMSKPS Reg32, XmmReg2 is vexMode=0 & mandover=0 & byte=0x0F; byte=0x50; XmmReg2 & Reg32 & check_Reg32_dest { Reg32 = movmskps(Reg32, XmmReg2); build check_Reg32_dest; } :MOVNTQ m64, mmxreg is vexMode=0 & mandover=0 & byte=0x0F; byte=0xE7; mmxreg ... & m64 { m64 = mmxreg; } @@ -8385,10 +8663,11 @@ define pcodeop pavgw; XmmReg1[96,32] = zext(XmmReg1[96,32] s> XmmReg2[96,32]) * 0xFFFFFFFF; } -:PEXTRW Reg32, mmxreg2, imm8 is vexMode=0 & mandover=0 & byte=0x0F; byte=0xC5; Reg32 & mmxreg2; imm8 +:PEXTRW Reg32, mmxreg2, imm8 is vexMode=0 & mandover=0 & byte=0x0F; byte=0xC5; Reg32 & check_Reg32_dest & mmxreg2; imm8 { temp:8 = mmxreg2 >> ( (imm8 & 0x03) * 16 ); Reg32 = zext(temp:2); + build check_Reg32_dest; } :PEXTRW Reg32, XmmReg2, imm8 is vexMode=0 & $(PRE_66) & byte=0x0F; byte=0xC5; Reg32 & XmmReg2 & check_Reg32_dest; imm8 @@ -8459,7 +8738,7 @@ define pcodeop phsubsw; :PINSRW mmxreg, Rmr32, imm8 is vexMode=0 & mandover=0 & byte=0x0F; byte=0xC4; mmxmod=3 & Rmr32 & mmxreg; imm8 { - local destIndex:1 = (imm8 & 0x7) * 16:1; + local destIndex:1 = (imm8 & 0x3) * 16:1; mmxreg = mmxreg & ~(0xffff:8 << destIndex); local newVal:8 = zext(Rmr32[0,16]); mmxreg = mmxreg | (newVal << destIndex); @@ -8467,7 +8746,7 @@ define pcodeop phsubsw; :PINSRW mmxreg, m16, imm8 is vexMode=0 & mandover=0 & byte=0x0F; byte=0xC4; m16 & mmxreg ... ; imm8 { - local destIndex:1 = (imm8 & 0x7) * 16:1; + local destIndex:1 = (imm8 & 0x3) * 16:1; mmxreg = mmxreg & ~(0xffff:8 << destIndex); local newVal:8 = zext(m16); mmxreg = mmxreg | (newVal << destIndex); @@ -8843,14 +9122,15 @@ define pcodeop psllw; :PSLLW mmxreg2, imm8 is vexMode=0 & mandover=0 & byte=0x0F; byte=0x71; mod = 0b11 & reg_opcode=6 & mmxreg2; imm8 { mmxreg2 = psllw(mmxreg2, imm8:8); } :PSLLD mmxreg, m64 is vexMode=0 & mandover=0 & byte=0x0F; byte=0xF2; mmxreg ... & m64 ... { - local m:8 = m64; - mmxreg[0,32] = mmxreg[0,32] << m[0,32]; - mmxreg[32,32] = mmxreg[32,32] << m[32,32]; + local count = m64; + mmxreg[0,32] = mmxreg[0,32] << count; + mmxreg[32,32] = mmxreg[32,32] << count; } :PSLLD mmxreg1, mmxreg2 is vexMode=0 & mandover=0 & byte=0x0F; byte=0xF2; mmxmod = 3 & mmxreg1 & mmxreg2 { - mmxreg1[0,32] = mmxreg1[0,32] << mmxreg2[0,32]; - mmxreg1[32,32] = mmxreg1[32,32] << mmxreg2[32,32]; + local count = mmxreg2; + mmxreg1[0,32] = mmxreg1[0,32] << count; + mmxreg1[32,32] = mmxreg1[32,32] << count; } :PSLLD mmxreg2, imm8 is vexMode=0 & mandover=0 & byte=0x0F; byte=0x72; mod = 0b11 & reg_opcode=6 & mmxreg2; imm8 { @@ -8868,17 +9148,19 @@ define pcodeop psllw; :PSLLD XmmReg, m128 is vexMode=0 & $(PRE_66) & byte=0x0F; byte=0xF2; XmmReg ... & m128 ... { local m:16 = m128; - XmmReg[0,32] = XmmReg[0,32] << m[0,32]; - XmmReg[32,32] = XmmReg[32,32] << m[32,32]; - XmmReg[64,32] = XmmReg[64,32] << m[64,32]; - XmmReg[96,32] = XmmReg[96,32] << m[96,32]; + local count:8 = m(0); + XmmReg[0,32] = XmmReg[0,32] << count; + XmmReg[32,32] = XmmReg[32,32] << count; + XmmReg[64,32] = XmmReg[64,32] << count; + XmmReg[96,32] = XmmReg[96,32] << count; } :PSLLD XmmReg1, XmmReg2 is vexMode=0 & $(PRE_66) & byte=0x0F; byte=0xF2; xmmmod = 3 & XmmReg1 & XmmReg2 { - XmmReg1[0,32] = XmmReg1[0,32] << XmmReg2[0,32]; - XmmReg1[32,32] = XmmReg1[32,32] << XmmReg2[32,32]; - XmmReg1[64,32] = XmmReg1[64,32] << XmmReg2[64,32]; - XmmReg1[96,32] = XmmReg1[96,32] << XmmReg2[96,32]; + local count = XmmReg2[0,64]; + XmmReg1[0,32] = XmmReg1[0,32] << count; + XmmReg1[32,32] = XmmReg1[32,32] << count; + XmmReg1[64,32] = XmmReg1[64,32] << count; + XmmReg1[96,32] = XmmReg1[96,32] << count; } :PSLLD XmmReg2, imm8 is vexMode=0 & $(PRE_66) & byte=0x0F; byte=0x72; mod = 0b11 & reg_opcode=6 & XmmReg2; imm8 { @@ -8890,13 +9172,15 @@ define pcodeop psllw; :PSLLQ XmmReg, m128 is vexMode=0 & $(PRE_66) & byte=0x0F; byte=0xF3; XmmReg ... & m128 ... { local m:16 = m128; - XmmReg[0,64] = XmmReg[0,64] << m[0,64]; - XmmReg[64,64] = XmmReg[64,64] << m[64,64]; + local count:8 = m[0,64]; + XmmReg[0,64] = XmmReg[0,64] << count; + XmmReg[64,64] = XmmReg[64,64] << count; } :PSLLQ XmmReg1, XmmReg2 is vexMode=0 & $(PRE_66) & byte=0x0F; byte=0xF3; xmmmod = 3 & XmmReg1 & XmmReg2 { - XmmReg1[0,64] = XmmReg1[0,64] << XmmReg2[0,64]; - XmmReg1[64,64] = XmmReg1[64,64] << XmmReg2[64,64]; + local count:8 = XmmReg2[0,64]; + XmmReg1[0,64] = XmmReg1[0,64] << count; + XmmReg1[64,64] = XmmReg1[64,64] << count; } :PSLLQ XmmReg2, imm8 is vexMode=0 & $(PRE_66) & byte=0x0F; byte=0x73; mod = 0b11 & reg_opcode=6 & XmmReg2; imm8 { @@ -8937,19 +9221,22 @@ define pcodeop psraw; :PSRAD XmmReg, m128 is vexMode=0 & $(PRE_66) & byte=0x0F; byte=0xE2; m128 & XmmReg ... { # a count greater than 31 just clears all the bits - XmmReg[0,32] = XmmReg[0,32] s>> m128; - XmmReg[32,32] = XmmReg[32,32] s>> m128; - XmmReg[64,32] = XmmReg[64,32] s>> m128; - XmmReg[96,32] = XmmReg[96,32] s>> m128; + local m:16 = m128; + local count:4 = m[0,32]; + XmmReg[0,32] = XmmReg[0,32] s>> count; + XmmReg[32,32] = XmmReg[32,32] s>> count; + XmmReg[64,32] = XmmReg[64,32] s>> count; + XmmReg[96,32] = XmmReg[96,32] s>> count; } :PSRAD XmmReg1, XmmReg2 is vexMode=0 & $(PRE_66) & byte=0x0F; byte=0xE2; xmmmod = 3 & XmmReg1 & XmmReg2 { # a count greater than 31 just clears all the bits - XmmReg1[0,32] = XmmReg1[0,32] s>> XmmReg2; - XmmReg1[32,32] = XmmReg1[32,32] s>> XmmReg2; - XmmReg1[64,32] = XmmReg1[64,32] s>> XmmReg2; - XmmReg1[96,32] = XmmReg1[96,32] s>> XmmReg2; + local count:4 = XmmReg2[0,32]; + XmmReg1[0,32] = XmmReg1[0,32] s>> count; + XmmReg1[32,32] = XmmReg1[32,32] s>> count; + XmmReg1[64,32] = XmmReg1[64,32] s>> count; + XmmReg1[96,32] = XmmReg1[96,32] s>> count; } :PSRAD XmmReg2, imm8 is vexMode=0 & $(PRE_66) & byte=0x0F; byte=0x72; mod = 0b11 & reg_opcode=4 & XmmReg2; imm8 @@ -9127,6 +9414,7 @@ define pcodeop psraw; :PSUBB mmxreg1, mmxreg2 is vexMode=0 & mandover=0 & byte=0x0F; byte=0xF8; mmxmod = 3 & mmxreg1 & mmxreg2 { mmxreg1[0,8] = mmxreg1[0,8] - mmxreg2[0,8]; + mmxreg1[8,8] = mmxreg1[8,8] - mmxreg2[8,8]; mmxreg1[16,8] = mmxreg1[16,8] - mmxreg2[16,8]; mmxreg1[24,8] = mmxreg1[24,8] - mmxreg2[24,8]; mmxreg1[32,8] = mmxreg1[32,8] - mmxreg2[32,8]; @@ -9605,6 +9893,18 @@ define pcodeop rsqrtss; :RSQRTSS XmmReg, m32 is vexMode=0 & $(PRE_F3) & byte=0x0F; byte=0x52; XmmReg ... & m32 { XmmReg = rsqrtss(XmmReg, m32); } :RSQRTSS XmmReg1, XmmReg2 is vexMode=0 & $(PRE_F3) & byte=0x0F; byte=0x52; xmmmod = 3 & XmmReg1 & XmmReg2 { XmmReg1 = rsqrtss(XmmReg1, XmmReg2); } +@ifdef IA64 +define pcodeop senduipi; +define pcodeop testui; +define pcodeop setui; +define pcodeop clearui; +:SENDUIPI Rmr64 is $(LONGMODE_ON) & $(PRE_F3) & byte=0x0F; byte=0xC7; mod=3 & reg_opcode=0x6 & Rmr64 { senduipi(Rmr64); } +:TESTUI is $(LONGMODE_ON) & $(PRE_F3) & byte=0x0F; byte=0x01; byte=0xED { CF = testui(); } +:UIRET is $(LONGMODE_ON) & $(PRE_F3) & byte=0x0F; byte=0x01; byte=0xEC { pop88(RIP); pop88(rflags); pop88(RSP); unpackflags(rflags); unpackeflags(rflags); setui(); return [RIP]; } +:CLUI is $(LONGMODE_ON) & $(PRE_F3) & byte=0x0F; byte=0x01; byte=0xEE { clearui(); } +:STUI is $(LONGMODE_ON) & $(PRE_F3) & byte=0x0F; byte=0x01; byte=0xEF { setui(); } +@endif + :SHUFPD XmmReg1, XmmReg2_m128, imm8 is vexMode=0 & $(PRE_66) & byte=0x0F; byte=0xC6; XmmReg1 ... & XmmReg2_m128; imm8 { local srcLow:8 = XmmReg2_m128[0,64]; @@ -10248,16 +10548,24 @@ define pcodeop crc32; @endif define pcodeop pcmpestri; -:PCMPESTRI XmmReg, m128, imm8 is vexMode=0 & $(PRE_66) & byte=0x0F; byte=0x3A; byte=0x61; XmmReg ... & m128; imm8 { ECX = pcmpestri(XmmReg, m128, imm8:8); } -:PCMPESTRI XmmReg1, XmmReg2, imm8 is vexMode=0 & $(PRE_66) & byte=0x0F; byte=0x3A; byte=0x61; xmmmod=3 & XmmReg1 & XmmReg2; imm8 { ECX = pcmpestri(XmmReg1, XmmReg2, imm8:8); } +:PCMPESTRI XmmReg, m128, imm8 is vexMode=0 & $(PRE_66) & byte=0x0F; byte=0x3A; byte=0x61 & check_ECX_dest; XmmReg ... & m128; imm8 { ECX = pcmpestri(XmmReg, m128, imm8:8, EAX, EDX); build check_ECX_dest; } +:PCMPESTRI XmmReg1, XmmReg2, imm8 is vexMode=0 & $(PRE_66) & byte=0x0F; byte=0x3A; byte=0x61 & check_ECX_dest; xmmmod=3 & XmmReg1 & XmmReg2; imm8 { ECX = pcmpestri(XmmReg1, XmmReg2, imm8:8, EAX, EDX); build check_ECX_dest; } +@ifdef IA64 +:PCMPESTRI XmmReg, m128, imm8 is vexMode=0 & $(REX_W) & opsize=2 & $(PRE_66) & byte=0x0F; byte=0x3A; byte=0x61 & check_ECX_dest; XmmReg ... & m128; imm8 { ECX = pcmpestri(XmmReg, m128, imm8:8, RAX, RDX); build check_ECX_dest; } +:PCMPESTRI XmmReg1, XmmReg2, imm8 is vexMode=0 & $(REX_W) & opsize=2 & $(PRE_66) & byte=0x0F; byte=0x3A; byte=0x61 & check_ECX_dest; xmmmod=3 & XmmReg1 & XmmReg2; imm8 { ECX = pcmpestri(XmmReg1, XmmReg2, imm8:8, RAX, RDX); build check_ECX_dest; } +@endif define pcodeop pcmpestrm; -:PCMPESTRM XmmReg, m128, imm8 is vexMode=0 & $(PRE_66) & byte=0x0F; byte=0x3A; byte=0x60; XmmReg ... & m128; imm8 { XMM0 = pcmpestrm(XmmReg, m128, imm8:8); } -:PCMPESTRM XmmReg1, XmmReg2, imm8 is vexMode=0 & $(PRE_66) & byte=0x0F; byte=0x3A; byte=0x60; xmmmod=3 & XmmReg1 & XmmReg2; imm8 { XMM0 = pcmpestrm(XmmReg1, XmmReg2, imm8:8); } +:PCMPESTRM XmmReg, m128, imm8 is vexMode=0 & $(PRE_66) & byte=0x0F; byte=0x3A; byte=0x60; XmmReg ... & m128; imm8 { XMM0 = pcmpestrm(XmmReg, m128, imm8:8, EAX, EDX); } +:PCMPESTRM XmmReg1, XmmReg2, imm8 is vexMode=0 & $(PRE_66) & byte=0x0F; byte=0x3A; byte=0x60; xmmmod=3 & XmmReg1 & XmmReg2; imm8 { XMM0 = pcmpestrm(XmmReg1, XmmReg2, imm8:8, EAX, EDX); } +@ifdef IA64 +:PCMPESTRM XmmReg, m128, imm8 is vexMode=0 & $(REX_W) & opsize=2 & $(PRE_66) & byte=0x0F; byte=0x3A; byte=0x60; XmmReg ... & m128; imm8 { XMM0 = pcmpestrm(XmmReg, m128, imm8:8, RAX, RDX); } +:PCMPESTRM XmmReg1, XmmReg2, imm8 is vexMode=0 & $(REX_W) & opsize=2 & $(PRE_66) & byte=0x0F; byte=0x3A; byte=0x60; xmmmod=3 & XmmReg1 & XmmReg2; imm8 { XMM0 = pcmpestrm(XmmReg1, XmmReg2, imm8:8, RAX, RDX); } +@endif define pcodeop pcmpistri; -:PCMPISTRI XmmReg, m128, imm8 is vexMode=0 & $(PRE_66) & byte=0x0F; byte=0x3A; byte=0x63; XmmReg ... & m128; imm8 { ECX = pcmpistri(XmmReg, m128, imm8:8); } -:PCMPISTRI XmmReg1, XmmReg2, imm8 is vexMode=0 & $(PRE_66) & byte=0x0F; byte=0x3A; byte=0x63; xmmmod=3 & XmmReg1 & XmmReg2; imm8 { ECX = pcmpistri(XmmReg1, XmmReg2, imm8:8); } +:PCMPISTRI XmmReg, m128, imm8 is vexMode=0 & $(PRE_66) & byte=0x0F; byte=0x3A; byte=0x63 & check_ECX_dest; XmmReg ... & m128; imm8 { ECX = pcmpistri(XmmReg, m128, imm8:8); build check_ECX_dest; } +:PCMPISTRI XmmReg1, XmmReg2, imm8 is vexMode=0 & $(PRE_66) & byte=0x0F; byte=0x3A; byte=0x63 & check_ECX_dest; xmmmod=3 & XmmReg1 & XmmReg2; imm8 { ECX = pcmpistri(XmmReg1, XmmReg2, imm8:8); build check_ECX_dest;} define pcodeop pcmpistrm; :PCMPISTRM XmmReg, m128, imm8 is vexMode=0 & $(PRE_66) & byte=0x0F; byte=0x3A; byte=0x62; XmmReg ... & m128; imm8 { XMM0 = pcmpistrm(XmmReg, m128, imm8:8); } @@ -10455,7 +10763,7 @@ define pcodeop PackedSwapDWords; :PSWAPD mmxreg1, mmxreg2 is vexMode=0 & suffix3D=0xBB & mandover=0 & byte=0x0F; byte=0x0F; mmxmod = 3 & mmxreg1 & mmxreg2 { mmxreg1 = PackedSwapDWords(mmxreg1, mmxreg2); } define pcodeop MaskedMoveQWord; -:MASKMOVQ mmxreg1, mmxreg2 is vexMode=0 & mandover=0 & byte=0x0F; byte=0xF7; mmxmod = 3 & mmxreg1 & mmxreg2 { mmxreg1 = MaskedMoveQWord(mmxreg1, mmxreg2); } +:MASKMOVQ mmxreg1, mmxreg2 is vexMode=0 & mandover=0 & byte=0x0F; byte=0xF7 & maskMovDI; mmxmod = 3 & mmxreg1 & mmxreg2 { maskMovDI = MaskedMoveQWord(mmxreg1, mmxreg2); } #### @@ -10499,4 +10807,7 @@ lsbOffset: val is imm8 [ val=imm8 & 0x3f; ] { export *[const]:1 val; } :MOVNTSS m32, XmmReg1 is vexMode=0 & $(PRE_F3) & byte=0x0F; byte=0x2B; XmmReg1 ... & m32 { m32 = XmmReg1[0,32]; } + + + } # end with : lockprefx=0 diff --git a/pypcode/processors/x86/data/languages/lockable.sinc b/pypcode/processors/x86/data/languages/lockable.sinc index 9f8e7c7..ebcbe97 100644 --- a/pypcode/processors/x86/data/languages/lockable.sinc +++ b/pypcode/processors/x86/data/languages/lockable.sinc @@ -643,7 +643,7 @@ } @endif -:CMPXCHG8B^lockx m64 is vexMode=0 & lockx & unlock & byte=0xf; byte=0xc7; ( mod != 0b11 & reg_opcode=1 ) ... & m64 +:CMPXCHG8B^lockx m64 is vexMode=0 & lockx & unlock & byte=0xf; byte=0xc7; ( mod != 0b11 & reg_opcode=1 & check_EAX_dest & check_EDX_dest ) ... & m64 { build lockx; local dest = m64; @@ -651,6 +651,8 @@ if (ZF == 1) goto ; EDX = dest(4); EAX = dest:4; + build check_EAX_dest; + build check_EDX_dest; goto ; m64 = (zext(ECX) << 32) | zext(EBX); @@ -1196,13 +1198,14 @@ build unlock; } -:XADD^lockx m32,Reg32 is vexMode=0 & lockx & unlock & opsize=1 & byte=0x0F; byte=0xC1; m32 & Reg32 ... +:XADD^lockx m32,Reg32 is vexMode=0 & lockx & unlock & opsize=1 & byte=0x0F; byte=0xC1; (check_Reg32_dest & Reg32) ... & m32 { build lockx; build m32; addflags(m32,Reg32); local tmp = m32 + Reg32; Reg32 = m32; + build check_Reg32_dest; m32 = tmp; resultflags(tmp); build unlock; diff --git a/pypcode/processors/x86/data/languages/rao.sinc b/pypcode/processors/x86/data/languages/rao.sinc new file mode 100644 index 0000000..ed804bf --- /dev/null +++ b/pypcode/processors/x86/data/languages/rao.sinc @@ -0,0 +1,44 @@ +#### +#### RAO-INT instructions +#### + +:AADD m32,Reg32 is vexMode=0 & rexprefix=0 & $(PRE_NO) & byte=0x0F; byte=0x38; byte=0xFC; Reg32 ... & m32 { + m32 = m32 + Reg32; +} + +@ifdef IA64 +:AADD m64,Reg64 is $(REX_W) & $(PRE_NO) & byte=0x0F; byte=0x38; byte=0xFC; Reg64 ... & m64 { + m64 = m64 + Reg64; +} +@endif + +:AAND m32,Reg32 is vexMode=0 & rexprefix=0 & $(PRE_66) & byte=0x0F; byte=0x38; byte=0xFC; Reg32 ... & m32 { + m32 = m32 & Reg32; +} + +@ifdef IA64 +:AAND m64,Reg64 is $(REX_W) & $(PRE_66) & byte=0x0F; byte=0x38; byte=0xFC; Reg64 ... & m64 { + m64 = m64 & Reg64; +} +@endif + +:AOR m32,Reg32 is vexMode=0 & rexprefix=0 & $(PRE_F2) & byte=0x0F; byte=0x38; byte=0xFC; Reg32 ... & m32 { + m32 = m32 | Reg32; +} + +@ifdef IA64 +:AOR m64,Reg64 is $(REX_W) & $(PRE_F2) & byte=0x0F; byte=0x38; byte=0xFC; Reg64 ... & m64 { + m64 = m64 | Reg64; +} +@endif + +:AXOR m32,Reg32 is vexMode=0 & rexprefix=0 & $(PRE_F3) & byte=0x0F; byte=0x38; byte=0xFC; Reg32 ... & m32 { + m32 = m32 ^ Reg32; +} + +@ifdef IA64 +:AXOR m64,Reg64 is $(REX_W) & $(PRE_F3) & byte=0x0F; byte=0x38; byte=0xFC; Reg64 ... & m64 { + m64 = m64 ^ Reg64; +} +@endif + diff --git a/pypcode/processors/x86/data/languages/rdrand.sinc b/pypcode/processors/x86/data/languages/rdrand.sinc index 4037bb9..3372e90 100644 --- a/pypcode/processors/x86/data/languages/rdrand.sinc +++ b/pypcode/processors/x86/data/languages/rdrand.sinc @@ -12,11 +12,12 @@ macro rdflags(){ rdflags(); } -:RDRAND Rmr32 is vexMode=0 & opsize=1 & byte=0x0f; byte=0xC7; mod=3 & Rmr32 & reg_opcode=6 +:RDRAND Rmr32 is vexMode=0 & opsize=1 & byte=0x0f; byte=0xC7; mod=3 & Rmr32 & check_Reg32_dest & reg_opcode=6 { Rmr32 = rdrand(); CF=rdrandIsValid(); rdflags(); + build check_Reg32_dest; } @ifdef IA64 :RDRAND Rmr64 is $(LONGMODE_ON) & vexMode=0 & opsize=2 & $(REX_W) & byte=0x0f; byte=0xC7; mod=3 & Rmr64 & reg_opcode=6 @@ -35,11 +36,12 @@ define pcodeop rdseedIsValid; CF=rdseedIsValid(); rdflags(); } -:RDSEED Rmr32 is vexMode=0 & opsize=1 & byte=0x0f; byte=0xC7; mod=3 & Rmr32 & reg_opcode=7 +:RDSEED Rmr32 is vexMode=0 & opsize=1 & byte=0x0f; byte=0xC7; mod=3 & Rmr32 & check_Rmr32_dest & reg_opcode=7 { Rmr32 = rdseed(); CF=rdseedIsValid(); rdflags(); + build check_Rmr32_dest; } @ifdef IA64 :RDSEED Rmr64 is $(LONGMODE_ON) & vexMode=0 & opsize=2 & $(REX_W) & byte=0x0f; byte=0xC7; mod=3 & Rmr64 & reg_opcode=7 diff --git a/pypcode/processors/x86/data/languages/sgx.sinc b/pypcode/processors/x86/data/languages/sgx.sinc index 9c124e1..54812ed 100644 --- a/pypcode/processors/x86/data/languages/sgx.sinc +++ b/pypcode/processors/x86/data/languages/sgx.sinc @@ -255,3 +255,48 @@ define pcodeop enclu_unknown; } + +define pcodeop enclv_edecvirtchild; +define pcodeop enclv_eincvirtchild; +define pcodeop enclv_esetcontext; +define pcodeop enclv_unknown; + +:ENCLV is vexMode=0 & byte=0x0f; byte=0x01; byte=0xc0 { + + if ( EAX != 0x0 ) goto ; + RAX = enclv_edecvirtchild( RBX, RCX ); + ZF = (RAX != 0); + CF = 0; + PF = 0; + AF = 0; + OF = 0; + SF = 0; + goto ; + + + if ( EAX != 0x1 ) goto ; + RAX = enclv_eincvirtchild( RBX, RCX ); + ZF = (RAX != 0); + CF = 0; + PF = 0; + AF = 0; + OF = 0; + SF = 0; + goto ; + + + if ( EAX != 0x2 ) goto ; + RAX = enclv_esetcontext( RCX, RDX ); + ZF = (RAX != 0); + CF = 0; + PF = 0; + AF = 0; + OF = 0; + SF = 0; + goto ; + + enclv_unknown(); + + + +} diff --git a/pypcode/processors/x86/data/languages/x86-64.slaspec b/pypcode/processors/x86/data/languages/x86-64.slaspec index 8b442ec..a682d8a 100644 --- a/pypcode/processors/x86/data/languages/x86-64.slaspec +++ b/pypcode/processors/x86/data/languages/x86-64.slaspec @@ -3,4 +3,5 @@ with : lockprefx=0 { @include "sgx.sinc" @include "fma.sinc" +@include "cmpccxadd.sinc" } diff --git a/pypcode/processors/x86/data/languages/x86.ldefs b/pypcode/processors/x86/data/languages/x86.ldefs index e39b57b..778d26b 100644 --- a/pypcode/processors/x86/data/languages/x86.ldefs +++ b/pypcode/processors/x86/data/languages/x86.ldefs @@ -5,7 +5,7 @@ endian="little" size="32" variant="default" - version="4.6" + version="4.9" slafile="x86.sla" processorspec="x86.pspec" manualindexfile="../manuals/x86.idx" @@ -37,7 +37,7 @@ endian="little" size="32" variant="System Management Mode" - version="4.6" + version="4.9" slafile="x86.sla" processorspec="x86-16.pspec" manualindexfile="../manuals/x86.idx" @@ -50,7 +50,7 @@ endian="little" size="16" variant="Real Mode" - version="4.6" + version="4.9" slafile="x86.sla" processorspec="x86-16-real.pspec" manualindexfile="../manuals/x86.idx" @@ -70,7 +70,7 @@ endian="little" size="16" variant="Protected Mode" - version="4.6" + version="4.9" slafile="x86.sla" processorspec="x86-16.pspec" manualindexfile="../manuals/x86.idx" @@ -85,7 +85,7 @@ endian="little" size="64" variant="default" - version="4.6" + version="4.9" slafile="x86-64.sla" processorspec="x86-64.pspec" manualindexfile="../manuals/x86.idx" @@ -108,7 +108,7 @@ endian="little" size="64" variant="compat32" - version="4.6" + version="4.9" slafile="x86-64.sla" processorspec="x86-64-compat32.pspec" manualindexfile="../manuals/x86.idx" diff --git a/pypcode/processors/x86/data/languages/x86.slaspec b/pypcode/processors/x86/data/languages/x86.slaspec index 5ec52e5..4f8904a 100644 --- a/pypcode/processors/x86/data/languages/x86.slaspec +++ b/pypcode/processors/x86/data/languages/x86.slaspec @@ -7,6 +7,7 @@ with : lockprefx=0 { @include "avx2_manual.sinc" @include "avx512.sinc" @include "avx512_manual.sinc" +@include "gfni.sinc" @include "adx.sinc" @include "clwb.sinc" @include "pclmulqdq.sinc" @@ -18,4 +19,5 @@ with : lockprefx=0 { @include "smx.sinc" @include "cet.sinc" @include "rdrand.sinc" +@include "rao.sinc" } diff --git a/pypcode/sleigh/Makefile b/pypcode/sleigh/Makefile index 2fbdd47..3b4b7c6 100644 --- a/pypcode/sleigh/Makefile +++ b/pypcode/sleigh/Makefile @@ -411,7 +411,3 @@ reallyclean: clean rm -rf coreext_*.cc coreext_*.hh ghidraext_*.cc ghidraext_*.hh consoleext_*.cc consoleext_*.hh rm -rf com_dbg com_opt test_dbg ghi_dbg ghi_opt sla_dbg sla_opt rm -f $(EXECS) TAGS *~ - -sleigh_src: - mkdir -p sleigh_src - cp $(LIBSLA_SOURCE) Makefile sleigh_src diff --git a/pypcode/sleigh/address.hh b/pypcode/sleigh/address.hh index 510432e..6fdc9a5 100644 --- a/pypcode/sleigh/address.hh +++ b/pypcode/sleigh/address.hh @@ -87,6 +87,7 @@ public: Address operator+(int8 off) const; ///< Increment address by a number of bytes Address operator-(int8 off) const; ///< Decrement address by a number of bytes friend ostream &operator<<(ostream &s,const Address &addr); ///< Write out an address to stream + bool isValidRange(uint8 size) const; ///< Is the range properly contained in its address space bool containedBy(int4 sz,const Address &op2,int4 sz2) const; ///< Determine if \e op2 range contains \b this range int4 justifiedContain(int4 sz,const Address &op2,int4 sz2,bool forceleft) const; ///< Determine if \e op2 is the least significant part of \e this. int4 overlap(int4 skip,const Address &op,int4 size) const; ///< Determine how \b this address falls in a given address range @@ -465,6 +466,14 @@ inline Address Address::operator-(int8 off) const { return Address(base,base->wrapOffset(offset-off)); } +/// If the range starting at \b this address and extending for \b size bytes, encompasses bytes beyond +/// the edge of the address space (or wraps), then return \b false. +/// \param size is the number of bytes in the range (must be non-zero) +/// \return \b true if the range is properly contained in the address space +inline bool Address::isValidRange(uint8 size) const { + return (size-1) <= (base->getHighest() - offset); +} + /// This method is equivalent to Address::overlap, but a range in the \e join space can be /// considered overlapped with its constituent pieces. /// If \e this + \e skip falls in the range, \e op to \e op + \e size, then a non-negative integer is diff --git a/pypcode/sleigh/error.hh b/pypcode/sleigh/error.hh index 4f8e185..855e20b 100644 --- a/pypcode/sleigh/error.hh +++ b/pypcode/sleigh/error.hh @@ -33,6 +33,7 @@ #include #include #include +#include namespace ghidra { @@ -65,6 +66,7 @@ using std::max; using std::to_string; using std::piecewise_construct; using std::forward_as_tuple; +using std::unique_ptr; /// \brief The lowest level error generated by the decompiler diff --git a/pypcode/sleigh/loadimage.cc b/pypcode/sleigh/loadimage.cc index 87bcb5d..5582299 100644 --- a/pypcode/sleigh/loadimage.cc +++ b/pypcode/sleigh/loadimage.cc @@ -4,9 +4,9 @@ * Licensed under the Apache License, Version 2.0 (the "License"); * you may not use this file except in compliance with the License. * You may obtain a copy of the License at - * + * * http://www.apache.org/licenses/LICENSE-2.0 - * + * * Unless required by applicable law or agreed to in writing, software * distributed under the License is distributed on an "AS IS" BASIS, * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. @@ -30,8 +30,6 @@ uint1 *LoadImage::load(int4 size,const Address &addr) { uint1 *buf = new uint1[ size ]; - if (buf == (uint1 *)0) - throw LowlevelError("Out of memory"); loadFill(buf,size,addr); return buf; } @@ -62,6 +60,7 @@ void RawLoadImage::open(void) thefile = new ifstream(filename.c_str()); if (!(*thefile)) { string errmsg = "Unable to open raw image file: "+filename; + delete thefile; throw LowlevelError(errmsg); } thefile->seekg(0,ios::end); diff --git a/pypcode/sleigh/marshal.cc b/pypcode/sleigh/marshal.cc index f1a43d8..66b1562 100644 --- a/pypcode/sleigh/marshal.cc +++ b/pypcode/sleigh/marshal.cc @@ -689,7 +689,10 @@ void PackedDecode::endIngest(int4 bufPos) } uint1 *buf = inStream.back().start; buf[bufPos] = ELEMENT_END; + } else { + throw DecoderError("Ended ingestion without any input"); } + } PackedDecode::~PackedDecode(void) @@ -961,11 +964,10 @@ string PackedDecode::readString(void) attributeRead = true; throw DecoderError("Expecting string attribute"); } - int4 length = readLengthCode(typeByte); - length = readInteger(length); + uint8 length = readInteger(readLengthCode(typeByte)); attributeRead = true; - int4 curLen = curPos.end - curPos.current; + uint8 curLen = curPos.end - curPos.current; if (curLen >= length) { string res((const char *)curPos.current,length); advancePosition(curPos, length); @@ -1002,10 +1004,12 @@ AddrSpace *PackedDecode::readSpace(void) getNextByte(curPos); uint1 typeByte = getNextByte(curPos); uint4 typeCode = typeByte >> TYPECODE_SHIFT; - int4 res; AddrSpace *spc; if (typeCode == TYPECODE_ADDRESSSPACE) { - res = readInteger(readLengthCode(typeByte)); + uint8 res = readInteger(readLengthCode(typeByte)); + if (res >= spcManager->numSpaces()) + throw DecoderError("Invalid address space index"); + spc = spcManager->getSpace(res); if (spc == (AddrSpace *)0) throw DecoderError("Unknown address space index"); diff --git a/pypcode/sleigh/marshal.hh b/pypcode/sleigh/marshal.hh index 3b0ec0e..9817f7b 100644 --- a/pypcode/sleigh/marshal.hh +++ b/pypcode/sleigh/marshal.hh @@ -536,7 +536,7 @@ private: uint1 getByte(Position &pos) { return *pos.current; } ///< Get the byte at the current position, do not advance uint1 getBytePlus1(Position &pos); ///< Get the byte following the current byte, do not advance position uint1 getNextByte(Position &pos); ///< Get the byte at the current position and advance to the next byte - void advancePosition(Position &pos,int4 skip); ///< Advance the position by the given number of bytes + void advancePosition(Position &pos,uint4 skip); ///< Advance the position by the given number of bytes uint8 readInteger(int4 len); ///< Read an integer from the \e current position given its length in bytes uint4 readLengthCode(uint1 typeByte) { return ((uint4)typeByte & PackedFormat::LENGTHCODE_MASK); } ///< Extract length code from type byte void findMatchingAttribute(const AttributeId &attribId); ///< Find attribute matching the given id in open element @@ -631,7 +631,7 @@ inline uint1 PackedDecode::getNextByte(Position &pos) /// An exception is thrown of position is advanced past the end of the stream /// \param pos is the position being advanced /// \param skip is the number of bytes to advance -inline void PackedDecode::advancePosition(Position &pos,int4 skip) +inline void PackedDecode::advancePosition(Position &pos,uint4 skip) { while(pos.end - pos.current <= skip) { diff --git a/pypcode/sleigh/pcodeparse.cc b/pypcode/sleigh/pcodeparse.cc index 61defeb..db00313 100644 --- a/pypcode/sleigh/pcodeparse.cc +++ b/pypcode/sleigh/pcodeparse.cc @@ -1,8 +1,23 @@ -/* A Bison parser, made by GNU Bison 3.8.2. */ +/* ### + * IP: GHIDRA + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +/* A Bison parser, made by GNU Bison 3.5.1. */ /* Bison implementation for Yacc-like parsers in C - Copyright (C) 1984, 1989-1990, 2000-2015, 2018-2021 Free Software Foundation, + Copyright (C) 1984, 1989-1990, 2000-2015, 2018-2020 Free Software Foundation, Inc. This program is free software: you can redistribute it and/or modify @@ -16,7 +31,7 @@ GNU General Public License for more details. You should have received a copy of the GNU General Public License - along with this program. If not, see . */ + along with this program. If not, see . */ /* As a special exception, you may create a larger work that contains part or all of the Bison parser skeleton and distribute that work @@ -34,10 +49,6 @@ /* C LALR(1) parser skeleton written by Richard Stallman, by simplifying the original so-called "semantic" parser. */ -/* DO NOT RELY ON FEATURES THAT ARE NOT DOCUMENTED in the manual, - especially those whose name start with YY_ or yy_. They are - private implementation details that can be changed or removed. */ - /* All symbols defined below should begin with yy or YY, to avoid infringing on user name space. This should be done even for local variables, as they might otherwise be expanded by user macros. @@ -45,11 +56,14 @@ define necessary library symbols; they are noted "INFRINGES ON USER NAME SPACE" below. */ -/* Identify Bison output, and Bison version. */ -#define YYBISON 30802 +/* Undocumented macros, especially those whose name start with YY_, + are private implementation details. Do not rely on them. */ + +/* Identify Bison output. */ +#define YYBISON 1 -/* Bison version string. */ -#define YYBISON_VERSION "3.8.2" +/* Bison version. */ +#define YYBISON_VERSION "3.5.1" /* Skeleton name. */ #define YYSKELETON_NAME "yacc.c" @@ -107,6 +121,14 @@ extern int pcodeerror(const char *str ); # endif # endif +/* Enabling verbose error messages. */ +#ifdef YYERROR_VERBOSE +# undef YYERROR_VERBOSE +# define YYERROR_VERBOSE 1 +#else +# define YYERROR_VERBOSE 0 +#endif + /* Debug traces. */ #ifndef PCODEDEBUG @@ -124,74 +146,69 @@ extern int pcodeerror(const char *str ); extern int pcodedebug; #endif -/* Token kinds. */ +/* Token type. */ #ifndef PCODETOKENTYPE # define PCODETOKENTYPE enum pcodetokentype { - PCODEEMPTY = -2, - PCODEEOF = 0, /* "end of file" */ - PCODEerror = 256, /* error */ - PCODEUNDEF = 257, /* "invalid token" */ - OP_BOOL_OR = 258, /* OP_BOOL_OR */ - OP_BOOL_AND = 259, /* OP_BOOL_AND */ - OP_BOOL_XOR = 260, /* OP_BOOL_XOR */ - OP_EQUAL = 261, /* OP_EQUAL */ - OP_NOTEQUAL = 262, /* OP_NOTEQUAL */ - OP_FEQUAL = 263, /* OP_FEQUAL */ - OP_FNOTEQUAL = 264, /* OP_FNOTEQUAL */ - OP_GREATEQUAL = 265, /* OP_GREATEQUAL */ - OP_LESSEQUAL = 266, /* OP_LESSEQUAL */ - OP_SLESS = 267, /* OP_SLESS */ - OP_SGREATEQUAL = 268, /* OP_SGREATEQUAL */ - OP_SLESSEQUAL = 269, /* OP_SLESSEQUAL */ - OP_SGREAT = 270, /* OP_SGREAT */ - OP_FLESS = 271, /* OP_FLESS */ - OP_FGREAT = 272, /* OP_FGREAT */ - OP_FLESSEQUAL = 273, /* OP_FLESSEQUAL */ - OP_FGREATEQUAL = 274, /* OP_FGREATEQUAL */ - OP_LEFT = 275, /* OP_LEFT */ - OP_RIGHT = 276, /* OP_RIGHT */ - OP_SRIGHT = 277, /* OP_SRIGHT */ - OP_FADD = 278, /* OP_FADD */ - OP_FSUB = 279, /* OP_FSUB */ - OP_SDIV = 280, /* OP_SDIV */ - OP_SREM = 281, /* OP_SREM */ - OP_FMULT = 282, /* OP_FMULT */ - OP_FDIV = 283, /* OP_FDIV */ - OP_ZEXT = 284, /* OP_ZEXT */ - OP_CARRY = 285, /* OP_CARRY */ - OP_BORROW = 286, /* OP_BORROW */ - OP_SEXT = 287, /* OP_SEXT */ - OP_SCARRY = 288, /* OP_SCARRY */ - OP_SBORROW = 289, /* OP_SBORROW */ - OP_NAN = 290, /* OP_NAN */ - OP_ABS = 291, /* OP_ABS */ - OP_SQRT = 292, /* OP_SQRT */ - OP_CEIL = 293, /* OP_CEIL */ - OP_FLOOR = 294, /* OP_FLOOR */ - OP_ROUND = 295, /* OP_ROUND */ - OP_INT2FLOAT = 296, /* OP_INT2FLOAT */ - OP_FLOAT2FLOAT = 297, /* OP_FLOAT2FLOAT */ - OP_TRUNC = 298, /* OP_TRUNC */ - OP_NEW = 299, /* OP_NEW */ - BADINTEGER = 300, /* BADINTEGER */ - GOTO_KEY = 301, /* GOTO_KEY */ - CALL_KEY = 302, /* CALL_KEY */ - RETURN_KEY = 303, /* RETURN_KEY */ - IF_KEY = 304, /* IF_KEY */ - ENDOFSTREAM = 305, /* ENDOFSTREAM */ - LOCAL_KEY = 306, /* LOCAL_KEY */ - INTEGER = 307, /* INTEGER */ - STRING = 308, /* STRING */ - SPACESYM = 309, /* SPACESYM */ - USEROPSYM = 310, /* USEROPSYM */ - VARSYM = 311, /* VARSYM */ - OPERANDSYM = 312, /* OPERANDSYM */ - JUMPSYM = 313, /* JUMPSYM */ - LABELSYM = 314 /* LABELSYM */ + OP_BOOL_OR = 258, + OP_BOOL_AND = 259, + OP_BOOL_XOR = 260, + OP_EQUAL = 261, + OP_NOTEQUAL = 262, + OP_FEQUAL = 263, + OP_FNOTEQUAL = 264, + OP_GREATEQUAL = 265, + OP_LESSEQUAL = 266, + OP_SLESS = 267, + OP_SGREATEQUAL = 268, + OP_SLESSEQUAL = 269, + OP_SGREAT = 270, + OP_FLESS = 271, + OP_FGREAT = 272, + OP_FLESSEQUAL = 273, + OP_FGREATEQUAL = 274, + OP_LEFT = 275, + OP_RIGHT = 276, + OP_SRIGHT = 277, + OP_FADD = 278, + OP_FSUB = 279, + OP_SDIV = 280, + OP_SREM = 281, + OP_FMULT = 282, + OP_FDIV = 283, + OP_ZEXT = 284, + OP_CARRY = 285, + OP_BORROW = 286, + OP_SEXT = 287, + OP_SCARRY = 288, + OP_SBORROW = 289, + OP_NAN = 290, + OP_ABS = 291, + OP_SQRT = 292, + OP_CEIL = 293, + OP_FLOOR = 294, + OP_ROUND = 295, + OP_INT2FLOAT = 296, + OP_FLOAT2FLOAT = 297, + OP_TRUNC = 298, + OP_NEW = 299, + BADINTEGER = 300, + GOTO_KEY = 301, + CALL_KEY = 302, + RETURN_KEY = 303, + IF_KEY = 304, + ENDOFSTREAM = 305, + LOCAL_KEY = 306, + INTEGER = 307, + STRING = 308, + SPACESYM = 309, + USEROPSYM = 310, + VARSYM = 311, + OPERANDSYM = 312, + JUMPSYM = 313, + LABELSYM = 314 }; - typedef enum pcodetokentype pcodetoken_kind_t; #endif /* Value type. */ @@ -225,112 +242,10 @@ typedef union PCODESTYPE PCODESTYPE; extern PCODESTYPE pcodelval; - int pcodeparse (void); -/* Symbol kind. */ -enum yysymbol_kind_t -{ - YYSYMBOL_YYEMPTY = -2, - YYSYMBOL_YYEOF = 0, /* "end of file" */ - YYSYMBOL_YYerror = 1, /* error */ - YYSYMBOL_YYUNDEF = 2, /* "invalid token" */ - YYSYMBOL_OP_BOOL_OR = 3, /* OP_BOOL_OR */ - YYSYMBOL_OP_BOOL_AND = 4, /* OP_BOOL_AND */ - YYSYMBOL_OP_BOOL_XOR = 5, /* OP_BOOL_XOR */ - YYSYMBOL_6_ = 6, /* '|' */ - YYSYMBOL_7_ = 7, /* ';' */ - YYSYMBOL_8_ = 8, /* '^' */ - YYSYMBOL_9_ = 9, /* '&' */ - YYSYMBOL_OP_EQUAL = 10, /* OP_EQUAL */ - YYSYMBOL_OP_NOTEQUAL = 11, /* OP_NOTEQUAL */ - YYSYMBOL_OP_FEQUAL = 12, /* OP_FEQUAL */ - YYSYMBOL_OP_FNOTEQUAL = 13, /* OP_FNOTEQUAL */ - YYSYMBOL_14_ = 14, /* '<' */ - YYSYMBOL_15_ = 15, /* '>' */ - YYSYMBOL_OP_GREATEQUAL = 16, /* OP_GREATEQUAL */ - YYSYMBOL_OP_LESSEQUAL = 17, /* OP_LESSEQUAL */ - YYSYMBOL_OP_SLESS = 18, /* OP_SLESS */ - YYSYMBOL_OP_SGREATEQUAL = 19, /* OP_SGREATEQUAL */ - YYSYMBOL_OP_SLESSEQUAL = 20, /* OP_SLESSEQUAL */ - YYSYMBOL_OP_SGREAT = 21, /* OP_SGREAT */ - YYSYMBOL_OP_FLESS = 22, /* OP_FLESS */ - YYSYMBOL_OP_FGREAT = 23, /* OP_FGREAT */ - YYSYMBOL_OP_FLESSEQUAL = 24, /* OP_FLESSEQUAL */ - YYSYMBOL_OP_FGREATEQUAL = 25, /* OP_FGREATEQUAL */ - YYSYMBOL_OP_LEFT = 26, /* OP_LEFT */ - YYSYMBOL_OP_RIGHT = 27, /* OP_RIGHT */ - YYSYMBOL_OP_SRIGHT = 28, /* OP_SRIGHT */ - YYSYMBOL_29_ = 29, /* '+' */ - YYSYMBOL_30_ = 30, /* '-' */ - YYSYMBOL_OP_FADD = 31, /* OP_FADD */ - YYSYMBOL_OP_FSUB = 32, /* OP_FSUB */ - YYSYMBOL_33_ = 33, /* '*' */ - YYSYMBOL_34_ = 34, /* '/' */ - YYSYMBOL_35_ = 35, /* '%' */ - YYSYMBOL_OP_SDIV = 36, /* OP_SDIV */ - YYSYMBOL_OP_SREM = 37, /* OP_SREM */ - YYSYMBOL_OP_FMULT = 38, /* OP_FMULT */ - YYSYMBOL_OP_FDIV = 39, /* OP_FDIV */ - YYSYMBOL_40_ = 40, /* '!' */ - YYSYMBOL_41_ = 41, /* '~' */ - YYSYMBOL_OP_ZEXT = 42, /* OP_ZEXT */ - YYSYMBOL_OP_CARRY = 43, /* OP_CARRY */ - YYSYMBOL_OP_BORROW = 44, /* OP_BORROW */ - YYSYMBOL_OP_SEXT = 45, /* OP_SEXT */ - YYSYMBOL_OP_SCARRY = 46, /* OP_SCARRY */ - YYSYMBOL_OP_SBORROW = 47, /* OP_SBORROW */ - YYSYMBOL_OP_NAN = 48, /* OP_NAN */ - YYSYMBOL_OP_ABS = 49, /* OP_ABS */ - YYSYMBOL_OP_SQRT = 50, /* OP_SQRT */ - YYSYMBOL_OP_CEIL = 51, /* OP_CEIL */ - YYSYMBOL_OP_FLOOR = 52, /* OP_FLOOR */ - YYSYMBOL_OP_ROUND = 53, /* OP_ROUND */ - YYSYMBOL_OP_INT2FLOAT = 54, /* OP_INT2FLOAT */ - YYSYMBOL_OP_FLOAT2FLOAT = 55, /* OP_FLOAT2FLOAT */ - YYSYMBOL_OP_TRUNC = 56, /* OP_TRUNC */ - YYSYMBOL_OP_NEW = 57, /* OP_NEW */ - YYSYMBOL_BADINTEGER = 58, /* BADINTEGER */ - YYSYMBOL_GOTO_KEY = 59, /* GOTO_KEY */ - YYSYMBOL_CALL_KEY = 60, /* CALL_KEY */ - YYSYMBOL_RETURN_KEY = 61, /* RETURN_KEY */ - YYSYMBOL_IF_KEY = 62, /* IF_KEY */ - YYSYMBOL_ENDOFSTREAM = 63, /* ENDOFSTREAM */ - YYSYMBOL_LOCAL_KEY = 64, /* LOCAL_KEY */ - YYSYMBOL_INTEGER = 65, /* INTEGER */ - YYSYMBOL_STRING = 66, /* STRING */ - YYSYMBOL_SPACESYM = 67, /* SPACESYM */ - YYSYMBOL_USEROPSYM = 68, /* USEROPSYM */ - YYSYMBOL_VARSYM = 69, /* VARSYM */ - YYSYMBOL_OPERANDSYM = 70, /* OPERANDSYM */ - YYSYMBOL_JUMPSYM = 71, /* JUMPSYM */ - YYSYMBOL_LABELSYM = 72, /* LABELSYM */ - YYSYMBOL_73_ = 73, /* ':' */ - YYSYMBOL_74_ = 74, /* '=' */ - YYSYMBOL_75_ = 75, /* '(' */ - YYSYMBOL_76_ = 76, /* ')' */ - YYSYMBOL_77_ = 77, /* '[' */ - YYSYMBOL_78_ = 78, /* ',' */ - YYSYMBOL_79_ = 79, /* ']' */ - YYSYMBOL_YYACCEPT = 80, /* $accept */ - YYSYMBOL_rtl = 81, /* rtl */ - YYSYMBOL_rtlmid = 82, /* rtlmid */ - YYSYMBOL_statement = 83, /* statement */ - YYSYMBOL_expr = 84, /* expr */ - YYSYMBOL_sizedstar = 85, /* sizedstar */ - YYSYMBOL_jumpdest = 86, /* jumpdest */ - YYSYMBOL_varnode = 87, /* varnode */ - YYSYMBOL_integervarnode = 88, /* integervarnode */ - YYSYMBOL_lhsvarnode = 89, /* lhsvarnode */ - YYSYMBOL_label = 90, /* label */ - YYSYMBOL_specificsymbol = 91, /* specificsymbol */ - YYSYMBOL_paramlist = 92 /* paramlist */ -}; -typedef enum yysymbol_kind_t yysymbol_kind_t; - - #ifdef short @@ -370,18 +285,6 @@ typedef int_least16_t yytype_int16; typedef short yytype_int16; #endif -/* Work around bug in HP-UX 11.23, which defines these macros - incorrectly for preprocessor constants. This workaround can likely - be removed in 2023, as HPE has promised support for HP-UX 11.23 - (aka HP-UX 11i v2) only through the end of 2022; see Table 2 of - . */ -#ifdef __hpux -# undef UINT_LEAST8_MAX -# undef UINT_LEAST16_MAX -# define UINT_LEAST8_MAX 255 -# define UINT_LEAST16_MAX 65535 -#endif - #if defined __UINT_LEAST8_MAX__ && __UINT_LEAST8_MAX__ <= __INT_MAX__ typedef __UINT_LEAST8_TYPE__ yytype_uint8; #elif (!defined __UINT_LEAST8_MAX__ && defined YY_STDINT_H \ @@ -441,7 +344,6 @@ typedef int yytype_uint16; #define YYSIZEOF(X) YY_CAST (YYPTRDIFF_T, sizeof (X)) - /* Stored state numbers (used for stacks). */ typedef yytype_int16 yy_state_t; @@ -460,7 +362,6 @@ typedef int yy_state_fast_t; # endif #endif - #ifndef YY_ATTRIBUTE_PURE # if defined __GNUC__ && 2 < __GNUC__ + (96 <= __GNUC_MINOR__) # define YY_ATTRIBUTE_PURE __attribute__ ((__pure__)) @@ -479,23 +380,17 @@ typedef int yy_state_fast_t; /* Suppress unused-variable warnings by "using" E. */ #if ! defined lint || defined __GNUC__ -# define YY_USE(E) ((void) (E)) +# define YYUSE(E) ((void) (E)) #else -# define YY_USE(E) /* empty */ +# define YYUSE(E) /* empty */ #endif +#if defined __GNUC__ && ! defined __ICC && 407 <= __GNUC__ * 100 + __GNUC_MINOR__ /* Suppress an incorrect diagnostic about yylval being uninitialized. */ -#if defined __GNUC__ && ! defined __ICC && 406 <= __GNUC__ * 100 + __GNUC_MINOR__ -# if __GNUC__ * 100 + __GNUC_MINOR__ < 407 -# define YY_IGNORE_MAYBE_UNINITIALIZED_BEGIN \ - _Pragma ("GCC diagnostic push") \ - _Pragma ("GCC diagnostic ignored \"-Wuninitialized\"") -# else -# define YY_IGNORE_MAYBE_UNINITIALIZED_BEGIN \ +# define YY_IGNORE_MAYBE_UNINITIALIZED_BEGIN \ _Pragma ("GCC diagnostic push") \ _Pragma ("GCC diagnostic ignored \"-Wuninitialized\"") \ _Pragma ("GCC diagnostic ignored \"-Wmaybe-uninitialized\"") -# endif # define YY_IGNORE_MAYBE_UNINITIALIZED_END \ _Pragma ("GCC diagnostic pop") #else @@ -524,7 +419,7 @@ typedef int yy_state_fast_t; #define YY_ASSERT(E) ((void) (0 && (E))) -#if !defined yyoverflow +#if ! defined yyoverflow || YYERROR_VERBOSE /* The parser invokes alloca or malloc; define the necessary symbols. */ @@ -589,7 +484,8 @@ void free (void *); /* INFRINGES ON USER NAME SPACE */ # endif # endif # endif -#endif /* !defined yyoverflow */ +#endif /* ! defined yyoverflow || YYERROR_VERBOSE */ + #if (! defined yyoverflow \ && (! defined __cplusplus \ @@ -665,16 +561,14 @@ union yyalloc /* YYNSTATES -- Number of states. */ #define YYNSTATES 294 -/* YYMAXUTOK -- Last valid token kind. */ +#define YYUNDEFTOK 2 #define YYMAXUTOK 314 /* YYTRANSLATE(TOKEN-NUM) -- Symbol number corresponding to TOKEN-NUM as returned by yylex, with out-of-bounds checking. */ -#define YYTRANSLATE(YYX) \ - (0 <= (YYX) && (YYX) <= YYMAXUTOK \ - ? YY_CAST (yysymbol_kind_t, yytranslate[YYX]) \ - : YYSYMBOL_YYUNDEF) +#define YYTRANSLATE(YYX) \ + (0 <= (YYX) && (YYX) <= YYMAXUTOK ? yytranslate[YYX] : YYUNDEFTOK) /* YYTRANSLATE[TOKEN-NUM] -- Symbol number corresponding to TOKEN-NUM as returned by yylex. */ @@ -715,7 +609,7 @@ static const yytype_int8 yytranslate[] = }; #if PCODEDEBUG -/* YYRLINE[YYN] -- Source line where rule number YYN was defined. */ + /* YYRLINE[YYN] -- Source line where rule number YYN was defined. */ static const yytype_uint8 yyrline[] = { 0, 99, 99, 101, 102, 103, 104, 106, 107, 108, @@ -733,42 +627,45 @@ static const yytype_uint8 yyrline[] = }; #endif -/** Accessing symbol of state STATE. */ -#define YY_ACCESSING_SYMBOL(State) YY_CAST (yysymbol_kind_t, yystos[State]) - -#if PCODEDEBUG || 0 -/* The user-facing name of the symbol whose (internal) number is - YYSYMBOL. No bounds checking. */ -static const char *yysymbol_name (yysymbol_kind_t yysymbol) YY_ATTRIBUTE_UNUSED; - +#if PCODEDEBUG || YYERROR_VERBOSE || 0 /* YYTNAME[SYMBOL-NUM] -- String name of the symbol SYMBOL-NUM. First, the terminals, then, starting at YYNTOKENS, nonterminals. */ static const char *const yytname[] = { - "\"end of file\"", "error", "\"invalid token\"", "OP_BOOL_OR", - "OP_BOOL_AND", "OP_BOOL_XOR", "'|'", "';'", "'^'", "'&'", "OP_EQUAL", - "OP_NOTEQUAL", "OP_FEQUAL", "OP_FNOTEQUAL", "'<'", "'>'", - "OP_GREATEQUAL", "OP_LESSEQUAL", "OP_SLESS", "OP_SGREATEQUAL", - "OP_SLESSEQUAL", "OP_SGREAT", "OP_FLESS", "OP_FGREAT", "OP_FLESSEQUAL", - "OP_FGREATEQUAL", "OP_LEFT", "OP_RIGHT", "OP_SRIGHT", "'+'", "'-'", - "OP_FADD", "OP_FSUB", "'*'", "'/'", "'%'", "OP_SDIV", "OP_SREM", - "OP_FMULT", "OP_FDIV", "'!'", "'~'", "OP_ZEXT", "OP_CARRY", "OP_BORROW", - "OP_SEXT", "OP_SCARRY", "OP_SBORROW", "OP_NAN", "OP_ABS", "OP_SQRT", - "OP_CEIL", "OP_FLOOR", "OP_ROUND", "OP_INT2FLOAT", "OP_FLOAT2FLOAT", - "OP_TRUNC", "OP_NEW", "BADINTEGER", "GOTO_KEY", "CALL_KEY", "RETURN_KEY", - "IF_KEY", "ENDOFSTREAM", "LOCAL_KEY", "INTEGER", "STRING", "SPACESYM", - "USEROPSYM", "VARSYM", "OPERANDSYM", "JUMPSYM", "LABELSYM", "':'", "'='", - "'('", "')'", "'['", "','", "']'", "$accept", "rtl", "rtlmid", - "statement", "expr", "sizedstar", "jumpdest", "varnode", - "integervarnode", "lhsvarnode", "label", "specificsymbol", "paramlist", YY_NULLPTR + "$end", "error", "$undefined", "OP_BOOL_OR", "OP_BOOL_AND", + "OP_BOOL_XOR", "'|'", "';'", "'^'", "'&'", "OP_EQUAL", "OP_NOTEQUAL", + "OP_FEQUAL", "OP_FNOTEQUAL", "'<'", "'>'", "OP_GREATEQUAL", + "OP_LESSEQUAL", "OP_SLESS", "OP_SGREATEQUAL", "OP_SLESSEQUAL", + "OP_SGREAT", "OP_FLESS", "OP_FGREAT", "OP_FLESSEQUAL", "OP_FGREATEQUAL", + "OP_LEFT", "OP_RIGHT", "OP_SRIGHT", "'+'", "'-'", "OP_FADD", "OP_FSUB", + "'*'", "'/'", "'%'", "OP_SDIV", "OP_SREM", "OP_FMULT", "OP_FDIV", "'!'", + "'~'", "OP_ZEXT", "OP_CARRY", "OP_BORROW", "OP_SEXT", "OP_SCARRY", + "OP_SBORROW", "OP_NAN", "OP_ABS", "OP_SQRT", "OP_CEIL", "OP_FLOOR", + "OP_ROUND", "OP_INT2FLOAT", "OP_FLOAT2FLOAT", "OP_TRUNC", "OP_NEW", + "BADINTEGER", "GOTO_KEY", "CALL_KEY", "RETURN_KEY", "IF_KEY", + "ENDOFSTREAM", "LOCAL_KEY", "INTEGER", "STRING", "SPACESYM", "USEROPSYM", + "VARSYM", "OPERANDSYM", "JUMPSYM", "LABELSYM", "':'", "'='", "'('", + "')'", "'['", "','", "']'", "$accept", "rtl", "rtlmid", "statement", + "expr", "sizedstar", "jumpdest", "varnode", "integervarnode", + "lhsvarnode", "label", "specificsymbol", "paramlist", YY_NULLPTR }; +#endif -static const char * -yysymbol_name (yysymbol_kind_t yysymbol) +# ifdef YYPRINT +/* YYTOKNUM[NUM] -- (External) token number corresponding to the + (internal) symbol number NUM (which must be that of a token). */ +static const yytype_int16 yytoknum[] = { - return yytname[yysymbol]; -} -#endif + 0, 256, 257, 258, 259, 260, 124, 59, 94, 38, + 261, 262, 263, 264, 60, 62, 265, 266, 267, 268, + 269, 270, 271, 272, 273, 274, 275, 276, 277, 43, + 45, 278, 279, 42, 47, 37, 280, 281, 282, 283, + 33, 126, 284, 285, 286, 287, 288, 289, 290, 291, + 292, 293, 294, 295, 296, 297, 298, 299, 300, 301, + 302, 303, 304, 305, 306, 307, 308, 309, 310, 311, + 312, 313, 314, 58, 61, 40, 41, 91, 44, 93 +}; +# endif #define YYPACT_NINF (-65) @@ -780,8 +677,8 @@ yysymbol_name (yysymbol_kind_t yysymbol) #define yytable_value_is_error(Yyn) \ ((Yyn) == YYTABLE_NINF) -/* YYPACT[STATE-NUM] -- Index in YYTABLE of the portion describing - STATE-NUM. */ + /* YYPACT[STATE-NUM] -- Index in YYTABLE of the portion describing + STATE-NUM. */ static const yytype_int16 yypact[] = { -65, 32, 1720, -65, 308, -45, -23, -65, -6, 416, @@ -816,9 +713,9 @@ static const yytype_int16 yypact[] = -65, 1670, 2068, -65 }; -/* YYDEFACT[STATE-NUM] -- Default reduction number in state STATE-NUM. - Performed when YYTABLE does not specify something else to do. Zero - means the default is an error. */ + /* YYDEFACT[STATE-NUM] -- Default reduction number in state STATE-NUM. + Performed when YYTABLE does not specify something else to do. Zero + means the default is an error. */ static const yytype_int8 yydefact[] = { 3, 0, 0, 1, 0, 0, 92, 103, 0, 0, @@ -853,23 +750,23 @@ static const yytype_int8 yydefact[] = 10, 0, 0, 15 }; -/* YYPGOTO[NTERM-NUM]. */ + /* YYPGOTO[NTERM-NUM]. */ static const yytype_int16 yypgoto[] = { -65, -65, -65, -65, -11, 348, -8, 1, 198, -65, 351, 0, 242 }; -/* YYDEFGOTO[NTERM-NUM]. */ -static const yytype_uint8 yydefgoto[] = + /* YYDEFGOTO[NTERM-NUM]. */ +static const yytype_int16 yydefgoto[] = { - 0, 1, 2, 20, 162, 68, 40, 69, 23, 24, + -1, 1, 2, 20, 162, 68, 40, 69, 23, 24, 41, 70, 163 }; -/* YYTABLE[YYPACT[STATE-NUM]] -- What to do in state STATE-NUM. If - positive, shift that token. If negative, reduce the rule whose - number is the opposite. If YYTABLE_NINF, syntax error. */ + /* YYTABLE[YYPACT[STATE-NUM]] -- What to do in state STATE-NUM. If + positive, shift that token. If negative, reduce the rule whose + number is the opposite. If YYTABLE_NINF, syntax error. */ static const yytype_int16 yytable[] = { 67, 43, 26, 22, 30, 29, 44, 4, 5, 73, @@ -1322,8 +1219,8 @@ static const yytype_int16 yycheck[] = 35, 36, 37, 38, 39 }; -/* YYSTOS[STATE-NUM] -- The symbol kind of the accessing symbol of - state STATE-NUM. */ + /* YYSTOS[STATE-NUM] -- The (internal number of the) accessing + symbol of state STATE-NUM. */ static const yytype_int8 yystos[] = { 0, 81, 82, 0, 9, 14, 33, 58, 59, 60, @@ -1358,7 +1255,7 @@ static const yytype_int8 yystos[] = 7, 74, 84, 7 }; -/* YYR1[RULE-NUM] -- Symbol kind of the left-hand side of rule RULE-NUM. */ + /* YYR1[YYN] -- Symbol number of symbol that rule YYN derives. */ static const yytype_int8 yyr1[] = { 0, 80, 81, 82, 82, 82, 82, 83, 83, 83, @@ -1375,7 +1272,7 @@ static const yytype_int8 yyr1[] = 90, 91, 91, 91, 92, 92, 92 }; -/* YYR2[RULE-NUM] -- Number of symbols on the right-hand side of rule RULE-NUM. */ + /* YYR2[YYN] -- Number of symbols on the right hand side of rule YYN. */ static const yytype_int8 yyr2[] = { 0, 2, 2, 0, 2, 4, 6, 4, 5, 4, @@ -1393,22 +1290,21 @@ static const yytype_int8 yyr2[] = }; -enum { YYENOMEM = -2 }; - #define yyerrok (yyerrstatus = 0) -#define yyclearin (yychar = PCODEEMPTY) +#define yyclearin (yychar = YYEMPTY) +#define YYEMPTY (-2) +#define YYEOF 0 #define YYACCEPT goto yyacceptlab #define YYABORT goto yyabortlab #define YYERROR goto yyerrorlab -#define YYNOMEM goto yyexhaustedlab #define YYRECOVERING() (!!yyerrstatus) #define YYBACKUP(Token, Value) \ do \ - if (yychar == PCODEEMPTY) \ + if (yychar == YYEMPTY) \ { \ yychar = (Token); \ yylval = (Value); \ @@ -1423,9 +1319,10 @@ enum { YYENOMEM = -2 }; } \ while (0) -/* Backward compatibility with an undocumented macro. - Use PCODEerror or PCODEUNDEF. */ -#define YYERRCODE PCODEUNDEF +/* Error token number */ +#define YYTERROR 1 +#define YYERRCODE 256 + /* Enable debugging if requested. */ @@ -1442,16 +1339,19 @@ do { \ YYFPRINTF Args; \ } while (0) +/* This macro is provided for backward compatibility. */ +#ifndef YY_LOCATION_PRINT +# define YY_LOCATION_PRINT(File, Loc) ((void) 0) +#endif - -# define YY_SYMBOL_PRINT(Title, Kind, Value, Location) \ +# define YY_SYMBOL_PRINT(Title, Type, Value, Location) \ do { \ if (yydebug) \ { \ YYFPRINTF (stderr, "%s ", Title); \ yy_symbol_print (stderr, \ - Kind, Value); \ + Type, Value); \ YYFPRINTF (stderr, "\n"); \ } \ } while (0) @@ -1462,15 +1362,18 @@ do { \ `-----------------------------------*/ static void -yy_symbol_value_print (FILE *yyo, - yysymbol_kind_t yykind, YYSTYPE const * const yyvaluep) +yy_symbol_value_print (FILE *yyo, int yytype, YYSTYPE const * const yyvaluep) { FILE *yyoutput = yyo; - YY_USE (yyoutput); + YYUSE (yyoutput); if (!yyvaluep) return; +# ifdef YYPRINT + if (yytype < YYNTOKENS) + YYPRINT (yyo, yytoknum[yytype], *yyvaluep); +# endif YY_IGNORE_MAYBE_UNINITIALIZED_BEGIN - YY_USE (yykind); + YYUSE (yytype); YY_IGNORE_MAYBE_UNINITIALIZED_END } @@ -1480,13 +1383,12 @@ yy_symbol_value_print (FILE *yyo, `---------------------------*/ static void -yy_symbol_print (FILE *yyo, - yysymbol_kind_t yykind, YYSTYPE const * const yyvaluep) +yy_symbol_print (FILE *yyo, int yytype, YYSTYPE const * const yyvaluep) { YYFPRINTF (yyo, "%s %s (", - yykind < YYNTOKENS ? "token" : "nterm", yysymbol_name (yykind)); + yytype < YYNTOKENS ? "token" : "nterm", yytname[yytype]); - yy_symbol_value_print (yyo, yykind, yyvaluep); + yy_symbol_value_print (yyo, yytype, yyvaluep); YYFPRINTF (yyo, ")"); } @@ -1519,8 +1421,7 @@ do { \ `------------------------------------------------*/ static void -yy_reduce_print (yy_state_t *yyssp, YYSTYPE *yyvsp, - int yyrule) +yy_reduce_print (yy_state_t *yyssp, YYSTYPE *yyvsp, int yyrule) { int yylno = yyrline[yyrule]; int yynrhs = yyr2[yyrule]; @@ -1532,8 +1433,9 @@ yy_reduce_print (yy_state_t *yyssp, YYSTYPE *yyvsp, { YYFPRINTF (stderr, " $%d = ", yyi + 1); yy_symbol_print (stderr, - YY_ACCESSING_SYMBOL (+yyssp[yyi + 1 - yynrhs]), - &yyvsp[(yyi + 1) - (yynrhs)]); + yystos[+yyssp[yyi + 1 - yynrhs]], + &yyvsp[(yyi + 1) - (yynrhs)] + ); YYFPRINTF (stderr, "\n"); } } @@ -1548,8 +1450,8 @@ do { \ multiple parsers can coexist. */ int yydebug; #else /* !PCODEDEBUG */ -# define YYDPRINTF(Args) ((void) 0) -# define YY_SYMBOL_PRINT(Title, Kind, Value, Location) +# define YYDPRINTF(Args) +# define YY_SYMBOL_PRINT(Title, Type, Value, Location) # define YY_STACK_PRINT(Bottom, Top) # define YY_REDUCE_PRINT(Rule) #endif /* !PCODEDEBUG */ @@ -1572,67 +1474,294 @@ int yydebug; #endif +#if YYERROR_VERBOSE + +# ifndef yystrlen +# if defined __GLIBC__ && defined _STRING_H +# define yystrlen(S) (YY_CAST (YYPTRDIFF_T, strlen (S))) +# else +/* Return the length of YYSTR. */ +static YYPTRDIFF_T +yystrlen (const char *yystr) +{ + YYPTRDIFF_T yylen; + for (yylen = 0; yystr[yylen]; yylen++) + continue; + return yylen; +} +# endif +# endif + +# ifndef yystpcpy +# if defined __GLIBC__ && defined _STRING_H && defined _GNU_SOURCE +# define yystpcpy stpcpy +# else +/* Copy YYSRC to YYDEST, returning the address of the terminating '\0' in + YYDEST. */ +static char * +yystpcpy (char *yydest, const char *yysrc) +{ + char *yyd = yydest; + const char *yys = yysrc; + + while ((*yyd++ = *yys++) != '\0') + continue; + return yyd - 1; +} +# endif +# endif +# ifndef yytnamerr +/* Copy to YYRES the contents of YYSTR after stripping away unnecessary + quotes and backslashes, so that it's suitable for yyerror. The + heuristic is that double-quoting is unnecessary unless the string + contains an apostrophe, a comma, or backslash (other than + backslash-backslash). YYSTR is taken from yytname. If YYRES is + null, do not copy; instead, return the length of what the result + would have been. */ +static YYPTRDIFF_T +yytnamerr (char *yyres, const char *yystr) +{ + if (*yystr == '"') + { + YYPTRDIFF_T yyn = 0; + char const *yyp = yystr; + + for (;;) + switch (*++yyp) + { + case '\'': + case ',': + goto do_not_strip_quotes; + + case '\\': + if (*++yyp != '\\') + goto do_not_strip_quotes; + else + goto append; + + append: + default: + if (yyres) + yyres[yyn] = *yyp; + yyn++; + break; + + case '"': + if (yyres) + yyres[yyn] = '\0'; + return yyn; + } + do_not_strip_quotes: ; + } + if (yyres) + return yystpcpy (yyres, yystr) - yyres; + else + return yystrlen (yystr); +} +# endif + +/* Copy into *YYMSG, which is of size *YYMSG_ALLOC, an error message + about the unexpected token YYTOKEN for the state stack whose top is + YYSSP. + + Return 0 if *YYMSG was successfully written. Return 1 if *YYMSG is + not large enough to hold the message. In that case, also set + *YYMSG_ALLOC to the required number of bytes. Return 2 if the + required number of bytes is too large to store. */ +static int +yysyntax_error (YYPTRDIFF_T *yymsg_alloc, char **yymsg, + yy_state_t *yyssp, int yytoken) +{ + enum { YYERROR_VERBOSE_ARGS_MAXIMUM = 5 }; + /* Internationalized format string. */ + const char *yyformat = YY_NULLPTR; + /* Arguments of yyformat: reported tokens (one for the "unexpected", + one per "expected"). */ + char const *yyarg[YYERROR_VERBOSE_ARGS_MAXIMUM]; + /* Actual size of YYARG. */ + int yycount = 0; + /* Cumulated lengths of YYARG. */ + YYPTRDIFF_T yysize = 0; + + /* There are many possibilities here to consider: + - If this state is a consistent state with a default action, then + the only way this function was invoked is if the default action + is an error action. In that case, don't check for expected + tokens because there are none. + - The only way there can be no lookahead present (in yychar) is if + this state is a consistent state with a default action. Thus, + detecting the absence of a lookahead is sufficient to determine + that there is no unexpected or expected token to report. In that + case, just report a simple "syntax error". + - Don't assume there isn't a lookahead just because this state is a + consistent state with a default action. There might have been a + previous inconsistent state, consistent state with a non-default + action, or user semantic action that manipulated yychar. + - Of course, the expected token list depends on states to have + correct lookahead information, and it depends on the parser not + to perform extra reductions after fetching a lookahead from the + scanner and before detecting a syntax error. Thus, state merging + (from LALR or IELR) and default reductions corrupt the expected + token list. However, the list is correct for canonical LR with + one exception: it will still contain any token that will not be + accepted due to an error action in a later state. + */ + if (yytoken != YYEMPTY) + { + int yyn = yypact[+*yyssp]; + YYPTRDIFF_T yysize0 = yytnamerr (YY_NULLPTR, yytname[yytoken]); + yysize = yysize0; + yyarg[yycount++] = yytname[yytoken]; + if (!yypact_value_is_default (yyn)) + { + /* Start YYX at -YYN if negative to avoid negative indexes in + YYCHECK. In other words, skip the first -YYN actions for + this state because they are default actions. */ + int yyxbegin = yyn < 0 ? -yyn : 0; + /* Stay within bounds of both yycheck and yytname. */ + int yychecklim = YYLAST - yyn + 1; + int yyxend = yychecklim < YYNTOKENS ? yychecklim : YYNTOKENS; + int yyx; + + for (yyx = yyxbegin; yyx < yyxend; ++yyx) + if (yycheck[yyx + yyn] == yyx && yyx != YYTERROR + && !yytable_value_is_error (yytable[yyx + yyn])) + { + if (yycount == YYERROR_VERBOSE_ARGS_MAXIMUM) + { + yycount = 1; + yysize = yysize0; + break; + } + yyarg[yycount++] = yytname[yyx]; + { + YYPTRDIFF_T yysize1 + = yysize + yytnamerr (YY_NULLPTR, yytname[yyx]); + if (yysize <= yysize1 && yysize1 <= YYSTACK_ALLOC_MAXIMUM) + yysize = yysize1; + else + return 2; + } + } + } + } + + switch (yycount) + { +# define YYCASE_(N, S) \ + case N: \ + yyformat = S; \ + break + default: /* Avoid compiler warnings. */ + YYCASE_(0, YY_("syntax error")); + YYCASE_(1, YY_("syntax error, unexpected %s")); + YYCASE_(2, YY_("syntax error, unexpected %s, expecting %s")); + YYCASE_(3, YY_("syntax error, unexpected %s, expecting %s or %s")); + YYCASE_(4, YY_("syntax error, unexpected %s, expecting %s or %s or %s")); + YYCASE_(5, YY_("syntax error, unexpected %s, expecting %s or %s or %s or %s")); +# undef YYCASE_ + } + + { + /* Don't count the "%s"s in the final size, but reserve room for + the terminator. */ + YYPTRDIFF_T yysize1 = yysize + (yystrlen (yyformat) - 2 * yycount) + 1; + if (yysize <= yysize1 && yysize1 <= YYSTACK_ALLOC_MAXIMUM) + yysize = yysize1; + else + return 2; + } + + if (*yymsg_alloc < yysize) + { + *yymsg_alloc = 2 * yysize; + if (! (yysize <= *yymsg_alloc + && *yymsg_alloc <= YYSTACK_ALLOC_MAXIMUM)) + *yymsg_alloc = YYSTACK_ALLOC_MAXIMUM; + return 1; + } + + /* Avoid sprintf, as that infringes on the user's name space. + Don't have undefined behavior even if the translation + produced a string with the wrong number of "%s"s. */ + { + char *yyp = *yymsg; + int yyi = 0; + while ((*yyp = *yyformat) != '\0') + if (*yyp == '%' && yyformat[1] == 's' && yyi < yycount) + { + yyp += yytnamerr (yyp, yyarg[yyi++]); + yyformat += 2; + } + else + { + ++yyp; + ++yyformat; + } + } + return 0; +} +#endif /* YYERROR_VERBOSE */ /*-----------------------------------------------. | Release the memory associated to this symbol. | `-----------------------------------------------*/ static void -yydestruct (const char *yymsg, - yysymbol_kind_t yykind, YYSTYPE *yyvaluep) +yydestruct (const char *yymsg, int yytype, YYSTYPE *yyvaluep) { - YY_USE (yyvaluep); + YYUSE (yyvaluep); if (!yymsg) yymsg = "Deleting"; - YY_SYMBOL_PRINT (yymsg, yykind, yyvaluep, yylocationp); + YY_SYMBOL_PRINT (yymsg, yytype, yyvaluep, yylocationp); YY_IGNORE_MAYBE_UNINITIALIZED_BEGIN - switch (yykind) + switch (yytype) { - case YYSYMBOL_INTEGER: /* INTEGER */ + case 65: /* INTEGER */ { delete ((*yyvaluep).i); } break; - case YYSYMBOL_STRING: /* STRING */ + case 66: /* STRING */ { delete ((*yyvaluep).str); } break; - case YYSYMBOL_rtlmid: /* rtlmid */ + case 82: /* rtlmid */ { delete ((*yyvaluep).sem); } break; - case YYSYMBOL_statement: /* statement */ + case 83: /* statement */ { if (((*yyvaluep).stmt) != (vector *)0) { for(int4 i=0;i<((*yyvaluep).stmt)->size();++i) delete (*((*yyvaluep).stmt))[i]; delete ((*yyvaluep).stmt);} } break; - case YYSYMBOL_expr: /* expr */ + case 84: /* expr */ { delete ((*yyvaluep).tree); } break; - case YYSYMBOL_sizedstar: /* sizedstar */ + case 85: /* sizedstar */ { delete ((*yyvaluep).starqual); } break; - case YYSYMBOL_jumpdest: /* jumpdest */ + case 86: /* jumpdest */ { if (((*yyvaluep).varnode) != (VarnodeTpl *)0) delete ((*yyvaluep).varnode); } break; - case YYSYMBOL_varnode: /* varnode */ + case 87: /* varnode */ { if (((*yyvaluep).varnode) != (VarnodeTpl *)0) delete ((*yyvaluep).varnode); } break; - case YYSYMBOL_integervarnode: /* integervarnode */ + case 88: /* integervarnode */ { if (((*yyvaluep).varnode) != (VarnodeTpl *)0) delete ((*yyvaluep).varnode); } break; - case YYSYMBOL_lhsvarnode: /* lhsvarnode */ + case 89: /* lhsvarnode */ { if (((*yyvaluep).varnode) != (VarnodeTpl *)0) delete ((*yyvaluep).varnode); } break; - case YYSYMBOL_paramlist: /* paramlist */ + case 92: /* paramlist */ { for(int4 i=0;i<((*yyvaluep).param)->size();++i) delete (*((*yyvaluep).param))[i]; delete ((*yyvaluep).param); } break; @@ -1643,7 +1772,9 @@ yydestruct (const char *yymsg, } -/* Lookahead token kind. */ + + +/* The lookahead symbol. */ int yychar; /* The semantic value of the lookahead symbol. */ @@ -1652,8 +1783,6 @@ YYSTYPE yylval; int yynerrs; - - /*----------. | yyparse. | `----------*/ @@ -1661,36 +1790,43 @@ int yynerrs; int yyparse (void) { - yy_state_fast_t yystate = 0; + yy_state_fast_t yystate; /* Number of tokens to shift before error messages enabled. */ - int yyerrstatus = 0; + int yyerrstatus; - /* Refer to the stacks through separate pointers, to allow yyoverflow - to reallocate them elsewhere. */ + /* The stacks and their tools: + 'yyss': related to states. + 'yyvs': related to semantic values. - /* Their size. */ - YYPTRDIFF_T yystacksize = YYINITDEPTH; + Refer to the stacks through separate pointers, to allow yyoverflow + to reallocate them elsewhere. */ - /* The state stack: array, bottom, top. */ + /* The state stack. */ yy_state_t yyssa[YYINITDEPTH]; - yy_state_t *yyss = yyssa; - yy_state_t *yyssp = yyss; + yy_state_t *yyss; + yy_state_t *yyssp; - /* The semantic value stack: array, bottom, top. */ + /* The semantic value stack. */ YYSTYPE yyvsa[YYINITDEPTH]; - YYSTYPE *yyvs = yyvsa; - YYSTYPE *yyvsp = yyvs; + YYSTYPE *yyvs; + YYSTYPE *yyvsp; + + YYPTRDIFF_T yystacksize; int yyn; - /* The return value of yyparse. */ int yyresult; - /* Lookahead symbol kind. */ - yysymbol_kind_t yytoken = YYSYMBOL_YYEMPTY; + /* Lookahead token as an internal (translated) token number. */ + int yytoken = 0; /* The variables used to return semantic value and location from the action routines. */ YYSTYPE yyval; - +#if YYERROR_VERBOSE + /* Buffer for error messages, and its allocated size. */ + char yymsgbuf[128]; + char *yymsg = yymsgbuf; + YYPTRDIFF_T yymsg_alloc = sizeof yymsgbuf; +#endif #define YYPOPSTACK(N) (yyvsp -= (N), yyssp -= (N)) @@ -1698,10 +1834,16 @@ yyparse (void) Keep to zero when no symbol should be popped. */ int yylen = 0; - YYDPRINTF ((stderr, "Starting parse\n")); + yyssp = yyss = yyssa; + yyvsp = yyvs = yyvsa; + yystacksize = YYINITDEPTH; - yychar = PCODEEMPTY; /* Cause a token to be read. */ + YYDPRINTF ((stderr, "Starting parse\n")); + yystate = 0; + yyerrstatus = 0; + yynerrs = 0; + yychar = YYEMPTY; /* Cause a token to be read. */ goto yysetstate; @@ -1723,11 +1865,10 @@ yyparse (void) YY_IGNORE_USELESS_CAST_BEGIN *yyssp = YY_CAST (yy_state_t, yystate); YY_IGNORE_USELESS_CAST_END - YY_STACK_PRINT (yyss, yyssp); if (yyss + yystacksize - 1 <= yyssp) #if !defined yyoverflow && !defined YYSTACK_RELOCATE - YYNOMEM; + goto yyexhaustedlab; #else { /* Get the current used size of the three stacks, in elements. */ @@ -1755,7 +1896,7 @@ yyparse (void) # else /* defined YYSTACK_RELOCATE */ /* Extend the stack our own way. */ if (YYMAXDEPTH <= yystacksize) - YYNOMEM; + goto yyexhaustedlab; yystacksize *= 2; if (YYMAXDEPTH < yystacksize) yystacksize = YYMAXDEPTH; @@ -1766,10 +1907,10 @@ yyparse (void) YY_CAST (union yyalloc *, YYSTACK_ALLOC (YY_CAST (YYSIZE_T, YYSTACK_BYTES (yystacksize)))); if (! yyptr) - YYNOMEM; + goto yyexhaustedlab; YYSTACK_RELOCATE (yyss_alloc, yyss); YYSTACK_RELOCATE (yyvs_alloc, yyvs); -# undef YYSTACK_RELOCATE +# undef YYSTACK_RELOCATE if (yyss1 != yyssa) YYSTACK_FREE (yyss1); } @@ -1788,7 +1929,6 @@ yyparse (void) } #endif /* !defined yyoverflow && !defined YYSTACK_RELOCATE */ - if (yystate == YYFINAL) YYACCEPT; @@ -1809,29 +1949,18 @@ yyparse (void) /* Not known => get a lookahead token if don't already have one. */ - /* YYCHAR is either empty, or end-of-input, or a valid lookahead. */ - if (yychar == PCODEEMPTY) + /* YYCHAR is either YYEMPTY or YYEOF or a valid lookahead symbol. */ + if (yychar == YYEMPTY) { - YYDPRINTF ((stderr, "Reading a token\n")); + YYDPRINTF ((stderr, "Reading a token: ")); yychar = yylex (); } - if (yychar <= PCODEEOF) + if (yychar <= YYEOF) { - yychar = PCODEEOF; - yytoken = YYSYMBOL_YYEOF; + yychar = yytoken = YYEOF; YYDPRINTF ((stderr, "Now at end of input.\n")); } - else if (yychar == PCODEerror) - { - /* The scanner already issued an error message, process directly - to error recovery. But do not keep the error token as - lookahead, it is too special and may lead us to an endless - loop in error recovery. */ - yychar = PCODEUNDEF; - yytoken = YYSYMBOL_YYerror; - goto yyerrlab1; - } else { yytoken = YYTRANSLATE (yychar); @@ -1865,7 +1994,7 @@ yyparse (void) YY_IGNORE_MAYBE_UNINITIALIZED_END /* Discard the shifted token. */ - yychar = PCODEEMPTY; + yychar = YYEMPTY; goto yynewstate; @@ -1900,463 +2029,463 @@ yyparse (void) YY_REDUCE_PRINT (yyn); switch (yyn) { - case 2: /* rtl: rtlmid ENDOFSTREAM */ + case 2: { pcode->setResult((yyvsp[-1].sem)); } break; - case 3: /* rtlmid: %empty */ + case 3: { (yyval.sem) = new ConstructTpl(); } break; - case 4: /* rtlmid: rtlmid statement */ + case 4: { (yyval.sem) = (yyvsp[-1].sem); if (!(yyval.sem)->addOpList(*(yyvsp[0].stmt))) { delete (yyvsp[0].stmt); yyerror("Multiple delayslot declarations"); YYERROR; } delete (yyvsp[0].stmt); } break; - case 5: /* rtlmid: rtlmid LOCAL_KEY STRING ';' */ + case 5: { (yyval.sem) = (yyvsp[-3].sem); pcode->newLocalDefinition((yyvsp[-1].str)); } break; - case 6: /* rtlmid: rtlmid LOCAL_KEY STRING ':' INTEGER ';' */ + case 6: { (yyval.sem) = (yyvsp[-5].sem); pcode->newLocalDefinition((yyvsp[-3].str),*(yyvsp[-1].i)); delete (yyvsp[-1].i); } break; - case 7: /* statement: lhsvarnode '=' expr ';' */ + case 7: { (yyvsp[-1].tree)->setOutput((yyvsp[-3].varnode)); (yyval.stmt) = ExprTree::toVector((yyvsp[-1].tree)); } break; - case 8: /* statement: LOCAL_KEY STRING '=' expr ';' */ + case 8: { (yyval.stmt) = pcode->newOutput(true,(yyvsp[-1].tree),(yyvsp[-3].str)); } break; - case 9: /* statement: STRING '=' expr ';' */ + case 9: { (yyval.stmt) = pcode->newOutput(false,(yyvsp[-1].tree),(yyvsp[-3].str)); } break; - case 10: /* statement: LOCAL_KEY STRING ':' INTEGER '=' expr ';' */ + case 10: { (yyval.stmt) = pcode->newOutput(true,(yyvsp[-1].tree),(yyvsp[-5].str),*(yyvsp[-3].i)); delete (yyvsp[-3].i); } break; - case 11: /* statement: STRING ':' INTEGER '=' expr ';' */ + case 11: { (yyval.stmt) = pcode->newOutput(true,(yyvsp[-1].tree),(yyvsp[-5].str),*(yyvsp[-3].i)); delete (yyvsp[-3].i); } break; - case 12: /* statement: LOCAL_KEY specificsymbol '=' */ + case 12: { (yyval.stmt) = (vector *)0; string errmsg = "Redefinition of symbol: "+(yyvsp[-1].specsym)->getName(); yyerror(errmsg.c_str()); YYERROR; } break; - case 13: /* statement: sizedstar expr '=' expr ';' */ + case 13: { (yyval.stmt) = pcode->createStore((yyvsp[-4].starqual),(yyvsp[-3].tree),(yyvsp[-1].tree)); } break; - case 14: /* statement: USEROPSYM '(' paramlist ')' ';' */ + case 14: { (yyval.stmt) = pcode->createUserOpNoOut((yyvsp[-4].useropsym),(yyvsp[-2].param)); } break; - case 15: /* statement: lhsvarnode '[' INTEGER ',' INTEGER ']' '=' expr ';' */ + case 15: { (yyval.stmt) = pcode->assignBitRange((yyvsp[-8].varnode),(uint4)*(yyvsp[-6].i),(uint4)*(yyvsp[-4].i),(yyvsp[-1].tree)); delete (yyvsp[-6].i), delete (yyvsp[-4].i); } break; - case 16: /* statement: varnode ':' INTEGER '=' */ + case 16: { (yyval.stmt) = (vector *)0; delete (yyvsp[-3].varnode); delete (yyvsp[-1].i); yyerror("Illegal truncation on left-hand side of assignment"); YYERROR; } break; - case 17: /* statement: varnode '(' INTEGER ')' */ + case 17: { (yyval.stmt) = (vector *)0; delete (yyvsp[-3].varnode); delete (yyvsp[-1].i); yyerror("Illegal subpiece on left-hand side of assignment"); YYERROR; } break; - case 18: /* statement: GOTO_KEY jumpdest ';' */ + case 18: { (yyval.stmt) = pcode->createOpNoOut(CPUI_BRANCH,new ExprTree((yyvsp[-1].varnode))); } break; - case 19: /* statement: IF_KEY expr GOTO_KEY jumpdest ';' */ + case 19: { (yyval.stmt) = pcode->createOpNoOut(CPUI_CBRANCH,new ExprTree((yyvsp[-1].varnode)),(yyvsp[-3].tree)); } break; - case 20: /* statement: GOTO_KEY '[' expr ']' ';' */ + case 20: { (yyval.stmt) = pcode->createOpNoOut(CPUI_BRANCHIND,(yyvsp[-2].tree)); } break; - case 21: /* statement: CALL_KEY jumpdest ';' */ + case 21: { (yyval.stmt) = pcode->createOpNoOut(CPUI_CALL,new ExprTree((yyvsp[-1].varnode))); } break; - case 22: /* statement: CALL_KEY '[' expr ']' ';' */ + case 22: { (yyval.stmt) = pcode->createOpNoOut(CPUI_CALLIND,(yyvsp[-2].tree)); } break; - case 23: /* statement: RETURN_KEY ';' */ + case 23: { (yyval.stmt) = (vector *)0; yyerror("Must specify an indirect parameter for return"); YYERROR; } break; - case 24: /* statement: RETURN_KEY '[' expr ']' ';' */ + case 24: { (yyval.stmt) = pcode->createOpNoOut(CPUI_RETURN,(yyvsp[-2].tree)); } break; - case 25: /* statement: label */ + case 25: { (yyval.stmt) = pcode->placeLabel( (yyvsp[0].labelsym) ); } break; - case 26: /* expr: varnode */ + case 26: { (yyval.tree) = new ExprTree((yyvsp[0].varnode)); } break; - case 27: /* expr: sizedstar expr */ + case 27: { (yyval.tree) = pcode->createLoad((yyvsp[-1].starqual),(yyvsp[0].tree)); } break; - case 28: /* expr: '(' expr ')' */ + case 28: { (yyval.tree) = (yyvsp[-1].tree); } break; - case 29: /* expr: expr '+' expr */ + case 29: { (yyval.tree) = pcode->createOp(CPUI_INT_ADD,(yyvsp[-2].tree),(yyvsp[0].tree)); } break; - case 30: /* expr: expr '-' expr */ + case 30: { (yyval.tree) = pcode->createOp(CPUI_INT_SUB,(yyvsp[-2].tree),(yyvsp[0].tree)); } break; - case 31: /* expr: expr OP_EQUAL expr */ + case 31: { (yyval.tree) = pcode->createOp(CPUI_INT_EQUAL,(yyvsp[-2].tree),(yyvsp[0].tree)); } break; - case 32: /* expr: expr OP_NOTEQUAL expr */ + case 32: { (yyval.tree) = pcode->createOp(CPUI_INT_NOTEQUAL,(yyvsp[-2].tree),(yyvsp[0].tree)); } break; - case 33: /* expr: expr '<' expr */ + case 33: { (yyval.tree) = pcode->createOp(CPUI_INT_LESS,(yyvsp[-2].tree),(yyvsp[0].tree)); } break; - case 34: /* expr: expr OP_GREATEQUAL expr */ + case 34: { (yyval.tree) = pcode->createOp(CPUI_INT_LESSEQUAL,(yyvsp[0].tree),(yyvsp[-2].tree)); } break; - case 35: /* expr: expr OP_LESSEQUAL expr */ + case 35: { (yyval.tree) = pcode->createOp(CPUI_INT_LESSEQUAL,(yyvsp[-2].tree),(yyvsp[0].tree)); } break; - case 36: /* expr: expr '>' expr */ + case 36: { (yyval.tree) = pcode->createOp(CPUI_INT_LESS,(yyvsp[0].tree),(yyvsp[-2].tree)); } break; - case 37: /* expr: expr OP_SLESS expr */ + case 37: { (yyval.tree) = pcode->createOp(CPUI_INT_SLESS,(yyvsp[-2].tree),(yyvsp[0].tree)); } break; - case 38: /* expr: expr OP_SGREATEQUAL expr */ + case 38: { (yyval.tree) = pcode->createOp(CPUI_INT_SLESSEQUAL,(yyvsp[0].tree),(yyvsp[-2].tree)); } break; - case 39: /* expr: expr OP_SLESSEQUAL expr */ + case 39: { (yyval.tree) = pcode->createOp(CPUI_INT_SLESSEQUAL,(yyvsp[-2].tree),(yyvsp[0].tree)); } break; - case 40: /* expr: expr OP_SGREAT expr */ + case 40: { (yyval.tree) = pcode->createOp(CPUI_INT_SLESS,(yyvsp[0].tree),(yyvsp[-2].tree)); } break; - case 41: /* expr: '-' expr */ + case 41: { (yyval.tree) = pcode->createOp(CPUI_INT_2COMP,(yyvsp[0].tree)); } break; - case 42: /* expr: '~' expr */ + case 42: { (yyval.tree) = pcode->createOp(CPUI_INT_NEGATE,(yyvsp[0].tree)); } break; - case 43: /* expr: expr '^' expr */ + case 43: { (yyval.tree) = pcode->createOp(CPUI_INT_XOR,(yyvsp[-2].tree),(yyvsp[0].tree)); } break; - case 44: /* expr: expr '&' expr */ + case 44: { (yyval.tree) = pcode->createOp(CPUI_INT_AND,(yyvsp[-2].tree),(yyvsp[0].tree)); } break; - case 45: /* expr: expr '|' expr */ + case 45: { (yyval.tree) = pcode->createOp(CPUI_INT_OR,(yyvsp[-2].tree),(yyvsp[0].tree)); } break; - case 46: /* expr: expr OP_LEFT expr */ + case 46: { (yyval.tree) = pcode->createOp(CPUI_INT_LEFT,(yyvsp[-2].tree),(yyvsp[0].tree)); } break; - case 47: /* expr: expr OP_RIGHT expr */ + case 47: { (yyval.tree) = pcode->createOp(CPUI_INT_RIGHT,(yyvsp[-2].tree),(yyvsp[0].tree)); } break; - case 48: /* expr: expr OP_SRIGHT expr */ + case 48: { (yyval.tree) = pcode->createOp(CPUI_INT_SRIGHT,(yyvsp[-2].tree),(yyvsp[0].tree)); } break; - case 49: /* expr: expr '*' expr */ + case 49: { (yyval.tree) = pcode->createOp(CPUI_INT_MULT,(yyvsp[-2].tree),(yyvsp[0].tree)); } break; - case 50: /* expr: expr '/' expr */ + case 50: { (yyval.tree) = pcode->createOp(CPUI_INT_DIV,(yyvsp[-2].tree),(yyvsp[0].tree)); } break; - case 51: /* expr: expr OP_SDIV expr */ + case 51: { (yyval.tree) = pcode->createOp(CPUI_INT_SDIV,(yyvsp[-2].tree),(yyvsp[0].tree)); } break; - case 52: /* expr: expr '%' expr */ + case 52: { (yyval.tree) = pcode->createOp(CPUI_INT_REM,(yyvsp[-2].tree),(yyvsp[0].tree)); } break; - case 53: /* expr: expr OP_SREM expr */ + case 53: { (yyval.tree) = pcode->createOp(CPUI_INT_SREM,(yyvsp[-2].tree),(yyvsp[0].tree)); } break; - case 54: /* expr: '!' expr */ + case 54: { (yyval.tree) = pcode->createOp(CPUI_BOOL_NEGATE,(yyvsp[0].tree)); } break; - case 55: /* expr: expr OP_BOOL_XOR expr */ + case 55: { (yyval.tree) = pcode->createOp(CPUI_BOOL_XOR,(yyvsp[-2].tree),(yyvsp[0].tree)); } break; - case 56: /* expr: expr OP_BOOL_AND expr */ + case 56: { (yyval.tree) = pcode->createOp(CPUI_BOOL_AND,(yyvsp[-2].tree),(yyvsp[0].tree)); } break; - case 57: /* expr: expr OP_BOOL_OR expr */ + case 57: { (yyval.tree) = pcode->createOp(CPUI_BOOL_OR,(yyvsp[-2].tree),(yyvsp[0].tree)); } break; - case 58: /* expr: expr OP_FEQUAL expr */ + case 58: { (yyval.tree) = pcode->createOp(CPUI_FLOAT_EQUAL,(yyvsp[-2].tree),(yyvsp[0].tree)); } break; - case 59: /* expr: expr OP_FNOTEQUAL expr */ + case 59: { (yyval.tree) = pcode->createOp(CPUI_FLOAT_NOTEQUAL,(yyvsp[-2].tree),(yyvsp[0].tree)); } break; - case 60: /* expr: expr OP_FLESS expr */ + case 60: { (yyval.tree) = pcode->createOp(CPUI_FLOAT_LESS,(yyvsp[-2].tree),(yyvsp[0].tree)); } break; - case 61: /* expr: expr OP_FGREAT expr */ + case 61: { (yyval.tree) = pcode->createOp(CPUI_FLOAT_LESS,(yyvsp[0].tree),(yyvsp[-2].tree)); } break; - case 62: /* expr: expr OP_FLESSEQUAL expr */ + case 62: { (yyval.tree) = pcode->createOp(CPUI_FLOAT_LESSEQUAL,(yyvsp[-2].tree),(yyvsp[0].tree)); } break; - case 63: /* expr: expr OP_FGREATEQUAL expr */ + case 63: { (yyval.tree) = pcode->createOp(CPUI_FLOAT_LESSEQUAL,(yyvsp[0].tree),(yyvsp[-2].tree)); } break; - case 64: /* expr: expr OP_FADD expr */ + case 64: { (yyval.tree) = pcode->createOp(CPUI_FLOAT_ADD,(yyvsp[-2].tree),(yyvsp[0].tree)); } break; - case 65: /* expr: expr OP_FSUB expr */ + case 65: { (yyval.tree) = pcode->createOp(CPUI_FLOAT_SUB,(yyvsp[-2].tree),(yyvsp[0].tree)); } break; - case 66: /* expr: expr OP_FMULT expr */ + case 66: { (yyval.tree) = pcode->createOp(CPUI_FLOAT_MULT,(yyvsp[-2].tree),(yyvsp[0].tree)); } break; - case 67: /* expr: expr OP_FDIV expr */ + case 67: { (yyval.tree) = pcode->createOp(CPUI_FLOAT_DIV,(yyvsp[-2].tree),(yyvsp[0].tree)); } break; - case 68: /* expr: OP_FSUB expr */ + case 68: { (yyval.tree) = pcode->createOp(CPUI_FLOAT_NEG,(yyvsp[0].tree)); } break; - case 69: /* expr: OP_ABS '(' expr ')' */ + case 69: { (yyval.tree) = pcode->createOp(CPUI_FLOAT_ABS,(yyvsp[-1].tree)); } break; - case 70: /* expr: OP_SQRT '(' expr ')' */ + case 70: { (yyval.tree) = pcode->createOp(CPUI_FLOAT_SQRT,(yyvsp[-1].tree)); } break; - case 71: /* expr: OP_SEXT '(' expr ')' */ + case 71: { (yyval.tree) = pcode->createOp(CPUI_INT_SEXT,(yyvsp[-1].tree)); } break; - case 72: /* expr: OP_ZEXT '(' expr ')' */ + case 72: { (yyval.tree) = pcode->createOp(CPUI_INT_ZEXT,(yyvsp[-1].tree)); } break; - case 73: /* expr: OP_CARRY '(' expr ',' expr ')' */ + case 73: { (yyval.tree) = pcode->createOp(CPUI_INT_CARRY,(yyvsp[-3].tree),(yyvsp[-1].tree)); } break; - case 74: /* expr: OP_SCARRY '(' expr ',' expr ')' */ + case 74: { (yyval.tree) = pcode->createOp(CPUI_INT_SCARRY,(yyvsp[-3].tree),(yyvsp[-1].tree)); } break; - case 75: /* expr: OP_SBORROW '(' expr ',' expr ')' */ + case 75: { (yyval.tree) = pcode->createOp(CPUI_INT_SBORROW,(yyvsp[-3].tree),(yyvsp[-1].tree)); } break; - case 76: /* expr: OP_FLOAT2FLOAT '(' expr ')' */ + case 76: { (yyval.tree) = pcode->createOp(CPUI_FLOAT_FLOAT2FLOAT,(yyvsp[-1].tree)); } break; - case 77: /* expr: OP_INT2FLOAT '(' expr ')' */ + case 77: { (yyval.tree) = pcode->createOp(CPUI_FLOAT_INT2FLOAT,(yyvsp[-1].tree)); } break; - case 78: /* expr: OP_NAN '(' expr ')' */ + case 78: { (yyval.tree) = pcode->createOp(CPUI_FLOAT_NAN,(yyvsp[-1].tree)); } break; - case 79: /* expr: OP_TRUNC '(' expr ')' */ + case 79: { (yyval.tree) = pcode->createOp(CPUI_FLOAT_TRUNC,(yyvsp[-1].tree)); } break; - case 80: /* expr: OP_CEIL '(' expr ')' */ + case 80: { (yyval.tree) = pcode->createOp(CPUI_FLOAT_CEIL,(yyvsp[-1].tree)); } break; - case 81: /* expr: OP_FLOOR '(' expr ')' */ + case 81: { (yyval.tree) = pcode->createOp(CPUI_FLOAT_FLOOR,(yyvsp[-1].tree)); } break; - case 82: /* expr: OP_ROUND '(' expr ')' */ + case 82: { (yyval.tree) = pcode->createOp(CPUI_FLOAT_ROUND,(yyvsp[-1].tree)); } break; - case 83: /* expr: OP_NEW '(' expr ')' */ + case 83: { (yyval.tree) = pcode->createOp(CPUI_NEW,(yyvsp[-1].tree)); } break; - case 84: /* expr: OP_NEW '(' expr ',' expr ')' */ + case 84: { (yyval.tree) = pcode->createOp(CPUI_NEW,(yyvsp[-3].tree),(yyvsp[-1].tree)); } break; - case 85: /* expr: specificsymbol '(' integervarnode ')' */ + case 85: { (yyval.tree) = pcode->createOp(CPUI_SUBPIECE,new ExprTree((yyvsp[-3].specsym)->getVarnode()),new ExprTree((yyvsp[-1].varnode))); } break; - case 86: /* expr: specificsymbol ':' INTEGER */ + case 86: { (yyval.tree) = pcode->createBitRange((yyvsp[-2].specsym),0,(uint4)(*(yyvsp[0].i) * 8)); delete (yyvsp[0].i); } break; - case 87: /* expr: specificsymbol '[' INTEGER ',' INTEGER ']' */ + case 87: { (yyval.tree) = pcode->createBitRange((yyvsp[-5].specsym),(uint4)*(yyvsp[-3].i),(uint4)*(yyvsp[-1].i)); delete (yyvsp[-3].i), delete (yyvsp[-1].i); } break; - case 88: /* expr: USEROPSYM '(' paramlist ')' */ + case 88: { (yyval.tree) = pcode->createUserOp((yyvsp[-3].useropsym),(yyvsp[-1].param)); } break; - case 89: /* sizedstar: '*' '[' SPACESYM ']' ':' INTEGER */ + case 89: { (yyval.starqual) = new StarQuality; (yyval.starqual)->size = *(yyvsp[0].i); delete (yyvsp[0].i); (yyval.starqual)->id=ConstTpl((yyvsp[-3].spacesym)->getSpace()); } break; - case 90: /* sizedstar: '*' '[' SPACESYM ']' */ + case 90: { (yyval.starqual) = new StarQuality; (yyval.starqual)->size = 0; (yyval.starqual)->id=ConstTpl((yyvsp[-1].spacesym)->getSpace()); } break; - case 91: /* sizedstar: '*' ':' INTEGER */ + case 91: { (yyval.starqual) = new StarQuality; (yyval.starqual)->size = *(yyvsp[0].i); delete (yyvsp[0].i); (yyval.starqual)->id=ConstTpl(pcode->getDefaultSpace()); } break; - case 92: /* sizedstar: '*' */ + case 92: { (yyval.starqual) = new StarQuality; (yyval.starqual)->size = 0; (yyval.starqual)->id=ConstTpl(pcode->getDefaultSpace()); } break; - case 93: /* jumpdest: JUMPSYM */ + case 93: { VarnodeTpl *sym = (yyvsp[0].specsym)->getVarnode(); (yyval.varnode) = new VarnodeTpl(ConstTpl(ConstTpl::j_curspace),sym->getOffset(),ConstTpl(ConstTpl::j_curspace_size)); delete sym; } break; - case 94: /* jumpdest: INTEGER */ + case 94: { (yyval.varnode) = new VarnodeTpl(ConstTpl(ConstTpl::j_curspace),ConstTpl(ConstTpl::real,*(yyvsp[0].i)),ConstTpl(ConstTpl::j_curspace_size)); delete (yyvsp[0].i); } break; - case 95: /* jumpdest: BADINTEGER */ + case 95: { (yyval.varnode) = new VarnodeTpl(ConstTpl(ConstTpl::j_curspace),ConstTpl(ConstTpl::real,0),ConstTpl(ConstTpl::j_curspace_size)); yyerror("Parsed integer is too big (overflow)"); } break; - case 96: /* jumpdest: INTEGER '[' SPACESYM ']' */ + case 96: { AddrSpace *spc = (yyvsp[-1].spacesym)->getSpace(); (yyval.varnode) = new VarnodeTpl(ConstTpl(spc),ConstTpl(ConstTpl::real,*(yyvsp[-3].i)),ConstTpl(ConstTpl::real,spc->getAddrSize())); delete (yyvsp[-3].i); } break; - case 97: /* jumpdest: label */ + case 97: { (yyval.varnode) = new VarnodeTpl(ConstTpl(pcode->getConstantSpace()),ConstTpl(ConstTpl::j_relative,(yyvsp[0].labelsym)->getIndex()),ConstTpl(ConstTpl::real,sizeof(uintm))); (yyvsp[0].labelsym)->incrementRefCount(); } break; - case 98: /* jumpdest: STRING */ + case 98: { (yyval.varnode) = (VarnodeTpl *)0; string errmsg = "Unknown jump destination: "+*(yyvsp[0].str); delete (yyvsp[0].str); yyerror(errmsg.c_str()); YYERROR; } break; - case 99: /* varnode: specificsymbol */ + case 99: { (yyval.varnode) = (yyvsp[0].specsym)->getVarnode(); } break; - case 100: /* varnode: integervarnode */ + case 100: { (yyval.varnode) = (yyvsp[0].varnode); } break; - case 101: /* varnode: STRING */ + case 101: { (yyval.varnode) = (VarnodeTpl *)0; string errmsg = "Unknown varnode parameter: "+*(yyvsp[0].str); delete (yyvsp[0].str); yyerror(errmsg.c_str()); YYERROR; } break; - case 102: /* integervarnode: INTEGER */ + case 102: { (yyval.varnode) = new VarnodeTpl(ConstTpl(pcode->getConstantSpace()),ConstTpl(ConstTpl::real,*(yyvsp[0].i)),ConstTpl(ConstTpl::real,0)); delete (yyvsp[0].i); } break; - case 103: /* integervarnode: BADINTEGER */ + case 103: { (yyval.varnode) = new VarnodeTpl(ConstTpl(pcode->getConstantSpace()),ConstTpl(ConstTpl::real,0),ConstTpl(ConstTpl::real,0)); yyerror("Parsed integer is too big (overflow)"); } break; - case 104: /* integervarnode: INTEGER ':' INTEGER */ + case 104: { (yyval.varnode) = new VarnodeTpl(ConstTpl(pcode->getConstantSpace()),ConstTpl(ConstTpl::real,*(yyvsp[-2].i)),ConstTpl(ConstTpl::real,*(yyvsp[0].i))); delete (yyvsp[-2].i); delete (yyvsp[0].i); } break; - case 105: /* integervarnode: '&' varnode */ + case 105: { (yyval.varnode) = pcode->addressOf((yyvsp[0].varnode),0); } break; - case 106: /* integervarnode: '&' ':' INTEGER varnode */ + case 106: { (yyval.varnode) = pcode->addressOf((yyvsp[0].varnode),*(yyvsp[-1].i)); delete (yyvsp[-1].i); } break; - case 107: /* lhsvarnode: specificsymbol */ + case 107: { (yyval.varnode) = (yyvsp[0].specsym)->getVarnode(); } break; - case 108: /* lhsvarnode: STRING */ + case 108: { (yyval.varnode) = (VarnodeTpl *)0; string errmsg = "Unknown assignment varnode: "+*(yyvsp[0].str); delete (yyvsp[0].str); yyerror(errmsg.c_str()); YYERROR; } break; - case 109: /* label: '<' LABELSYM '>' */ + case 109: { (yyval.labelsym) = (yyvsp[-1].labelsym); } break; - case 110: /* label: '<' STRING '>' */ + case 110: { (yyval.labelsym) = pcode->defineLabel( (yyvsp[-1].str) ); } break; - case 111: /* specificsymbol: VARSYM */ + case 111: { (yyval.specsym) = (yyvsp[0].varsym); } break; - case 112: /* specificsymbol: OPERANDSYM */ + case 112: { (yyval.specsym) = (yyvsp[0].operandsym); } break; - case 113: /* specificsymbol: JUMPSYM */ + case 113: { (yyval.specsym) = (yyvsp[0].specsym); } break; - case 114: /* paramlist: %empty */ + case 114: { (yyval.param) = new vector; } break; - case 115: /* paramlist: expr */ + case 115: { (yyval.param) = new vector; (yyval.param)->push_back((yyvsp[0].tree)); } break; - case 116: /* paramlist: paramlist ',' expr */ + case 116: { (yyval.param) = (yyvsp[-2].param); (yyval.param)->push_back((yyvsp[0].tree)); } break; @@ -2375,10 +2504,11 @@ yyparse (void) case of YYERROR or YYBACKUP, subsequent parser actions might lead to an incorrect destructor call or verbose syntax error message before the lookahead is translated. */ - YY_SYMBOL_PRINT ("-> $$ =", YY_CAST (yysymbol_kind_t, yyr1[yyn]), &yyval, &yyloc); + YY_SYMBOL_PRINT ("-> $$ =", yyr1[yyn], &yyval, &yyloc); YYPOPSTACK (yylen); yylen = 0; + YY_STACK_PRINT (yyss, yyssp); *++yyvsp = yyval; @@ -2402,30 +2532,66 @@ yyparse (void) yyerrlab: /* Make sure we have latest lookahead translation. See comments at user semantic actions for why this is necessary. */ - yytoken = yychar == PCODEEMPTY ? YYSYMBOL_YYEMPTY : YYTRANSLATE (yychar); + yytoken = yychar == YYEMPTY ? YYEMPTY : YYTRANSLATE (yychar); + /* If not already recovering from an error, report this error. */ if (!yyerrstatus) { ++yynerrs; +#if ! YYERROR_VERBOSE yyerror (YY_("syntax error")); +#else +# define YYSYNTAX_ERROR yysyntax_error (&yymsg_alloc, &yymsg, \ + yyssp, yytoken) + { + char const *yymsgp = YY_("syntax error"); + int yysyntax_error_status; + yysyntax_error_status = YYSYNTAX_ERROR; + if (yysyntax_error_status == 0) + yymsgp = yymsg; + else if (yysyntax_error_status == 1) + { + if (yymsg != yymsgbuf) + YYSTACK_FREE (yymsg); + yymsg = YY_CAST (char *, YYSTACK_ALLOC (YY_CAST (YYSIZE_T, yymsg_alloc))); + if (!yymsg) + { + yymsg = yymsgbuf; + yymsg_alloc = sizeof yymsgbuf; + yysyntax_error_status = 2; + } + else + { + yysyntax_error_status = YYSYNTAX_ERROR; + yymsgp = yymsg; + } + } + yyerror (yymsgp); + if (yysyntax_error_status == 2) + goto yyexhaustedlab; + } +# undef YYSYNTAX_ERROR +#endif } + + if (yyerrstatus == 3) { /* If just tried and failed to reuse lookahead token after an error, discard it. */ - if (yychar <= PCODEEOF) + if (yychar <= YYEOF) { /* Return failure if at end of input. */ - if (yychar == PCODEEOF) + if (yychar == YYEOF) YYABORT; } else { yydestruct ("Error: discarding", yytoken, &yylval); - yychar = PCODEEMPTY; + yychar = YYEMPTY; } } @@ -2442,7 +2608,6 @@ yyparse (void) label yyerrorlab therefore never appears in user code. */ if (0) YYERROR; - ++yynerrs; /* Do not reclaim the symbols of the rule whose action triggered this YYERROR. */ @@ -2459,14 +2624,13 @@ yyparse (void) yyerrlab1: yyerrstatus = 3; /* Each real token shifted decrements this. */ - /* Pop stack until we find a state that shifts the error token. */ for (;;) { yyn = yypact[yystate]; if (!yypact_value_is_default (yyn)) { - yyn += YYSYMBOL_YYerror; - if (0 <= yyn && yyn <= YYLAST && yycheck[yyn] == YYSYMBOL_YYerror) + yyn += YYTERROR; + if (0 <= yyn && yyn <= YYLAST && yycheck[yyn] == YYTERROR) { yyn = yytable[yyn]; if (0 < yyn) @@ -2480,7 +2644,7 @@ yyparse (void) yydestruct ("Error: popping", - YY_ACCESSING_SYMBOL (yystate), yyvsp); + yystos[yystate], yyvsp); YYPOPSTACK (1); yystate = *yyssp; YY_STACK_PRINT (yyss, yyssp); @@ -2492,7 +2656,7 @@ yyparse (void) /* Shift the error token. */ - YY_SYMBOL_PRINT ("Shifting", YY_ACCESSING_SYMBOL (yyn), yyvsp, yylsp); + YY_SYMBOL_PRINT ("Shifting", yystos[yyn], yyvsp, yylsp); yystate = yyn; goto yynewstate; @@ -2503,7 +2667,7 @@ yyparse (void) `-------------------------------------*/ yyacceptlab: yyresult = 0; - goto yyreturnlab; + goto yyreturn; /*-----------------------------------. @@ -2511,23 +2675,25 @@ yyparse (void) `-----------------------------------*/ yyabortlab: yyresult = 1; - goto yyreturnlab; + goto yyreturn; -/*-----------------------------------------------------------. -| yyexhaustedlab -- YYNOMEM (memory exhaustion) comes here. | -`-----------------------------------------------------------*/ +#if !defined yyoverflow || YYERROR_VERBOSE +/*-------------------------------------------------. +| yyexhaustedlab -- memory exhaustion comes here. | +`-------------------------------------------------*/ yyexhaustedlab: yyerror (YY_("memory exhausted")); yyresult = 2; - goto yyreturnlab; + /* Fall through. */ +#endif -/*----------------------------------------------------------. -| yyreturnlab -- parsing is finished, clean up and return. | -`----------------------------------------------------------*/ -yyreturnlab: - if (yychar != PCODEEMPTY) +/*-----------------------------------------------------. +| yyreturn -- parsing is finished, return the result. | +`-----------------------------------------------------*/ +yyreturn: + if (yychar != YYEMPTY) { /* Make sure we have latest lookahead translation. See comments at user semantic actions for why this is necessary. */ @@ -2542,19 +2708,21 @@ yyparse (void) while (yyssp != yyss) { yydestruct ("Cleanup: popping", - YY_ACCESSING_SYMBOL (+*yyssp), yyvsp); + yystos[+*yyssp], yyvsp); YYPOPSTACK (1); } #ifndef yyoverflow if (yyss != yyssa) YYSTACK_FREE (yyss); #endif - +#if YYERROR_VERBOSE + if (yymsg != yymsgbuf) + YYSTACK_FREE (yymsg); +#endif return yyresult; } - #define IDENTREC_SIZE 46 const IdentRec PcodeLexer::idents[]= { // Sorted list of identifiers { "!=", OP_NOTEQUAL }, diff --git a/pypcode/sleigh/pcoderaw.cc b/pypcode/sleigh/pcoderaw.cc index 58d50ac..dd589b6 100644 --- a/pypcode/sleigh/pcoderaw.cc +++ b/pypcode/sleigh/pcoderaw.cc @@ -96,7 +96,7 @@ bool VarnodeData::isContiguous(const VarnodeData &lo) const OpCode PcodeOpRaw::decode(Decoder &decoder,int4 isize,VarnodeData *invar,VarnodeData **outvar) { - OpCode opcode = (OpCode)decoder.readSignedInteger(ATTRIB_CODE); + OpCode opcode = decoder.readOpcode(ATTRIB_CODE); uint4 subId = decoder.peekElement(); if (subId == ELEM_VOID) { decoder.openElement(); diff --git a/pypcode/sleigh/semantics.cc b/pypcode/sleigh/semantics.cc index 18e2ff8..7b06da8 100644 --- a/pypcode/sleigh/semantics.cc +++ b/pypcode/sleigh/semantics.cc @@ -721,8 +721,8 @@ void OpTpl::decode(Decoder &decoder) } while(decoder.peekElement() != 0) { VarnodeTpl *vn = new VarnodeTpl(); - vn->decode(decoder); input.push_back(vn); + vn->decode(decoder); } decoder.closeElement(el); } @@ -915,8 +915,8 @@ int4 ConstructTpl::decode(Decoder &decoder) } while(decoder.peekElement() != 0) { OpTpl *op = new OpTpl(); - op->decode(decoder); vec.push_back(op); + op->decode(decoder); } decoder.closeElement(el); return sectionid; diff --git a/pypcode/sleigh/semantics.hh b/pypcode/sleigh/semantics.hh index b53b187..2a768a7 100644 --- a/pypcode/sleigh/semantics.hh +++ b/pypcode/sleigh/semantics.hh @@ -142,7 +142,7 @@ class OpTpl { OpCode opc; vector input; public: - OpTpl(void) {} + OpTpl(void) : output(nullptr) {} OpTpl(OpCode oc) { opc = oc; output = (VarnodeTpl *)0; } ~OpTpl(void); VarnodeTpl *getOut(void) const { return output; } diff --git a/pypcode/sleigh/sleigh.cc b/pypcode/sleigh/sleigh.cc index 304a73b..25c6b71 100644 --- a/pypcode/sleigh/sleigh.cc +++ b/pypcode/sleigh/sleigh.cc @@ -453,8 +453,8 @@ void DisassemblyCache::initialize(int4 min,int4 hashsize) hashtable = new ParserContext *[hashsize]; for(int4 i=0;iinitialize(75,20,constspace); list[i] = pos; + pos->initialize(75,20,constspace); } ParserContext *pos = list[0]; for(int4 i=0;isetMainSection(vec->getMainSection()); + big->setMainSection(vec->releaseMainSection()); int4 max = vec->getMaxId(); for(int4 i=0;igetNamedSection(i); + ConstructTpl *section = vec->releaseNamedSection(i); if (section != (ConstructTpl *)0) big->setNamedSection(section,i); } @@ -3708,6 +3739,9 @@ void SleighCompile::buildConstructor(Constructor *big,PatternEquation *pateq,vec delete contvec; } } + else { + PatternEquation::release(pateq); + } symtab.popScope(); // In all cases pop scope } @@ -3768,6 +3802,7 @@ int4 SleighCompile::run_compilation(const string &filein,const string &fileout) try { int4 parseres = sleighparse(); // Try to parse fclose(sleighin); + sleighlex_destroy(); // Make sure lexer is reset so we can parse multiple files if (parseres==0) process(); // Do all the post-processing if ((parseres==0)&&(numErrors()==0)) { // If no errors @@ -3794,7 +3829,6 @@ int4 SleighCompile::run_compilation(const string &filein,const string &fileout) cerr << "No output produced" < named; ///< Named sections accessed by index public: - SectionVector(ConstructTpl *rtl,SymbolScope *scope); ///< Constructor - ConstructTpl *getMainSection(void) const { return main.section; } ///< Get the \e main section - ConstructTpl *getNamedSection(int4 index) const { return named[index].section; } ///< Get a \e named section by index - RtlPair getMainPair(void) const { return main; } ///< Get the \e main section/namespace pair - RtlPair getNamedPair(int4 i) const { return named[i]; } ///< Get a \e named section/namespace pair by index - void setNextIndex(int4 i) { nextindex = i; } ///< Set the index of the currently parsing \e named section - int4 getMaxId(void) const { return named.size(); } ///< Get the maximum (exclusive) named section index - void append(ConstructTpl *rtl,SymbolScope *scope); ///< Add a new \e named section + SectionVector(ConstructTpl *rtl,SymbolScope *scope); ///< Constructor + ~SectionVector(void); ///< Destructor + ConstructTpl *releaseMainSection(void); ///< Get the \e main section, giving up ownership + ConstructTpl *releaseNamedSection(int4 index); ///< Get a \e named section by index, giving up ownership + RtlPair getMainPair(void) const { return main; } ///< Get the \e main section/namespace pair + RtlPair getNamedPair(int4 i) const { return named[i]; } ///< Get a \e named section/namespace pair by index + void setNextIndex(int4 i) { nextindex = i; } ///< Set the index of the currently parsing \e named section + int4 getMaxId(void) const { return named.size(); } ///< Get the maximum (exclusive) named section index + void append(ConstructTpl *rtl,SymbolScope *scope); ///< Add a new \e named section }; /// \brief Qualities associated (via parsing) with an address space diff --git a/pypcode/sleigh/slghparse.cc b/pypcode/sleigh/slghparse.cc index 741525a..cf50b19 100644 --- a/pypcode/sleigh/slghparse.cc +++ b/pypcode/sleigh/slghparse.cc @@ -13,7 +13,7 @@ * See the License for the specific language governing permissions and * limitations under the License. */ -/* A Bison parser, made by GNU Bison 3.5.1. */ +/* A Bison parser, made by GNU Bison 3.7.4. */ /* Bison implementation for Yacc-like parsers in C @@ -49,6 +49,10 @@ /* C LALR(1) parser skeleton written by Richard Stallman, by simplifying the original so-called "semantic" parser. */ +/* DO NOT RELY ON FEATURES THAT ARE NOT DOCUMENTED in the manual, + especially those whose name start with YY_ or yy_. They are + private implementation details that can be changed or removed. */ + /* All symbols defined below should begin with yy or YY, to avoid infringing on user name space. This should be done even for local variables, as they might otherwise be expanded by user macros. @@ -56,14 +60,11 @@ define necessary library symbols; they are noted "INFRINGES ON USER NAME SPACE" below. */ -/* Undocumented macros, especially those whose name start with YY_, - are private implementation details. Do not rely on them. */ - -/* Identify Bison output. */ -#define YYBISON 1 +/* Identify Bison output, and Bison version. */ +#define YYBISON 30704 -/* Bison version. */ -#define YYBISON_VERSION "3.5.1" +/* Bison version string. */ +#define YYBISON_VERSION "3.7.4" /* Skeleton name. */ #define YYSKELETON_NAME "yacc.c" @@ -124,211 +125,222 @@ extern int sleigherror(const char *str ); # endif # endif -/* Enabling verbose error messages. */ -#ifdef YYERROR_VERBOSE -# undef YYERROR_VERBOSE -# define YYERROR_VERBOSE 1 -#else -# define YYERROR_VERBOSE 0 -#endif - -/* Use api.header.include to #include this header - instead of duplicating it here. */ -#ifndef YY_SLEIGH_SLGHPARSE_HH_INCLUDED -# define YY_SLEIGH_SLGHPARSE_HH_INCLUDED -/* Debug traces. */ -#ifndef SLEIGHDEBUG -# if defined YYDEBUG -#if YYDEBUG -# define SLEIGHDEBUG 1 -# else -# define SLEIGHDEBUG 0 -# endif -# else /* ! defined YYDEBUG */ -# define SLEIGHDEBUG 0 -# endif /* ! defined YYDEBUG */ -#endif /* ! defined SLEIGHDEBUG */ -#if SLEIGHDEBUG -extern int sleighdebug; -#endif - -/* Token type. */ -#ifndef SLEIGHTOKENTYPE -# define SLEIGHTOKENTYPE - enum sleightokentype - { - OP_BOOL_OR = 258, - OP_BOOL_AND = 259, - OP_BOOL_XOR = 260, - OP_OR = 261, - OP_XOR = 262, - OP_AND = 263, - OP_EQUAL = 264, - OP_NOTEQUAL = 265, - OP_FEQUAL = 266, - OP_FNOTEQUAL = 267, - OP_GREATEQUAL = 268, - OP_LESSEQUAL = 269, - OP_SLESS = 270, - OP_SGREATEQUAL = 271, - OP_SLESSEQUAL = 272, - OP_SGREAT = 273, - OP_FLESS = 274, - OP_FGREAT = 275, - OP_FLESSEQUAL = 276, - OP_FGREATEQUAL = 277, - OP_LEFT = 278, - OP_RIGHT = 279, - OP_SRIGHT = 280, - OP_FADD = 281, - OP_FSUB = 282, - OP_SDIV = 283, - OP_SREM = 284, - OP_FMULT = 285, - OP_FDIV = 286, - OP_ZEXT = 287, - OP_CARRY = 288, - OP_BORROW = 289, - OP_SEXT = 290, - OP_SCARRY = 291, - OP_SBORROW = 292, - OP_NAN = 293, - OP_ABS = 294, - OP_SQRT = 295, - OP_CEIL = 296, - OP_FLOOR = 297, - OP_ROUND = 298, - OP_INT2FLOAT = 299, - OP_FLOAT2FLOAT = 300, - OP_TRUNC = 301, - OP_CPOOLREF = 302, - OP_NEW = 303, - OP_POPCOUNT = 304, - OP_LZCOUNT = 305, - BADINTEGER = 306, - GOTO_KEY = 307, - CALL_KEY = 308, - RETURN_KEY = 309, - IF_KEY = 310, - DEFINE_KEY = 311, - ATTACH_KEY = 312, - MACRO_KEY = 313, - SPACE_KEY = 314, - TYPE_KEY = 315, - RAM_KEY = 316, - DEFAULT_KEY = 317, - REGISTER_KEY = 318, - ENDIAN_KEY = 319, - WITH_KEY = 320, - ALIGN_KEY = 321, - OP_UNIMPL = 322, - TOKEN_KEY = 323, - SIGNED_KEY = 324, - NOFLOW_KEY = 325, - HEX_KEY = 326, - DEC_KEY = 327, - BIG_KEY = 328, - LITTLE_KEY = 329, - SIZE_KEY = 330, - WORDSIZE_KEY = 331, - OFFSET_KEY = 332, - NAMES_KEY = 333, - VALUES_KEY = 334, - VARIABLES_KEY = 335, - PCODEOP_KEY = 336, - IS_KEY = 337, - LOCAL_KEY = 338, - DELAYSLOT_KEY = 339, - CROSSBUILD_KEY = 340, - EXPORT_KEY = 341, - BUILD_KEY = 342, - CONTEXT_KEY = 343, - ELLIPSIS_KEY = 344, - GLOBALSET_KEY = 345, - BITRANGE_KEY = 346, - CHAR = 347, - INTEGER = 348, - INTB = 349, - STRING = 350, - SYMBOLSTRING = 351, - SPACESYM = 352, - SECTIONSYM = 353, - TOKENSYM = 354, - USEROPSYM = 355, - VALUESYM = 356, - VALUEMAPSYM = 357, - CONTEXTSYM = 358, - NAMESYM = 359, - VARSYM = 360, - BITSYM = 361, - SPECSYM = 362, - VARLISTSYM = 363, - OPERANDSYM = 364, - JUMPSYM = 365, - MACROSYM = 366, - LABELSYM = 367, - SUBTABLESYM = 368 - }; -#endif - -/* Value type. */ -#if ! defined SLEIGHSTYPE && ! defined SLEIGHSTYPE_IS_DECLARED -union SLEIGHSTYPE +#include "slghparse.hh" +/* Symbol kind. */ +enum yysymbol_kind_t { - - char ch; - uintb *i; - intb *big; - string *str; - vector *strlist; - vector *biglist; - vector *param; - SpaceQuality *spacequal; - FieldQuality *fieldqual; - StarQuality *starqual; - VarnodeTpl *varnode; - ExprTree *tree; - vector *stmt; - ConstructTpl *sem; - SectionVector *sectionstart; - Constructor *construct; - PatternEquation *pateq; - PatternExpression *patexp; - - vector *symlist; - vector *contop; - SleighSymbol *anysym; - SpaceSymbol *spacesym; - SectionSymbol *sectionsym; - TokenSymbol *tokensym; - UserOpSymbol *useropsym; - MacroSymbol *macrosym; - LabelSymbol *labelsym; - SubtableSymbol *subtablesym; - OperandSymbol *operandsym; - VarnodeListSymbol *varlistsym; - VarnodeSymbol *varsym; - BitrangeSymbol *bitsym; - NameSymbol *namesym; - ValueSymbol *valuesym; - ValueMapSymbol *valuemapsym; - ContextSymbol *contextsym; - FamilySymbol *famsym; - SpecificSymbol *specsym; - - + YYSYMBOL_YYEMPTY = -2, + YYSYMBOL_YYEOF = 0, /* "end of file" */ + YYSYMBOL_YYerror = 1, /* error */ + YYSYMBOL_YYUNDEF = 2, /* "invalid token" */ + YYSYMBOL_OP_BOOL_OR = 3, /* OP_BOOL_OR */ + YYSYMBOL_OP_BOOL_AND = 4, /* OP_BOOL_AND */ + YYSYMBOL_OP_BOOL_XOR = 5, /* OP_BOOL_XOR */ + YYSYMBOL_6_ = 6, /* '|' */ + YYSYMBOL_OP_OR = 7, /* OP_OR */ + YYSYMBOL_8_ = 8, /* ';' */ + YYSYMBOL_9_ = 9, /* '^' */ + YYSYMBOL_OP_XOR = 10, /* OP_XOR */ + YYSYMBOL_11_ = 11, /* '&' */ + YYSYMBOL_OP_AND = 12, /* OP_AND */ + YYSYMBOL_OP_EQUAL = 13, /* OP_EQUAL */ + YYSYMBOL_OP_NOTEQUAL = 14, /* OP_NOTEQUAL */ + YYSYMBOL_OP_FEQUAL = 15, /* OP_FEQUAL */ + YYSYMBOL_OP_FNOTEQUAL = 16, /* OP_FNOTEQUAL */ + YYSYMBOL_17_ = 17, /* '<' */ + YYSYMBOL_18_ = 18, /* '>' */ + YYSYMBOL_OP_GREATEQUAL = 19, /* OP_GREATEQUAL */ + YYSYMBOL_OP_LESSEQUAL = 20, /* OP_LESSEQUAL */ + YYSYMBOL_OP_SLESS = 21, /* OP_SLESS */ + YYSYMBOL_OP_SGREATEQUAL = 22, /* OP_SGREATEQUAL */ + YYSYMBOL_OP_SLESSEQUAL = 23, /* OP_SLESSEQUAL */ + YYSYMBOL_OP_SGREAT = 24, /* OP_SGREAT */ + YYSYMBOL_OP_FLESS = 25, /* OP_FLESS */ + YYSYMBOL_OP_FGREAT = 26, /* OP_FGREAT */ + YYSYMBOL_OP_FLESSEQUAL = 27, /* OP_FLESSEQUAL */ + YYSYMBOL_OP_FGREATEQUAL = 28, /* OP_FGREATEQUAL */ + YYSYMBOL_OP_LEFT = 29, /* OP_LEFT */ + YYSYMBOL_OP_RIGHT = 30, /* OP_RIGHT */ + YYSYMBOL_OP_SRIGHT = 31, /* OP_SRIGHT */ + YYSYMBOL_32_ = 32, /* '+' */ + YYSYMBOL_33_ = 33, /* '-' */ + YYSYMBOL_OP_FADD = 34, /* OP_FADD */ + YYSYMBOL_OP_FSUB = 35, /* OP_FSUB */ + YYSYMBOL_36_ = 36, /* '*' */ + YYSYMBOL_37_ = 37, /* '/' */ + YYSYMBOL_38_ = 38, /* '%' */ + YYSYMBOL_OP_SDIV = 39, /* OP_SDIV */ + YYSYMBOL_OP_SREM = 40, /* OP_SREM */ + YYSYMBOL_OP_FMULT = 41, /* OP_FMULT */ + YYSYMBOL_OP_FDIV = 42, /* OP_FDIV */ + YYSYMBOL_43_ = 43, /* '!' */ + YYSYMBOL_44_ = 44, /* '~' */ + YYSYMBOL_OP_ZEXT = 45, /* OP_ZEXT */ + YYSYMBOL_OP_CARRY = 46, /* OP_CARRY */ + YYSYMBOL_OP_BORROW = 47, /* OP_BORROW */ + YYSYMBOL_OP_SEXT = 48, /* OP_SEXT */ + YYSYMBOL_OP_SCARRY = 49, /* OP_SCARRY */ + YYSYMBOL_OP_SBORROW = 50, /* OP_SBORROW */ + YYSYMBOL_OP_NAN = 51, /* OP_NAN */ + YYSYMBOL_OP_ABS = 52, /* OP_ABS */ + YYSYMBOL_OP_SQRT = 53, /* OP_SQRT */ + YYSYMBOL_OP_CEIL = 54, /* OP_CEIL */ + YYSYMBOL_OP_FLOOR = 55, /* OP_FLOOR */ + YYSYMBOL_OP_ROUND = 56, /* OP_ROUND */ + YYSYMBOL_OP_INT2FLOAT = 57, /* OP_INT2FLOAT */ + YYSYMBOL_OP_FLOAT2FLOAT = 58, /* OP_FLOAT2FLOAT */ + YYSYMBOL_OP_TRUNC = 59, /* OP_TRUNC */ + YYSYMBOL_OP_CPOOLREF = 60, /* OP_CPOOLREF */ + YYSYMBOL_OP_NEW = 61, /* OP_NEW */ + YYSYMBOL_OP_POPCOUNT = 62, /* OP_POPCOUNT */ + YYSYMBOL_OP_LZCOUNT = 63, /* OP_LZCOUNT */ + YYSYMBOL_BADINTEGER = 64, /* BADINTEGER */ + YYSYMBOL_GOTO_KEY = 65, /* GOTO_KEY */ + YYSYMBOL_CALL_KEY = 66, /* CALL_KEY */ + YYSYMBOL_RETURN_KEY = 67, /* RETURN_KEY */ + YYSYMBOL_IF_KEY = 68, /* IF_KEY */ + YYSYMBOL_DEFINE_KEY = 69, /* DEFINE_KEY */ + YYSYMBOL_ATTACH_KEY = 70, /* ATTACH_KEY */ + YYSYMBOL_MACRO_KEY = 71, /* MACRO_KEY */ + YYSYMBOL_SPACE_KEY = 72, /* SPACE_KEY */ + YYSYMBOL_TYPE_KEY = 73, /* TYPE_KEY */ + YYSYMBOL_RAM_KEY = 74, /* RAM_KEY */ + YYSYMBOL_DEFAULT_KEY = 75, /* DEFAULT_KEY */ + YYSYMBOL_REGISTER_KEY = 76, /* REGISTER_KEY */ + YYSYMBOL_ENDIAN_KEY = 77, /* ENDIAN_KEY */ + YYSYMBOL_WITH_KEY = 78, /* WITH_KEY */ + YYSYMBOL_ALIGN_KEY = 79, /* ALIGN_KEY */ + YYSYMBOL_OP_UNIMPL = 80, /* OP_UNIMPL */ + YYSYMBOL_TOKEN_KEY = 81, /* TOKEN_KEY */ + YYSYMBOL_SIGNED_KEY = 82, /* SIGNED_KEY */ + YYSYMBOL_NOFLOW_KEY = 83, /* NOFLOW_KEY */ + YYSYMBOL_HEX_KEY = 84, /* HEX_KEY */ + YYSYMBOL_DEC_KEY = 85, /* DEC_KEY */ + YYSYMBOL_BIG_KEY = 86, /* BIG_KEY */ + YYSYMBOL_LITTLE_KEY = 87, /* LITTLE_KEY */ + YYSYMBOL_SIZE_KEY = 88, /* SIZE_KEY */ + YYSYMBOL_WORDSIZE_KEY = 89, /* WORDSIZE_KEY */ + YYSYMBOL_OFFSET_KEY = 90, /* OFFSET_KEY */ + YYSYMBOL_NAMES_KEY = 91, /* NAMES_KEY */ + YYSYMBOL_VALUES_KEY = 92, /* VALUES_KEY */ + YYSYMBOL_VARIABLES_KEY = 93, /* VARIABLES_KEY */ + YYSYMBOL_PCODEOP_KEY = 94, /* PCODEOP_KEY */ + YYSYMBOL_IS_KEY = 95, /* IS_KEY */ + YYSYMBOL_LOCAL_KEY = 96, /* LOCAL_KEY */ + YYSYMBOL_DELAYSLOT_KEY = 97, /* DELAYSLOT_KEY */ + YYSYMBOL_CROSSBUILD_KEY = 98, /* CROSSBUILD_KEY */ + YYSYMBOL_EXPORT_KEY = 99, /* EXPORT_KEY */ + YYSYMBOL_BUILD_KEY = 100, /* BUILD_KEY */ + YYSYMBOL_CONTEXT_KEY = 101, /* CONTEXT_KEY */ + YYSYMBOL_ELLIPSIS_KEY = 102, /* ELLIPSIS_KEY */ + YYSYMBOL_GLOBALSET_KEY = 103, /* GLOBALSET_KEY */ + YYSYMBOL_BITRANGE_KEY = 104, /* BITRANGE_KEY */ + YYSYMBOL_CHAR = 105, /* CHAR */ + YYSYMBOL_INTEGER = 106, /* INTEGER */ + YYSYMBOL_INTB = 107, /* INTB */ + YYSYMBOL_STRING = 108, /* STRING */ + YYSYMBOL_SYMBOLSTRING = 109, /* SYMBOLSTRING */ + YYSYMBOL_SPACESYM = 110, /* SPACESYM */ + YYSYMBOL_SECTIONSYM = 111, /* SECTIONSYM */ + YYSYMBOL_TOKENSYM = 112, /* TOKENSYM */ + YYSYMBOL_USEROPSYM = 113, /* USEROPSYM */ + YYSYMBOL_VALUESYM = 114, /* VALUESYM */ + YYSYMBOL_VALUEMAPSYM = 115, /* VALUEMAPSYM */ + YYSYMBOL_CONTEXTSYM = 116, /* CONTEXTSYM */ + YYSYMBOL_NAMESYM = 117, /* NAMESYM */ + YYSYMBOL_VARSYM = 118, /* VARSYM */ + YYSYMBOL_BITSYM = 119, /* BITSYM */ + YYSYMBOL_SPECSYM = 120, /* SPECSYM */ + YYSYMBOL_VARLISTSYM = 121, /* VARLISTSYM */ + YYSYMBOL_OPERANDSYM = 122, /* OPERANDSYM */ + YYSYMBOL_JUMPSYM = 123, /* JUMPSYM */ + YYSYMBOL_MACROSYM = 124, /* MACROSYM */ + YYSYMBOL_LABELSYM = 125, /* LABELSYM */ + YYSYMBOL_SUBTABLESYM = 126, /* SUBTABLESYM */ + YYSYMBOL_127_ = 127, /* '}' */ + YYSYMBOL_128_ = 128, /* '=' */ + YYSYMBOL_129_ = 129, /* '(' */ + YYSYMBOL_130_ = 130, /* ')' */ + YYSYMBOL_131_ = 131, /* ',' */ + YYSYMBOL_132_ = 132, /* '[' */ + YYSYMBOL_133_ = 133, /* ']' */ + YYSYMBOL_134_ = 134, /* '{' */ + YYSYMBOL_135_ = 135, /* ':' */ + YYSYMBOL_136_ = 136, /* ' ' */ + YYSYMBOL_YYACCEPT = 137, /* $accept */ + YYSYMBOL_spec = 138, /* spec */ + YYSYMBOL_definition = 139, /* definition */ + YYSYMBOL_constructorlike = 140, /* constructorlike */ + YYSYMBOL_endiandef = 141, /* endiandef */ + YYSYMBOL_aligndef = 142, /* aligndef */ + YYSYMBOL_tokendef = 143, /* tokendef */ + YYSYMBOL_tokenprop = 144, /* tokenprop */ + YYSYMBOL_contextdef = 145, /* contextdef */ + YYSYMBOL_contextprop = 146, /* contextprop */ + YYSYMBOL_fielddef = 147, /* fielddef */ + YYSYMBOL_contextfielddef = 148, /* contextfielddef */ + YYSYMBOL_spacedef = 149, /* spacedef */ + YYSYMBOL_spaceprop = 150, /* spaceprop */ + YYSYMBOL_varnodedef = 151, /* varnodedef */ + YYSYMBOL_bitrangedef = 152, /* bitrangedef */ + YYSYMBOL_bitrangelist = 153, /* bitrangelist */ + YYSYMBOL_bitrangesingle = 154, /* bitrangesingle */ + YYSYMBOL_pcodeopdef = 155, /* pcodeopdef */ + YYSYMBOL_valueattach = 156, /* valueattach */ + YYSYMBOL_nameattach = 157, /* nameattach */ + YYSYMBOL_varattach = 158, /* varattach */ + YYSYMBOL_macrodef = 159, /* macrodef */ + YYSYMBOL_withblockstart = 160, /* withblockstart */ + YYSYMBOL_withblockmid = 161, /* withblockmid */ + YYSYMBOL_withblock = 162, /* withblock */ + YYSYMBOL_id_or_nil = 163, /* id_or_nil */ + YYSYMBOL_bitpat_or_nil = 164, /* bitpat_or_nil */ + YYSYMBOL_macrostart = 165, /* macrostart */ + YYSYMBOL_rtlbody = 166, /* rtlbody */ + YYSYMBOL_constructor = 167, /* constructor */ + YYSYMBOL_constructprint = 168, /* constructprint */ + YYSYMBOL_subtablestart = 169, /* subtablestart */ + YYSYMBOL_pexpression = 170, /* pexpression */ + YYSYMBOL_pequation = 171, /* pequation */ + YYSYMBOL_elleq = 172, /* elleq */ + YYSYMBOL_ellrt = 173, /* ellrt */ + YYSYMBOL_atomic = 174, /* atomic */ + YYSYMBOL_constraint = 175, /* constraint */ + YYSYMBOL_contextblock = 176, /* contextblock */ + YYSYMBOL_contextlist = 177, /* contextlist */ + YYSYMBOL_section_def = 178, /* section_def */ + YYSYMBOL_rtlfirstsection = 179, /* rtlfirstsection */ + YYSYMBOL_rtlcontinue = 180, /* rtlcontinue */ + YYSYMBOL_rtl = 181, /* rtl */ + YYSYMBOL_rtlmid = 182, /* rtlmid */ + YYSYMBOL_statement = 183, /* statement */ + YYSYMBOL_expr = 184, /* expr */ + YYSYMBOL_sizedstar = 185, /* sizedstar */ + YYSYMBOL_jumpdest = 186, /* jumpdest */ + YYSYMBOL_varnode = 187, /* varnode */ + YYSYMBOL_integervarnode = 188, /* integervarnode */ + YYSYMBOL_lhsvarnode = 189, /* lhsvarnode */ + YYSYMBOL_label = 190, /* label */ + YYSYMBOL_exportvarnode = 191, /* exportvarnode */ + YYSYMBOL_familysymbol = 192, /* familysymbol */ + YYSYMBOL_specificsymbol = 193, /* specificsymbol */ + YYSYMBOL_charstring = 194, /* charstring */ + YYSYMBOL_intblist = 195, /* intblist */ + YYSYMBOL_intbpart = 196, /* intbpart */ + YYSYMBOL_stringlist = 197, /* stringlist */ + YYSYMBOL_stringpart = 198, /* stringpart */ + YYSYMBOL_anystringlist = 199, /* anystringlist */ + YYSYMBOL_anystringpart = 200, /* anystringpart */ + YYSYMBOL_valuelist = 201, /* valuelist */ + YYSYMBOL_valuepart = 202, /* valuepart */ + YYSYMBOL_varlist = 203, /* varlist */ + YYSYMBOL_varpart = 204, /* varpart */ + YYSYMBOL_paramlist = 205, /* paramlist */ + YYSYMBOL_oplist = 206, /* oplist */ + YYSYMBOL_anysymbol = 207 /* anysymbol */ }; -typedef union SLEIGHSTYPE SLEIGHSTYPE; -# define SLEIGHSTYPE_IS_TRIVIAL 1 -# define SLEIGHSTYPE_IS_DECLARED 1 -#endif - - -extern SLEIGHSTYPE sleighlval; +typedef enum yysymbol_kind_t yysymbol_kind_t; -int sleighparse (void); - -#endif /* !YY_SLEIGH_SLGHPARSE_HH_INCLUDED */ @@ -428,6 +440,7 @@ typedef int yytype_uint16; #define YYSIZEOF(X) YY_CAST (YYPTRDIFF_T, sizeof (X)) + /* Stored state numbers (used for stacks). */ typedef yytype_int16 yy_state_t; @@ -446,6 +459,7 @@ typedef int yy_state_fast_t; # endif #endif + #ifndef YY_ATTRIBUTE_PURE # if defined __GNUC__ && 2 < __GNUC__ + (96 <= __GNUC_MINOR__) # define YY_ATTRIBUTE_PURE __attribute__ ((__pure__)) @@ -503,7 +517,7 @@ typedef int yy_state_fast_t; #define YY_ASSERT(E) ((void) (0 && (E))) -#if ! defined yyoverflow || YYERROR_VERBOSE +#if !defined yyoverflow /* The parser invokes alloca or malloc; define the necessary symbols. */ @@ -568,8 +582,7 @@ void free (void *); /* INFRINGES ON USER NAME SPACE */ # endif # endif # endif -#endif /* ! defined yyoverflow || YYERROR_VERBOSE */ - +#endif /* !defined yyoverflow */ #if (! defined yyoverflow \ && (! defined __cplusplus \ @@ -645,14 +658,16 @@ union yyalloc /* YYNSTATES -- Number of states. */ #define YYNSTATES 714 -#define YYUNDEFTOK 2 +/* YYMAXUTOK -- Last valid token kind. */ #define YYMAXUTOK 368 /* YYTRANSLATE(TOKEN-NUM) -- Symbol number corresponding to TOKEN-NUM as returned by yylex, with out-of-bounds checking. */ -#define YYTRANSLATE(YYX) \ - (0 <= (YYX) && (YYX) <= YYMAXUTOK ? yytranslate[YYX] : YYUNDEFTOK) +#define YYTRANSLATE(YYX) \ + (0 <= (YYX) && (YYX) <= YYMAXUTOK \ + ? YY_CAST (yysymbol_kind_t, yytranslate[YYX]) \ + : YYSYMBOL_YYUNDEF) /* YYTRANSLATE[TOKEN-NUM] -- Symbol number corresponding to TOKEN-NUM as returned by yylex. */ @@ -701,64 +716,71 @@ static const yytype_uint8 yytranslate[] = /* YYRLINE[YYN] -- Source line where rule number YYN was defined. */ static const yytype_int16 yyrline[] = { - 0, 155, 155, 156, 157, 158, 160, 161, 162, 163, - 164, 165, 166, 167, 168, 169, 171, 172, 173, 174, - 176, 177, 179, 181, 183, 184, 185, 186, 187, 189, - 191, 192, 195, 196, 197, 198, 199, 201, 202, 203, - 204, 205, 206, 208, 210, 211, 212, 213, 214, 215, - 216, 218, 220, 222, 224, 225, 227, 230, 232, 234, - 236, 238, 241, 243, 244, 245, 247, 249, 250, 251, - 254, 255, 258, 260, 261, 262, 264, 265, 267, 268, - 269, 270, 271, 272, 273, 274, 275, 277, 278, 279, - 280, 282, 284, 287, 288, 289, 290, 291, 292, 293, - 294, 295, 296, 297, 298, 299, 301, 302, 303, 304, - 306, 307, 309, 310, 312, 313, 315, 316, 317, 318, - 319, 320, 321, 324, 325, 326, 327, 329, 330, 332, - 333, 334, 335, 336, 337, 339, 340, 342, 344, 345, - 347, 348, 349, 350, 351, 353, 354, 355, 356, 358, - 359, 360, 361, 362, 363, 364, 365, 366, 367, 368, - 369, 370, 371, 372, 373, 374, 375, 376, 377, 378, - 379, 380, 381, 382, 384, 385, 386, 387, 388, 389, - 390, 391, 392, 393, 394, 395, 396, 397, 398, 399, - 400, 401, 402, 403, 404, 405, 406, 407, 408, 409, - 410, 411, 412, 413, 414, 415, 416, 417, 418, 419, - 420, 421, 422, 423, 424, 425, 426, 427, 428, 429, - 430, 431, 432, 433, 434, 435, 436, 437, 438, 439, - 440, 441, 442, 443, 444, 445, 446, 447, 448, 449, - 450, 452, 453, 454, 455, 457, 458, 459, 460, 461, - 462, 463, 465, 466, 467, 468, 470, 471, 472, 473, - 474, 476, 477, 478, 480, 481, 483, 484, 485, 486, - 487, 488, 490, 491, 492, 493, 494, 496, 497, 498, - 499, 501, 502, 504, 505, 506, 508, 509, 510, 512, - 513, 514, 517, 518, 520, 521, 522, 524, 526, 527, - 528, 529, 531, 532, 533, 535, 536, 537, 538, 539, - 541, 542, 544, 545, 547, 548, 551, 552, 553, 555, - 556, 557, 559, 560, 561, 562, 563, 564, 565, 566, - 567, 568, 569, 570, 571, 572, 573 + 0, 163, 163, 164, 165, 166, 168, 169, 170, 171, + 172, 173, 174, 175, 176, 177, 179, 180, 181, 182, + 184, 185, 187, 189, 191, 192, 193, 194, 195, 197, + 199, 200, 203, 204, 205, 206, 207, 209, 210, 211, + 212, 213, 214, 216, 218, 219, 220, 221, 222, 223, + 224, 226, 228, 230, 232, 233, 235, 238, 240, 242, + 244, 246, 249, 251, 252, 253, 255, 257, 258, 259, + 262, 263, 266, 268, 269, 270, 272, 273, 275, 276, + 277, 278, 279, 280, 281, 282, 283, 285, 286, 287, + 288, 290, 292, 295, 296, 297, 298, 299, 300, 301, + 302, 303, 304, 305, 306, 307, 309, 310, 311, 312, + 314, 315, 317, 318, 320, 321, 323, 324, 325, 326, + 327, 328, 329, 332, 333, 334, 335, 337, 338, 340, + 341, 342, 343, 344, 345, 347, 348, 350, 352, 353, + 355, 356, 357, 358, 359, 361, 362, 363, 364, 366, + 367, 368, 369, 370, 371, 372, 373, 374, 375, 376, + 377, 378, 379, 380, 381, 382, 383, 384, 385, 386, + 387, 388, 389, 390, 392, 393, 394, 395, 396, 397, + 398, 399, 400, 401, 402, 403, 404, 405, 406, 407, + 408, 409, 410, 411, 412, 413, 414, 415, 416, 417, + 418, 419, 420, 421, 422, 423, 424, 425, 426, 427, + 428, 429, 430, 431, 432, 433, 434, 435, 436, 437, + 438, 439, 440, 441, 442, 443, 444, 445, 446, 447, + 448, 449, 450, 451, 452, 453, 454, 455, 456, 457, + 458, 460, 461, 462, 463, 465, 466, 467, 468, 469, + 470, 471, 473, 474, 475, 476, 478, 479, 480, 481, + 482, 484, 485, 486, 488, 489, 491, 492, 493, 494, + 495, 496, 498, 499, 500, 501, 502, 504, 505, 506, + 507, 509, 510, 512, 513, 514, 516, 517, 518, 520, + 521, 522, 525, 526, 528, 529, 530, 532, 534, 535, + 536, 537, 539, 540, 541, 543, 544, 545, 546, 547, + 549, 550, 552, 553, 555, 556, 559, 560, 561, 563, + 564, 565, 567, 568, 569, 570, 571, 572, 573, 574, + 575, 576, 577, 578, 579, 580, 581 }; #endif -#if SLEIGHDEBUG || YYERROR_VERBOSE || 0 +/** Accessing symbol of state STATE. */ +#define YY_ACCESSING_SYMBOL(State) YY_CAST (yysymbol_kind_t, yystos[State]) + +#if SLEIGHDEBUG || 0 +/* The user-facing name of the symbol whose (internal) number is + YYSYMBOL. No bounds checking. */ +static const char *yysymbol_name (yysymbol_kind_t yysymbol) YY_ATTRIBUTE_UNUSED; + /* YYTNAME[SYMBOL-NUM] -- String name of the symbol SYMBOL-NUM. First, the terminals, then, starting at YYNTOKENS, nonterminals. */ static const char *const yytname[] = { - "$end", "error", "$undefined", "OP_BOOL_OR", "OP_BOOL_AND", - "OP_BOOL_XOR", "'|'", "OP_OR", "';'", "'^'", "OP_XOR", "'&'", "OP_AND", - "OP_EQUAL", "OP_NOTEQUAL", "OP_FEQUAL", "OP_FNOTEQUAL", "'<'", "'>'", - "OP_GREATEQUAL", "OP_LESSEQUAL", "OP_SLESS", "OP_SGREATEQUAL", - "OP_SLESSEQUAL", "OP_SGREAT", "OP_FLESS", "OP_FGREAT", "OP_FLESSEQUAL", - "OP_FGREATEQUAL", "OP_LEFT", "OP_RIGHT", "OP_SRIGHT", "'+'", "'-'", - "OP_FADD", "OP_FSUB", "'*'", "'/'", "'%'", "OP_SDIV", "OP_SREM", - "OP_FMULT", "OP_FDIV", "'!'", "'~'", "OP_ZEXT", "OP_CARRY", "OP_BORROW", - "OP_SEXT", "OP_SCARRY", "OP_SBORROW", "OP_NAN", "OP_ABS", "OP_SQRT", - "OP_CEIL", "OP_FLOOR", "OP_ROUND", "OP_INT2FLOAT", "OP_FLOAT2FLOAT", - "OP_TRUNC", "OP_CPOOLREF", "OP_NEW", "OP_POPCOUNT", "OP_LZCOUNT", - "BADINTEGER", "GOTO_KEY", "CALL_KEY", "RETURN_KEY", "IF_KEY", - "DEFINE_KEY", "ATTACH_KEY", "MACRO_KEY", "SPACE_KEY", "TYPE_KEY", - "RAM_KEY", "DEFAULT_KEY", "REGISTER_KEY", "ENDIAN_KEY", "WITH_KEY", - "ALIGN_KEY", "OP_UNIMPL", "TOKEN_KEY", "SIGNED_KEY", "NOFLOW_KEY", - "HEX_KEY", "DEC_KEY", "BIG_KEY", "LITTLE_KEY", "SIZE_KEY", + "\"end of file\"", "error", "\"invalid token\"", "OP_BOOL_OR", + "OP_BOOL_AND", "OP_BOOL_XOR", "'|'", "OP_OR", "';'", "'^'", "OP_XOR", + "'&'", "OP_AND", "OP_EQUAL", "OP_NOTEQUAL", "OP_FEQUAL", "OP_FNOTEQUAL", + "'<'", "'>'", "OP_GREATEQUAL", "OP_LESSEQUAL", "OP_SLESS", + "OP_SGREATEQUAL", "OP_SLESSEQUAL", "OP_SGREAT", "OP_FLESS", "OP_FGREAT", + "OP_FLESSEQUAL", "OP_FGREATEQUAL", "OP_LEFT", "OP_RIGHT", "OP_SRIGHT", + "'+'", "'-'", "OP_FADD", "OP_FSUB", "'*'", "'/'", "'%'", "OP_SDIV", + "OP_SREM", "OP_FMULT", "OP_FDIV", "'!'", "'~'", "OP_ZEXT", "OP_CARRY", + "OP_BORROW", "OP_SEXT", "OP_SCARRY", "OP_SBORROW", "OP_NAN", "OP_ABS", + "OP_SQRT", "OP_CEIL", "OP_FLOOR", "OP_ROUND", "OP_INT2FLOAT", + "OP_FLOAT2FLOAT", "OP_TRUNC", "OP_CPOOLREF", "OP_NEW", "OP_POPCOUNT", + "OP_LZCOUNT", "BADINTEGER", "GOTO_KEY", "CALL_KEY", "RETURN_KEY", + "IF_KEY", "DEFINE_KEY", "ATTACH_KEY", "MACRO_KEY", "SPACE_KEY", + "TYPE_KEY", "RAM_KEY", "DEFAULT_KEY", "REGISTER_KEY", "ENDIAN_KEY", + "WITH_KEY", "ALIGN_KEY", "OP_UNIMPL", "TOKEN_KEY", "SIGNED_KEY", + "NOFLOW_KEY", "HEX_KEY", "DEC_KEY", "BIG_KEY", "LITTLE_KEY", "SIZE_KEY", "WORDSIZE_KEY", "OFFSET_KEY", "NAMES_KEY", "VALUES_KEY", "VARIABLES_KEY", "PCODEOP_KEY", "IS_KEY", "LOCAL_KEY", "DELAYSLOT_KEY", "CROSSBUILD_KEY", "EXPORT_KEY", "BUILD_KEY", "CONTEXT_KEY", "ELLIPSIS_KEY", @@ -783,9 +805,15 @@ static const char *const yytname[] = "stringpart", "anystringlist", "anystringpart", "valuelist", "valuepart", "varlist", "varpart", "paramlist", "oplist", "anysymbol", YY_NULLPTR }; + +static const char * +yysymbol_name (yysymbol_kind_t yysymbol) +{ + return yytname[yysymbol]; +} #endif -# ifdef YYPRINT +#ifdef YYPRINT /* YYTOKNUM[NUM] -- (External) token number corresponding to the (internal) symbol number NUM (which must be that of a token). */ static const yytype_int16 yytoknum[] = @@ -805,7 +833,7 @@ static const yytype_int16 yytoknum[] = 362, 363, 364, 365, 366, 367, 368, 125, 61, 40, 41, 44, 91, 93, 123, 58, 32 }; -# endif +#endif #define YYPACT_NINF (-293) @@ -1694,10 +1722,10 @@ static const yytype_int8 yyr2[] = }; +enum { YYENOMEM = -2 }; + #define yyerrok (yyerrstatus = 0) -#define yyclearin (yychar = YYEMPTY) -#define YYEMPTY (-2) -#define YYEOF 0 +#define yyclearin (yychar = SLEIGHEMPTY) #define YYACCEPT goto yyacceptlab #define YYABORT goto yyabortlab @@ -1708,7 +1736,7 @@ static const yytype_int8 yyr2[] = #define YYBACKUP(Token, Value) \ do \ - if (yychar == YYEMPTY) \ + if (yychar == SLEIGHEMPTY) \ { \ yychar = (Token); \ yylval = (Value); \ @@ -1723,10 +1751,9 @@ static const yytype_int8 yyr2[] = } \ while (0) -/* Error token number */ -#define YYTERROR 1 -#define YYERRCODE 256 - +/* Backward compatibility with an undocumented macro. + Use SLEIGHerror or SLEIGHUNDEF. */ +#define YYERRCODE SLEIGHUNDEF /* Enable debugging if requested. */ @@ -1744,18 +1771,18 @@ do { \ } while (0) /* This macro is provided for backward compatibility. */ -#ifndef YY_LOCATION_PRINT -# define YY_LOCATION_PRINT(File, Loc) ((void) 0) -#endif +# ifndef YY_LOCATION_PRINT +# define YY_LOCATION_PRINT(File, Loc) ((void) 0) +# endif -# define YY_SYMBOL_PRINT(Title, Type, Value, Location) \ +# define YY_SYMBOL_PRINT(Title, Kind, Value, Location) \ do { \ if (yydebug) \ { \ YYFPRINTF (stderr, "%s ", Title); \ yy_symbol_print (stderr, \ - Type, Value); \ + Kind, Value); \ YYFPRINTF (stderr, "\n"); \ } \ } while (0) @@ -1766,18 +1793,19 @@ do { \ `-----------------------------------*/ static void -yy_symbol_value_print (FILE *yyo, int yytype, YYSTYPE const * const yyvaluep) +yy_symbol_value_print (FILE *yyo, + yysymbol_kind_t yykind, YYSTYPE const * const yyvaluep) { FILE *yyoutput = yyo; YYUSE (yyoutput); if (!yyvaluep) return; # ifdef YYPRINT - if (yytype < YYNTOKENS) - YYPRINT (yyo, yytoknum[yytype], *yyvaluep); + if (yykind < YYNTOKENS) + YYPRINT (yyo, yytoknum[yykind], *yyvaluep); # endif YY_IGNORE_MAYBE_UNINITIALIZED_BEGIN - YYUSE (yytype); + YYUSE (yykind); YY_IGNORE_MAYBE_UNINITIALIZED_END } @@ -1787,12 +1815,13 @@ yy_symbol_value_print (FILE *yyo, int yytype, YYSTYPE const * const yyvaluep) `---------------------------*/ static void -yy_symbol_print (FILE *yyo, int yytype, YYSTYPE const * const yyvaluep) +yy_symbol_print (FILE *yyo, + yysymbol_kind_t yykind, YYSTYPE const * const yyvaluep) { YYFPRINTF (yyo, "%s %s (", - yytype < YYNTOKENS ? "token" : "nterm", yytname[yytype]); + yykind < YYNTOKENS ? "token" : "nterm", yysymbol_name (yykind)); - yy_symbol_value_print (yyo, yytype, yyvaluep); + yy_symbol_value_print (yyo, yykind, yyvaluep); YYFPRINTF (yyo, ")"); } @@ -1825,7 +1854,8 @@ do { \ `------------------------------------------------*/ static void -yy_reduce_print (yy_state_t *yyssp, YYSTYPE *yyvsp, int yyrule) +yy_reduce_print (yy_state_t *yyssp, YYSTYPE *yyvsp, + int yyrule) { int yylno = yyrline[yyrule]; int yynrhs = yyr2[yyrule]; @@ -1837,9 +1867,8 @@ yy_reduce_print (yy_state_t *yyssp, YYSTYPE *yyvsp, int yyrule) { YYFPRINTF (stderr, " $%d = ", yyi + 1); yy_symbol_print (stderr, - yystos[+yyssp[yyi + 1 - yynrhs]], - &yyvsp[(yyi + 1) - (yynrhs)] - ); + YY_ACCESSING_SYMBOL (+yyssp[yyi + 1 - yynrhs]), + &yyvsp[(yyi + 1) - (yynrhs)]); YYFPRINTF (stderr, "\n"); } } @@ -1854,8 +1883,8 @@ do { \ multiple parsers can coexist. */ int yydebug; #else /* !SLEIGHDEBUG */ -# define YYDPRINTF(Args) -# define YY_SYMBOL_PRINT(Title, Type, Value, Location) +# define YYDPRINTF(Args) ((void) 0) +# define YY_SYMBOL_PRINT(Title, Kind, Value, Location) # define YY_STACK_PRINT(Bottom, Top) # define YY_REDUCE_PRINT(Rule) #endif /* !SLEIGHDEBUG */ @@ -1878,259 +1907,202 @@ int yydebug; #endif -#if YYERROR_VERBOSE -# ifndef yystrlen -# if defined __GLIBC__ && defined _STRING_H -# define yystrlen(S) (YY_CAST (YYPTRDIFF_T, strlen (S))) -# else -/* Return the length of YYSTR. */ -static YYPTRDIFF_T -yystrlen (const char *yystr) -{ - YYPTRDIFF_T yylen; - for (yylen = 0; yystr[yylen]; yylen++) - continue; - return yylen; -} -# endif -# endif -# ifndef yystpcpy -# if defined __GLIBC__ && defined _STRING_H && defined _GNU_SOURCE -# define yystpcpy stpcpy -# else -/* Copy YYSRC to YYDEST, returning the address of the terminating '\0' in - YYDEST. */ -static char * -yystpcpy (char *yydest, const char *yysrc) -{ - char *yyd = yydest; - const char *yys = yysrc; - while ((*yyd++ = *yys++) != '\0') - continue; - return yyd - 1; -} -# endif -# endif +/*-----------------------------------------------. +| Release the memory associated to this symbol. | +`-----------------------------------------------*/ -# ifndef yytnamerr -/* Copy to YYRES the contents of YYSTR after stripping away unnecessary - quotes and backslashes, so that it's suitable for yyerror. The - heuristic is that double-quoting is unnecessary unless the string - contains an apostrophe, a comma, or backslash (other than - backslash-backslash). YYSTR is taken from yytname. If YYRES is - null, do not copy; instead, return the length of what the result - would have been. */ -static YYPTRDIFF_T -yytnamerr (char *yyres, const char *yystr) +static void +yydestruct (const char *yymsg, + yysymbol_kind_t yykind, YYSTYPE *yyvaluep) { - if (*yystr == '"') + YYUSE (yyvaluep); + if (!yymsg) + yymsg = "Deleting"; + YY_SYMBOL_PRINT (yymsg, yykind, yyvaluep, yylocationp); + + YY_IGNORE_MAYBE_UNINITIALIZED_BEGIN + switch (yykind) { - YYPTRDIFF_T yyn = 0; - char const *yyp = yystr; - - for (;;) - switch (*++yyp) - { - case '\'': - case ',': - goto do_not_strip_quotes; - - case '\\': - if (*++yyp != '\\') - goto do_not_strip_quotes; - else - goto append; - - append: - default: - if (yyres) - yyres[yyn] = *yyp; - yyn++; - break; - - case '"': - if (yyres) - yyres[yyn] = '\0'; - return yyn; - } - do_not_strip_quotes: ; - } + case YYSYMBOL_INTEGER: /* INTEGER */ + { delete ((*yyvaluep).i); } + break; - if (yyres) - return yystpcpy (yyres, yystr) - yyres; - else - return yystrlen (yystr); -} -# endif + case YYSYMBOL_INTB: /* INTB */ + { delete ((*yyvaluep).big); } + break; -/* Copy into *YYMSG, which is of size *YYMSG_ALLOC, an error message - about the unexpected token YYTOKEN for the state stack whose top is - YYSSP. - - Return 0 if *YYMSG was successfully written. Return 1 if *YYMSG is - not large enough to hold the message. In that case, also set - *YYMSG_ALLOC to the required number of bytes. Return 2 if the - required number of bytes is too large to store. */ -static int -yysyntax_error (YYPTRDIFF_T *yymsg_alloc, char **yymsg, - yy_state_t *yyssp, int yytoken) -{ - enum { YYERROR_VERBOSE_ARGS_MAXIMUM = 5 }; - /* Internationalized format string. */ - const char *yyformat = YY_NULLPTR; - /* Arguments of yyformat: reported tokens (one for the "unexpected", - one per "expected"). */ - char const *yyarg[YYERROR_VERBOSE_ARGS_MAXIMUM]; - /* Actual size of YYARG. */ - int yycount = 0; - /* Cumulated lengths of YYARG. */ - YYPTRDIFF_T yysize = 0; - - /* There are many possibilities here to consider: - - If this state is a consistent state with a default action, then - the only way this function was invoked is if the default action - is an error action. In that case, don't check for expected - tokens because there are none. - - The only way there can be no lookahead present (in yychar) is if - this state is a consistent state with a default action. Thus, - detecting the absence of a lookahead is sufficient to determine - that there is no unexpected or expected token to report. In that - case, just report a simple "syntax error". - - Don't assume there isn't a lookahead just because this state is a - consistent state with a default action. There might have been a - previous inconsistent state, consistent state with a non-default - action, or user semantic action that manipulated yychar. - - Of course, the expected token list depends on states to have - correct lookahead information, and it depends on the parser not - to perform extra reductions after fetching a lookahead from the - scanner and before detecting a syntax error. Thus, state merging - (from LALR or IELR) and default reductions corrupt the expected - token list. However, the list is correct for canonical LR with - one exception: it will still contain any token that will not be - accepted due to an error action in a later state. - */ - if (yytoken != YYEMPTY) - { - int yyn = yypact[+*yyssp]; - YYPTRDIFF_T yysize0 = yytnamerr (YY_NULLPTR, yytname[yytoken]); - yysize = yysize0; - yyarg[yycount++] = yytname[yytoken]; - if (!yypact_value_is_default (yyn)) - { - /* Start YYX at -YYN if negative to avoid negative indexes in - YYCHECK. In other words, skip the first -YYN actions for - this state because they are default actions. */ - int yyxbegin = yyn < 0 ? -yyn : 0; - /* Stay within bounds of both yycheck and yytname. */ - int yychecklim = YYLAST - yyn + 1; - int yyxend = yychecklim < YYNTOKENS ? yychecklim : YYNTOKENS; - int yyx; - - for (yyx = yyxbegin; yyx < yyxend; ++yyx) - if (yycheck[yyx + yyn] == yyx && yyx != YYTERROR - && !yytable_value_is_error (yytable[yyx + yyn])) - { - if (yycount == YYERROR_VERBOSE_ARGS_MAXIMUM) - { - yycount = 1; - yysize = yysize0; - break; - } - yyarg[yycount++] = yytname[yyx]; - { - YYPTRDIFF_T yysize1 - = yysize + yytnamerr (YY_NULLPTR, yytname[yyx]); - if (yysize <= yysize1 && yysize1 <= YYSTACK_ALLOC_MAXIMUM) - yysize = yysize1; - else - return 2; - } - } - } - } + case YYSYMBOL_STRING: /* STRING */ + { delete ((*yyvaluep).str); } + break; - switch (yycount) - { -# define YYCASE_(N, S) \ - case N: \ - yyformat = S; \ - break - default: /* Avoid compiler warnings. */ - YYCASE_(0, YY_("syntax error")); - YYCASE_(1, YY_("syntax error, unexpected %s")); - YYCASE_(2, YY_("syntax error, unexpected %s, expecting %s")); - YYCASE_(3, YY_("syntax error, unexpected %s, expecting %s or %s")); - YYCASE_(4, YY_("syntax error, unexpected %s, expecting %s or %s or %s")); - YYCASE_(5, YY_("syntax error, unexpected %s, expecting %s or %s or %s or %s")); -# undef YYCASE_ - } + case YYSYMBOL_SYMBOLSTRING: /* SYMBOLSTRING */ + { delete ((*yyvaluep).str); } + break; - { - /* Don't count the "%s"s in the final size, but reserve room for - the terminator. */ - YYPTRDIFF_T yysize1 = yysize + (yystrlen (yyformat) - 2 * yycount) + 1; - if (yysize <= yysize1 && yysize1 <= YYSTACK_ALLOC_MAXIMUM) - yysize = yysize1; - else - return 2; - } + case YYSYMBOL_fielddef: /* fielddef */ + { delete ((*yyvaluep).fieldqual); } + break; - if (*yymsg_alloc < yysize) - { - *yymsg_alloc = 2 * yysize; - if (! (yysize <= *yymsg_alloc - && *yymsg_alloc <= YYSTACK_ALLOC_MAXIMUM)) - *yymsg_alloc = YYSTACK_ALLOC_MAXIMUM; - return 1; - } + case YYSYMBOL_contextfielddef: /* contextfielddef */ + { delete ((*yyvaluep).fieldqual); } + break; - /* Avoid sprintf, as that infringes on the user's name space. - Don't have undefined behavior even if the translation - produced a string with the wrong number of "%s"s. */ - { - char *yyp = *yymsg; - int yyi = 0; - while ((*yyp = *yyformat) != '\0') - if (*yyp == '%' && yyformat[1] == 's' && yyi < yycount) - { - yyp += yytnamerr (yyp, yyarg[yyi++]); - yyformat += 2; - } - else - { - ++yyp; - ++yyformat; - } - } - return 0; -} -#endif /* YYERROR_VERBOSE */ + case YYSYMBOL_spaceprop: /* spaceprop */ + { delete ((*yyvaluep).spacequal); } + break; -/*-----------------------------------------------. -| Release the memory associated to this symbol. | -`-----------------------------------------------*/ + case YYSYMBOL_bitpat_or_nil: /* bitpat_or_nil */ + { if (((*yyvaluep).pateq)) PatternEquation::release(((*yyvaluep).pateq)); } + break; -static void -yydestruct (const char *yymsg, int yytype, YYSTYPE *yyvaluep) -{ - YYUSE (yyvaluep); - if (!yymsg) - yymsg = "Deleting"; - YY_SYMBOL_PRINT (yymsg, yytype, yyvaluep, yylocationp); + case YYSYMBOL_rtlbody: /* rtlbody */ + { delete ((*yyvaluep).sectionstart); } + break; - YY_IGNORE_MAYBE_UNINITIALIZED_BEGIN - YYUSE (yytype); - YY_IGNORE_MAYBE_UNINITIALIZED_END -} + case YYSYMBOL_pexpression: /* pexpression */ + { PatternExpression::release(((*yyvaluep).patexp)); } + break; + + case YYSYMBOL_pequation: /* pequation */ + { if (((*yyvaluep).pateq)) PatternEquation::release(((*yyvaluep).pateq)); } + break; + + case YYSYMBOL_elleq: /* elleq */ + { if (((*yyvaluep).pateq)) PatternEquation::release(((*yyvaluep).pateq)); } + break; + + case YYSYMBOL_ellrt: /* ellrt */ + { if (((*yyvaluep).pateq)) PatternEquation::release(((*yyvaluep).pateq)); } + break; + + case YYSYMBOL_atomic: /* atomic */ + { if (((*yyvaluep).pateq)) PatternEquation::release(((*yyvaluep).pateq)); } + break; + + case YYSYMBOL_constraint: /* constraint */ + { if (((*yyvaluep).pateq)) PatternEquation::release(((*yyvaluep).pateq)); } + break; + + case YYSYMBOL_contextblock: /* contextblock */ + { delete ((*yyvaluep).contop); } + break; + + case YYSYMBOL_contextlist: /* contextlist */ + { delete ((*yyvaluep).contop); } + break; + + case YYSYMBOL_rtlfirstsection: /* rtlfirstsection */ + { delete ((*yyvaluep).sectionstart); } + break; + + case YYSYMBOL_rtlcontinue: /* rtlcontinue */ + { delete ((*yyvaluep).sectionstart); } + break; + + case YYSYMBOL_rtl: /* rtl */ + { delete ((*yyvaluep).sem); } + break; + + case YYSYMBOL_rtlmid: /* rtlmid */ + { delete ((*yyvaluep).sem); } + break; + + case YYSYMBOL_statement: /* statement */ + { delete ((*yyvaluep).stmt); } + break; + + case YYSYMBOL_expr: /* expr */ + { delete ((*yyvaluep).tree); } + break; + + case YYSYMBOL_sizedstar: /* sizedstar */ + { delete ((*yyvaluep).starqual); } + break; + + case YYSYMBOL_jumpdest: /* jumpdest */ + { delete ((*yyvaluep).varnode); } + break; + + case YYSYMBOL_varnode: /* varnode */ + { delete ((*yyvaluep).varnode); } + break; + + case YYSYMBOL_integervarnode: /* integervarnode */ + { delete ((*yyvaluep).varnode); } + break; + + case YYSYMBOL_lhsvarnode: /* lhsvarnode */ + { delete ((*yyvaluep).varnode); } + break; + + case YYSYMBOL_exportvarnode: /* exportvarnode */ + { delete ((*yyvaluep).varnode); } + break; + + case YYSYMBOL_charstring: /* charstring */ + { delete ((*yyvaluep).str); } + break; + + case YYSYMBOL_intblist: /* intblist */ + { delete ((*yyvaluep).biglist); } + break; + + case YYSYMBOL_intbpart: /* intbpart */ + { delete ((*yyvaluep).biglist); } + break; + case YYSYMBOL_stringlist: /* stringlist */ + { delete ((*yyvaluep).strlist); } + break; + case YYSYMBOL_stringpart: /* stringpart */ + { delete ((*yyvaluep).strlist); } + break; + case YYSYMBOL_anystringlist: /* anystringlist */ + { delete ((*yyvaluep).strlist); } + break; -/* The lookahead symbol. */ + case YYSYMBOL_anystringpart: /* anystringpart */ + { delete ((*yyvaluep).strlist); } + break; + + case YYSYMBOL_valuelist: /* valuelist */ + { delete ((*yyvaluep).symlist); } + break; + + case YYSYMBOL_valuepart: /* valuepart */ + { delete ((*yyvaluep).symlist); } + break; + + case YYSYMBOL_varlist: /* varlist */ + { delete ((*yyvaluep).symlist); } + break; + + case YYSYMBOL_varpart: /* varpart */ + { delete ((*yyvaluep).symlist); } + break; + + case YYSYMBOL_paramlist: /* paramlist */ + { delete ((*yyvaluep).param); } + break; + + case YYSYMBOL_oplist: /* oplist */ + { delete ((*yyvaluep).strlist); } + break; + + default: + break; + } + YY_IGNORE_MAYBE_UNINITIALIZED_END +} + + +/* Lookahead token kind. */ int yychar; /* The semantic value of the lookahead symbol. */ @@ -2139,6 +2111,8 @@ YYSTYPE yylval; int yynerrs; + + /*----------. | yyparse. | `----------*/ @@ -2146,43 +2120,36 @@ int yynerrs; int yyparse (void) { - yy_state_fast_t yystate; + yy_state_fast_t yystate = 0; /* Number of tokens to shift before error messages enabled. */ - int yyerrstatus; - - /* The stacks and their tools: - 'yyss': related to states. - 'yyvs': related to semantic values. + int yyerrstatus = 0; - Refer to the stacks through separate pointers, to allow yyoverflow + /* Refer to the stacks through separate pointers, to allow yyoverflow to reallocate them elsewhere. */ - /* The state stack. */ + /* Their size. */ + YYPTRDIFF_T yystacksize = YYINITDEPTH; + + /* The state stack: array, bottom, top. */ yy_state_t yyssa[YYINITDEPTH]; - yy_state_t *yyss; - yy_state_t *yyssp; + yy_state_t *yyss = yyssa; + yy_state_t *yyssp = yyss; - /* The semantic value stack. */ + /* The semantic value stack: array, bottom, top. */ YYSTYPE yyvsa[YYINITDEPTH]; - YYSTYPE *yyvs; - YYSTYPE *yyvsp; - - YYPTRDIFF_T yystacksize; + YYSTYPE *yyvs = yyvsa; + YYSTYPE *yyvsp = yyvs; int yyn; + /* The return value of yyparse. */ int yyresult; - /* Lookahead token as an internal (translated) token number. */ - int yytoken = 0; + /* Lookahead symbol kind. */ + yysymbol_kind_t yytoken = YYSYMBOL_YYEMPTY; /* The variables used to return semantic value and location from the action routines. */ YYSTYPE yyval; -#if YYERROR_VERBOSE - /* Buffer for error messages, and its allocated size. */ - char yymsgbuf[128]; - char *yymsg = yymsgbuf; - YYPTRDIFF_T yymsg_alloc = sizeof yymsgbuf; -#endif + #define YYPOPSTACK(N) (yyvsp -= (N), yyssp -= (N)) @@ -2190,16 +2157,9 @@ yyparse (void) Keep to zero when no symbol should be popped. */ int yylen = 0; - yyssp = yyss = yyssa; - yyvsp = yyvs = yyvsa; - yystacksize = YYINITDEPTH; - YYDPRINTF ((stderr, "Starting parse\n")); - yystate = 0; - yyerrstatus = 0; - yynerrs = 0; - yychar = YYEMPTY; /* Cause a token to be read. */ + yychar = SLEIGHEMPTY; /* Cause a token to be read. */ goto yysetstate; @@ -2221,6 +2181,7 @@ yyparse (void) YY_IGNORE_USELESS_CAST_BEGIN *yyssp = YY_CAST (yy_state_t, yystate); YY_IGNORE_USELESS_CAST_END + YY_STACK_PRINT (yyss, yyssp); if (yyss + yystacksize - 1 <= yyssp) #if !defined yyoverflow && !defined YYSTACK_RELOCATE @@ -2266,7 +2227,7 @@ yyparse (void) goto yyexhaustedlab; YYSTACK_RELOCATE (yyss_alloc, yyss); YYSTACK_RELOCATE (yyvs_alloc, yyvs); -# undef YYSTACK_RELOCATE +# undef YYSTACK_RELOCATE if (yyss1 != yyssa) YYSTACK_FREE (yyss1); } @@ -2305,18 +2266,29 @@ yyparse (void) /* Not known => get a lookahead token if don't already have one. */ - /* YYCHAR is either YYEMPTY or YYEOF or a valid lookahead symbol. */ - if (yychar == YYEMPTY) + /* YYCHAR is either empty, or end-of-input, or a valid lookahead. */ + if (yychar == SLEIGHEMPTY) { - YYDPRINTF ((stderr, "Reading a token: ")); + YYDPRINTF ((stderr, "Reading a token\n")); yychar = yylex (); } - if (yychar <= YYEOF) + if (yychar <= SLEIGHEOF) { - yychar = yytoken = YYEOF; + yychar = SLEIGHEOF; + yytoken = YYSYMBOL_YYEOF; YYDPRINTF ((stderr, "Now at end of input.\n")); } + else if (yychar == SLEIGHerror) + { + /* The scanner already issued an error message, process directly + to error recovery. But do not keep the error token as + lookahead, it is too special and may lead us to an endless + loop in error recovery. */ + yychar = SLEIGHUNDEF; + yytoken = YYSYMBOL_YYerror; + goto yyerrlab1; + } else { yytoken = YYTRANSLATE (yychar); @@ -2350,7 +2322,7 @@ yyparse (void) YY_IGNORE_MAYBE_UNINITIALIZED_END /* Discard the shifted token. */ - yychar = YYEMPTY; + yychar = SLEIGHEMPTY; goto yynewstate; @@ -2385,1245 +2357,1245 @@ yyparse (void) YY_REDUCE_PRINT (yyn); switch (yyn) { - case 19: + case 19: /* constructorlike: error '}' */ { slgh->resetConstructors(); } break; - case 20: + case 20: /* endiandef: DEFINE_KEY ENDIAN_KEY '=' BIG_KEY ';' */ { slgh->setEndian(1); } break; - case 21: + case 21: /* endiandef: DEFINE_KEY ENDIAN_KEY '=' LITTLE_KEY ';' */ { slgh->setEndian(0); } break; - case 22: + case 22: /* aligndef: DEFINE_KEY ALIGN_KEY '=' INTEGER ';' */ { slgh->setAlignment(*(yyvsp[-1].i)); delete (yyvsp[-1].i); } break; - case 23: + case 23: /* tokendef: tokenprop ';' */ {} break; - case 24: + case 24: /* tokenprop: DEFINE_KEY TOKEN_KEY STRING '(' INTEGER ')' */ { (yyval.tokensym) = slgh->defineToken((yyvsp[-3].str),(yyvsp[-1].i),0); } break; - case 25: + case 25: /* tokenprop: DEFINE_KEY TOKEN_KEY STRING '(' INTEGER ')' ENDIAN_KEY '=' LITTLE_KEY */ { (yyval.tokensym) = slgh->defineToken((yyvsp[-6].str),(yyvsp[-4].i),-1); } break; - case 26: + case 26: /* tokenprop: DEFINE_KEY TOKEN_KEY STRING '(' INTEGER ')' ENDIAN_KEY '=' BIG_KEY */ { (yyval.tokensym) = slgh->defineToken((yyvsp[-6].str),(yyvsp[-4].i),1); } break; - case 27: + case 27: /* tokenprop: tokenprop fielddef */ { (yyval.tokensym) = (yyvsp[-1].tokensym); slgh->addTokenField((yyvsp[-1].tokensym),(yyvsp[0].fieldqual)); } break; - case 28: + case 28: /* tokenprop: DEFINE_KEY TOKEN_KEY anysymbol */ { string errmsg=(yyvsp[0].anysym)->getName()+": redefined as a token"; slgh->reportError(errmsg); YYERROR; } break; - case 29: + case 29: /* contextdef: contextprop ';' */ {} break; - case 30: + case 30: /* contextprop: DEFINE_KEY CONTEXT_KEY VARSYM */ { (yyval.varsym) = (yyvsp[0].varsym); } break; - case 31: + case 31: /* contextprop: contextprop contextfielddef */ { (yyval.varsym) = (yyvsp[-1].varsym); if (!slgh->addContextField( (yyvsp[-1].varsym), (yyvsp[0].fieldqual) )) { slgh->reportError("All context definitions must come before constructors"); YYERROR; } } break; - case 32: + case 32: /* fielddef: STRING '=' '(' INTEGER ',' INTEGER ')' */ { (yyval.fieldqual) = new FieldQuality((yyvsp[-6].str),(yyvsp[-3].i),(yyvsp[-1].i)); } break; - case 33: - { delete (yyvsp[-3].i); delete (yyvsp[-1].i); string errmsg = (yyvsp[-6].anysym)->getName()+": redefined as field"; slgh->reportError(errmsg); YYERROR; } + case 33: /* fielddef: anysymbol '=' '(' INTEGER ',' INTEGER ')' */ + { (yyval.fieldqual) = (FieldQuality *)0; delete (yyvsp[-3].i); delete (yyvsp[-1].i); string errmsg = (yyvsp[-6].anysym)->getName()+": redefined as field"; slgh->reportError(errmsg); YYERROR; } break; - case 34: + case 34: /* fielddef: fielddef SIGNED_KEY */ { (yyval.fieldqual) = (yyvsp[-1].fieldqual); (yyval.fieldqual)->signext = true; } break; - case 35: + case 35: /* fielddef: fielddef HEX_KEY */ { (yyval.fieldqual) = (yyvsp[-1].fieldqual); (yyval.fieldqual)->hex = true; } break; - case 36: + case 36: /* fielddef: fielddef DEC_KEY */ { (yyval.fieldqual) = (yyvsp[-1].fieldqual); (yyval.fieldqual)->hex = false; } break; - case 37: + case 37: /* contextfielddef: STRING '=' '(' INTEGER ',' INTEGER ')' */ { (yyval.fieldqual) = new FieldQuality((yyvsp[-6].str),(yyvsp[-3].i),(yyvsp[-1].i)); } break; - case 38: - { delete (yyvsp[-3].i); delete (yyvsp[-1].i); string errmsg = (yyvsp[-6].anysym)->getName()+": redefined as field"; slgh->reportError(errmsg); YYERROR; } + case 38: /* contextfielddef: anysymbol '=' '(' INTEGER ',' INTEGER ')' */ + { (yyval.fieldqual) = (FieldQuality *)0; delete (yyvsp[-3].i); delete (yyvsp[-1].i); string errmsg = (yyvsp[-6].anysym)->getName()+": redefined as field"; slgh->reportError(errmsg); YYERROR; } break; - case 39: + case 39: /* contextfielddef: contextfielddef SIGNED_KEY */ { (yyval.fieldqual) = (yyvsp[-1].fieldqual); (yyval.fieldqual)->signext = true; } break; - case 40: + case 40: /* contextfielddef: contextfielddef NOFLOW_KEY */ { (yyval.fieldqual) = (yyvsp[-1].fieldqual); (yyval.fieldqual)->flow = false; } break; - case 41: + case 41: /* contextfielddef: contextfielddef HEX_KEY */ { (yyval.fieldqual) = (yyvsp[-1].fieldqual); (yyval.fieldqual)->hex = true; } break; - case 42: + case 42: /* contextfielddef: contextfielddef DEC_KEY */ { (yyval.fieldqual) = (yyvsp[-1].fieldqual); (yyval.fieldqual)->hex = false; } break; - case 43: + case 43: /* spacedef: spaceprop ';' */ { slgh->newSpace((yyvsp[-1].spacequal)); } break; - case 44: + case 44: /* spaceprop: DEFINE_KEY SPACE_KEY STRING */ { (yyval.spacequal) = new SpaceQuality(*(yyvsp[0].str)); delete (yyvsp[0].str); } break; - case 45: - { string errmsg = (yyvsp[0].anysym)->getName()+": redefined as space"; slgh->reportError(errmsg); YYERROR; } + case 45: /* spaceprop: DEFINE_KEY SPACE_KEY anysymbol */ + { (yyval.spacequal) = (SpaceQuality *)0; string errmsg = (yyvsp[0].anysym)->getName()+": redefined as space"; slgh->reportError(errmsg); YYERROR; } break; - case 46: + case 46: /* spaceprop: spaceprop TYPE_KEY '=' RAM_KEY */ { (yyval.spacequal) = (yyvsp[-3].spacequal); (yyval.spacequal)->type = SpaceQuality::ramtype; } break; - case 47: + case 47: /* spaceprop: spaceprop TYPE_KEY '=' REGISTER_KEY */ { (yyval.spacequal) = (yyvsp[-3].spacequal); (yyval.spacequal)->type = SpaceQuality::registertype; } break; - case 48: + case 48: /* spaceprop: spaceprop SIZE_KEY '=' INTEGER */ { (yyval.spacequal) = (yyvsp[-3].spacequal); (yyval.spacequal)->size = *(yyvsp[0].i); delete (yyvsp[0].i); } break; - case 49: + case 49: /* spaceprop: spaceprop WORDSIZE_KEY '=' INTEGER */ { (yyval.spacequal) = (yyvsp[-3].spacequal); (yyval.spacequal)->wordsize = *(yyvsp[0].i); delete (yyvsp[0].i); } break; - case 50: + case 50: /* spaceprop: spaceprop DEFAULT_KEY */ { (yyval.spacequal) = (yyvsp[-1].spacequal); (yyval.spacequal)->isdefault = true; } break; - case 51: + case 51: /* varnodedef: DEFINE_KEY SPACESYM OFFSET_KEY '=' INTEGER SIZE_KEY '=' INTEGER stringlist ';' */ { slgh->defineVarnodes((yyvsp[-8].spacesym),(yyvsp[-5].i),(yyvsp[-2].i),(yyvsp[-1].strlist)); } break; - case 52: + case 52: /* varnodedef: DEFINE_KEY SPACESYM OFFSET_KEY '=' BADINTEGER */ { slgh->reportError("Parsed integer is too big (overflow)"); YYERROR; } break; - case 56: + case 56: /* bitrangesingle: STRING '=' VARSYM '[' INTEGER ',' INTEGER ']' */ { slgh->defineBitrange((yyvsp[-7].str),(yyvsp[-5].varsym),(uint4)*(yyvsp[-3].i),(uint4)*(yyvsp[-1].i)); delete (yyvsp[-3].i); delete (yyvsp[-1].i); } break; - case 57: + case 57: /* pcodeopdef: DEFINE_KEY PCODEOP_KEY stringlist ';' */ { slgh->addUserOp((yyvsp[-1].strlist)); } break; - case 58: + case 58: /* valueattach: ATTACH_KEY VALUES_KEY valuelist intblist ';' */ { slgh->attachValues((yyvsp[-2].symlist),(yyvsp[-1].biglist)); } break; - case 59: + case 59: /* nameattach: ATTACH_KEY NAMES_KEY valuelist anystringlist ';' */ { slgh->attachNames((yyvsp[-2].symlist),(yyvsp[-1].strlist)); } break; - case 60: + case 60: /* varattach: ATTACH_KEY VARIABLES_KEY valuelist varlist ';' */ { slgh->attachVarnodes((yyvsp[-2].symlist),(yyvsp[-1].symlist)); } break; - case 61: + case 61: /* macrodef: macrostart '{' rtl '}' */ { slgh->buildMacro((yyvsp[-3].macrosym),(yyvsp[-1].sem)); } break; - case 62: + case 62: /* withblockstart: WITH_KEY id_or_nil ':' bitpat_or_nil contextblock '{' */ { slgh->pushWith((yyvsp[-4].subtablesym),(yyvsp[-2].pateq),(yyvsp[-1].contop)); } break; - case 66: + case 66: /* withblock: withblockmid '}' */ { slgh->popWith(); } break; - case 67: + case 67: /* id_or_nil: %empty */ { (yyval.subtablesym) = (SubtableSymbol *)0; } break; - case 68: + case 68: /* id_or_nil: SUBTABLESYM */ { (yyval.subtablesym) = (yyvsp[0].subtablesym); } break; - case 69: + case 69: /* id_or_nil: STRING */ { (yyval.subtablesym) = slgh->newTable((yyvsp[0].str)); } break; - case 70: + case 70: /* bitpat_or_nil: %empty */ { (yyval.pateq) = (PatternEquation *)0; } break; - case 71: + case 71: /* bitpat_or_nil: pequation */ { (yyval.pateq) = (yyvsp[0].pateq); } break; - case 72: + case 72: /* macrostart: MACRO_KEY STRING '(' oplist ')' */ { (yyval.macrosym) = slgh->createMacro((yyvsp[-3].str),(yyvsp[-1].strlist)); } break; - case 73: + case 73: /* rtlbody: '{' rtl '}' */ { (yyval.sectionstart) = slgh->standaloneSection((yyvsp[-1].sem)); } break; - case 74: + case 74: /* rtlbody: '{' rtlcontinue rtlmid '}' */ { (yyval.sectionstart) = slgh->finalNamedSection((yyvsp[-2].sectionstart),(yyvsp[-1].sem)); } break; - case 75: + case 75: /* rtlbody: OP_UNIMPL */ { (yyval.sectionstart) = (SectionVector *)0; } break; - case 76: + case 76: /* constructor: constructprint IS_KEY pequation contextblock rtlbody */ { slgh->buildConstructor((yyvsp[-4].construct),(yyvsp[-2].pateq),(yyvsp[-1].contop),(yyvsp[0].sectionstart)); } break; - case 77: + case 77: /* constructor: subtablestart IS_KEY pequation contextblock rtlbody */ { slgh->buildConstructor((yyvsp[-4].construct),(yyvsp[-2].pateq),(yyvsp[-1].contop),(yyvsp[0].sectionstart)); } break; - case 78: + case 78: /* constructprint: subtablestart STRING */ { (yyval.construct) = (yyvsp[-1].construct); (yyval.construct)->addSyntax(*(yyvsp[0].str)); delete (yyvsp[0].str); } break; - case 79: + case 79: /* constructprint: subtablestart charstring */ { (yyval.construct) = (yyvsp[-1].construct); (yyval.construct)->addSyntax(*(yyvsp[0].str)); delete (yyvsp[0].str); } break; - case 80: + case 80: /* constructprint: subtablestart SYMBOLSTRING */ { (yyval.construct) = (yyvsp[-1].construct); if (slgh->isInRoot((yyvsp[-1].construct))) { (yyval.construct)->addSyntax(*(yyvsp[0].str)); delete (yyvsp[0].str); } else slgh->newOperand((yyvsp[-1].construct),(yyvsp[0].str)); } break; - case 81: + case 81: /* constructprint: subtablestart '^' */ { (yyval.construct) = (yyvsp[-1].construct); if (!slgh->isInRoot((yyvsp[-1].construct))) { slgh->reportError("Unexpected '^' at start of print pieces"); YYERROR; } } break; - case 82: + case 82: /* constructprint: constructprint '^' */ { (yyval.construct) = (yyvsp[-1].construct); } break; - case 83: + case 83: /* constructprint: constructprint STRING */ { (yyval.construct) = (yyvsp[-1].construct); (yyval.construct)->addSyntax(*(yyvsp[0].str)); delete (yyvsp[0].str); } break; - case 84: + case 84: /* constructprint: constructprint charstring */ { (yyval.construct) = (yyvsp[-1].construct); (yyval.construct)->addSyntax(*(yyvsp[0].str)); delete (yyvsp[0].str); } break; - case 85: + case 85: /* constructprint: constructprint ' ' */ { (yyval.construct) = (yyvsp[-1].construct); (yyval.construct)->addSyntax(string(" ")); } break; - case 86: + case 86: /* constructprint: constructprint SYMBOLSTRING */ { (yyval.construct) = (yyvsp[-1].construct); slgh->newOperand((yyvsp[-1].construct),(yyvsp[0].str)); } break; - case 87: + case 87: /* subtablestart: SUBTABLESYM ':' */ { (yyval.construct) = slgh->createConstructor((yyvsp[-1].subtablesym)); } break; - case 88: + case 88: /* subtablestart: STRING ':' */ { SubtableSymbol *sym=slgh->newTable((yyvsp[-1].str)); (yyval.construct) = slgh->createConstructor(sym); } break; - case 89: + case 89: /* subtablestart: ':' */ { (yyval.construct) = slgh->createConstructor((SubtableSymbol *)0); } break; - case 90: + case 90: /* subtablestart: subtablestart ' ' */ { (yyval.construct) = (yyvsp[-1].construct); } break; - case 91: + case 91: /* pexpression: INTB */ { (yyval.patexp) = new ConstantValue(*(yyvsp[0].big)); delete (yyvsp[0].big); } break; - case 92: + case 92: /* pexpression: familysymbol */ { if ((actionon==1)&&((yyvsp[0].famsym)->getType() != SleighSymbol::context_symbol)) { string errmsg="Global symbol "+(yyvsp[0].famsym)->getName(); errmsg += " is not allowed in action expression"; slgh->reportError(errmsg); } (yyval.patexp) = (yyvsp[0].famsym)->getPatternValue(); } break; - case 93: + case 93: /* pexpression: specificsymbol */ { (yyval.patexp) = (yyvsp[0].specsym)->getPatternExpression(); } break; - case 94: + case 94: /* pexpression: '(' pexpression ')' */ { (yyval.patexp) = (yyvsp[-1].patexp); } break; - case 95: + case 95: /* pexpression: pexpression '+' pexpression */ { (yyval.patexp) = new PlusExpression((yyvsp[-2].patexp),(yyvsp[0].patexp)); } break; - case 96: + case 96: /* pexpression: pexpression '-' pexpression */ { (yyval.patexp) = new SubExpression((yyvsp[-2].patexp),(yyvsp[0].patexp)); } break; - case 97: + case 97: /* pexpression: pexpression '*' pexpression */ { (yyval.patexp) = new MultExpression((yyvsp[-2].patexp),(yyvsp[0].patexp)); } break; - case 98: + case 98: /* pexpression: pexpression OP_LEFT pexpression */ { (yyval.patexp) = new LeftShiftExpression((yyvsp[-2].patexp),(yyvsp[0].patexp)); } break; - case 99: + case 99: /* pexpression: pexpression OP_RIGHT pexpression */ { (yyval.patexp) = new RightShiftExpression((yyvsp[-2].patexp),(yyvsp[0].patexp)); } break; - case 100: + case 100: /* pexpression: pexpression OP_AND pexpression */ { (yyval.patexp) = new AndExpression((yyvsp[-2].patexp),(yyvsp[0].patexp)); } break; - case 101: + case 101: /* pexpression: pexpression OP_OR pexpression */ { (yyval.patexp) = new OrExpression((yyvsp[-2].patexp),(yyvsp[0].patexp)); } break; - case 102: + case 102: /* pexpression: pexpression OP_XOR pexpression */ { (yyval.patexp) = new XorExpression((yyvsp[-2].patexp),(yyvsp[0].patexp)); } break; - case 103: + case 103: /* pexpression: pexpression '/' pexpression */ { (yyval.patexp) = new DivExpression((yyvsp[-2].patexp),(yyvsp[0].patexp)); } break; - case 104: + case 104: /* pexpression: '-' pexpression */ { (yyval.patexp) = new MinusExpression((yyvsp[0].patexp)); } break; - case 105: + case 105: /* pexpression: '~' pexpression */ { (yyval.patexp) = new NotExpression((yyvsp[0].patexp)); } break; - case 107: + case 107: /* pequation: pequation '&' pequation */ { (yyval.pateq) = new EquationAnd((yyvsp[-2].pateq),(yyvsp[0].pateq)); } break; - case 108: + case 108: /* pequation: pequation '|' pequation */ { (yyval.pateq) = new EquationOr((yyvsp[-2].pateq),(yyvsp[0].pateq)); } break; - case 109: + case 109: /* pequation: pequation ';' pequation */ { (yyval.pateq) = new EquationCat((yyvsp[-2].pateq),(yyvsp[0].pateq)); } break; - case 110: + case 110: /* elleq: ELLIPSIS_KEY ellrt */ { (yyval.pateq) = new EquationLeftEllipsis((yyvsp[0].pateq)); } break; - case 112: + case 112: /* ellrt: atomic ELLIPSIS_KEY */ { (yyval.pateq) = new EquationRightEllipsis((yyvsp[-1].pateq)); } break; - case 115: + case 115: /* atomic: '(' pequation ')' */ { (yyval.pateq) = (yyvsp[-1].pateq); } break; - case 116: + case 116: /* constraint: familysymbol '=' pexpression */ { (yyval.pateq) = new EqualEquation((yyvsp[-2].famsym)->getPatternValue(),(yyvsp[0].patexp)); } break; - case 117: + case 117: /* constraint: familysymbol OP_NOTEQUAL pexpression */ { (yyval.pateq) = new NotEqualEquation((yyvsp[-2].famsym)->getPatternValue(),(yyvsp[0].patexp)); } break; - case 118: + case 118: /* constraint: familysymbol '<' pexpression */ { (yyval.pateq) = new LessEquation((yyvsp[-2].famsym)->getPatternValue(),(yyvsp[0].patexp)); } break; - case 119: + case 119: /* constraint: familysymbol OP_LESSEQUAL pexpression */ { (yyval.pateq) = new LessEqualEquation((yyvsp[-2].famsym)->getPatternValue(),(yyvsp[0].patexp)); } break; - case 120: + case 120: /* constraint: familysymbol '>' pexpression */ { (yyval.pateq) = new GreaterEquation((yyvsp[-2].famsym)->getPatternValue(),(yyvsp[0].patexp)); } break; - case 121: + case 121: /* constraint: familysymbol OP_GREATEQUAL pexpression */ { (yyval.pateq) = new GreaterEqualEquation((yyvsp[-2].famsym)->getPatternValue(),(yyvsp[0].patexp)); } break; - case 122: + case 122: /* constraint: OPERANDSYM '=' pexpression */ { (yyval.pateq) = slgh->constrainOperand((yyvsp[-2].operandsym),(yyvsp[0].patexp)); if ((yyval.pateq) == (PatternEquation *)0) { string errmsg="Constraining currently undefined operand "+(yyvsp[-2].operandsym)->getName(); slgh->reportError(errmsg); } } break; - case 123: + case 123: /* constraint: OPERANDSYM */ { (yyval.pateq) = new OperandEquation((yyvsp[0].operandsym)->getIndex()); slgh->selfDefine((yyvsp[0].operandsym)); } break; - case 124: + case 124: /* constraint: SPECSYM */ { (yyval.pateq) = new UnconstrainedEquation((yyvsp[0].specsym)->getPatternExpression()); } break; - case 125: + case 125: /* constraint: familysymbol */ { (yyval.pateq) = slgh->defineInvisibleOperand((yyvsp[0].famsym)); } break; - case 126: + case 126: /* constraint: SUBTABLESYM */ { (yyval.pateq) = slgh->defineInvisibleOperand((yyvsp[0].subtablesym)); } break; - case 127: + case 127: /* contextblock: %empty */ { (yyval.contop) = (vector *)0; } break; - case 128: + case 128: /* contextblock: '[' contextlist ']' */ { (yyval.contop) = (yyvsp[-1].contop); } break; - case 129: + case 129: /* contextlist: %empty */ { (yyval.contop) = new vector; } break; - case 130: - { (yyval.contop) = (yyvsp[-4].contop); if (!slgh->contextMod((yyvsp[-4].contop),(yyvsp[-3].contextsym),(yyvsp[-1].patexp))) { string errmsg="Cannot use 'inst_next' or 'inst_next2' to set context variable: "+(yyvsp[-3].contextsym)->getName(); slgh->reportError(errmsg); YYERROR; } } + case 130: /* contextlist: contextlist CONTEXTSYM '=' pexpression ';' */ + { (yyval.contop) = (yyvsp[-4].contop); if (!slgh->contextMod((yyvsp[-4].contop),(yyvsp[-3].contextsym),(yyvsp[-1].patexp))) { string errmsg="Cannot use 'inst_next' or 'inst_next2' to set context variable: "+(yyvsp[-3].contextsym)->getName(); slgh->reportError(errmsg); delete (yyvsp[-4].contop); (yyvsp[-1].patexp)->layClaim(); PatternExpression::release((yyvsp[-1].patexp)); YYERROR; } } break; - case 131: + case 131: /* contextlist: contextlist GLOBALSET_KEY '(' familysymbol ',' CONTEXTSYM ')' ';' */ { (yyval.contop) = (yyvsp[-7].contop); slgh->contextSet((yyvsp[-7].contop),(yyvsp[-4].famsym),(yyvsp[-2].contextsym)); } break; - case 132: + case 132: /* contextlist: contextlist GLOBALSET_KEY '(' specificsymbol ',' CONTEXTSYM ')' ';' */ { (yyval.contop) = (yyvsp[-7].contop); slgh->contextSet((yyvsp[-7].contop),(yyvsp[-4].specsym),(yyvsp[-2].contextsym)); } break; - case 133: + case 133: /* contextlist: contextlist OPERANDSYM '=' pexpression ';' */ { (yyval.contop) = (yyvsp[-4].contop); slgh->defineOperand((yyvsp[-3].operandsym),(yyvsp[-1].patexp)); } break; - case 134: - { string errmsg="Expecting context symbol, not "+*(yyvsp[0].str); delete (yyvsp[0].str); slgh->reportError(errmsg); YYERROR; } + case 134: /* contextlist: contextlist STRING */ + { (yyval.contop) = (vector *)0; delete (yyvsp[-1].contop); string errmsg="Expecting context symbol, not "+*(yyvsp[0].str); delete (yyvsp[0].str); slgh->reportError(errmsg); YYERROR; } break; - case 135: + case 135: /* section_def: OP_LEFT STRING OP_RIGHT */ { (yyval.sectionsym) = slgh->newSectionSymbol( *(yyvsp[-1].str) ); delete (yyvsp[-1].str); } break; - case 136: + case 136: /* section_def: OP_LEFT SECTIONSYM OP_RIGHT */ { (yyval.sectionsym) = (yyvsp[-1].sectionsym); } break; - case 137: + case 137: /* rtlfirstsection: rtl section_def */ { (yyval.sectionstart) = slgh->firstNamedSection((yyvsp[-1].sem),(yyvsp[0].sectionsym)); } break; - case 138: + case 138: /* rtlcontinue: rtlfirstsection */ { (yyval.sectionstart) = (yyvsp[0].sectionstart); } break; - case 139: + case 139: /* rtlcontinue: rtlcontinue rtlmid section_def */ { (yyval.sectionstart) = slgh->nextNamedSection((yyvsp[-2].sectionstart),(yyvsp[-1].sem),(yyvsp[0].sectionsym)); } break; - case 140: + case 140: /* rtl: rtlmid */ { (yyval.sem) = (yyvsp[0].sem); if ((yyval.sem)->getOpvec().empty() && ((yyval.sem)->getResult() == (HandleTpl *)0)) slgh->recordNop(); } break; - case 141: + case 141: /* rtl: rtlmid EXPORT_KEY exportvarnode ';' */ { (yyval.sem) = slgh->setResultVarnode((yyvsp[-3].sem),(yyvsp[-1].varnode)); } break; - case 142: + case 142: /* rtl: rtlmid EXPORT_KEY sizedstar lhsvarnode ';' */ { (yyval.sem) = slgh->setResultStarVarnode((yyvsp[-4].sem),(yyvsp[-2].starqual),(yyvsp[-1].varnode)); } break; - case 143: - { string errmsg="Unknown export varnode: "+*(yyvsp[0].str); delete (yyvsp[0].str); slgh->reportError(errmsg); YYERROR; } + case 143: /* rtl: rtlmid EXPORT_KEY STRING */ + { (yyval.sem) = (ConstructTpl *)0; delete (yyvsp[-2].sem); string errmsg="Unknown export varnode: "+*(yyvsp[0].str); delete (yyvsp[0].str); slgh->reportError(errmsg); YYERROR; } break; - case 144: - { string errmsg="Unknown pointer varnode: "+*(yyvsp[0].str); delete (yyvsp[-1].starqual); delete (yyvsp[0].str); slgh->reportError(errmsg); YYERROR; } + case 144: /* rtl: rtlmid EXPORT_KEY sizedstar STRING */ + { (yyval.sem) = (ConstructTpl *)0; delete (yyvsp[-3].sem); string errmsg="Unknown pointer varnode: "+*(yyvsp[0].str); delete (yyvsp[-1].starqual); delete (yyvsp[0].str); slgh->reportError(errmsg); YYERROR; } break; - case 145: + case 145: /* rtlmid: %empty */ { (yyval.sem) = slgh->enterSection(); } break; - case 146: - { (yyval.sem) = (yyvsp[-1].sem); if (!(yyval.sem)->addOpList(*(yyvsp[0].stmt))) { delete (yyvsp[0].stmt); slgh->reportError("Multiple delayslot declarations"); YYERROR; } delete (yyvsp[0].stmt); } + case 146: /* rtlmid: rtlmid statement */ + { (yyval.sem) = (yyvsp[-1].sem); if (!(yyval.sem)->addOpList(*(yyvsp[0].stmt))) { delete (yyvsp[-1].sem); delete (yyvsp[0].stmt); slgh->reportError("Multiple delayslot declarations"); YYERROR; } delete (yyvsp[0].stmt); } break; - case 147: + case 147: /* rtlmid: rtlmid LOCAL_KEY STRING ';' */ { (yyval.sem) = (yyvsp[-3].sem); slgh->pcode.newLocalDefinition((yyvsp[-1].str)); } break; - case 148: + case 148: /* rtlmid: rtlmid LOCAL_KEY STRING ':' INTEGER ';' */ { (yyval.sem) = (yyvsp[-5].sem); slgh->pcode.newLocalDefinition((yyvsp[-3].str),*(yyvsp[-1].i)); delete (yyvsp[-1].i); } break; - case 149: + case 149: /* statement: lhsvarnode '=' expr ';' */ { (yyvsp[-1].tree)->setOutput((yyvsp[-3].varnode)); (yyval.stmt) = ExprTree::toVector((yyvsp[-1].tree)); } break; - case 150: + case 150: /* statement: LOCAL_KEY STRING '=' expr ';' */ { (yyval.stmt) = slgh->pcode.newOutput(true,(yyvsp[-1].tree),(yyvsp[-3].str)); } break; - case 151: + case 151: /* statement: STRING '=' expr ';' */ { (yyval.stmt) = slgh->pcode.newOutput(false,(yyvsp[-1].tree),(yyvsp[-3].str)); } break; - case 152: + case 152: /* statement: LOCAL_KEY STRING ':' INTEGER '=' expr ';' */ { (yyval.stmt) = slgh->pcode.newOutput(true,(yyvsp[-1].tree),(yyvsp[-5].str),*(yyvsp[-3].i)); delete (yyvsp[-3].i); } break; - case 153: + case 153: /* statement: STRING ':' INTEGER '=' expr ';' */ { (yyval.stmt) = slgh->pcode.newOutput(true,(yyvsp[-1].tree),(yyvsp[-5].str),*(yyvsp[-3].i)); delete (yyvsp[-3].i); } break; - case 154: + case 154: /* statement: LOCAL_KEY specificsymbol '=' */ { (yyval.stmt) = (vector *)0; string errmsg = "Redefinition of symbol: "+(yyvsp[-1].specsym)->getName(); slgh->reportError(errmsg); YYERROR; } break; - case 155: + case 155: /* statement: sizedstar expr '=' expr ';' */ { (yyval.stmt) = slgh->pcode.createStore((yyvsp[-4].starqual),(yyvsp[-3].tree),(yyvsp[-1].tree)); } break; - case 156: + case 156: /* statement: USEROPSYM '(' paramlist ')' ';' */ { (yyval.stmt) = slgh->pcode.createUserOpNoOut((yyvsp[-4].useropsym),(yyvsp[-2].param)); } break; - case 157: + case 157: /* statement: lhsvarnode '[' INTEGER ',' INTEGER ']' '=' expr ';' */ { (yyval.stmt) = slgh->pcode.assignBitRange((yyvsp[-8].varnode),(uint4)*(yyvsp[-6].i),(uint4)*(yyvsp[-4].i),(yyvsp[-1].tree)); delete (yyvsp[-6].i), delete (yyvsp[-4].i); } break; - case 158: + case 158: /* statement: BITSYM '=' expr ';' */ { (yyval.stmt)=slgh->pcode.assignBitRange((yyvsp[-3].bitsym)->getParentSymbol()->getVarnode(),(yyvsp[-3].bitsym)->getBitOffset(),(yyvsp[-3].bitsym)->numBits(),(yyvsp[-1].tree)); } break; - case 159: - { delete (yyvsp[-3].varnode); delete (yyvsp[-1].i); slgh->reportError("Illegal truncation on left-hand side of assignment"); YYERROR; } + case 159: /* statement: varnode ':' INTEGER '=' */ + { (yyval.stmt) = (vector *)0; delete (yyvsp[-3].varnode); delete (yyvsp[-1].i); slgh->reportError("Illegal truncation on left-hand side of assignment"); YYERROR; } break; - case 160: - { delete (yyvsp[-3].varnode); delete (yyvsp[-1].i); slgh->reportError("Illegal subpiece on left-hand side of assignment"); YYERROR; } + case 160: /* statement: varnode '(' INTEGER ')' */ + { (yyval.stmt) = (vector *)0; delete (yyvsp[-3].varnode); delete (yyvsp[-1].i); slgh->reportError("Illegal subpiece on left-hand side of assignment"); YYERROR; } break; - case 161: + case 161: /* statement: BUILD_KEY OPERANDSYM ';' */ { (yyval.stmt) = slgh->pcode.createOpConst(BUILD,(yyvsp[-1].operandsym)->getIndex()); } break; - case 162: + case 162: /* statement: CROSSBUILD_KEY varnode ',' SECTIONSYM ';' */ { (yyval.stmt) = slgh->createCrossBuild((yyvsp[-3].varnode),(yyvsp[-1].sectionsym)); } break; - case 163: + case 163: /* statement: CROSSBUILD_KEY varnode ',' STRING ';' */ { (yyval.stmt) = slgh->createCrossBuild((yyvsp[-3].varnode),slgh->newSectionSymbol(*(yyvsp[-1].str))); delete (yyvsp[-1].str); } break; - case 164: + case 164: /* statement: DELAYSLOT_KEY '(' INTEGER ')' ';' */ { (yyval.stmt) = slgh->pcode.createOpConst(DELAY_SLOT,*(yyvsp[-2].i)); delete (yyvsp[-2].i); } break; - case 165: + case 165: /* statement: GOTO_KEY jumpdest ';' */ { (yyval.stmt) = slgh->pcode.createOpNoOut(CPUI_BRANCH,new ExprTree((yyvsp[-1].varnode))); } break; - case 166: + case 166: /* statement: IF_KEY expr GOTO_KEY jumpdest ';' */ { (yyval.stmt) = slgh->pcode.createOpNoOut(CPUI_CBRANCH,new ExprTree((yyvsp[-1].varnode)),(yyvsp[-3].tree)); } break; - case 167: + case 167: /* statement: GOTO_KEY '[' expr ']' ';' */ { (yyval.stmt) = slgh->pcode.createOpNoOut(CPUI_BRANCHIND,(yyvsp[-2].tree)); } break; - case 168: + case 168: /* statement: CALL_KEY jumpdest ';' */ { (yyval.stmt) = slgh->pcode.createOpNoOut(CPUI_CALL,new ExprTree((yyvsp[-1].varnode))); } break; - case 169: + case 169: /* statement: CALL_KEY '[' expr ']' ';' */ { (yyval.stmt) = slgh->pcode.createOpNoOut(CPUI_CALLIND,(yyvsp[-2].tree)); } break; - case 170: - { slgh->reportError("Must specify an indirect parameter for return"); YYERROR; } + case 170: /* statement: RETURN_KEY ';' */ + { (yyval.stmt) = (vector *)0; slgh->reportError("Must specify an indirect parameter for return"); YYERROR; } break; - case 171: + case 171: /* statement: RETURN_KEY '[' expr ']' ';' */ { (yyval.stmt) = slgh->pcode.createOpNoOut(CPUI_RETURN,(yyvsp[-2].tree)); } break; - case 172: + case 172: /* statement: MACROSYM '(' paramlist ')' ';' */ { (yyval.stmt) = slgh->createMacroUse((yyvsp[-4].macrosym),(yyvsp[-2].param)); } break; - case 173: + case 173: /* statement: label */ { (yyval.stmt) = slgh->pcode.placeLabel( (yyvsp[0].labelsym) ); } break; - case 174: + case 174: /* expr: varnode */ { (yyval.tree) = new ExprTree((yyvsp[0].varnode)); } break; - case 175: + case 175: /* expr: sizedstar expr */ { (yyval.tree) = slgh->pcode.createLoad((yyvsp[-1].starqual),(yyvsp[0].tree)); } break; - case 176: + case 176: /* expr: '(' expr ')' */ { (yyval.tree) = (yyvsp[-1].tree); } break; - case 177: + case 177: /* expr: expr '+' expr */ { (yyval.tree) = slgh->pcode.createOp(CPUI_INT_ADD,(yyvsp[-2].tree),(yyvsp[0].tree)); } break; - case 178: + case 178: /* expr: expr '-' expr */ { (yyval.tree) = slgh->pcode.createOp(CPUI_INT_SUB,(yyvsp[-2].tree),(yyvsp[0].tree)); } break; - case 179: + case 179: /* expr: expr OP_EQUAL expr */ { (yyval.tree) = slgh->pcode.createOp(CPUI_INT_EQUAL,(yyvsp[-2].tree),(yyvsp[0].tree)); } break; - case 180: + case 180: /* expr: expr OP_NOTEQUAL expr */ { (yyval.tree) = slgh->pcode.createOp(CPUI_INT_NOTEQUAL,(yyvsp[-2].tree),(yyvsp[0].tree)); } break; - case 181: + case 181: /* expr: expr '<' expr */ { (yyval.tree) = slgh->pcode.createOp(CPUI_INT_LESS,(yyvsp[-2].tree),(yyvsp[0].tree)); } break; - case 182: + case 182: /* expr: expr OP_GREATEQUAL expr */ { (yyval.tree) = slgh->pcode.createOp(CPUI_INT_LESSEQUAL,(yyvsp[0].tree),(yyvsp[-2].tree)); } break; - case 183: + case 183: /* expr: expr OP_LESSEQUAL expr */ { (yyval.tree) = slgh->pcode.createOp(CPUI_INT_LESSEQUAL,(yyvsp[-2].tree),(yyvsp[0].tree)); } break; - case 184: + case 184: /* expr: expr '>' expr */ { (yyval.tree) = slgh->pcode.createOp(CPUI_INT_LESS,(yyvsp[0].tree),(yyvsp[-2].tree)); } break; - case 185: + case 185: /* expr: expr OP_SLESS expr */ { (yyval.tree) = slgh->pcode.createOp(CPUI_INT_SLESS,(yyvsp[-2].tree),(yyvsp[0].tree)); } break; - case 186: + case 186: /* expr: expr OP_SGREATEQUAL expr */ { (yyval.tree) = slgh->pcode.createOp(CPUI_INT_SLESSEQUAL,(yyvsp[0].tree),(yyvsp[-2].tree)); } break; - case 187: + case 187: /* expr: expr OP_SLESSEQUAL expr */ { (yyval.tree) = slgh->pcode.createOp(CPUI_INT_SLESSEQUAL,(yyvsp[-2].tree),(yyvsp[0].tree)); } break; - case 188: + case 188: /* expr: expr OP_SGREAT expr */ { (yyval.tree) = slgh->pcode.createOp(CPUI_INT_SLESS,(yyvsp[0].tree),(yyvsp[-2].tree)); } break; - case 189: + case 189: /* expr: '-' expr */ { (yyval.tree) = slgh->pcode.createOp(CPUI_INT_2COMP,(yyvsp[0].tree)); } break; - case 190: + case 190: /* expr: '~' expr */ { (yyval.tree) = slgh->pcode.createOp(CPUI_INT_NEGATE,(yyvsp[0].tree)); } break; - case 191: + case 191: /* expr: expr '^' expr */ { (yyval.tree) = slgh->pcode.createOp(CPUI_INT_XOR,(yyvsp[-2].tree),(yyvsp[0].tree)); } break; - case 192: + case 192: /* expr: expr '&' expr */ { (yyval.tree) = slgh->pcode.createOp(CPUI_INT_AND,(yyvsp[-2].tree),(yyvsp[0].tree)); } break; - case 193: + case 193: /* expr: expr '|' expr */ { (yyval.tree) = slgh->pcode.createOp(CPUI_INT_OR,(yyvsp[-2].tree),(yyvsp[0].tree)); } break; - case 194: + case 194: /* expr: expr OP_LEFT expr */ { (yyval.tree) = slgh->pcode.createOp(CPUI_INT_LEFT,(yyvsp[-2].tree),(yyvsp[0].tree)); } break; - case 195: + case 195: /* expr: expr OP_RIGHT expr */ { (yyval.tree) = slgh->pcode.createOp(CPUI_INT_RIGHT,(yyvsp[-2].tree),(yyvsp[0].tree)); } break; - case 196: + case 196: /* expr: expr OP_SRIGHT expr */ { (yyval.tree) = slgh->pcode.createOp(CPUI_INT_SRIGHT,(yyvsp[-2].tree),(yyvsp[0].tree)); } break; - case 197: + case 197: /* expr: expr '*' expr */ { (yyval.tree) = slgh->pcode.createOp(CPUI_INT_MULT,(yyvsp[-2].tree),(yyvsp[0].tree)); } break; - case 198: + case 198: /* expr: expr '/' expr */ { (yyval.tree) = slgh->pcode.createOp(CPUI_INT_DIV,(yyvsp[-2].tree),(yyvsp[0].tree)); } break; - case 199: + case 199: /* expr: expr OP_SDIV expr */ { (yyval.tree) = slgh->pcode.createOp(CPUI_INT_SDIV,(yyvsp[-2].tree),(yyvsp[0].tree)); } break; - case 200: + case 200: /* expr: expr '%' expr */ { (yyval.tree) = slgh->pcode.createOp(CPUI_INT_REM,(yyvsp[-2].tree),(yyvsp[0].tree)); } break; - case 201: + case 201: /* expr: expr OP_SREM expr */ { (yyval.tree) = slgh->pcode.createOp(CPUI_INT_SREM,(yyvsp[-2].tree),(yyvsp[0].tree)); } break; - case 202: + case 202: /* expr: '!' expr */ { (yyval.tree) = slgh->pcode.createOp(CPUI_BOOL_NEGATE,(yyvsp[0].tree)); } break; - case 203: + case 203: /* expr: expr OP_BOOL_XOR expr */ { (yyval.tree) = slgh->pcode.createOp(CPUI_BOOL_XOR,(yyvsp[-2].tree),(yyvsp[0].tree)); } break; - case 204: + case 204: /* expr: expr OP_BOOL_AND expr */ { (yyval.tree) = slgh->pcode.createOp(CPUI_BOOL_AND,(yyvsp[-2].tree),(yyvsp[0].tree)); } break; - case 205: + case 205: /* expr: expr OP_BOOL_OR expr */ { (yyval.tree) = slgh->pcode.createOp(CPUI_BOOL_OR,(yyvsp[-2].tree),(yyvsp[0].tree)); } break; - case 206: + case 206: /* expr: expr OP_FEQUAL expr */ { (yyval.tree) = slgh->pcode.createOp(CPUI_FLOAT_EQUAL,(yyvsp[-2].tree),(yyvsp[0].tree)); } break; - case 207: + case 207: /* expr: expr OP_FNOTEQUAL expr */ { (yyval.tree) = slgh->pcode.createOp(CPUI_FLOAT_NOTEQUAL,(yyvsp[-2].tree),(yyvsp[0].tree)); } break; - case 208: + case 208: /* expr: expr OP_FLESS expr */ { (yyval.tree) = slgh->pcode.createOp(CPUI_FLOAT_LESS,(yyvsp[-2].tree),(yyvsp[0].tree)); } break; - case 209: + case 209: /* expr: expr OP_FGREAT expr */ { (yyval.tree) = slgh->pcode.createOp(CPUI_FLOAT_LESS,(yyvsp[0].tree),(yyvsp[-2].tree)); } break; - case 210: + case 210: /* expr: expr OP_FLESSEQUAL expr */ { (yyval.tree) = slgh->pcode.createOp(CPUI_FLOAT_LESSEQUAL,(yyvsp[-2].tree),(yyvsp[0].tree)); } break; - case 211: + case 211: /* expr: expr OP_FGREATEQUAL expr */ { (yyval.tree) = slgh->pcode.createOp(CPUI_FLOAT_LESSEQUAL,(yyvsp[0].tree),(yyvsp[-2].tree)); } break; - case 212: + case 212: /* expr: expr OP_FADD expr */ { (yyval.tree) = slgh->pcode.createOp(CPUI_FLOAT_ADD,(yyvsp[-2].tree),(yyvsp[0].tree)); } break; - case 213: + case 213: /* expr: expr OP_FSUB expr */ { (yyval.tree) = slgh->pcode.createOp(CPUI_FLOAT_SUB,(yyvsp[-2].tree),(yyvsp[0].tree)); } break; - case 214: + case 214: /* expr: expr OP_FMULT expr */ { (yyval.tree) = slgh->pcode.createOp(CPUI_FLOAT_MULT,(yyvsp[-2].tree),(yyvsp[0].tree)); } break; - case 215: + case 215: /* expr: expr OP_FDIV expr */ { (yyval.tree) = slgh->pcode.createOp(CPUI_FLOAT_DIV,(yyvsp[-2].tree),(yyvsp[0].tree)); } break; - case 216: + case 216: /* expr: OP_FSUB expr */ { (yyval.tree) = slgh->pcode.createOp(CPUI_FLOAT_NEG,(yyvsp[0].tree)); } break; - case 217: + case 217: /* expr: OP_ABS '(' expr ')' */ { (yyval.tree) = slgh->pcode.createOp(CPUI_FLOAT_ABS,(yyvsp[-1].tree)); } break; - case 218: + case 218: /* expr: OP_SQRT '(' expr ')' */ { (yyval.tree) = slgh->pcode.createOp(CPUI_FLOAT_SQRT,(yyvsp[-1].tree)); } break; - case 219: + case 219: /* expr: OP_SEXT '(' expr ')' */ { (yyval.tree) = slgh->pcode.createOp(CPUI_INT_SEXT,(yyvsp[-1].tree)); } break; - case 220: + case 220: /* expr: OP_ZEXT '(' expr ')' */ { (yyval.tree) = slgh->pcode.createOp(CPUI_INT_ZEXT,(yyvsp[-1].tree)); } break; - case 221: + case 221: /* expr: OP_CARRY '(' expr ',' expr ')' */ { (yyval.tree) = slgh->pcode.createOp(CPUI_INT_CARRY,(yyvsp[-3].tree),(yyvsp[-1].tree)); } break; - case 222: + case 222: /* expr: OP_SCARRY '(' expr ',' expr ')' */ { (yyval.tree) = slgh->pcode.createOp(CPUI_INT_SCARRY,(yyvsp[-3].tree),(yyvsp[-1].tree)); } break; - case 223: + case 223: /* expr: OP_SBORROW '(' expr ',' expr ')' */ { (yyval.tree) = slgh->pcode.createOp(CPUI_INT_SBORROW,(yyvsp[-3].tree),(yyvsp[-1].tree)); } break; - case 224: + case 224: /* expr: OP_FLOAT2FLOAT '(' expr ')' */ { (yyval.tree) = slgh->pcode.createOp(CPUI_FLOAT_FLOAT2FLOAT,(yyvsp[-1].tree)); } break; - case 225: + case 225: /* expr: OP_INT2FLOAT '(' expr ')' */ { (yyval.tree) = slgh->pcode.createOp(CPUI_FLOAT_INT2FLOAT,(yyvsp[-1].tree)); } break; - case 226: + case 226: /* expr: OP_NAN '(' expr ')' */ { (yyval.tree) = slgh->pcode.createOp(CPUI_FLOAT_NAN,(yyvsp[-1].tree)); } break; - case 227: + case 227: /* expr: OP_TRUNC '(' expr ')' */ { (yyval.tree) = slgh->pcode.createOp(CPUI_FLOAT_TRUNC,(yyvsp[-1].tree)); } break; - case 228: + case 228: /* expr: OP_CEIL '(' expr ')' */ { (yyval.tree) = slgh->pcode.createOp(CPUI_FLOAT_CEIL,(yyvsp[-1].tree)); } break; - case 229: + case 229: /* expr: OP_FLOOR '(' expr ')' */ { (yyval.tree) = slgh->pcode.createOp(CPUI_FLOAT_FLOOR,(yyvsp[-1].tree)); } break; - case 230: + case 230: /* expr: OP_ROUND '(' expr ')' */ { (yyval.tree) = slgh->pcode.createOp(CPUI_FLOAT_ROUND,(yyvsp[-1].tree)); } break; - case 231: + case 231: /* expr: OP_NEW '(' expr ')' */ { (yyval.tree) = slgh->pcode.createOp(CPUI_NEW,(yyvsp[-1].tree)); } break; - case 232: + case 232: /* expr: OP_NEW '(' expr ',' expr ')' */ { (yyval.tree) = slgh->pcode.createOp(CPUI_NEW,(yyvsp[-3].tree),(yyvsp[-1].tree)); } break; - case 233: + case 233: /* expr: OP_POPCOUNT '(' expr ')' */ { (yyval.tree) = slgh->pcode.createOp(CPUI_POPCOUNT,(yyvsp[-1].tree)); } break; - case 234: + case 234: /* expr: OP_LZCOUNT '(' expr ')' */ { (yyval.tree) = slgh->pcode.createOp(CPUI_LZCOUNT,(yyvsp[-1].tree)); } break; - case 235: + case 235: /* expr: specificsymbol '(' integervarnode ')' */ { (yyval.tree) = slgh->pcode.createOp(CPUI_SUBPIECE,new ExprTree((yyvsp[-3].specsym)->getVarnode()),new ExprTree((yyvsp[-1].varnode))); } break; - case 236: + case 236: /* expr: specificsymbol ':' INTEGER */ { (yyval.tree) = slgh->pcode.createBitRange((yyvsp[-2].specsym),0,(uint4)(*(yyvsp[0].i) * 8)); delete (yyvsp[0].i); } break; - case 237: + case 237: /* expr: specificsymbol '[' INTEGER ',' INTEGER ']' */ { (yyval.tree) = slgh->pcode.createBitRange((yyvsp[-5].specsym),(uint4)*(yyvsp[-3].i),(uint4)*(yyvsp[-1].i)); delete (yyvsp[-3].i), delete (yyvsp[-1].i); } break; - case 238: + case 238: /* expr: BITSYM */ { (yyval.tree)=slgh->pcode.createBitRange((yyvsp[0].bitsym)->getParentSymbol(),(yyvsp[0].bitsym)->getBitOffset(),(yyvsp[0].bitsym)->numBits()); } break; - case 239: + case 239: /* expr: USEROPSYM '(' paramlist ')' */ { (yyval.tree) = slgh->pcode.createUserOp((yyvsp[-3].useropsym),(yyvsp[-1].param)); } break; - case 240: - { if ((*(yyvsp[-1].param)).size() < 2) { string errmsg = "Must at least two inputs to cpool"; slgh->reportError(errmsg); YYERROR; } (yyval.tree) = slgh->pcode.createVariadic(CPUI_CPOOLREF,(yyvsp[-1].param)); } + case 240: /* expr: OP_CPOOLREF '(' paramlist ')' */ + { if ((*(yyvsp[-1].param)).size() < 2) { string errmsg = "Must be at least two inputs to cpool"; slgh->reportError(errmsg); delete (yyvsp[-1].param); YYERROR; } (yyval.tree) = slgh->pcode.createVariadic(CPUI_CPOOLREF,(yyvsp[-1].param)); } break; - case 241: + case 241: /* sizedstar: '*' '[' SPACESYM ']' ':' INTEGER */ { (yyval.starqual) = new StarQuality; (yyval.starqual)->size = *(yyvsp[0].i); delete (yyvsp[0].i); (yyval.starqual)->id=ConstTpl((yyvsp[-3].spacesym)->getSpace()); } break; - case 242: + case 242: /* sizedstar: '*' '[' SPACESYM ']' */ { (yyval.starqual) = new StarQuality; (yyval.starqual)->size = 0; (yyval.starqual)->id=ConstTpl((yyvsp[-1].spacesym)->getSpace()); } break; - case 243: + case 243: /* sizedstar: '*' ':' INTEGER */ { (yyval.starqual) = new StarQuality; (yyval.starqual)->size = *(yyvsp[0].i); delete (yyvsp[0].i); (yyval.starqual)->id=ConstTpl(slgh->getDefaultCodeSpace()); } break; - case 244: + case 244: /* sizedstar: '*' */ { (yyval.starqual) = new StarQuality; (yyval.starqual)->size = 0; (yyval.starqual)->id=ConstTpl(slgh->getDefaultCodeSpace()); } break; - case 245: + case 245: /* jumpdest: JUMPSYM */ { VarnodeTpl *sym = (yyvsp[0].specsym)->getVarnode(); (yyval.varnode) = new VarnodeTpl(ConstTpl(ConstTpl::j_curspace),sym->getOffset(),ConstTpl(ConstTpl::j_curspace_size)); delete sym; } break; - case 246: + case 246: /* jumpdest: INTEGER */ { (yyval.varnode) = new VarnodeTpl(ConstTpl(ConstTpl::j_curspace),ConstTpl(ConstTpl::real,*(yyvsp[0].i)),ConstTpl(ConstTpl::j_curspace_size)); delete (yyvsp[0].i); } break; - case 247: + case 247: /* jumpdest: BADINTEGER */ { (yyval.varnode) = new VarnodeTpl(ConstTpl(ConstTpl::j_curspace),ConstTpl(ConstTpl::real,0),ConstTpl(ConstTpl::j_curspace_size)); slgh->reportError("Parsed integer is too big (overflow)"); } break; - case 248: + case 248: /* jumpdest: OPERANDSYM */ { (yyval.varnode) = (yyvsp[0].operandsym)->getVarnode(); (yyvsp[0].operandsym)->setCodeAddress(); } break; - case 249: + case 249: /* jumpdest: INTEGER '[' SPACESYM ']' */ { AddrSpace *spc = (yyvsp[-1].spacesym)->getSpace(); (yyval.varnode) = new VarnodeTpl(ConstTpl(spc),ConstTpl(ConstTpl::real,*(yyvsp[-3].i)),ConstTpl(ConstTpl::real,spc->getAddrSize())); delete (yyvsp[-3].i); } break; - case 250: + case 250: /* jumpdest: label */ { (yyval.varnode) = new VarnodeTpl(ConstTpl(slgh->getConstantSpace()),ConstTpl(ConstTpl::j_relative,(yyvsp[0].labelsym)->getIndex()),ConstTpl(ConstTpl::real,sizeof(uintm))); (yyvsp[0].labelsym)->incrementRefCount(); } break; - case 251: - { string errmsg = "Unknown jump destination: "+*(yyvsp[0].str); delete (yyvsp[0].str); slgh->reportError(errmsg); YYERROR; } + case 251: /* jumpdest: STRING */ + { (yyval.varnode) = (VarnodeTpl *)0; string errmsg = "Unknown jump destination: "+*(yyvsp[0].str); delete (yyvsp[0].str); slgh->reportError(errmsg); YYERROR; } break; - case 252: + case 252: /* varnode: specificsymbol */ { (yyval.varnode) = (yyvsp[0].specsym)->getVarnode(); } break; - case 253: + case 253: /* varnode: integervarnode */ { (yyval.varnode) = (yyvsp[0].varnode); } break; - case 254: - { string errmsg = "Unknown varnode parameter: "+*(yyvsp[0].str); delete (yyvsp[0].str); slgh->reportError(errmsg); YYERROR; } + case 254: /* varnode: STRING */ + { (yyval.varnode) = (VarnodeTpl *)0; string errmsg = "Unknown varnode parameter: "+*(yyvsp[0].str); delete (yyvsp[0].str); slgh->reportError(errmsg); YYERROR; } break; - case 255: - { string errmsg = "Subtable not attached to operand: "+(yyvsp[0].subtablesym)->getName(); slgh->reportError(errmsg); YYERROR; } + case 255: /* varnode: SUBTABLESYM */ + { (yyval.varnode) = (VarnodeTpl *)0; string errmsg = "Subtable not attached to operand: "+(yyvsp[0].subtablesym)->getName(); slgh->reportError(errmsg); YYERROR; } break; - case 256: + case 256: /* integervarnode: INTEGER */ { (yyval.varnode) = new VarnodeTpl(ConstTpl(slgh->getConstantSpace()),ConstTpl(ConstTpl::real,*(yyvsp[0].i)),ConstTpl(ConstTpl::real,0)); delete (yyvsp[0].i); } break; - case 257: + case 257: /* integervarnode: BADINTEGER */ { (yyval.varnode) = new VarnodeTpl(ConstTpl(slgh->getConstantSpace()),ConstTpl(ConstTpl::real,0),ConstTpl(ConstTpl::real,0)); slgh->reportError("Parsed integer is too big (overflow)"); } break; - case 258: + case 258: /* integervarnode: INTEGER ':' INTEGER */ { (yyval.varnode) = new VarnodeTpl(ConstTpl(slgh->getConstantSpace()),ConstTpl(ConstTpl::real,*(yyvsp[-2].i)),ConstTpl(ConstTpl::real,*(yyvsp[0].i))); delete (yyvsp[-2].i); delete (yyvsp[0].i); } break; - case 259: + case 259: /* integervarnode: '&' varnode */ { (yyval.varnode) = slgh->pcode.addressOf((yyvsp[0].varnode),0); } break; - case 260: + case 260: /* integervarnode: '&' ':' INTEGER varnode */ { (yyval.varnode) = slgh->pcode.addressOf((yyvsp[0].varnode),*(yyvsp[-1].i)); delete (yyvsp[-1].i); } break; - case 261: + case 261: /* lhsvarnode: specificsymbol */ { (yyval.varnode) = (yyvsp[0].specsym)->getVarnode(); } break; - case 262: - { string errmsg = "Unknown assignment varnode: "+*(yyvsp[0].str); delete (yyvsp[0].str); slgh->reportError(errmsg); YYERROR; } + case 262: /* lhsvarnode: STRING */ + { (yyval.varnode) = (VarnodeTpl *)0; string errmsg = "Unknown assignment varnode: "+*(yyvsp[0].str); delete (yyvsp[0].str); slgh->reportError(errmsg); YYERROR; } break; - case 263: - { string errmsg = "Subtable not attached to operand: "+(yyvsp[0].subtablesym)->getName(); slgh->reportError(errmsg); YYERROR; } + case 263: /* lhsvarnode: SUBTABLESYM */ + { (yyval.varnode) = (VarnodeTpl *)0; string errmsg = "Subtable not attached to operand: "+(yyvsp[0].subtablesym)->getName(); slgh->reportError(errmsg); YYERROR; } break; - case 264: + case 264: /* label: '<' LABELSYM '>' */ { (yyval.labelsym) = (yyvsp[-1].labelsym); } break; - case 265: + case 265: /* label: '<' STRING '>' */ { (yyval.labelsym) = slgh->pcode.defineLabel( (yyvsp[-1].str) ); } break; - case 266: + case 266: /* exportvarnode: specificsymbol */ { (yyval.varnode) = (yyvsp[0].specsym)->getVarnode(); } break; - case 267: + case 267: /* exportvarnode: '&' varnode */ { (yyval.varnode) = slgh->pcode.addressOf((yyvsp[0].varnode),0); } break; - case 268: + case 268: /* exportvarnode: '&' ':' INTEGER varnode */ { (yyval.varnode) = slgh->pcode.addressOf((yyvsp[0].varnode),*(yyvsp[-1].i)); delete (yyvsp[-1].i); } break; - case 269: + case 269: /* exportvarnode: INTEGER ':' INTEGER */ { (yyval.varnode) = new VarnodeTpl(ConstTpl(slgh->getConstantSpace()),ConstTpl(ConstTpl::real,*(yyvsp[-2].i)),ConstTpl(ConstTpl::real,*(yyvsp[0].i))); delete (yyvsp[-2].i); delete (yyvsp[0].i); } break; - case 270: - { string errmsg="Unknown export varnode: "+*(yyvsp[0].str); delete (yyvsp[0].str); slgh->reportError(errmsg); YYERROR; } + case 270: /* exportvarnode: STRING */ + { (yyval.varnode) = (VarnodeTpl *)0; string errmsg="Unknown export varnode: "+*(yyvsp[0].str); delete (yyvsp[0].str); slgh->reportError(errmsg); YYERROR; } break; - case 271: - { string errmsg = "Subtable not attached to operand: "+(yyvsp[0].subtablesym)->getName(); slgh->reportError(errmsg); YYERROR; } + case 271: /* exportvarnode: SUBTABLESYM */ + { (yyval.varnode) = (VarnodeTpl *)0; string errmsg = "Subtable not attached to operand: "+(yyvsp[0].subtablesym)->getName(); slgh->reportError(errmsg); YYERROR; } break; - case 272: + case 272: /* familysymbol: VALUESYM */ { (yyval.famsym) = (yyvsp[0].valuesym); } break; - case 273: + case 273: /* familysymbol: VALUEMAPSYM */ { (yyval.famsym) = (yyvsp[0].valuemapsym); } break; - case 274: + case 274: /* familysymbol: CONTEXTSYM */ { (yyval.famsym) = (yyvsp[0].contextsym); } break; - case 275: + case 275: /* familysymbol: NAMESYM */ { (yyval.famsym) = (yyvsp[0].namesym); } break; - case 276: + case 276: /* familysymbol: VARLISTSYM */ { (yyval.famsym) = (yyvsp[0].varlistsym); } break; - case 277: + case 277: /* specificsymbol: VARSYM */ { (yyval.specsym) = (yyvsp[0].varsym); } break; - case 278: + case 278: /* specificsymbol: SPECSYM */ { (yyval.specsym) = (yyvsp[0].specsym); } break; - case 279: + case 279: /* specificsymbol: OPERANDSYM */ { (yyval.specsym) = (yyvsp[0].operandsym); } break; - case 280: + case 280: /* specificsymbol: JUMPSYM */ { (yyval.specsym) = (yyvsp[0].specsym); } break; - case 281: + case 281: /* charstring: CHAR */ { (yyval.str) = new string; (*(yyval.str)) += (yyvsp[0].ch); } break; - case 282: + case 282: /* charstring: charstring CHAR */ { (yyval.str) = (yyvsp[-1].str); (*(yyval.str)) += (yyvsp[0].ch); } break; - case 283: + case 283: /* intblist: '[' intbpart ']' */ { (yyval.biglist) = (yyvsp[-1].biglist); } break; - case 284: + case 284: /* intblist: INTEGER */ { (yyval.biglist) = new vector; (yyval.biglist)->push_back(intb(*(yyvsp[0].i))); delete (yyvsp[0].i); } break; - case 285: + case 285: /* intblist: '-' INTEGER */ { (yyval.biglist) = new vector; (yyval.biglist)->push_back(-intb(*(yyvsp[0].i))); delete (yyvsp[0].i); } break; - case 286: + case 286: /* intbpart: INTEGER */ { (yyval.biglist) = new vector; (yyval.biglist)->push_back(intb(*(yyvsp[0].i))); delete (yyvsp[0].i); } break; - case 287: + case 287: /* intbpart: '-' INTEGER */ { (yyval.biglist) = new vector; (yyval.biglist)->push_back(-intb(*(yyvsp[0].i))); delete (yyvsp[0].i); } break; - case 288: + case 288: /* intbpart: STRING */ { if (*(yyvsp[0].str)!="_") { string errmsg = "Expecting integer but saw: "+*(yyvsp[0].str); delete (yyvsp[0].str); slgh->reportError(errmsg); YYERROR; } (yyval.biglist) = new vector; (yyval.biglist)->push_back((intb)0xBADBEEF); delete (yyvsp[0].str); } break; - case 289: + case 289: /* intbpart: intbpart INTEGER */ { (yyval.biglist) = (yyvsp[-1].biglist); (yyval.biglist)->push_back(intb(*(yyvsp[0].i))); delete (yyvsp[0].i); } break; - case 290: + case 290: /* intbpart: intbpart '-' INTEGER */ { (yyval.biglist) = (yyvsp[-2].biglist); (yyval.biglist)->push_back(-intb(*(yyvsp[0].i))); delete (yyvsp[0].i); } break; - case 291: - { if (*(yyvsp[0].str)!="_") { string errmsg = "Expecting integer but saw: "+*(yyvsp[0].str); delete (yyvsp[0].str); slgh->reportError(errmsg); YYERROR; } + case 291: /* intbpart: intbpart STRING */ + { if (*(yyvsp[0].str)!="_") { string errmsg = "Expecting integer but saw: "+*(yyvsp[0].str); delete (yyvsp[-1].biglist); delete (yyvsp[0].str); slgh->reportError(errmsg); YYERROR; } (yyval.biglist) = (yyvsp[-1].biglist); (yyval.biglist)->push_back((intb)0xBADBEEF); delete (yyvsp[0].str); } break; - case 292: + case 292: /* stringlist: '[' stringpart ']' */ { (yyval.strlist) = (yyvsp[-1].strlist); } break; - case 293: + case 293: /* stringlist: STRING */ { (yyval.strlist) = new vector; (yyval.strlist)->push_back(*(yyvsp[0].str)); delete (yyvsp[0].str); } break; - case 294: + case 294: /* stringpart: STRING */ { (yyval.strlist) = new vector; (yyval.strlist)->push_back( *(yyvsp[0].str) ); delete (yyvsp[0].str); } break; - case 295: + case 295: /* stringpart: stringpart STRING */ { (yyval.strlist) = (yyvsp[-1].strlist); (yyval.strlist)->push_back(*(yyvsp[0].str)); delete (yyvsp[0].str); } break; - case 296: - { string errmsg = (yyvsp[0].anysym)->getName()+": redefined"; slgh->reportError(errmsg); YYERROR; } + case 296: /* stringpart: stringpart anysymbol */ + { (yyval.strlist) = (vector *)0; delete (yyvsp[-1].strlist); string errmsg = (yyvsp[0].anysym)->getName()+": redefined"; slgh->reportError(errmsg); YYERROR; } break; - case 297: + case 297: /* anystringlist: '[' anystringpart ']' */ { (yyval.strlist) = (yyvsp[-1].strlist); } break; - case 298: + case 298: /* anystringpart: STRING */ { (yyval.strlist) = new vector; (yyval.strlist)->push_back( *(yyvsp[0].str) ); delete (yyvsp[0].str); } break; - case 299: + case 299: /* anystringpart: anysymbol */ { (yyval.strlist) = new vector; (yyval.strlist)->push_back( (yyvsp[0].anysym)->getName() ); } break; - case 300: + case 300: /* anystringpart: anystringpart STRING */ { (yyval.strlist) = (yyvsp[-1].strlist); (yyval.strlist)->push_back(*(yyvsp[0].str)); delete (yyvsp[0].str); } break; - case 301: + case 301: /* anystringpart: anystringpart anysymbol */ { (yyval.strlist) = (yyvsp[-1].strlist); (yyval.strlist)->push_back((yyvsp[0].anysym)->getName()); } break; - case 302: + case 302: /* valuelist: '[' valuepart ']' */ { (yyval.symlist) = (yyvsp[-1].symlist); } break; - case 303: + case 303: /* valuelist: VALUESYM */ { (yyval.symlist) = new vector; (yyval.symlist)->push_back((yyvsp[0].valuesym)); } break; - case 304: + case 304: /* valuelist: CONTEXTSYM */ { (yyval.symlist) = new vector; (yyval.symlist)->push_back((yyvsp[0].contextsym)); } break; - case 305: + case 305: /* valuepart: VALUESYM */ { (yyval.symlist) = new vector; (yyval.symlist)->push_back( (yyvsp[0].valuesym) ); } break; - case 306: + case 306: /* valuepart: CONTEXTSYM */ { (yyval.symlist) = new vector; (yyval.symlist)->push_back((yyvsp[0].contextsym)); } break; - case 307: + case 307: /* valuepart: valuepart VALUESYM */ { (yyval.symlist) = (yyvsp[-1].symlist); (yyval.symlist)->push_back((yyvsp[0].valuesym)); } break; - case 308: + case 308: /* valuepart: valuepart CONTEXTSYM */ { (yyval.symlist) = (yyvsp[-1].symlist); (yyval.symlist)->push_back((yyvsp[0].contextsym)); } break; - case 309: - { string errmsg = *(yyvsp[0].str)+": is not a value pattern"; delete (yyvsp[0].str); slgh->reportError(errmsg); YYERROR; } + case 309: /* valuepart: valuepart STRING */ + { (yyval.symlist) = (vector *)0; delete (yyvsp[-1].symlist); string errmsg = *(yyvsp[0].str)+": is not a value pattern"; delete (yyvsp[0].str); slgh->reportError(errmsg); YYERROR; } break; - case 310: + case 310: /* varlist: '[' varpart ']' */ { (yyval.symlist) = (yyvsp[-1].symlist); } break; - case 311: + case 311: /* varlist: VARSYM */ { (yyval.symlist) = new vector; (yyval.symlist)->push_back((yyvsp[0].varsym)); } break; - case 312: + case 312: /* varpart: VARSYM */ { (yyval.symlist) = new vector; (yyval.symlist)->push_back((yyvsp[0].varsym)); } break; - case 313: + case 313: /* varpart: STRING */ { if (*(yyvsp[0].str)!="_") { string errmsg = *(yyvsp[0].str)+": is not a varnode symbol"; delete (yyvsp[0].str); slgh->reportError(errmsg); YYERROR; } (yyval.symlist) = new vector; (yyval.symlist)->push_back((SleighSymbol *)0); delete (yyvsp[0].str); } break; - case 314: + case 314: /* varpart: varpart VARSYM */ { (yyval.symlist) = (yyvsp[-1].symlist); (yyval.symlist)->push_back((yyvsp[0].varsym)); } break; - case 315: - { if (*(yyvsp[0].str)!="_") { string errmsg = *(yyvsp[0].str)+": is not a varnode symbol"; delete (yyvsp[0].str); slgh->reportError(errmsg); YYERROR; } + case 315: /* varpart: varpart STRING */ + { if (*(yyvsp[0].str)!="_") { string errmsg = *(yyvsp[0].str)+": is not a varnode symbol"; delete (yyvsp[-1].symlist); delete (yyvsp[0].str); slgh->reportError(errmsg); YYERROR; } (yyval.symlist) = (yyvsp[-1].symlist); (yyval.symlist)->push_back((SleighSymbol *)0); delete (yyvsp[0].str); } break; - case 316: + case 316: /* paramlist: %empty */ { (yyval.param) = new vector; } break; - case 317: + case 317: /* paramlist: expr */ { (yyval.param) = new vector; (yyval.param)->push_back((yyvsp[0].tree)); } break; - case 318: + case 318: /* paramlist: paramlist ',' expr */ { (yyval.param) = (yyvsp[-2].param); (yyval.param)->push_back((yyvsp[0].tree)); } break; - case 319: + case 319: /* oplist: %empty */ { (yyval.strlist) = new vector; } break; - case 320: + case 320: /* oplist: STRING */ { (yyval.strlist) = new vector; (yyval.strlist)->push_back(*(yyvsp[0].str)); delete (yyvsp[0].str); } break; - case 321: + case 321: /* oplist: oplist ',' STRING */ { (yyval.strlist) = (yyvsp[-2].strlist); (yyval.strlist)->push_back(*(yyvsp[0].str)); delete (yyvsp[0].str); } break; - case 322: + case 322: /* anysymbol: SPACESYM */ { (yyval.anysym) = (yyvsp[0].spacesym); } break; - case 323: + case 323: /* anysymbol: SECTIONSYM */ { (yyval.anysym) = (yyvsp[0].sectionsym); } break; - case 324: + case 324: /* anysymbol: TOKENSYM */ { (yyval.anysym) = (yyvsp[0].tokensym); } break; - case 325: + case 325: /* anysymbol: USEROPSYM */ { (yyval.anysym) = (yyvsp[0].useropsym); } break; - case 326: + case 326: /* anysymbol: MACROSYM */ { (yyval.anysym) = (yyvsp[0].macrosym); } break; - case 327: + case 327: /* anysymbol: SUBTABLESYM */ { (yyval.anysym) = (yyvsp[0].subtablesym); } break; - case 328: + case 328: /* anysymbol: VALUESYM */ { (yyval.anysym) = (yyvsp[0].valuesym); } break; - case 329: + case 329: /* anysymbol: VALUEMAPSYM */ { (yyval.anysym) = (yyvsp[0].valuemapsym); } break; - case 330: + case 330: /* anysymbol: CONTEXTSYM */ { (yyval.anysym) = (yyvsp[0].contextsym); } break; - case 331: + case 331: /* anysymbol: NAMESYM */ { (yyval.anysym) = (yyvsp[0].namesym); } break; - case 332: + case 332: /* anysymbol: VARSYM */ { (yyval.anysym) = (yyvsp[0].varsym); } break; - case 333: + case 333: /* anysymbol: VARLISTSYM */ { (yyval.anysym) = (yyvsp[0].varlistsym); } break; - case 334: + case 334: /* anysymbol: OPERANDSYM */ { (yyval.anysym) = (yyvsp[0].operandsym); } break; - case 335: + case 335: /* anysymbol: JUMPSYM */ { (yyval.anysym) = (yyvsp[0].specsym); } break; - case 336: + case 336: /* anysymbol: BITSYM */ { (yyval.anysym) = (yyvsp[0].bitsym); } break; @@ -3642,11 +3614,10 @@ yyparse (void) case of YYERROR or YYBACKUP, subsequent parser actions might lead to an incorrect destructor call or verbose syntax error message before the lookahead is translated. */ - YY_SYMBOL_PRINT ("-> $$ =", yyr1[yyn], &yyval, &yyloc); + YY_SYMBOL_PRINT ("-> $$ =", YY_CAST (yysymbol_kind_t, yyr1[yyn]), &yyval, &yyloc); YYPOPSTACK (yylen); yylen = 0; - YY_STACK_PRINT (yyss, yyssp); *++yyvsp = yyval; @@ -3670,66 +3641,30 @@ yyparse (void) yyerrlab: /* Make sure we have latest lookahead translation. See comments at user semantic actions for why this is necessary. */ - yytoken = yychar == YYEMPTY ? YYEMPTY : YYTRANSLATE (yychar); - + yytoken = yychar == SLEIGHEMPTY ? YYSYMBOL_YYEMPTY : YYTRANSLATE (yychar); /* If not already recovering from an error, report this error. */ if (!yyerrstatus) { ++yynerrs; -#if ! YYERROR_VERBOSE yyerror (YY_("syntax error")); -#else -# define YYSYNTAX_ERROR yysyntax_error (&yymsg_alloc, &yymsg, \ - yyssp, yytoken) - { - char const *yymsgp = YY_("syntax error"); - int yysyntax_error_status; - yysyntax_error_status = YYSYNTAX_ERROR; - if (yysyntax_error_status == 0) - yymsgp = yymsg; - else if (yysyntax_error_status == 1) - { - if (yymsg != yymsgbuf) - YYSTACK_FREE (yymsg); - yymsg = YY_CAST (char *, YYSTACK_ALLOC (YY_CAST (YYSIZE_T, yymsg_alloc))); - if (!yymsg) - { - yymsg = yymsgbuf; - yymsg_alloc = sizeof yymsgbuf; - yysyntax_error_status = 2; - } - else - { - yysyntax_error_status = YYSYNTAX_ERROR; - yymsgp = yymsg; - } - } - yyerror (yymsgp); - if (yysyntax_error_status == 2) - goto yyexhaustedlab; - } -# undef YYSYNTAX_ERROR -#endif } - - if (yyerrstatus == 3) { /* If just tried and failed to reuse lookahead token after an error, discard it. */ - if (yychar <= YYEOF) + if (yychar <= SLEIGHEOF) { /* Return failure if at end of input. */ - if (yychar == YYEOF) + if (yychar == SLEIGHEOF) YYABORT; } else { yydestruct ("Error: discarding", yytoken, &yylval); - yychar = YYEMPTY; + yychar = SLEIGHEMPTY; } } @@ -3762,13 +3697,14 @@ yyparse (void) yyerrlab1: yyerrstatus = 3; /* Each real token shifted decrements this. */ + /* Pop stack until we find a state that shifts the error token. */ for (;;) { yyn = yypact[yystate]; if (!yypact_value_is_default (yyn)) { - yyn += YYTERROR; - if (0 <= yyn && yyn <= YYLAST && yycheck[yyn] == YYTERROR) + yyn += YYSYMBOL_YYerror; + if (0 <= yyn && yyn <= YYLAST && yycheck[yyn] == YYSYMBOL_YYerror) { yyn = yytable[yyn]; if (0 < yyn) @@ -3782,7 +3718,7 @@ yyparse (void) yydestruct ("Error: popping", - yystos[yystate], yyvsp); + YY_ACCESSING_SYMBOL (yystate), yyvsp); YYPOPSTACK (1); yystate = *yyssp; YY_STACK_PRINT (yyss, yyssp); @@ -3794,7 +3730,7 @@ yyparse (void) /* Shift the error token. */ - YY_SYMBOL_PRINT ("Shifting", yystos[yyn], yyvsp, yylsp); + YY_SYMBOL_PRINT ("Shifting", YY_ACCESSING_SYMBOL (yyn), yyvsp, yylsp); yystate = yyn; goto yynewstate; @@ -3816,22 +3752,22 @@ yyparse (void) goto yyreturn; -#if !defined yyoverflow || YYERROR_VERBOSE +#if !defined yyoverflow /*-------------------------------------------------. | yyexhaustedlab -- memory exhaustion comes here. | `-------------------------------------------------*/ yyexhaustedlab: yyerror (YY_("memory exhausted")); yyresult = 2; - /* Fall through. */ + goto yyreturn; #endif -/*-----------------------------------------------------. -| yyreturn -- parsing is finished, return the result. | -`-----------------------------------------------------*/ +/*-------------------------------------------------------. +| yyreturn -- parsing is finished, clean up and return. | +`-------------------------------------------------------*/ yyreturn: - if (yychar != YYEMPTY) + if (yychar != SLEIGHEMPTY) { /* Make sure we have latest lookahead translation. See comments at user semantic actions for why this is necessary. */ @@ -3846,21 +3782,19 @@ yyparse (void) while (yyssp != yyss) { yydestruct ("Cleanup: popping", - yystos[+*yyssp], yyvsp); + YY_ACCESSING_SYMBOL (+*yyssp), yyvsp); YYPOPSTACK (1); } #ifndef yyoverflow if (yyss != yyssa) YYSTACK_FREE (yyss); #endif -#if YYERROR_VERBOSE - if (yymsg != yymsgbuf) - YYSTACK_FREE (yymsg); -#endif + return yyresult; } + int sleigherror(const char *s) { diff --git a/pypcode/sleigh/slghparse.hh b/pypcode/sleigh/slghparse.hh index 3d615cc..5d72496 100644 --- a/pypcode/sleigh/slghparse.hh +++ b/pypcode/sleigh/slghparse.hh @@ -4,16 +4,16 @@ * Licensed under the Apache License, Version 2.0 (the "License"); * you may not use this file except in compliance with the License. * You may obtain a copy of the License at - * + * * http://www.apache.org/licenses/LICENSE-2.0 - * + * * Unless required by applicable law or agreed to in writing, software * distributed under the License is distributed on an "AS IS" BASIS, * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. */ -/* A Bison parser, made by GNU Bison 3.5.1. */ +/* A Bison parser, made by GNU Bison 3.7.4. */ /* Bison interface for Yacc-like parsers in C @@ -46,8 +46,9 @@ This special exception was added by the Free Software Foundation in version 2.2 of Bison. */ -/* Undocumented macros, especially those whose name start with YY_, - are private implementation details. Do not rely on them. */ +/* DO NOT RELY ON FEATURES THAT ARE NOT DOCUMENTED in the manual, + especially those whose name start with YY_ or yy_. They are + private implementation details that can be changed or removed. */ #ifndef YY_SLEIGH_SLGHPARSE_HH_INCLUDED # define YY_SLEIGH_SLGHPARSE_HH_INCLUDED @@ -67,123 +68,128 @@ extern int sleighdebug; #endif -/* Token type. */ +/* Token kinds. */ #ifndef SLEIGHTOKENTYPE # define SLEIGHTOKENTYPE enum sleightokentype { - OP_BOOL_OR = 258, - OP_BOOL_AND = 259, - OP_BOOL_XOR = 260, - OP_OR = 261, - OP_XOR = 262, - OP_AND = 263, - OP_EQUAL = 264, - OP_NOTEQUAL = 265, - OP_FEQUAL = 266, - OP_FNOTEQUAL = 267, - OP_GREATEQUAL = 268, - OP_LESSEQUAL = 269, - OP_SLESS = 270, - OP_SGREATEQUAL = 271, - OP_SLESSEQUAL = 272, - OP_SGREAT = 273, - OP_FLESS = 274, - OP_FGREAT = 275, - OP_FLESSEQUAL = 276, - OP_FGREATEQUAL = 277, - OP_LEFT = 278, - OP_RIGHT = 279, - OP_SRIGHT = 280, - OP_FADD = 281, - OP_FSUB = 282, - OP_SDIV = 283, - OP_SREM = 284, - OP_FMULT = 285, - OP_FDIV = 286, - OP_ZEXT = 287, - OP_CARRY = 288, - OP_BORROW = 289, - OP_SEXT = 290, - OP_SCARRY = 291, - OP_SBORROW = 292, - OP_NAN = 293, - OP_ABS = 294, - OP_SQRT = 295, - OP_CEIL = 296, - OP_FLOOR = 297, - OP_ROUND = 298, - OP_INT2FLOAT = 299, - OP_FLOAT2FLOAT = 300, - OP_TRUNC = 301, - OP_CPOOLREF = 302, - OP_NEW = 303, - OP_POPCOUNT = 304, - OP_LZCOUNT = 305, - BADINTEGER = 306, - GOTO_KEY = 307, - CALL_KEY = 308, - RETURN_KEY = 309, - IF_KEY = 310, - DEFINE_KEY = 311, - ATTACH_KEY = 312, - MACRO_KEY = 313, - SPACE_KEY = 314, - TYPE_KEY = 315, - RAM_KEY = 316, - DEFAULT_KEY = 317, - REGISTER_KEY = 318, - ENDIAN_KEY = 319, - WITH_KEY = 320, - ALIGN_KEY = 321, - OP_UNIMPL = 322, - TOKEN_KEY = 323, - SIGNED_KEY = 324, - NOFLOW_KEY = 325, - HEX_KEY = 326, - DEC_KEY = 327, - BIG_KEY = 328, - LITTLE_KEY = 329, - SIZE_KEY = 330, - WORDSIZE_KEY = 331, - OFFSET_KEY = 332, - NAMES_KEY = 333, - VALUES_KEY = 334, - VARIABLES_KEY = 335, - PCODEOP_KEY = 336, - IS_KEY = 337, - LOCAL_KEY = 338, - DELAYSLOT_KEY = 339, - CROSSBUILD_KEY = 340, - EXPORT_KEY = 341, - BUILD_KEY = 342, - CONTEXT_KEY = 343, - ELLIPSIS_KEY = 344, - GLOBALSET_KEY = 345, - BITRANGE_KEY = 346, - CHAR = 347, - INTEGER = 348, - INTB = 349, - STRING = 350, - SYMBOLSTRING = 351, - SPACESYM = 352, - SECTIONSYM = 353, - TOKENSYM = 354, - USEROPSYM = 355, - VALUESYM = 356, - VALUEMAPSYM = 357, - CONTEXTSYM = 358, - NAMESYM = 359, - VARSYM = 360, - BITSYM = 361, - SPECSYM = 362, - VARLISTSYM = 363, - OPERANDSYM = 364, - JUMPSYM = 365, - MACROSYM = 366, - LABELSYM = 367, - SUBTABLESYM = 368 + SLEIGHEMPTY = -2, + SLEIGHEOF = 0, /* "end of file" */ + SLEIGHerror = 256, /* error */ + SLEIGHUNDEF = 257, /* "invalid token" */ + OP_BOOL_OR = 258, /* OP_BOOL_OR */ + OP_BOOL_AND = 259, /* OP_BOOL_AND */ + OP_BOOL_XOR = 260, /* OP_BOOL_XOR */ + OP_OR = 261, /* OP_OR */ + OP_XOR = 262, /* OP_XOR */ + OP_AND = 263, /* OP_AND */ + OP_EQUAL = 264, /* OP_EQUAL */ + OP_NOTEQUAL = 265, /* OP_NOTEQUAL */ + OP_FEQUAL = 266, /* OP_FEQUAL */ + OP_FNOTEQUAL = 267, /* OP_FNOTEQUAL */ + OP_GREATEQUAL = 268, /* OP_GREATEQUAL */ + OP_LESSEQUAL = 269, /* OP_LESSEQUAL */ + OP_SLESS = 270, /* OP_SLESS */ + OP_SGREATEQUAL = 271, /* OP_SGREATEQUAL */ + OP_SLESSEQUAL = 272, /* OP_SLESSEQUAL */ + OP_SGREAT = 273, /* OP_SGREAT */ + OP_FLESS = 274, /* OP_FLESS */ + OP_FGREAT = 275, /* OP_FGREAT */ + OP_FLESSEQUAL = 276, /* OP_FLESSEQUAL */ + OP_FGREATEQUAL = 277, /* OP_FGREATEQUAL */ + OP_LEFT = 278, /* OP_LEFT */ + OP_RIGHT = 279, /* OP_RIGHT */ + OP_SRIGHT = 280, /* OP_SRIGHT */ + OP_FADD = 281, /* OP_FADD */ + OP_FSUB = 282, /* OP_FSUB */ + OP_SDIV = 283, /* OP_SDIV */ + OP_SREM = 284, /* OP_SREM */ + OP_FMULT = 285, /* OP_FMULT */ + OP_FDIV = 286, /* OP_FDIV */ + OP_ZEXT = 287, /* OP_ZEXT */ + OP_CARRY = 288, /* OP_CARRY */ + OP_BORROW = 289, /* OP_BORROW */ + OP_SEXT = 290, /* OP_SEXT */ + OP_SCARRY = 291, /* OP_SCARRY */ + OP_SBORROW = 292, /* OP_SBORROW */ + OP_NAN = 293, /* OP_NAN */ + OP_ABS = 294, /* OP_ABS */ + OP_SQRT = 295, /* OP_SQRT */ + OP_CEIL = 296, /* OP_CEIL */ + OP_FLOOR = 297, /* OP_FLOOR */ + OP_ROUND = 298, /* OP_ROUND */ + OP_INT2FLOAT = 299, /* OP_INT2FLOAT */ + OP_FLOAT2FLOAT = 300, /* OP_FLOAT2FLOAT */ + OP_TRUNC = 301, /* OP_TRUNC */ + OP_CPOOLREF = 302, /* OP_CPOOLREF */ + OP_NEW = 303, /* OP_NEW */ + OP_POPCOUNT = 304, /* OP_POPCOUNT */ + OP_LZCOUNT = 305, /* OP_LZCOUNT */ + BADINTEGER = 306, /* BADINTEGER */ + GOTO_KEY = 307, /* GOTO_KEY */ + CALL_KEY = 308, /* CALL_KEY */ + RETURN_KEY = 309, /* RETURN_KEY */ + IF_KEY = 310, /* IF_KEY */ + DEFINE_KEY = 311, /* DEFINE_KEY */ + ATTACH_KEY = 312, /* ATTACH_KEY */ + MACRO_KEY = 313, /* MACRO_KEY */ + SPACE_KEY = 314, /* SPACE_KEY */ + TYPE_KEY = 315, /* TYPE_KEY */ + RAM_KEY = 316, /* RAM_KEY */ + DEFAULT_KEY = 317, /* DEFAULT_KEY */ + REGISTER_KEY = 318, /* REGISTER_KEY */ + ENDIAN_KEY = 319, /* ENDIAN_KEY */ + WITH_KEY = 320, /* WITH_KEY */ + ALIGN_KEY = 321, /* ALIGN_KEY */ + OP_UNIMPL = 322, /* OP_UNIMPL */ + TOKEN_KEY = 323, /* TOKEN_KEY */ + SIGNED_KEY = 324, /* SIGNED_KEY */ + NOFLOW_KEY = 325, /* NOFLOW_KEY */ + HEX_KEY = 326, /* HEX_KEY */ + DEC_KEY = 327, /* DEC_KEY */ + BIG_KEY = 328, /* BIG_KEY */ + LITTLE_KEY = 329, /* LITTLE_KEY */ + SIZE_KEY = 330, /* SIZE_KEY */ + WORDSIZE_KEY = 331, /* WORDSIZE_KEY */ + OFFSET_KEY = 332, /* OFFSET_KEY */ + NAMES_KEY = 333, /* NAMES_KEY */ + VALUES_KEY = 334, /* VALUES_KEY */ + VARIABLES_KEY = 335, /* VARIABLES_KEY */ + PCODEOP_KEY = 336, /* PCODEOP_KEY */ + IS_KEY = 337, /* IS_KEY */ + LOCAL_KEY = 338, /* LOCAL_KEY */ + DELAYSLOT_KEY = 339, /* DELAYSLOT_KEY */ + CROSSBUILD_KEY = 340, /* CROSSBUILD_KEY */ + EXPORT_KEY = 341, /* EXPORT_KEY */ + BUILD_KEY = 342, /* BUILD_KEY */ + CONTEXT_KEY = 343, /* CONTEXT_KEY */ + ELLIPSIS_KEY = 344, /* ELLIPSIS_KEY */ + GLOBALSET_KEY = 345, /* GLOBALSET_KEY */ + BITRANGE_KEY = 346, /* BITRANGE_KEY */ + CHAR = 347, /* CHAR */ + INTEGER = 348, /* INTEGER */ + INTB = 349, /* INTB */ + STRING = 350, /* STRING */ + SYMBOLSTRING = 351, /* SYMBOLSTRING */ + SPACESYM = 352, /* SPACESYM */ + SECTIONSYM = 353, /* SECTIONSYM */ + TOKENSYM = 354, /* TOKENSYM */ + USEROPSYM = 355, /* USEROPSYM */ + VALUESYM = 356, /* VALUESYM */ + VALUEMAPSYM = 357, /* VALUEMAPSYM */ + CONTEXTSYM = 358, /* CONTEXTSYM */ + NAMESYM = 359, /* NAMESYM */ + VARSYM = 360, /* VARSYM */ + BITSYM = 361, /* BITSYM */ + SPECSYM = 362, /* SPECSYM */ + VARLISTSYM = 363, /* VARLISTSYM */ + OPERANDSYM = 364, /* OPERANDSYM */ + JUMPSYM = 365, /* JUMPSYM */ + MACROSYM = 366, /* MACROSYM */ + LABELSYM = 367, /* LABELSYM */ + SUBTABLESYM = 368 /* SUBTABLESYM */ }; + typedef enum sleightokentype sleightoken_kind_t; #endif /* Value type. */ diff --git a/pypcode/sleigh/slghparse.y b/pypcode/sleigh/slghparse.y index cddc09f..27c326b 100644 --- a/pypcode/sleigh/slghparse.y +++ b/pypcode/sleigh/slghparse.y @@ -151,6 +151,14 @@ extern int sleigherror(const char *str ); %type specificsymbol %type id_or_nil +%destructor { delete $$; } INTEGER INTB STRING SYMBOLSTRING +%destructor { delete $$; } paramlist rtl rtlmid rtlbody rtlfirstsection rtlcontinue statement expr +%destructor { delete $$; } varnode integervarnode exportvarnode lhsvarnode jumpdest charstring +%destructor { if ($$) PatternEquation::release($$); } pequation elleq ellrt atomic constraint bitpat_or_nil +%destructor { PatternExpression::release($$); } pexpression +%destructor { delete $$; } spaceprop fielddef contextfielddef sizedstar stringlist stringpart anystringlist anystringpart +%destructor { delete $$; } oplist intblist intbpart valuelist valuepart varlist varpart contextlist contextblock + %% spec: endiandef | spec aligndef @@ -193,13 +201,13 @@ contextprop: DEFINE_KEY CONTEXT_KEY VARSYM { $$ = $3; } { slgh->reportError("All context definitions must come before constructors"); YYERROR; } } ; fielddef: STRING '=' '(' INTEGER ',' INTEGER ')' { $$ = new FieldQuality($1,$4,$6); } - | anysymbol '=' '(' INTEGER ',' INTEGER ')' { delete $4; delete $6; string errmsg = $1->getName()+": redefined as field"; slgh->reportError(errmsg); YYERROR; } + | anysymbol '=' '(' INTEGER ',' INTEGER ')' { $$ = (FieldQuality *)0; delete $4; delete $6; string errmsg = $1->getName()+": redefined as field"; slgh->reportError(errmsg); YYERROR; } | fielddef SIGNED_KEY { $$ = $1; $$->signext = true; } | fielddef HEX_KEY { $$ = $1; $$->hex = true; } | fielddef DEC_KEY { $$ = $1; $$->hex = false; } ; contextfielddef: STRING '=' '(' INTEGER ',' INTEGER ')' { $$ = new FieldQuality($1,$4,$6); } - | anysymbol '=' '(' INTEGER ',' INTEGER ')' { delete $4; delete $6; string errmsg = $1->getName()+": redefined as field"; slgh->reportError(errmsg); YYERROR; } + | anysymbol '=' '(' INTEGER ',' INTEGER ')' { $$ = (FieldQuality *)0; delete $4; delete $6; string errmsg = $1->getName()+": redefined as field"; slgh->reportError(errmsg); YYERROR; } | contextfielddef SIGNED_KEY { $$ = $1; $$->signext = true; } | contextfielddef NOFLOW_KEY { $$ = $1; $$->flow = false; } | contextfielddef HEX_KEY { $$ = $1; $$->hex = true; } @@ -208,7 +216,7 @@ contextfielddef: STRING '=' '(' INTEGER ',' INTEGER ')' { $$ = new FieldQuality( spacedef: spaceprop ';' { slgh->newSpace($1); } ; spaceprop: DEFINE_KEY SPACE_KEY STRING { $$ = new SpaceQuality(*$3); delete $3; } - | DEFINE_KEY SPACE_KEY anysymbol { string errmsg = $3->getName()+": redefined as space"; slgh->reportError(errmsg); YYERROR; } + | DEFINE_KEY SPACE_KEY anysymbol { $$ = (SpaceQuality *)0; string errmsg = $3->getName()+": redefined as space"; slgh->reportError(errmsg); YYERROR; } | spaceprop TYPE_KEY '=' RAM_KEY { $$ = $1; $$->type = SpaceQuality::ramtype; } | spaceprop TYPE_KEY '=' REGISTER_KEY { $$ = $1; $$->type = SpaceQuality::registertype; } | spaceprop SIZE_KEY '=' INTEGER { $$ = $1; $$->size = *$4; delete $4; } @@ -330,11 +338,11 @@ contextblock: { $$ = (vector *)0; } | '[' contextlist ']' { $$ = $2; } ; contextlist: { $$ = new vector; } - | contextlist CONTEXTSYM '=' pexpression ';' { $$ = $1; if (!slgh->contextMod($1,$2,$4)) { string errmsg="Cannot use 'inst_next' or 'inst_next2' to set context variable: "+$2->getName(); slgh->reportError(errmsg); YYERROR; } } + | contextlist CONTEXTSYM '=' pexpression ';' { $$ = $1; if (!slgh->contextMod($1,$2,$4)) { string errmsg="Cannot use 'inst_next' or 'inst_next2' to set context variable: "+$2->getName(); slgh->reportError(errmsg); delete $1; $4->layClaim(); PatternExpression::release($4); YYERROR; } } | contextlist GLOBALSET_KEY '(' familysymbol ',' CONTEXTSYM ')' ';' { $$ = $1; slgh->contextSet($1,$4,$6); } | contextlist GLOBALSET_KEY '(' specificsymbol ',' CONTEXTSYM ')' ';' { $$ = $1; slgh->contextSet($1,$4,$6); } | contextlist OPERANDSYM '=' pexpression ';' { $$ = $1; slgh->defineOperand($2,$4); } - | contextlist STRING { string errmsg="Expecting context symbol, not "+*$2; delete $2; slgh->reportError(errmsg); YYERROR; } + | contextlist STRING { $$ = (vector *)0; delete $1; string errmsg="Expecting context symbol, not "+*$2; delete $2; slgh->reportError(errmsg); YYERROR; } ; section_def: OP_LEFT STRING OP_RIGHT { $$ = slgh->newSectionSymbol( *$2 ); delete $2; } | OP_LEFT SECTIONSYM OP_RIGHT { $$ = $2; } @@ -347,11 +355,11 @@ rtlcontinue: rtlfirstsection { $$ = $1; } rtl: rtlmid { $$ = $1; if ($$->getOpvec().empty() && ($$->getResult() == (HandleTpl *)0)) slgh->recordNop(); } | rtlmid EXPORT_KEY exportvarnode ';' { $$ = slgh->setResultVarnode($1,$3); } | rtlmid EXPORT_KEY sizedstar lhsvarnode ';' { $$ = slgh->setResultStarVarnode($1,$3,$4); } - | rtlmid EXPORT_KEY STRING { string errmsg="Unknown export varnode: "+*$3; delete $3; slgh->reportError(errmsg); YYERROR; } - | rtlmid EXPORT_KEY sizedstar STRING { string errmsg="Unknown pointer varnode: "+*$4; delete $3; delete $4; slgh->reportError(errmsg); YYERROR; } + | rtlmid EXPORT_KEY STRING { $$ = (ConstructTpl *)0; delete $1; string errmsg="Unknown export varnode: "+*$3; delete $3; slgh->reportError(errmsg); YYERROR; } + | rtlmid EXPORT_KEY sizedstar STRING { $$ = (ConstructTpl *)0; delete $1; string errmsg="Unknown pointer varnode: "+*$4; delete $3; delete $4; slgh->reportError(errmsg); YYERROR; } ; rtlmid: /* EMPTY */ { $$ = slgh->enterSection(); } - | rtlmid statement { $$ = $1; if (!$$->addOpList(*$2)) { delete $2; slgh->reportError("Multiple delayslot declarations"); YYERROR; } delete $2; } + | rtlmid statement { $$ = $1; if (!$$->addOpList(*$2)) { delete $1; delete $2; slgh->reportError("Multiple delayslot declarations"); YYERROR; } delete $2; } | rtlmid LOCAL_KEY STRING ';' { $$ = $1; slgh->pcode.newLocalDefinition($3); } | rtlmid LOCAL_KEY STRING ':' INTEGER ';' { $$ = $1; slgh->pcode.newLocalDefinition($3,*$5); delete $5; } ; @@ -365,8 +373,8 @@ statement: lhsvarnode '=' expr ';' { $3->setOutput($1); $$ = ExprTree::toVector( | USEROPSYM '(' paramlist ')' ';' { $$ = slgh->pcode.createUserOpNoOut($1,$3); } | lhsvarnode '[' INTEGER ',' INTEGER ']' '=' expr ';' { $$ = slgh->pcode.assignBitRange($1,(uint4)*$3,(uint4)*$5,$8); delete $3, delete $5; } | BITSYM '=' expr ';' { $$=slgh->pcode.assignBitRange($1->getParentSymbol()->getVarnode(),$1->getBitOffset(),$1->numBits(),$3); } - | varnode ':' INTEGER '=' { delete $1; delete $3; slgh->reportError("Illegal truncation on left-hand side of assignment"); YYERROR; } - | varnode '(' INTEGER ')' { delete $1; delete $3; slgh->reportError("Illegal subpiece on left-hand side of assignment"); YYERROR; } + | varnode ':' INTEGER '=' { $$ = (vector *)0; delete $1; delete $3; slgh->reportError("Illegal truncation on left-hand side of assignment"); YYERROR; } + | varnode '(' INTEGER ')' { $$ = (vector *)0; delete $1; delete $3; slgh->reportError("Illegal subpiece on left-hand side of assignment"); YYERROR; } | BUILD_KEY OPERANDSYM ';' { $$ = slgh->pcode.createOpConst(BUILD,$2->getIndex()); } | CROSSBUILD_KEY varnode ',' SECTIONSYM ';' { $$ = slgh->createCrossBuild($2,$4); } | CROSSBUILD_KEY varnode ',' STRING ';' { $$ = slgh->createCrossBuild($2,slgh->newSectionSymbol(*$4)); delete $4; } @@ -376,7 +384,7 @@ statement: lhsvarnode '=' expr ';' { $3->setOutput($1); $$ = ExprTree::toVector( | GOTO_KEY '[' expr ']' ';' { $$ = slgh->pcode.createOpNoOut(CPUI_BRANCHIND,$3); } | CALL_KEY jumpdest ';' { $$ = slgh->pcode.createOpNoOut(CPUI_CALL,new ExprTree($2)); } | CALL_KEY '[' expr ']' ';' { $$ = slgh->pcode.createOpNoOut(CPUI_CALLIND,$3); } - | RETURN_KEY ';' { slgh->reportError("Must specify an indirect parameter for return"); YYERROR; } + | RETURN_KEY ';' { $$ = (vector *)0; slgh->reportError("Must specify an indirect parameter for return"); YYERROR; } | RETURN_KEY '[' expr ']' ';' { $$ = slgh->pcode.createOpNoOut(CPUI_RETURN,$3); } | MACROSYM '(' paramlist ')' ';' { $$ = slgh->createMacroUse($1,$3); } | label { $$ = slgh->pcode.placeLabel( $1 ); } @@ -447,7 +455,7 @@ expr: varnode { $$ = new ExprTree($1); } | specificsymbol '[' INTEGER ',' INTEGER ']' { $$ = slgh->pcode.createBitRange($1,(uint4)*$3,(uint4)*$5); delete $3, delete $5; } | BITSYM { $$=slgh->pcode.createBitRange($1->getParentSymbol(),$1->getBitOffset(),$1->numBits()); } | USEROPSYM '(' paramlist ')' { $$ = slgh->pcode.createUserOp($1,$3); } - | OP_CPOOLREF '(' paramlist ')' { if ((*$3).size() < 2) { string errmsg = "Must at least two inputs to cpool"; slgh->reportError(errmsg); YYERROR; } $$ = slgh->pcode.createVariadic(CPUI_CPOOLREF,$3); } + | OP_CPOOLREF '(' paramlist ')' { if ((*$3).size() < 2) { string errmsg = "Must be at least two inputs to cpool"; slgh->reportError(errmsg); delete $3; YYERROR; } $$ = slgh->pcode.createVariadic(CPUI_CPOOLREF,$3); } ; sizedstar: '*' '[' SPACESYM ']' ':' INTEGER { $$ = new StarQuality; $$->size = *$6; delete $6; $$->id=ConstTpl($3->getSpace()); } | '*' '[' SPACESYM ']' { $$ = new StarQuality; $$->size = 0; $$->id=ConstTpl($3->getSpace()); } @@ -460,12 +468,12 @@ jumpdest: JUMPSYM { VarnodeTpl *sym = $1->getVarnode(); $$ = new VarnodeTpl(Con | OPERANDSYM { $$ = $1->getVarnode(); $1->setCodeAddress(); } | INTEGER '[' SPACESYM ']' { AddrSpace *spc = $3->getSpace(); $$ = new VarnodeTpl(ConstTpl(spc),ConstTpl(ConstTpl::real,*$1),ConstTpl(ConstTpl::real,spc->getAddrSize())); delete $1; } | label { $$ = new VarnodeTpl(ConstTpl(slgh->getConstantSpace()),ConstTpl(ConstTpl::j_relative,$1->getIndex()),ConstTpl(ConstTpl::real,sizeof(uintm))); $1->incrementRefCount(); } - | STRING { string errmsg = "Unknown jump destination: "+*$1; delete $1; slgh->reportError(errmsg); YYERROR; } + | STRING { $$ = (VarnodeTpl *)0; string errmsg = "Unknown jump destination: "+*$1; delete $1; slgh->reportError(errmsg); YYERROR; } ; varnode: specificsymbol { $$ = $1->getVarnode(); } | integervarnode { $$ = $1; } - | STRING { string errmsg = "Unknown varnode parameter: "+*$1; delete $1; slgh->reportError(errmsg); YYERROR; } - | SUBTABLESYM { string errmsg = "Subtable not attached to operand: "+$1->getName(); slgh->reportError(errmsg); YYERROR; } + | STRING { $$ = (VarnodeTpl *)0; string errmsg = "Unknown varnode parameter: "+*$1; delete $1; slgh->reportError(errmsg); YYERROR; } + | SUBTABLESYM { $$ = (VarnodeTpl *)0; string errmsg = "Subtable not attached to operand: "+$1->getName(); slgh->reportError(errmsg); YYERROR; } ; integervarnode: INTEGER { $$ = new VarnodeTpl(ConstTpl(slgh->getConstantSpace()),ConstTpl(ConstTpl::real,*$1),ConstTpl(ConstTpl::real,0)); delete $1; } | BADINTEGER { $$ = new VarnodeTpl(ConstTpl(slgh->getConstantSpace()),ConstTpl(ConstTpl::real,0),ConstTpl(ConstTpl::real,0)); slgh->reportError("Parsed integer is too big (overflow)"); } @@ -474,8 +482,8 @@ integervarnode: INTEGER { $$ = new VarnodeTpl(ConstTpl(slgh->getConstantSpace() | '&' ':' INTEGER varnode { $$ = slgh->pcode.addressOf($4,*$3); delete $3; } ; lhsvarnode: specificsymbol { $$ = $1->getVarnode(); } - | STRING { string errmsg = "Unknown assignment varnode: "+*$1; delete $1; slgh->reportError(errmsg); YYERROR; } - | SUBTABLESYM { string errmsg = "Subtable not attached to operand: "+$1->getName(); slgh->reportError(errmsg); YYERROR; } + | STRING { $$ = (VarnodeTpl *)0; string errmsg = "Unknown assignment varnode: "+*$1; delete $1; slgh->reportError(errmsg); YYERROR; } + | SUBTABLESYM { $$ = (VarnodeTpl *)0; string errmsg = "Subtable not attached to operand: "+$1->getName(); slgh->reportError(errmsg); YYERROR; } ; label: '<' LABELSYM '>' { $$ = $2; } | '<' STRING '>' { $$ = slgh->pcode.defineLabel( $2 ); } @@ -484,8 +492,8 @@ exportvarnode: specificsymbol { $$ = $1->getVarnode(); } | '&' varnode { $$ = slgh->pcode.addressOf($2,0); } | '&' ':' INTEGER varnode { $$ = slgh->pcode.addressOf($4,*$3); delete $3; } | INTEGER ':' INTEGER { $$ = new VarnodeTpl(ConstTpl(slgh->getConstantSpace()),ConstTpl(ConstTpl::real,*$1),ConstTpl(ConstTpl::real,*$3)); delete $1; delete $3; } - | STRING { string errmsg="Unknown export varnode: "+*$1; delete $1; slgh->reportError(errmsg); YYERROR; } - | SUBTABLESYM { string errmsg = "Subtable not attached to operand: "+$1->getName(); slgh->reportError(errmsg); YYERROR; } + | STRING { $$ = (VarnodeTpl *)0; string errmsg="Unknown export varnode: "+*$1; delete $1; slgh->reportError(errmsg); YYERROR; } + | SUBTABLESYM { $$ = (VarnodeTpl *)0; string errmsg = "Subtable not attached to operand: "+$1->getName(); slgh->reportError(errmsg); YYERROR; } ; familysymbol: VALUESYM { $$ = $1; } | VALUEMAPSYM { $$ = $1; } @@ -511,7 +519,7 @@ intbpart: INTEGER { $$ = new vector; $$->push_back(intb(*$1)); delete $1; $$ = new vector; $$->push_back((intb)0xBADBEEF); delete $1; } | intbpart INTEGER { $$ = $1; $$->push_back(intb(*$2)); delete $2; } | intbpart '-' INTEGER { $$ = $1; $$->push_back(-intb(*$3)); delete $3; } - | intbpart STRING { if (*$2!="_") { string errmsg = "Expecting integer but saw: "+*$2; delete $2; slgh->reportError(errmsg); YYERROR; } + | intbpart STRING { if (*$2!="_") { string errmsg = "Expecting integer but saw: "+*$2; delete $1; delete $2; slgh->reportError(errmsg); YYERROR; } $$ = $1; $$->push_back((intb)0xBADBEEF); delete $2; } ; stringlist: '[' stringpart ']' { $$ = $2; } @@ -519,7 +527,7 @@ stringlist: '[' stringpart ']' { $$ = $2; } ; stringpart: STRING { $$ = new vector; $$->push_back( *$1 ); delete $1; } | stringpart STRING { $$ = $1; $$->push_back(*$2); delete $2; } - | stringpart anysymbol { string errmsg = $2->getName()+": redefined"; slgh->reportError(errmsg); YYERROR; } + | stringpart anysymbol { $$ = (vector *)0; delete $1; string errmsg = $2->getName()+": redefined"; slgh->reportError(errmsg); YYERROR; } ; anystringlist: '[' anystringpart ']' { $$ = $2; } ; @@ -536,7 +544,7 @@ valuepart: VALUESYM { $$ = new vector; $$->push_back( $1 ); } | CONTEXTSYM { $$ = new vector; $$->push_back($1); } | valuepart VALUESYM { $$ = $1; $$->push_back($2); } | valuepart CONTEXTSYM { $$ = $1; $$->push_back($2); } - | valuepart STRING { string errmsg = *$2+": is not a value pattern"; delete $2; slgh->reportError(errmsg); YYERROR; } + | valuepart STRING { $$ = (vector *)0; delete $1; string errmsg = *$2+": is not a value pattern"; delete $2; slgh->reportError(errmsg); YYERROR; } ; varlist: '[' varpart ']' { $$ = $2; } | VARSYM { $$ = new vector; $$->push_back($1); } @@ -545,7 +553,7 @@ varpart: VARSYM { $$ = new vector; $$->push_back($1); } | STRING { if (*$1!="_") { string errmsg = *$1+": is not a varnode symbol"; delete $1; slgh->reportError(errmsg); YYERROR; } $$ = new vector; $$->push_back((SleighSymbol *)0); delete $1; } | varpart VARSYM { $$ = $1; $$->push_back($2); } - | varpart STRING { if (*$2!="_") { string errmsg = *$2+": is not a varnode symbol"; delete $2; slgh->reportError(errmsg); YYERROR; } + | varpart STRING { if (*$2!="_") { string errmsg = *$2+": is not a varnode symbol"; delete $1; delete $2; slgh->reportError(errmsg); YYERROR; } $$ = $1; $$->push_back((SleighSymbol *)0); delete $2; } ; paramlist: /* EMPTY */ { $$ = new vector; } diff --git a/pypcode/sleigh/slghpatexpress.cc b/pypcode/sleigh/slghpatexpress.cc index 9410978..a724f30 100644 --- a/pypcode/sleigh/slghpatexpress.cc +++ b/pypcode/sleigh/slghpatexpress.cc @@ -4,9 +4,9 @@ * Licensed under the Apache License, Version 2.0 (the "License"); * you may not use this file except in compliance with the License. * You may obtain a copy of the License at - * + * * http://www.apache.org/licenses/LICENSE-2.0 - * + * * Unless required by applicable law or agreed to in writing, software * distributed under the License is distributed on an "AS IS" BASIS, * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. @@ -503,9 +503,13 @@ PatternExpression *PatternExpression::decodeExpression(Decoder &decoder,Translat else if (el == sla::ELEM_NOT_EXP) res = new NotExpression(); else - return (PatternExpression *)0; - - res->decode(decoder,trans); + throw DecoderError("Invalid pattern expression element"); + try { + res->decode(decoder,trans); + } catch(...) { + delete res; + throw; + } return res; } @@ -826,6 +830,9 @@ void OperandValue::decode(Decoder &decoder,Translate *trans) uintm ctid = decoder.readUnsignedInteger(sla::ATTRIB_CT); SleighBase *sleigh = (SleighBase *)trans; SubtableSymbol *tab = dynamic_cast(sleigh->findSymbol(tabid)); + if (ctid >= tab->getNumConstructors()) { + throw DecoderError("Invalid constructor id"); + } ct = tab->getConstructor(ctid); decoder.closeElement(el); } diff --git a/pypcode/sleigh/slghpattern.cc b/pypcode/sleigh/slghpattern.cc index fc99393..6253ca1 100644 --- a/pypcode/sleigh/slghpattern.cc +++ b/pypcode/sleigh/slghpattern.cc @@ -4,9 +4,9 @@ * Licensed under the Apache License, Version 2.0 (the "License"); * you may not use this file except in compliance with the License. * You may obtain a copy of the License at - * + * * http://www.apache.org/licenses/LICENSE-2.0 - * + * * Unless required by applicable law or agreed to in writing, software * distributed under the License is distributed on an "AS IS" BASIS, * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. @@ -141,16 +141,16 @@ bool DisjointPattern::resolvesIntersect(const DisjointPattern *op1,const Disjoin DisjointPattern *DisjointPattern::decodeDisjoint(Decoder &decoder) { // DisjointPattern factory - DisjointPattern *res; + unique_ptr res; uint4 el = decoder.peekElement(); if (el == sla::ELEM_INSTRUCT_PAT) - res = new InstructionPattern(); + res.reset(new InstructionPattern()); else if (el == sla::ELEM_CONTEXT_PAT) - res = new ContextPattern(); + res.reset(new ContextPattern()); else - res = new CombinePattern(); + res.reset(new CombinePattern()); res->decode(decoder); - return res; + return res.release(); } void PatternBlock::normalize(void) diff --git a/pypcode/sleigh/slghscan.cc b/pypcode/sleigh/slghscan.cc index 82f7e82..ee01186 100644 --- a/pypcode/sleigh/slghscan.cc +++ b/pypcode/sleigh/slghscan.cc @@ -4,9 +4,9 @@ * Licensed under the Apache License, Version 2.0 (the "License"); * you may not use this file except in compliance with the License. * You may obtain a copy of the License at - * + * * http://www.apache.org/licenses/LICENSE-2.0 - * + * * Unless required by applicable law or agreed to in writing, software * distributed under the License is distributed on an "AS IS" BASIS, * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. @@ -1126,9 +1126,9 @@ char *yytext; * Licensed under the Apache License, Version 2.0 (the "License"); * you may not use this file except in compliance with the License. * You may obtain a copy of the License at - * + * * http://www.apache.org/licenses/LICENSE-2.0 - * + * * Unless required by applicable law or agreed to in writing, software * distributed under the License is distributed on an "AS IS" BASIS, * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. diff --git a/pypcode/sleigh/slghsymbol.cc b/pypcode/sleigh/slghsymbol.cc index e62c470..deadf3b 100644 --- a/pypcode/sleigh/slghsymbol.cc +++ b/pypcode/sleigh/slghsymbol.cc @@ -49,10 +49,12 @@ SymbolTable::~SymbolTable(void) { vector::iterator iter; for(iter=table.begin();iter!=table.end();++iter) - delete *iter; + if (*iter) + delete *iter; vector::iterator siter; for(siter=symbollist.begin();siter!=symbollist.end();++siter) - delete *siter; + if (*siter) + delete *siter; } void SymbolTable::addScope(void) @@ -170,13 +172,33 @@ void SymbolTable::decode(Decoder &decoder,SleighBase *trans) { int4 el = decoder.openElement(sla::ELEM_SYMBOL_TABLE); - table.resize(decoder.readSignedInteger(sla::ATTRIB_SCOPESIZE), (SymbolScope *)0); - symbollist.resize(decoder.readSignedInteger(sla::ATTRIB_SYMBOLSIZE), (SleighSymbol *)0); + int8 tableSize = decoder.readSignedInteger(sla::ATTRIB_SCOPESIZE); + int8 symbolSize = decoder.readSignedInteger(sla::ATTRIB_SYMBOLSIZE); + if (tableSize < 0 || symbolSize < 0) + throw SleighError("Bad symbol table size"); + if (tableSize > MAX_TABLES) + throw SleighError("Maximum scopes exceeded"); + if (symbolSize > MAX_SYMBOLS) + throw SleighError("Maximum symbols exceeded"); + table.resize(tableSize, (SymbolScope *)0); + symbollist.resize(symbolSize, (SleighSymbol *)0); for(int4 i=0;i= table.size()) { + throw SleighError("Bad symbol scope id: exceeds symbol scope table size"); + } + uintm parent = decoder.readUnsignedInteger(sla::ATTRIB_PARENT); + if (parent >= table.size()) { + throw SleighError("Bad symbol scope parent id: exceeds symbol scope table size"); + } + SymbolScope *parscope = (parent==id) ? (SymbolScope *)0 : table[parent]; + if (table[id]) { + throw SleighError("Bad symbol scope parent id: not unique"); + } + table[id] = new SymbolScope( parscope, id ); decoder.closeElement(subel); } @@ -202,39 +224,58 @@ void SymbolTable::decodeSymbolHeader(Decoder &decoder) { // Put the shell of a symbol in the symbol table // in order to allow recursion - SleighSymbol *sym; + unique_ptr sym; uint4 el = decoder.peekElement(); if (el == sla::ELEM_USEROP_HEAD) - sym = new UserOpSymbol(); + sym.reset(new UserOpSymbol()); else if (el == sla::ELEM_EPSILON_SYM_HEAD) - sym = new EpsilonSymbol(); + sym.reset(new EpsilonSymbol()); else if (el == sla::ELEM_VALUE_SYM_HEAD) - sym = new ValueSymbol(); + sym.reset(new ValueSymbol()); else if (el == sla::ELEM_VALUEMAP_SYM_HEAD) - sym = new ValueMapSymbol(); + sym.reset(new ValueMapSymbol()); else if (el == sla::ELEM_NAME_SYM_HEAD) - sym = new NameSymbol(); + sym.reset(new NameSymbol()); else if (el == sla::ELEM_VARNODE_SYM_HEAD) - sym = new VarnodeSymbol(); + sym.reset(new VarnodeSymbol()); else if (el == sla::ELEM_CONTEXT_SYM_HEAD) - sym = new ContextSymbol(); + sym.reset(new ContextSymbol()); else if (el == sla::ELEM_VARLIST_SYM_HEAD) - sym = new VarnodeListSymbol(); + sym.reset(new VarnodeListSymbol()); else if (el == sla::ELEM_OPERAND_SYM_HEAD) - sym = new OperandSymbol(); + sym.reset(new OperandSymbol()); else if (el == sla::ELEM_START_SYM_HEAD) - sym = new StartSymbol(); + sym.reset(new StartSymbol()); else if (el == sla::ELEM_END_SYM_HEAD) - sym = new EndSymbol(); + sym.reset(new EndSymbol()); else if (el == sla::ELEM_NEXT2_SYM_HEAD) - sym = new Next2Symbol(); + sym.reset(new Next2Symbol()); else if (el == sla::ELEM_SUBTABLE_SYM_HEAD) - sym = new SubtableSymbol(); + sym.reset(new SubtableSymbol()); else throw SleighError("Bad symbol xml"); + sym->decodeHeader(decoder); // Restore basic elements of symbol - symbollist[sym->id] = sym; // Put the basic symbol in the table - table[sym->scopeid]->addSymbol(sym); // to allow recursion + + if (sym->id >= symbollist.size()) { + throw SleighError("Bad symbol id: exceeds symbollist size"); + } + + if (symbollist[sym->id] != (SleighSymbol *)0) { + throw SleighError("Bad symbol id: not unique"); + } + + if (sym->scopeid >= table.size()) { + throw SleighError("Bad symbol scope id: too large"); + } + + if (table[sym->scopeid] == (SymbolScope *)0) { + throw SleighError("Bad symbol scope id: undefined"); + } + + SleighSymbol *res = sym.release(); + symbollist[res->id] = res; // Put the basic symbol in the table + table[res->scopeid]->addSymbol(res); // to allow recursion } void SymbolTable::purge(void) @@ -500,6 +541,9 @@ void ValueSymbol::encodeHeader(Encoder &encoder) const void ValueSymbol::decode(Decoder &decoder,SleighBase *trans) { + if (patval) + throw DecoderError("Already decoded symbol"); + patval = (PatternValue *) PatternExpression::decodeExpression(decoder,trans); patval->layClaim(); decoder.closeElement(sla::ELEM_VALUE_SYM.getId()); @@ -581,6 +625,9 @@ void ValueMapSymbol::encodeHeader(Encoder &encoder) const void ValueMapSymbol::decode(Decoder &decoder,SleighBase *trans) { + if (patval) + throw DecoderError("Already decoded symbol"); + patval = (PatternValue *) PatternExpression::decodeExpression(decoder,trans); patval->layClaim(); while(decoder.peekElement() != 0) { @@ -660,6 +707,9 @@ void NameSymbol::encodeHeader(Encoder &encoder) const void NameSymbol::decode(Decoder &decoder,SleighBase *trans) { + if (patval) + throw DecoderError("Already decoded symbol"); + patval = (PatternValue *) PatternExpression::decodeExpression(decoder,trans); patval->layClaim(); while(decoder.peekElement() != 0) { @@ -794,6 +844,10 @@ void ContextSymbol::decode(Decoder &decoder,SleighBase *trans) if (lowMissing || highMissing) { throw DecoderError("Missing high/low attributes"); } + + if (patval) + throw DecoderError("Already decoded symbol"); + patval = (PatternValue *) PatternExpression::decodeExpression(decoder,trans); patval->layClaim(); decoder.closeElement(sla::ELEM_CONTEXT_SYM.getId()); @@ -898,6 +952,9 @@ void VarnodeListSymbol::encodeHeader(Encoder &encoder) const void VarnodeListSymbol::decode(Decoder &decoder,SleighBase *trans) { + if (patval) + throw DecoderError("Already decoded symbol"); + patval = (PatternValue *) PatternExpression::decodeExpression(decoder,trans); patval->layClaim(); while(decoder.peekElement() != 0) { @@ -945,7 +1002,9 @@ void OperandSymbol::defineOperand(TripleSymbol *tri) OperandSymbol::~OperandSymbol(void) { - PatternExpression::release(localexp); + if (localexp != (PatternExpression *)0) + PatternExpression::release(localexp); + if (defexp != (PatternExpression *)0) PatternExpression::release(defexp); } @@ -1040,6 +1099,9 @@ void OperandSymbol::encodeHeader(Encoder &encoder) const void OperandSymbol::decode(Decoder &decoder,SleighBase *trans) { + if (defexp || localexp) + throw DecoderError("Already decoded symbol"); + defexp = (PatternExpression *)0; triple = (TripleSymbol *)0; flags = 0; @@ -1631,28 +1693,28 @@ void Constructor::decode(Decoder &decoder,SleighBase *trans) } else if (subel == sla::ELEM_CONTEXT_OP) { ContextOp *c_op = new ContextOp(); - c_op->decode(decoder,trans); context.push_back(c_op); + c_op->decode(decoder,trans); } else if (subel == sla::ELEM_COMMIT) { ContextCommit *c_op = new ContextCommit(); - c_op->decode(decoder,trans); context.push_back(c_op); + c_op->decode(decoder,trans); } else { - ConstructTpl *cur = new ConstructTpl(); + unique_ptr cur(new ConstructTpl()); int4 sectionid = cur->decode(decoder); if (sectionid < 0) { if (templ != (ConstructTpl *)0) throw LowlevelError("Duplicate main section"); - templ = cur; + templ = cur.release(); } else { while(namedtempl.size() <= sectionid) namedtempl.push_back((ConstructTpl *)0); if (namedtempl[sectionid] != (ConstructTpl *)0) throw LowlevelError("Duplicate named section"); - namedtempl[sectionid] = cur; + namedtempl[sectionid] = cur.release(); } } subel = decoder.peekElement(); @@ -2334,6 +2396,9 @@ void DecisionNode::decode(Decoder &decoder,DecisionNode *par,SubtableSymbol *sub if (subel == sla::ELEM_PAIR) { decoder.openElement(); uintm id = decoder.readSignedInteger(sla::ATTRIB_ID); + if (id >= sub->getNumConstructors()) { + throw DecoderError("Invalid constructor id"); + } Constructor *ct = sub->getConstructor(id); DisjointPattern *pat = DisjointPattern::decodeDisjoint(decoder); list.push_back(pair(pat,ct)); @@ -2341,8 +2406,8 @@ void DecisionNode::decode(Decoder &decoder,DecisionNode *par,SubtableSymbol *sub } else if (subel == sla::ELEM_DECISION) { DecisionNode *subnode = new DecisionNode(); - subnode->decode(decoder,this,sub); children.push_back(subnode); + subnode->decode(decoder,this,sub); } subel = decoder.peekElement(); } diff --git a/pypcode/sleigh/slghsymbol.hh b/pypcode/sleigh/slghsymbol.hh index 5e8b4d3..e3be244 100644 --- a/pypcode/sleigh/slghsymbol.hh +++ b/pypcode/sleigh/slghsymbol.hh @@ -4,9 +4,9 @@ * Licensed under the Apache License, Version 2.0 (the "License"); * you may not use this file except in compliance with the License. * You may obtain a copy of the License at - * + * * http://www.apache.org/licenses/LICENSE-2.0 - * + * * Unless required by applicable law or agreed to in writing, software * distributed under the License is distributed on an "AS IS" BASIS, * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. @@ -76,6 +76,8 @@ class SymbolTable { SymbolScope *skipScope(int4 i) const; SleighSymbol *findSymbolInternal(SymbolScope *scope,const string &nm) const; void renumber(void); + static constexpr int8 MAX_TABLES = 0x100000; + static constexpr int8 MAX_SYMBOLS = 0x1000000; public: SymbolTable(void) { curscope = (SymbolScope *)0; } ~SymbolTable(void); @@ -326,7 +328,7 @@ private: void setVariableLength(void) { flags |= variable_len; } bool isVariableLength(void) const { return ((flags&variable_len)!=0); } public: - OperandSymbol(void) {} // For use with decode + OperandSymbol(void) : localexp(nullptr), defexp(nullptr) {} // For use with decode OperandSymbol(const string &nm,int4 index,Constructor *ct); uint4 getRelativeOffset(void) const { return reloffset; } int4 getOffsetBase(void) const { return offsetbase; } @@ -448,8 +450,8 @@ class ContextOp : public ContextChange { int4 shift; // Number of bits to shift value into place public: ContextOp(int4 startbit,int4 endbit,PatternExpression *pe); - ContextOp(void) {} // For use with decode - virtual ~ContextOp(void) { PatternExpression::release(patexp); } + ContextOp(void) : patexp(nullptr) {} // For use with decode + virtual ~ContextOp(void) { if (patexp) PatternExpression::release(patexp); } virtual void validate(void) const; virtual void encode(Encoder &encoder) const; virtual void decode(Decoder &decoder,SleighBase *trans); diff --git a/pypcode/sleigh/space.hh b/pypcode/sleigh/space.hh index bc88fcd..ff49ee9 100644 --- a/pypcode/sleigh/space.hh +++ b/pypcode/sleigh/space.hh @@ -4,9 +4,9 @@ * Licensed under the Apache License, Version 2.0 (the "License"); * you may not use this file except in compliance with the License. * You may obtain a copy of the License at - * + * * http://www.apache.org/licenses/LICENSE-2.0 - * + * * Unless required by applicable law or agreed to in writing, software * distributed under the License is distributed on an "AS IS" BASIS, * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. @@ -94,7 +94,8 @@ public: truncated = 0x100, ///< Space is truncated from its original size, expect pointers larger than this size hasphysical = 0x200, ///< Has physical memory associated with it is_otherspace = 0x400, ///< Quick check for the OtherSpace derived class - has_nearpointers = 0x800 ///< Does there exist near pointers into this space + has_nearpointers = 0x800, ///< Does there exist near pointers into this space + allows_wrapped_range = 0x1000 ///< A memory range for \b this space can wrap from high addresses to low }; private: spacetype type; ///< Type of space (PROCESSOR, CONSTANT, INTERNAL, ...) @@ -150,6 +151,7 @@ public: bool isOtherSpace(void) const; ///< Return \b true if \b this is the \e other address space bool isTruncated(void) const; ///< Return \b true if this space is truncated from its original size bool hasNearPointers(void) const; ///< Return \b true if \e near (truncated) pointers into \b this space are possible + bool allowsWrappedRange(void) const; ///< Return \b true if memory range can span high to low addresses in \b this space void printOffset(ostream &s,uintb offset) const; ///< Write an address offset to a stream virtual int4 numSpacebase(void) const; ///< Number of base registers associated with this space @@ -467,6 +469,10 @@ inline bool AddrSpace::hasNearPointers(void) const { return ((flags&has_nearpointers)!=0); } +inline bool AddrSpace::allowsWrappedRange(void) const { + return ((flags & allows_wrapped_range)!=0); +} + /// Some spaces are "virtual", like the stack spaces, where addresses are really relative to a /// base pointer stored in a register, like the stackpointer. This routine will return non-zero /// if \b this space is virtual and there is 1 (or more) associated pointer registers diff --git a/pypcode/sleigh/translate.cc b/pypcode/sleigh/translate.cc index 98060c2..d5b5219 100644 --- a/pypcode/sleigh/translate.cc +++ b/pypcode/sleigh/translate.cc @@ -61,6 +61,7 @@ SpacebaseSpace::SpacebaseSpace(AddrSpaceManager *m,const Translate *t,const stri contain = base; hasbaseregister = false; // No base register assigned yet isNegativeStack = true; // default stack growth + setFlags(allows_wrapped_range); if (isFormal) setFlags(formal_stackspace); } @@ -73,9 +74,10 @@ SpacebaseSpace::SpacebaseSpace(AddrSpaceManager *m,const Translate *t,const stri SpacebaseSpace::SpacebaseSpace(AddrSpaceManager *m,const Translate *t) : AddrSpace(m,t,IPTR_SPACEBASE) { + contain = (AddrSpace *)0; hasbaseregister = false; isNegativeStack = true; - setFlags(programspecific); + setFlags(programspecific | allows_wrapped_range); } /// This routine sets the base register associated with this \b virtual space @@ -258,20 +260,20 @@ AddrSpace *AddrSpaceManager::decodeSpace(Decoder &decoder,const Translate *trans { uint4 elemId = decoder.peekElement(); - AddrSpace *res; + unique_ptr res; if (elemId == ELEM_SPACE_BASE) - res = new SpacebaseSpace(this,trans); + res.reset(new SpacebaseSpace(this,trans)); else if (elemId == ELEM_SPACE_UNIQUE) - res = new UniqueSpace(this,trans); + res.reset(new UniqueSpace(this,trans)); else if (elemId == ELEM_SPACE_OTHER) - res = new OtherSpace(this,trans); + res.reset(new OtherSpace(this,trans)); else if (elemId == ELEM_SPACE_OVERLAY) - res = new OverlaySpace(this,trans); + res.reset(new OverlaySpace(this,trans)); else - res = new AddrSpace(this,trans,IPTR_PROCESSOR); + res.reset(new AddrSpace(this,trans,IPTR_PROCESSOR)); res->decode(decoder); - return res; + return res.release(); } /// This routine initializes (almost) all the address spaces used @@ -352,49 +354,49 @@ void AddrSpaceManager::setReverseJustified(AddrSpace *spc) void AddrSpaceManager::insertSpace(AddrSpace *spc) { - bool nameTypeMismatch = false; - bool duplicateName = false; - bool duplicateId = false; + unique_ptr owner; + if (spc->refcount == 0) + owner.reset(spc); // Take ownership if this is the first reference switch(spc->getType()) { case IPTR_CONSTANT: if (spc->getName() != ConstantSpace::NAME) - nameTypeMismatch = true; + throw LowlevelError("Space " + spc->getName() + " was initialized with wrong type"); if (spc->index != ConstantSpace::INDEX) throw LowlevelError("const space must be assigned index 0"); constantspace = spc; break; case IPTR_INTERNAL: if (spc->getName() != UniqueSpace::NAME) - nameTypeMismatch = true; + throw LowlevelError("Space " + spc->getName() + " was initialized with wrong type"); if (uniqspace != (AddrSpace *)0) - duplicateName = true; + throw LowlevelError("Space " + spc->getName() + " was initialized more than once"); uniqspace = spc; break; case IPTR_FSPEC: if (spc->getName() != "fspec") - nameTypeMismatch = true; + throw LowlevelError("Space " + spc->getName() + " was initialized with wrong type"); if (fspecspace != (AddrSpace *)0) - duplicateName = true; + throw LowlevelError("Space " + spc->getName() + " was initialized more than once"); fspecspace = spc; break; case IPTR_JOIN: if (spc->getName() != JoinSpace::NAME) - nameTypeMismatch = true; + throw LowlevelError("Space " + spc->getName() + " was initialized with wrong type"); if (joinspace != (AddrSpace *)0) - duplicateName = true; + throw LowlevelError("Space " + spc->getName() + " was initialized more than once"); joinspace = spc; break; case IPTR_IOP: if (spc->getName() != "iop") - nameTypeMismatch = true; + throw LowlevelError("Space " + spc->getName() + " was initialized with wrong type"); if (iopspace != (AddrSpace *)0) - duplicateName = true; + throw LowlevelError("Space " + spc->getName() + " was initialized more than once"); iopspace = spc; break; case IPTR_SPACEBASE: if (spc->getName() == "stack") { if (stackspace != (AddrSpace *)0) - duplicateName = true; + throw LowlevelError("Space " + spc->getName() + " was initialized more than once"); stackspace = spc; } // fallthru @@ -412,26 +414,14 @@ void AddrSpaceManager::insertSpace(AddrSpace *spc) if (baselist.size() <= spc->index) baselist.resize(spc->index+1, (AddrSpace *)0); - duplicateId = baselist[spc->index] != (AddrSpace *)0; + if (baselist[spc->index] != (AddrSpace *)0) + throw LowlevelError("Space " + spc->getName() + " was assigned id duplicating: "+baselist[spc->index]->getName()); - if (!nameTypeMismatch && !duplicateName && !duplicateId) { - duplicateName = !name2Space.insert(pair(spc->getName(),spc)).second; - } + if (!name2Space.insert(pair(spc->getName(),spc)).second) + throw LowlevelError("Space " + spc->getName() + " was initialized more than once"); - if (nameTypeMismatch || duplicateName || duplicateId) { - string errMsg = "Space " + spc->getName(); - if (nameTypeMismatch) - errMsg = errMsg + " was initialized with wrong type"; - if (duplicateName) - errMsg = errMsg + " was initialized more than once"; - if (duplicateId) - errMsg = errMsg + " was assigned as id duplicating: "+baselist[spc->index]->getName(); - if (spc->refcount == 0) - delete spc; - spc = (AddrSpace *)0; - throw LowlevelError(errMsg); - } baselist[spc->index] = spc; + owner.release(); spc->refcount += 1; assignShortcut(spc); } @@ -859,6 +849,38 @@ Address AddrSpaceManager::constructJoinAddress(const Translate *translate, return join->getUnified().getAddr(); } +/// Check if the address space allows wrapped ranges. If so, construct a \e joined address +/// out of the high address piece of the range and the low address piece. +/// \param addr is the initial address in the range +/// \param size is the number of bytes in the range +/// \return the address representing the wrapped range +Address AddrSpaceManager::constructWrappingAddress(const Address &addr,int4 size) + +{ + AddrSpace *spc = addr.getSpace(); + if (!spc->isHeritaged()) + return addr; // Size is ignored + uintb dist = spc->getHighest() - addr.getOffset() + 1; + if (size <= dist) + return addr; + if (!spc->allowsWrappedRange()) + throw LowlevelError("Trying to construct memory range beyond end of address space: "+spc->getName()); + int4 sizehi = (int4)dist; + int4 sizelo = size - sizehi; + vector pieces; + pieces.emplace_back(); + pieces.emplace_back(); + int4 highIndex = spc->isBigEndian() ? 0 : 1; + pieces[highIndex].space = spc; + pieces[highIndex].offset = addr.getOffset(); + pieces[highIndex].size = sizehi; + pieces[1-highIndex].space = spc; + pieces[1-highIndex].offset = 0; + pieces[1-highIndex].size = sizelo; + JoinRecord *join = findAddJoin(pieces,0); + return join->getUnified().getAddr(); +} + /// If an Address in the \e join AddressSpace is shifted from its original offset, it may no /// longer have a valid JoinRecord. The shift or size change may even make the address of /// one of the pieces a more natural representation. Given a new Address and size, this method @@ -1024,7 +1046,7 @@ const FloatFormat *Translate::getFloatFormat(int4 size) const void PcodeEmit::decodeOp(const Address &addr,Decoder &decoder) { - int4 opcode; + OpCode opcode; int4 isize; VarnodeData outvar; VarnodeData invar[16]; @@ -1033,14 +1055,19 @@ void PcodeEmit::decodeOp(const Address &addr,Decoder &decoder) uint4 elemId = decoder.openElement(ELEM_OP); isize = decoder.readSignedInteger(ATTRIB_SIZE); outptr = &outvar; - if (isize <= 16) + if (isize <= 16) { + if (isize < 0) + throw DecoderError("Bad size attribute"); opcode = PcodeOpRaw::decode(decoder, isize, invar, &outptr); + decoder.closeElement(elemId); + dump(addr,opcode,outptr,invar,isize); + } else { vector varStorage(isize,VarnodeData()); opcode = PcodeOpRaw::decode(decoder, isize, varStorage.data(), &outptr); + decoder.closeElement(elemId); + dump(addr,opcode,outptr,varStorage.data(),isize); } - decoder.closeElement(elemId); - dump(addr,(OpCode)opcode,outptr,invar,isize); } } // End namespace ghidra diff --git a/pypcode/sleigh/translate.hh b/pypcode/sleigh/translate.hh index 5abc655..0048fb7 100644 --- a/pypcode/sleigh/translate.hh +++ b/pypcode/sleigh/translate.hh @@ -278,6 +278,9 @@ public: /// \brief Build a logical whole from register pairs Address constructJoinAddress(const Translate *translate,const Address &hiaddr,int4 hisz,const Address &loaddr,int4 losz); + /// \brief Build a logical whole representing a range that \e wraps from a high address to a low address + Address constructWrappingAddress(const Address &addr,int4 size); + /// \brief Make sure a possibly offset \e join address has a proper JoinRecord void renormalizeJoinAddress(Address &addr,int4 size);