From 58a8c03a1b4fa2b0fd2f7a7317390a25cd87e555 Mon Sep 17 00:00:00 2001 From: Andrew Savonichev Date: Thu, 2 Jul 2026 17:40:36 +0900 Subject: [PATCH] [mlir][dxsa] Add ld, ld2dms, ld_raw, ld_structured, ld_uav_typed --- .../mlir/Dialect/DXSA/IR/DXSAResourceOps.td | 368 +++++++++++++ mlir/lib/Target/DXSA/BinaryParser.cpp | 221 ++++++++ mlir/test/Target/DXSA/asm/cs3.test | 8 +- mlir/test/Target/DXSA/hlsl/cs1.test | 18 +- mlir/test/Target/DXSA/hlsl/cs2.test | 87 ++- mlir/test/Target/DXSA/hlsl/cs4.test | 43 +- mlir/test/Target/DXSA/hlsl/cs5.test | 87 ++- mlir/test/Target/DXSA/hlsl/hs1.test | 11 +- mlir/test/Target/DXSA/hlsl/raw_buf1.test | 280 +++------- mlir/test/Target/DXSA/hlsl/srv_ms_load1.test | 82 +-- .../Target/DXSA/hlsl/srv_typed_load1.test | 64 +-- .../Target/DXSA/hlsl/srv_typed_load2.test | 28 +- mlir/test/Target/DXSA/hlsl/struct_buf1.test | 495 +++++------------- mlir/test/Target/DXSA/hlsl/uav_raw1.test | 41 +- .../DXSA/hlsl/uav_typed_load_store1.test | 49 +- .../DXSA/hlsl/uav_typed_load_store2.test | 69 +-- mlir/test/Target/DXSA/ld.test | 26 + mlir/test/Target/DXSA/ld2dms.test | 40 ++ mlir/test/Target/DXSA/ld_raw.test | 19 + mlir/test/Target/DXSA/ld_structured.test | 27 + mlir/test/Target/DXSA/ld_uav_typed.test | 27 + 21 files changed, 1123 insertions(+), 967 deletions(-) create mode 100644 mlir/test/Target/DXSA/ld.test create mode 100644 mlir/test/Target/DXSA/ld2dms.test create mode 100644 mlir/test/Target/DXSA/ld_raw.test create mode 100644 mlir/test/Target/DXSA/ld_structured.test create mode 100644 mlir/test/Target/DXSA/ld_uav_typed.test diff --git a/mlir/include/mlir/Dialect/DXSA/IR/DXSAResourceOps.td b/mlir/include/mlir/Dialect/DXSA/IR/DXSAResourceOps.td index 502d72d3be5c..d92f75809f2c 100644 --- a/mlir/include/mlir/Dialect/DXSA/IR/DXSAResourceOps.td +++ b/mlir/include/mlir/Dialect/DXSA/IR/DXSAResourceOps.td @@ -821,4 +821,372 @@ def DXSA_Gather4POCFeedback : DXSA_Op<"gather4_po_c_s"> { }]; } +//===----------------------------------------------------------------------===// +// dxsa.ld +//===----------------------------------------------------------------------===// + +def DXSA_Ld : DXSA_Op<"ld"> { + let summary = "simplified alternative to the `dxsa.sample` instruction"; + let description = [{ + Using the provided integer address, `dxsa.ld` fetches data from + the specified Buffer/Texture without any filtering (e.g. point + sampling). The source data may come from any Resource Type, + other than TextureCube. + + Unlike `dxsa.sample`, `dxsa.ld` is also capable of fetching data + from Buffers. + + This instruction is available in the Vertex Shader, Pixel Shader + and Geometry Shader. + + `src_address` provides the set of texture coordinates needed to + perform the sample in the form of unsigned integers. + + The optional `offset` operand suffix (address offset by immediate + integer) indicates that the texture coordinates for the sample are + to be offset by a set of provided immediate texel space integer + constant values. The literal values are a set of 4 bit 2's + complement numbers, having integer range [-8,7]. + + Example: + + ```mlir + dxsa.ld r<0>, r<0>, t<3, vector> + dxsa.ld r<2>, r<1, >, t<3, vector>, + ``` + }]; + + let arguments = (ins + DXSA_DstOperandAttr:$dst, + DXSA_SrcOperandAttr:$src_address, + DXSA_SrcOperandAttr:$src_resource, + OptionalAttr:$offset); + let results = (outs); + + let assemblyFormat = [{ + $dst `,` $src_address `,` $src_resource + (`,` $offset^)? + attr-dict + }]; +} + +def DXSA_LdFeedback : DXSA_Op<"ld_s"> { + let summary = "same as `dxsa.ld`, but with an additional status output"; + let description = [{ + `dst`, `src_address`, `src_resource`, `offset` operands are the + same as in `dxsa.ld` instruction. + + The `feedback` operand appends an additional 32 bit scalar Tiled + Resources shader feedback status output value. Can be NULL (or not + present) if not used. See Tiled Resources Texture Sampling + Features(5.9.4.5) for details. + + Example: + + ```mlir + dxsa.ld_s r<2>, r<1, >, t<3, vector>, r<3, >, + ``` + }]; + + let arguments = (ins + DXSA_DstOperandAttr:$dst, + DXSA_SrcOperandAttr:$src_address, + DXSA_SrcOperandAttr:$src_resource, + DXSA_DstOperandAttr:$feedback, + OptionalAttr:$offset); + let results = (outs); + + let assemblyFormat = [{ + $dst `,` $src_address `,` $src_resource `,` $feedback + (`,` $offset^)? + attr-dict + }]; +} + +//===----------------------------------------------------------------------===// +// dxsa.ld2dms +//===----------------------------------------------------------------------===// + +def DXSA_Ld2dms : DXSA_Op<"ld2dms"> { + let summary = "variant of `dxsa.ld` for reading individual samples out of 2d multisample textures"; + let description = [{ + Simplified alternative to the `dxsa.sample` instruction for MS + resources. Using the provided integer address and `sample_index`, + `dxsa.ld2dms` fetches data from the specified Texture without any + filtering (e.g. point sampling). `sample_index` does not have to + be a literal, the multisample count does not have to be specified + on the texture resource, and it works with depth/stencil views, + otherwise it is identical to the DX10 version of this instruction. + + Example: + + ```mlir + dxsa.ld2dms r<2, >, r<1, >, t<3, vector>, v<0, > + dxsa.ld2dms r<2, >, r<1, >, t<3, vector>, v<0, >, + ``` + }]; + + let arguments = (ins + DXSA_DstOperandAttr:$dst, + DXSA_SrcOperandAttr:$src_address, + DXSA_SrcOperandAttr:$src_resource, + DXSA_SrcOperandAttr:$sample_index, + OptionalAttr:$offset); + let results = (outs); + + let assemblyFormat = [{ + $dst `,` $src_address `,` $src_resource `,` $sample_index + (`,` $offset^)? + attr-dict + }]; +} + +def DXSA_Ld2dmsFeedback : DXSA_Op<"ld2dms_s"> { + let summary = "same as `dxsa.ld2dms`, but with an additional status output"; + let description = [{ + `dst`, `src_address`, `src_resource`, `sample_index`, `offset` + operands are the same as in `dxsa.ld2dms` instruction. + + The `feedback` operand appends an additional 32 bit scalar Tiled + Resources shader feedback status output value. Can be NULL (or not + present) if not used. See Tiled Resources Texture Sampling + Features(5.9.4.5) for details. + + Example: + + ```mlir + dxsa.ld2dms_s r<2, >, r<1, >, t<3, vector>, v<0, >, r<3, > + dxsa.ld2dms_s r<2, >, r<1, >, t<3, vector>, v<0, >, r<3, >, + ``` + }]; + + let arguments = (ins + DXSA_DstOperandAttr:$dst, + DXSA_SrcOperandAttr:$src_address, + DXSA_SrcOperandAttr:$src_resource, + DXSA_SrcOperandAttr:$sample_index, + DXSA_DstOperandAttr:$feedback, + OptionalAttr:$offset); + let results = (outs); + + let assemblyFormat = [{ + $dst `,` $src_address `,` $src_resource `,` $sample_index `,` $feedback + (`,` $offset^)? + attr-dict + }]; +} + +//===----------------------------------------------------------------------===// +// dxsa.ld_raw +//===----------------------------------------------------------------------===// + +def DXSA_LdRaw : DXSA_Op<"ld_raw"> { + let summary = "random-access read of a 1-4 32 bit components from a raw buffer"; + let description = [{ + The `dxsa.ld_raw` reads (1-4) component 32 bit from `src` at `src_offset`. + + `src` must be: + - Any shader stage: SRV (t#). + - Compute Shader or Pixel Shader: UAV (u#). + - Compute Shader:Thread Group Shared Memory (g#). + + `src_byte_offset` specifies the base 32-bit value in memory for a + window of 4 sequential 32-bit values in which data may be read + (depending on the swizzle and mask on other parameters). + + Example: + + ```mlir + dxsa.ld_raw r<0, >, r<0, >, g<0, vector, > + ``` + }]; + + let arguments = (ins + DXSA_DstOperandAttr:$dst, + DXSA_SrcOperandAttr:$src_byte_offset, + DXSA_SrcOperandAttr:$src); + let results = (outs); + + let assemblyFormat = [{ + $dst `,` $src_byte_offset `,` $src + attr-dict + }]; +} + +def DXSA_LdRawFeedback : DXSA_Op<"ld_raw_s"> { + let summary = "same as `dxsa.ld_raw`, but with an additional status output"; + let description = [{ + `dst`, `src_byte_offset`, `src` operands are the same as in + `dxsa.ld_raw` instruction. + + The `feedback` operand appends an additional 32 bit scalar Tiled + Resources shader feedback status output value. Can be NULL (or not present) + if not used. See Tiled Resources Texture Sampling Features(5.9.4.5) for + details. + + Example: + + ```mlir + dxsa.ld_raw_s r<5, >, r<0, >, u<1, vector, >, r<6, > + ``` + }]; + + let arguments = (ins + DXSA_DstOperandAttr:$dst, + DXSA_SrcOperandAttr:$src_byte_offset, + DXSA_SrcOperandAttr:$src, + DXSA_DstOperandAttr:$feedback); + let results = (outs); + + let assemblyFormat = [{ + $dst `,` $src_byte_offset `,` $src `,` $feedback + attr-dict + }]; +} + +//===----------------------------------------------------------------------===// +// dxsa.ld_structured +//===----------------------------------------------------------------------===// + +def DXSA_LdStructured : DXSA_Op<"ld_structured"> { + let summary = "random-access read of a 1-4 32 bit components from a structured buffer"; + let description = [{ + The `dxsa.ld_structured` reads (1-4) component 32bit from `src` at + `src_address` and `src_byte_offset`. + + `src` must be an SRV (t#), UAV (u#), or in the Compute Shader it can + also be Thread Group Shared Memory (g#). + + `src_address` specifies the index of the structure to read. + + `src_byte_offset` specifies the byte offset in the structure to + start reading from. + + Example: + + ```mlir + dxsa.ld_structured r<0, >, r<0, >, l(0x8), g<0, vector, > + ``` + }]; + + let arguments = (ins + DXSA_DstOperandAttr:$dst, + DXSA_SrcOperandAttr:$src_address, + DXSA_SrcOperandAttr:$src_byte_offset, + DXSA_SrcOperandAttr:$src); + let results = (outs); + + let assemblyFormat = [{ + $dst `,` $src_address `,` $src_byte_offset `,` $src + attr-dict + }]; +} + +def DXSA_LdStructuredFeedback : DXSA_Op<"ld_structured_s"> { + let summary = "same as `dxsa.ld_structured`, but with an additional status output"; + let description = [{ + `dst`, `src_address`, `src_byte_offset`, `src` operands are the + same as in `dxsa.ld_structured` instruction. + + The `feedback` operand appends an additional 32 bit scalar Tiled + Resources shader feedback status output value. Can be NULL (or not present) + if not used. See Tiled Resources Texture Sampling Features(5.9.4.5) for + details. + + Example: + + ```mlir + dxsa.ld_structured_s r<5, >, r<0, >, l(0x0), u<1, vector>, r<0, > + ``` + }]; + + let arguments = (ins + DXSA_DstOperandAttr:$dst, + DXSA_SrcOperandAttr:$src_address, + DXSA_SrcOperandAttr:$src_byte_offset, + DXSA_SrcOperandAttr:$src, + DXSA_DstOperandAttr:$feedback); + let results = (outs); + + let assemblyFormat = [{ + $dst `,` $src_address `,` $src_byte_offset `,` $src `,` $feedback + attr-dict + }]; +} + +//===----------------------------------------------------------------------===// +// dxsa.ld_uav_typed +//===----------------------------------------------------------------------===// + +def DXSA_LdUavTyped : DXSA_Op<"ld_uav_typed"> { + let summary = "random-access read of an element from a typed UAV"; + let description = [{ + The `dxsa.ld_uav_typed` reads 4 component element from `src_uav` + at the unsigned integer address in `src_address`, converted to 32 + bit per component based on the format, then written to `dst` in + Shader. + + `src_uav` is a UAV (u#) declared as typed. However, the type of the + bound resource must be R32_UINT/SINT/FLOAT. This is a limitation + on some D3D11 Hardware that is intended to be relaxed in future + releases. Note that `dxsa.store_uav_typed` has no such + limitation. + + The number of 32-bit unsigned integer components taken from + address are determined by the dimensionality of the resource + declared at `src_uav`. Addressing is the same as the `dxsa.ld` + instruction. + + Out of bounds addressing is the same as the `dxsa.ld` instruction. + + Example: + + ```mlir + dxsa.ld_uav_typed r<0, min16i, >, v<0, >, u<3, vector> + ``` + }]; + + let arguments = (ins + DXSA_DstOperandAttr:$dst, + DXSA_SrcOperandAttr:$src_address, + DXSA_SrcOperandAttr:$src_uav); + let results = (outs); + + let assemblyFormat = [{ + $dst `,` $src_address `,` $src_uav + attr-dict + }]; +} + +def DXSA_LdUavTypedFeedback : DXSA_Op<"ld_uav_typed_s"> { + let summary = "same as `dxsa.ld_uav_typed`, but with an additional status output"; + let description = [{ + `dst`, `src_address`, `src_uav` operands are the same as in + `dxsa.ld_uav_typed` instruction. + + The `feedback` operand appends an additional 32 bit scalar Tiled + Resources shader feedback status output value. Can be NULL (or not present) + if not used. See Tiled Resources Texture Sampling Features(5.9.4.5) for + details. + + Example: + + ```mlir + dxsa.ld_uav_typed_s r<0, min16i, >, v<0, >, u<3, vector, >, r<4, > + ``` + }]; + + let arguments = (ins + DXSA_DstOperandAttr:$dst, + DXSA_SrcOperandAttr:$src_address, + DXSA_SrcOperandAttr:$src_uav, + DXSA_DstOperandAttr:$feedback); + let results = (outs); + + let assemblyFormat = [{ + $dst `,` $src_address `,` $src_uav `,` $feedback + attr-dict + }]; +} + #endif // MLIR_DIALECT_DXSA_IR_DXSARESOURCEOPS diff --git a/mlir/lib/Target/DXSA/BinaryParser.cpp b/mlir/lib/Target/DXSA/BinaryParser.cpp index 74c790453192..ba1368850856 100644 --- a/mlir/lib/Target/DXSA/BinaryParser.cpp +++ b/mlir/lib/Target/DXSA/BinaryParser.cpp @@ -1251,6 +1251,88 @@ class DXBuilder { srcReferenceValue, feedback); } + Instruction buildLd(dxsa::DstOperandAttr dst, dxsa::SrcOperandAttr srcAddress, + dxsa::SrcOperandAttr srcResource, + dxsa::SampleOffsetAttr offset, Location loc) { + return dxsa::Ld::create(builder, loc, dst, srcAddress, srcResource, offset); + } + + Instruction buildLdFeedback(dxsa::DstOperandAttr dst, + dxsa::SrcOperandAttr srcAddress, + dxsa::SrcOperandAttr srcResource, + dxsa::DstOperandAttr feedback, + dxsa::SampleOffsetAttr offset, Location loc) { + return dxsa::LdFeedback::create(builder, loc, dst, srcAddress, srcResource, + feedback, offset); + } + + Instruction buildLd2dms(dxsa::DstOperandAttr dst, + dxsa::SrcOperandAttr srcAddress, + dxsa::SrcOperandAttr srcResource, + dxsa::SrcOperandAttr sampleIndex, + dxsa::SampleOffsetAttr offset, Location loc) { + return dxsa::Ld2dms::create(builder, loc, dst, srcAddress, srcResource, + sampleIndex, offset); + } + + Instruction buildLd2dmsFeedback(dxsa::DstOperandAttr dst, + dxsa::SrcOperandAttr srcAddress, + dxsa::SrcOperandAttr srcResource, + dxsa::SrcOperandAttr sampleIndex, + dxsa::DstOperandAttr feedback, + dxsa::SampleOffsetAttr offset, Location loc) { + return dxsa::Ld2dmsFeedback::create(builder, loc, dst, srcAddress, + srcResource, sampleIndex, feedback, + offset); + } + + Instruction buildLdRaw(dxsa::DstOperandAttr dst, + dxsa::SrcOperandAttr srcByteOffset, + dxsa::SrcOperandAttr src, Location loc) { + return dxsa::LdRaw::create(builder, loc, dst, srcByteOffset, src); + } + + Instruction buildLdRawFeedback(dxsa::DstOperandAttr dst, + dxsa::SrcOperandAttr srcByteOffset, + dxsa::SrcOperandAttr src, + dxsa::DstOperandAttr feedback, Location loc) { + return dxsa::LdRawFeedback::create(builder, loc, dst, srcByteOffset, src, + feedback); + } + + Instruction buildLdStructured(dxsa::DstOperandAttr dst, + dxsa::SrcOperandAttr srcAddress, + dxsa::SrcOperandAttr srcByteOffset, + dxsa::SrcOperandAttr src, Location loc) { + return dxsa::LdStructured::create(builder, loc, dst, srcAddress, + srcByteOffset, src); + } + + Instruction buildLdStructuredFeedback(dxsa::DstOperandAttr dst, + dxsa::SrcOperandAttr srcAddress, + dxsa::SrcOperandAttr srcByteOffset, + dxsa::SrcOperandAttr src, + dxsa::DstOperandAttr feedback, + Location loc) { + return dxsa::LdStructuredFeedback::create(builder, loc, dst, srcAddress, + srcByteOffset, src, feedback); + } + + Instruction buildLdUavTyped(dxsa::DstOperandAttr dst, + dxsa::SrcOperandAttr srcAddress, + dxsa::SrcOperandAttr srcUav, Location loc) { + return dxsa::LdUavTyped::create(builder, loc, dst, srcAddress, srcUav); + } + + Instruction buildLdUavTypedFeedback(dxsa::DstOperandAttr dst, + dxsa::SrcOperandAttr srcAddress, + dxsa::SrcOperandAttr srcUav, + dxsa::DstOperandAttr feedback, + Location loc) { + return dxsa::LdUavTypedFeedback::create(builder, loc, dst, srcAddress, + srcUav, feedback); + } + private: MLIRContext *context; OpBuilder builder; @@ -2311,6 +2393,133 @@ class Parser { return instr; } + FailureOr parseLdInstructions(uint32_t opcode, + ExtendedInstruction &ext, + size_t beginOffset, + uint32_t length, Location loc) { + dxsa::SampleOffsetAttr offset; + if (ext.sampleOffset) { + offset = builder.buildSampleOffsetAttr(*ext.sampleOffset); + } + + auto dst = parseDstOperand(); + FAILURE_IF_FAILED(dst); + + dxsa::DstOperandAttr feedback; + switch (opcode) { + case D3DWDDM1_3_SB_OPCODE_LD_FEEDBACK: + case D3DWDDM1_3_SB_OPCODE_LD_MS_FEEDBACK: + case D3DWDDM1_3_SB_OPCODE_LD_RAW_FEEDBACK: + case D3DWDDM1_3_SB_OPCODE_LD_STRUCTURED_FEEDBACK: + case D3DWDDM1_3_SB_OPCODE_LD_UAV_TYPED_FEEDBACK: + // For Feedback variant, feedback operand is the second dst + // register. + auto op = parseDstOperand(); + FAILURE_IF_FAILED(op); + feedback = *op; + break; + } + + FailureOr instr; + switch (opcode) { + case D3D10_SB_OPCODE_LD: + case D3DWDDM1_3_SB_OPCODE_LD_FEEDBACK: { + auto srcAddress = parseSrcOperand(); + FAILURE_IF_FAILED(srcAddress); + + auto srcResource = parseSrcOperand(); + FAILURE_IF_FAILED(srcResource); + + if (feedback) { + instr = builder.buildLdFeedback(*dst, *srcAddress, *srcResource, + feedback, offset, loc); + } else { + instr = builder.buildLd(*dst, *srcAddress, *srcResource, offset, loc); + } + break; + } + case D3D10_SB_OPCODE_LD_MS: + case D3DWDDM1_3_SB_OPCODE_LD_MS_FEEDBACK: { + auto srcAddress = parseSrcOperand(); + FAILURE_IF_FAILED(srcAddress); + + auto srcResource = parseSrcOperand(); + FAILURE_IF_FAILED(srcResource); + + auto sampleIndex = parseSrcOperand(); + FAILURE_IF_FAILED(sampleIndex); + + if (feedback) { + instr = + builder.buildLd2dmsFeedback(*dst, *srcAddress, *srcResource, + *sampleIndex, feedback, offset, loc); + } else { + instr = builder.buildLd2dms(*dst, *srcAddress, *srcResource, + *sampleIndex, offset, loc); + } + break; + } + case D3D11_SB_OPCODE_LD_RAW: + case D3DWDDM1_3_SB_OPCODE_LD_RAW_FEEDBACK: { + auto srcByteOffset = parseSrcOperand(); + FAILURE_IF_FAILED(srcByteOffset); + + auto src = parseSrcOperand(); + FAILURE_IF_FAILED(src); + + if (feedback) { + instr = builder.buildLdRawFeedback(*dst, *srcByteOffset, *src, feedback, + loc); + } else { + instr = builder.buildLdRaw(*dst, *srcByteOffset, *src, loc); + } + break; + } + case D3D11_SB_OPCODE_LD_STRUCTURED: + case D3DWDDM1_3_SB_OPCODE_LD_STRUCTURED_FEEDBACK: { + auto srcAddress = parseSrcOperand(); + FAILURE_IF_FAILED(srcAddress); + + auto srcByteOffset = parseSrcOperand(); + FAILURE_IF_FAILED(srcByteOffset); + + auto src = parseSrcOperand(); + FAILURE_IF_FAILED(src); + + if (feedback) { + instr = builder.buildLdStructuredFeedback( + *dst, *srcAddress, *srcByteOffset, *src, feedback, loc); + } else { + instr = builder.buildLdStructured(*dst, *srcAddress, *srcByteOffset, + *src, loc); + } + break; + } + case D3D11_SB_OPCODE_LD_UAV_TYPED: + case D3DWDDM1_3_SB_OPCODE_LD_UAV_TYPED_FEEDBACK: { + auto srcAddress = parseSrcOperand(); + FAILURE_IF_FAILED(srcAddress); + + auto srcUav = parseSrcOperand(); + FAILURE_IF_FAILED(srcUav); + + if (feedback) { + instr = builder.buildLdUavTypedFeedback(*dst, *srcAddress, *srcUav, + feedback, loc); + } else { + instr = builder.buildLdUavTyped(*dst, *srcAddress, *srcUav, loc); + } + break; + } + default: + llvm_unreachable("unhandled instruction"); + } + + FAILURE_IF_FAILED(instr); + FAILURE_IF_FAILED(verifyInstructionLength(beginOffset, length)); + return instr; + } + FailureOr parseDclInput(Location loc) { auto operand = parseDstOperand(); FAILURE_IF_FAILED(operand); @@ -3295,6 +3504,18 @@ class Parser { case D3DWDDM1_3_SB_OPCODE_GATHER4_PO_FEEDBACK: return parseGather4Instructions(opcode, extendedInst, beginOffset, instructionLengthInTokens, getLocation()); + case D3D10_SB_OPCODE_LD: + case D3D10_SB_OPCODE_LD_MS: + case D3D11_SB_OPCODE_LD_RAW: + case D3D11_SB_OPCODE_LD_STRUCTURED: + case D3D11_SB_OPCODE_LD_UAV_TYPED: + case D3DWDDM1_3_SB_OPCODE_LD_FEEDBACK: + case D3DWDDM1_3_SB_OPCODE_LD_MS_FEEDBACK: + case D3DWDDM1_3_SB_OPCODE_LD_RAW_FEEDBACK: + case D3DWDDM1_3_SB_OPCODE_LD_STRUCTURED_FEEDBACK: + case D3DWDDM1_3_SB_OPCODE_LD_UAV_TYPED_FEEDBACK: + return parseLdInstructions(opcode, extendedInst, beginOffset, + instructionLengthInTokens, getLocation()); } #undef SATURABLE_OP #undef PLAIN_OP diff --git a/mlir/test/Target/DXSA/asm/cs3.test b/mlir/test/Target/DXSA/asm/cs3.test index 91ffb8cc1011..1f4a5d92c295 100644 --- a/mlir/test/Target/DXSA/asm/cs3.test +++ b/mlir/test/Target/DXSA/asm/cs3.test @@ -27,13 +27,7 @@ // CHECK: dxsa.sync // CHECK: dxsa.sync // CHECK: dxsa.sync -// CHECK: %[[INDEX_4:.*]] = dxsa.index.imm {imm = 0 : i32} -// CHECK: %[[OPERAND_3:.*]] = dxsa.operand %[[INDEX_4]] {mask = 80 : i32, num_components = 4 : i32, type = 0 : i32} -// CHECK: %[[INDEX_5:.*]] = dxsa.index.imm {imm = 0 : i32} -// CHECK: %[[OPERAND_4:.*]] = dxsa.operand %[[INDEX_5]] {num_components = 4 : i32, one = 0 : i32, type = 0 : i32} -// CHECK: %[[INDEX_6:.*]] = dxsa.index.imm {imm = 0 : i32} -// CHECK: %[[OPERAND_5:.*]] = dxsa.operand %[[INDEX_6]] {num_components = 4 : i32, swizzle = dense<[2, 0, 3, 1]> : vector<4xi32>, type = 31 : i32} -// CHECK: dxsa.instruction "ld_raw" %[[OPERAND_3]], %[[OPERAND_4]], %[[OPERAND_5]] +// CHECK: dxsa.ld_raw r<0, >, r<0, >, g<0, vector, > // CHECK: dxsa.imm_atomic_iadd r<2, >, g<0>, r<1, >, vThreadIDInGroup<> // CHECK: dxsa.atomic_or g<0>, r<1, >, vThreadIDInGroup<> // CHECK: dxsa.atomic_cmp_store g<0>, r<1, >, vThreadIDInGroup<>, vThreadIDInGroup<> diff --git a/mlir/test/Target/DXSA/hlsl/cs1.test b/mlir/test/Target/DXSA/hlsl/cs1.test index 8a796da585b2..8d42ed4aface 100644 --- a/mlir/test/Target/DXSA/hlsl/cs1.test +++ b/mlir/test/Target/DXSA/hlsl/cs1.test @@ -15,22 +15,16 @@ // CHECK: dxsa.iadd r<0, >, r<0, >, r<0, > // CHECK: dxsa.iadd r<0, >, r<0, >, vThreadIDInGroup<> // CHECK: dxsa.iadd r<0, >, r<0, >, vThreadIDInGroupFlattened> +// CHECK: dxsa.ld_raw r<0, >, r<0, >, u<0, vector, > +// CHECK: dxsa.add r<0, >, r<0, >, l(0x40400000) +// CHECK: dxsa.sync // CHECK: %[[INDEX_0:.*]] = dxsa.index.imm {imm = 0 : i32} -// CHECK: %[[OPERAND_0:.*]] = dxsa.operand %[[INDEX_0]] {mask = 32 : i32, num_components = 4 : i32, type = 0 : i32} +// CHECK: %[[OPERAND_0:.*]] = dxsa.operand %[[INDEX_0]] {mask = 16 : i32, num_components = 4 : i32, type = 30 : i32} // CHECK: %[[INDEX_1:.*]] = dxsa.index.imm {imm = 0 : i32} // CHECK: %[[OPERAND_1:.*]] = dxsa.operand %[[INDEX_1]] {num_components = 4 : i32, one = 0 : i32, type = 0 : i32} // CHECK: %[[INDEX_2:.*]] = dxsa.index.imm {imm = 0 : i32} -// CHECK: %[[OPERAND_2:.*]] = dxsa.operand %[[INDEX_2]] {num_components = 4 : i32, swizzle = dense<0> : vector<4xi32>, type = 30 : i32} -// CHECK: dxsa.instruction "ld_raw" %[[OPERAND_0]], %[[OPERAND_1]], %[[OPERAND_2]] -// CHECK: dxsa.add r<0, >, r<0, >, l(0x40400000) -// CHECK: dxsa.sync -// CHECK: %[[INDEX_3:.*]] = dxsa.index.imm {imm = 0 : i32} -// CHECK: %[[OPERAND_3:.*]] = dxsa.operand %[[INDEX_3]] {mask = 16 : i32, num_components = 4 : i32, type = 30 : i32} -// CHECK: %[[INDEX_4:.*]] = dxsa.index.imm {imm = 0 : i32} -// CHECK: %[[OPERAND_4:.*]] = dxsa.operand %[[INDEX_4]] {num_components = 4 : i32, one = 0 : i32, type = 0 : i32} -// CHECK: %[[INDEX_5:.*]] = dxsa.index.imm {imm = 0 : i32} -// CHECK: %[[OPERAND_5:.*]] = dxsa.operand %[[INDEX_5]] {num_components = 4 : i32, one = 1 : i32, type = 0 : i32} -// CHECK: dxsa.instruction "store_raw" %[[OPERAND_3]], %[[OPERAND_4]], %[[OPERAND_5]] +// CHECK: %[[OPERAND_2:.*]] = dxsa.operand %[[INDEX_2]] {num_components = 4 : i32, one = 1 : i32, type = 0 : i32} +// CHECK: dxsa.instruction "store_raw" %[[OPERAND_0]], %[[OPERAND_1]], %[[OPERAND_2]] // CHECK: dxsa.sync // CHECK: dxsa.ret diff --git a/mlir/test/Target/DXSA/hlsl/cs2.test b/mlir/test/Target/DXSA/hlsl/cs2.test index 716279857b99..84c6e14d0904 100644 --- a/mlir/test/Target/DXSA/hlsl/cs2.test +++ b/mlir/test/Target/DXSA/hlsl/cs2.test @@ -17,74 +17,47 @@ // CHECK: dxsa.iadd r<0, >, r<0, >, r<0, > // CHECK: dxsa.iadd r<0, >, r<0, >, vThreadIDInGroup<> // CHECK: dxsa.iadd r<0, >, r<0, >, vThreadIDInGroupFlattened> +// CHECK: dxsa.ld_raw r<0, >, r<0, >, u<0, vector, > +// CHECK: dxsa.add r<1, min16f, >, r<0, >, l(0x40000000) // CHECK: %[[INDEX_0:.*]] = dxsa.index.imm {imm = 0 : i32} -// CHECK: %[[OPERAND_0:.*]] = dxsa.operand %[[INDEX_0]] {mask = 32 : i32, num_components = 4 : i32, type = 0 : i32} -// CHECK: %[[INDEX_1:.*]] = dxsa.index.imm {imm = 0 : i32} -// CHECK: %[[OPERAND_1:.*]] = dxsa.operand %[[INDEX_1]] {num_components = 4 : i32, one = 0 : i32, type = 0 : i32} +// CHECK: %[[OPERAND_0:.*]] = dxsa.operand %[[INDEX_0]] {mask = 16 : i32, num_components = 4 : i32, type = 31 : i32} +// CHECK: %[[OPERAND_1:.*]] = dxsa.operand {num_components = 4 : i32, one = 0 : i32, type = 36 : i32} +// CHECK: %[[OPERAND_2:.*]] = dxsa.operand.imm {imm = dense<4> : vector<1xi32>} +// CHECK: %[[INDEX_1:.*]] = dxsa.index.imm {imm = 1 : i32} +// CHECK: %[[OPERAND_3:.*]] = dxsa.operand %[[INDEX_1]] {min_precision = 1 : i32, num_components = 4 : i32, one = 0 : i32, type = 0 : i32} +// CHECK: dxsa.instruction "store_structured" %[[OPERAND_0]], %[[OPERAND_1]], %[[OPERAND_2]], %[[OPERAND_3]] // CHECK: %[[INDEX_2:.*]] = dxsa.index.imm {imm = 0 : i32} -// CHECK: %[[OPERAND_2:.*]] = dxsa.operand %[[INDEX_2]] {num_components = 4 : i32, swizzle = dense<0> : vector<4xi32>, type = 30 : i32} -// CHECK: dxsa.instruction "ld_raw" %[[OPERAND_0]], %[[OPERAND_1]], %[[OPERAND_2]] -// CHECK: dxsa.add r<1, min16f, >, r<0, >, l(0x40000000) +// CHECK: %[[OPERAND_4:.*]] = dxsa.operand %[[INDEX_2]] {mask = 16 : i32, num_components = 4 : i32, type = 31 : i32} +// CHECK: %[[OPERAND_5:.*]] = dxsa.operand {num_components = 4 : i32, one = 0 : i32, type = 36 : i32} +// CHECK: %[[OPERAND_6:.*]] = dxsa.operand.imm {imm = dense<8> : vector<1xi32>} // CHECK: %[[INDEX_3:.*]] = dxsa.index.imm {imm = 0 : i32} -// CHECK: %[[OPERAND_3:.*]] = dxsa.operand %[[INDEX_3]] {mask = 16 : i32, num_components = 4 : i32, type = 31 : i32} -// CHECK: %[[OPERAND_4:.*]] = dxsa.operand {num_components = 4 : i32, one = 0 : i32, type = 36 : i32} -// CHECK: %[[OPERAND_5:.*]] = dxsa.operand.imm {imm = dense<4> : vector<1xi32>} -// CHECK: %[[INDEX_4:.*]] = dxsa.index.imm {imm = 1 : i32} -// CHECK: %[[OPERAND_6:.*]] = dxsa.operand %[[INDEX_4]] {min_precision = 1 : i32, num_components = 4 : i32, one = 0 : i32, type = 0 : i32} -// CHECK: dxsa.instruction "store_structured" %[[OPERAND_3]], %[[OPERAND_4]], %[[OPERAND_5]], %[[OPERAND_6]] -// CHECK: %[[INDEX_5:.*]] = dxsa.index.imm {imm = 0 : i32} -// CHECK: %[[OPERAND_7:.*]] = dxsa.operand %[[INDEX_5]] {mask = 16 : i32, num_components = 4 : i32, type = 31 : i32} -// CHECK: %[[OPERAND_8:.*]] = dxsa.operand {num_components = 4 : i32, one = 0 : i32, type = 36 : i32} -// CHECK: %[[OPERAND_9:.*]] = dxsa.operand.imm {imm = dense<8> : vector<1xi32>} -// CHECK: %[[INDEX_6:.*]] = dxsa.index.imm {imm = 0 : i32} -// CHECK: %[[OPERAND_10:.*]] = dxsa.operand %[[INDEX_6]] {num_components = 4 : i32, one = 1 : i32, type = 0 : i32} -// CHECK: dxsa.instruction "store_structured" %[[OPERAND_7]], %[[OPERAND_8]], %[[OPERAND_9]], %[[OPERAND_10]] +// CHECK: %[[OPERAND_7:.*]] = dxsa.operand %[[INDEX_3]] {num_components = 4 : i32, one = 1 : i32, type = 0 : i32} +// CHECK: dxsa.instruction "store_structured" %[[OPERAND_4]], %[[OPERAND_5]], %[[OPERAND_6]], %[[OPERAND_7]] // CHECK: dxsa.ftoi r<2, min16i, >, r<0, > -// CHECK: %[[INDEX_7:.*]] = dxsa.index.imm {imm = 0 : i32} -// CHECK: %[[OPERAND_11:.*]] = dxsa.operand %[[INDEX_7]] {mask = 16 : i32, num_components = 4 : i32, type = 31 : i32} -// CHECK: %[[OPERAND_12:.*]] = dxsa.operand {num_components = 4 : i32, one = 0 : i32, type = 36 : i32} -// CHECK: %[[OPERAND_13:.*]] = dxsa.operand.imm {imm = dense<12> : vector<1xi32>} -// CHECK: %[[INDEX_8:.*]] = dxsa.index.imm {imm = 2 : i32} -// CHECK: %[[OPERAND_14:.*]] = dxsa.operand %[[INDEX_8]] {min_precision = 4 : i32, num_components = 4 : i32, one = 0 : i32, type = 0 : i32} -// CHECK: dxsa.instruction "store_structured" %[[OPERAND_11]], %[[OPERAND_12]], %[[OPERAND_13]], %[[OPERAND_14]] +// CHECK: %[[INDEX_4:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_8:.*]] = dxsa.operand %[[INDEX_4]] {mask = 16 : i32, num_components = 4 : i32, type = 31 : i32} +// CHECK: %[[OPERAND_9:.*]] = dxsa.operand {num_components = 4 : i32, one = 0 : i32, type = 36 : i32} +// CHECK: %[[OPERAND_10:.*]] = dxsa.operand.imm {imm = dense<12> : vector<1xi32>} +// CHECK: %[[INDEX_5:.*]] = dxsa.index.imm {imm = 2 : i32} +// CHECK: %[[OPERAND_11:.*]] = dxsa.operand %[[INDEX_5]] {min_precision = 4 : i32, num_components = 4 : i32, one = 0 : i32, type = 0 : i32} +// CHECK: dxsa.instruction "store_structured" %[[OPERAND_8]], %[[OPERAND_9]], %[[OPERAND_10]], %[[OPERAND_11]] // CHECK: dxsa.sync // CHECK: dxsa.iadd r<0, >, vThreadIDInGroupFlattened>, cb<[0, 0], vector, > -// CHECK: %[[INDEX_9:.*]] = dxsa.index.imm {imm = 0 : i32} -// CHECK: %[[OPERAND_15:.*]] = dxsa.operand %[[INDEX_9]] {mask = 128 : i32, num_components = 4 : i32, type = 0 : i32} -// CHECK: %[[INDEX_10:.*]] = dxsa.index.imm {imm = 0 : i32} -// CHECK: %[[OPERAND_16:.*]] = dxsa.operand %[[INDEX_10]] {num_components = 4 : i32, one = 2 : i32, type = 0 : i32} -// CHECK: %[[OPERAND_17:.*]] = dxsa.operand.imm {imm = dense<8> : vector<1xi32>} -// CHECK: %[[INDEX_11:.*]] = dxsa.index.imm {imm = 0 : i32} -// CHECK: %[[OPERAND_18:.*]] = dxsa.operand %[[INDEX_11]] {num_components = 4 : i32, swizzle = dense<0> : vector<4xi32>, type = 31 : i32} -// CHECK: dxsa.instruction "ld_structured" %[[OPERAND_15]], %[[OPERAND_16]], %[[OPERAND_17]], %[[OPERAND_18]] +// CHECK: dxsa.ld_structured r<0, >, r<0, >, l(0x8), g<0, vector, > // CHECK: dxsa.add r<0, >, r<0, >, r<0, > -// CHECK: %[[INDEX_12:.*]] = dxsa.index.imm {imm = 2 : i32} -// CHECK: %[[OPERAND_19:.*]] = dxsa.operand %[[INDEX_12]] {mask = 16 : i32, min_precision = 4 : i32, num_components = 4 : i32, type = 0 : i32} -// CHECK: %[[INDEX_13:.*]] = dxsa.index.imm {imm = 0 : i32} -// CHECK: %[[OPERAND_20:.*]] = dxsa.operand %[[INDEX_13]] {num_components = 4 : i32, one = 2 : i32, type = 0 : i32} -// CHECK: %[[OPERAND_21:.*]] = dxsa.operand.imm {imm = dense<12> : vector<1xi32>} -// CHECK: %[[INDEX_14:.*]] = dxsa.index.imm {imm = 0 : i32} -// CHECK: %[[OPERAND_22:.*]] = dxsa.operand %[[INDEX_14]] {num_components = 4 : i32, swizzle = dense<0> : vector<4xi32>, type = 31 : i32} -// CHECK: dxsa.instruction "ld_structured" %[[OPERAND_19]], %[[OPERAND_20]], %[[OPERAND_21]], %[[OPERAND_22]] +// CHECK: dxsa.ld_structured r<2, min16i, >, r<0, >, l(0xC), g<0, vector, > // CHECK: dxsa.itof r<0, >, r<2, min16i, > // CHECK: dxsa.add r<0, >, r<0, >, r<0, > // CHECK: dxsa.sync // CHECK: dxsa.sync -// CHECK: %[[INDEX_15:.*]] = dxsa.index.imm {imm = 1 : i32} -// CHECK: %[[OPERAND_23:.*]] = dxsa.operand %[[INDEX_15]] {mask = 16 : i32, min_precision = 1 : i32, num_components = 4 : i32, type = 0 : i32} -// CHECK: %[[INDEX_16:.*]] = dxsa.index.imm {imm = 0 : i32} -// CHECK: %[[OPERAND_24:.*]] = dxsa.operand %[[INDEX_16]] {num_components = 4 : i32, one = 2 : i32, type = 0 : i32} -// CHECK: %[[OPERAND_25:.*]] = dxsa.operand.imm {imm = dense<4> : vector<1xi32>} -// CHECK: %[[INDEX_17:.*]] = dxsa.index.imm {imm = 0 : i32} -// CHECK: %[[OPERAND_26:.*]] = dxsa.operand %[[INDEX_17]] {num_components = 4 : i32, swizzle = dense<0> : vector<4xi32>, type = 31 : i32} -// CHECK: dxsa.instruction "ld_structured" %[[OPERAND_23]], %[[OPERAND_24]], %[[OPERAND_25]], %[[OPERAND_26]] +// CHECK: dxsa.ld_structured r<1, min16f, >, r<0, >, l(0x4), g<0, vector, > // CHECK: dxsa.add r<0, >, r<0, >, r<1, min16f, > -// CHECK: %[[INDEX_18:.*]] = dxsa.index.imm {imm = 0 : i32} -// CHECK: %[[OPERAND_27:.*]] = dxsa.operand %[[INDEX_18]] {mask = 16 : i32, num_components = 4 : i32, type = 30 : i32} -// CHECK: %[[INDEX_19:.*]] = dxsa.index.imm {imm = 0 : i32} -// CHECK: %[[OPERAND_28:.*]] = dxsa.operand %[[INDEX_19]] {num_components = 4 : i32, one = 0 : i32, type = 0 : i32} -// CHECK: %[[INDEX_20:.*]] = dxsa.index.imm {imm = 0 : i32} -// CHECK: %[[OPERAND_29:.*]] = dxsa.operand %[[INDEX_20]] {num_components = 4 : i32, one = 1 : i32, type = 0 : i32} -// CHECK: dxsa.instruction "store_raw" %[[OPERAND_27]], %[[OPERAND_28]], %[[OPERAND_29]] +// CHECK: %[[INDEX_6:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_12:.*]] = dxsa.operand %[[INDEX_6]] {mask = 16 : i32, num_components = 4 : i32, type = 30 : i32} +// CHECK: %[[INDEX_7:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_13:.*]] = dxsa.operand %[[INDEX_7]] {num_components = 4 : i32, one = 0 : i32, type = 0 : i32} +// CHECK: %[[INDEX_8:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_14:.*]] = dxsa.operand %[[INDEX_8]] {num_components = 4 : i32, one = 1 : i32, type = 0 : i32} +// CHECK: dxsa.instruction "store_raw" %[[OPERAND_12]], %[[OPERAND_13]], %[[OPERAND_14]] // CHECK: dxsa.ret diff --git a/mlir/test/Target/DXSA/hlsl/cs4.test b/mlir/test/Target/DXSA/hlsl/cs4.test index 3645ca48a37c..4a67d9e5f330 100644 --- a/mlir/test/Target/DXSA/hlsl/cs4.test +++ b/mlir/test/Target/DXSA/hlsl/cs4.test @@ -17,21 +17,15 @@ // CHECK: dxsa.iadd r<0, >, r<0, >, r<0, > // CHECK: dxsa.iadd r<0, >, r<0, >, vThreadIDInGroup<> // CHECK: dxsa.iadd r<0, >, r<0, >, vThreadIDInGroupFlattened> +// CHECK: dxsa.ld_raw r<0, >, r<0, >, u<0, vector, > +// CHECK: dxsa.ftou r<0, >, r<0, > // CHECK: %[[INDEX_0:.*]] = dxsa.index.imm {imm = 0 : i32} -// CHECK: %[[OPERAND_0:.*]] = dxsa.operand %[[INDEX_0]] {mask = 32 : i32, num_components = 4 : i32, type = 0 : i32} +// CHECK: %[[OPERAND_0:.*]] = dxsa.operand %[[INDEX_0]] {mask = 16 : i32, num_components = 4 : i32, type = 31 : i32} +// CHECK: %[[OPERAND_1:.*]] = dxsa.operand {num_components = 4 : i32, one = 0 : i32, type = 36 : i32} +// CHECK: %[[OPERAND_2:.*]] = dxsa.operand.imm {imm = dense<16> : vector<1xi32>} // CHECK: %[[INDEX_1:.*]] = dxsa.index.imm {imm = 0 : i32} -// CHECK: %[[OPERAND_1:.*]] = dxsa.operand %[[INDEX_1]] {num_components = 4 : i32, one = 0 : i32, type = 0 : i32} -// CHECK: %[[INDEX_2:.*]] = dxsa.index.imm {imm = 0 : i32} -// CHECK: %[[OPERAND_2:.*]] = dxsa.operand %[[INDEX_2]] {num_components = 4 : i32, swizzle = dense<0> : vector<4xi32>, type = 30 : i32} -// CHECK: dxsa.instruction "ld_raw" %[[OPERAND_0]], %[[OPERAND_1]], %[[OPERAND_2]] -// CHECK: dxsa.ftou r<0, >, r<0, > -// CHECK: %[[INDEX_3:.*]] = dxsa.index.imm {imm = 0 : i32} -// CHECK: %[[OPERAND_3:.*]] = dxsa.operand %[[INDEX_3]] {mask = 16 : i32, num_components = 4 : i32, type = 31 : i32} -// CHECK: %[[OPERAND_4:.*]] = dxsa.operand {num_components = 4 : i32, one = 0 : i32, type = 36 : i32} -// CHECK: %[[OPERAND_5:.*]] = dxsa.operand.imm {imm = dense<16> : vector<1xi32>} -// CHECK: %[[INDEX_4:.*]] = dxsa.index.imm {imm = 0 : i32} -// CHECK: %[[OPERAND_6:.*]] = dxsa.operand %[[INDEX_4]] {num_components = 4 : i32, one = 2 : i32, type = 0 : i32} -// CHECK: dxsa.instruction "store_structured" %[[OPERAND_3]], %[[OPERAND_4]], %[[OPERAND_5]], %[[OPERAND_6]] +// CHECK: %[[OPERAND_3:.*]] = dxsa.operand %[[INDEX_1]] {num_components = 4 : i32, one = 2 : i32, type = 0 : i32} +// CHECK: dxsa.instruction "store_structured" %[[OPERAND_0]], %[[OPERAND_1]], %[[OPERAND_2]], %[[OPERAND_3]] // CHECK: dxsa.mov r<1, >, vThreadIDInGroupFlattened> // CHECK: dxsa.mov r<1, >, l(0x10) // CHECK: dxsa.imm_atomic_iadd r<2, >, g<0>, r<1, >, vThreadID<> @@ -44,22 +38,15 @@ // CHECK: dxsa.utof r<0, >, r<1, > // CHECK: dxsa.add r<0, >, r<0, >, r<0, > // CHECK: dxsa.iadd r<0, >, vThreadIDInGroupFlattened>, cb<[0, 0], vector, > -// CHECK: %[[INDEX_5:.*]] = dxsa.index.imm {imm = 0 : i32} -// CHECK: %[[OPERAND_7:.*]] = dxsa.operand %[[INDEX_5]] {mask = 64 : i32, num_components = 4 : i32, type = 0 : i32} -// CHECK: %[[INDEX_6:.*]] = dxsa.index.imm {imm = 0 : i32} -// CHECK: %[[OPERAND_8:.*]] = dxsa.operand %[[INDEX_6]] {num_components = 4 : i32, one = 2 : i32, type = 0 : i32} -// CHECK: %[[OPERAND_9:.*]] = dxsa.operand.imm {imm = dense<16> : vector<1xi32>} -// CHECK: %[[INDEX_7:.*]] = dxsa.index.imm {imm = 0 : i32} -// CHECK: %[[OPERAND_10:.*]] = dxsa.operand %[[INDEX_7]] {num_components = 4 : i32, swizzle = dense<0> : vector<4xi32>, type = 31 : i32} -// CHECK: dxsa.instruction "ld_structured" %[[OPERAND_7]], %[[OPERAND_8]], %[[OPERAND_9]], %[[OPERAND_10]] +// CHECK: dxsa.ld_structured r<0, >, r<0, >, l(0x10), g<0, vector, > // CHECK: dxsa.utof r<0, >, r<0, > // CHECK: dxsa.add r<0, >, r<0, >, r<0, > -// CHECK: %[[INDEX_8:.*]] = dxsa.index.imm {imm = 0 : i32} -// CHECK: %[[OPERAND_11:.*]] = dxsa.operand %[[INDEX_8]] {mask = 16 : i32, num_components = 4 : i32, type = 30 : i32} -// CHECK: %[[INDEX_9:.*]] = dxsa.index.imm {imm = 0 : i32} -// CHECK: %[[OPERAND_12:.*]] = dxsa.operand %[[INDEX_9]] {num_components = 4 : i32, one = 0 : i32, type = 0 : i32} -// CHECK: %[[INDEX_10:.*]] = dxsa.index.imm {imm = 0 : i32} -// CHECK: %[[OPERAND_13:.*]] = dxsa.operand %[[INDEX_10]] {num_components = 4 : i32, one = 1 : i32, type = 0 : i32} -// CHECK: dxsa.instruction "store_raw" %[[OPERAND_11]], %[[OPERAND_12]], %[[OPERAND_13]] +// CHECK: %[[INDEX_2:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_4:.*]] = dxsa.operand %[[INDEX_2]] {mask = 16 : i32, num_components = 4 : i32, type = 30 : i32} +// CHECK: %[[INDEX_3:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_5:.*]] = dxsa.operand %[[INDEX_3]] {num_components = 4 : i32, one = 0 : i32, type = 0 : i32} +// CHECK: %[[INDEX_4:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_6:.*]] = dxsa.operand %[[INDEX_4]] {num_components = 4 : i32, one = 1 : i32, type = 0 : i32} +// CHECK: dxsa.instruction "store_raw" %[[OPERAND_4]], %[[OPERAND_5]], %[[OPERAND_6]] // CHECK: dxsa.ret diff --git a/mlir/test/Target/DXSA/hlsl/cs5.test b/mlir/test/Target/DXSA/hlsl/cs5.test index 6e6e5163b20d..16634beba918 100644 --- a/mlir/test/Target/DXSA/hlsl/cs5.test +++ b/mlir/test/Target/DXSA/hlsl/cs5.test @@ -17,74 +17,47 @@ // CHECK: dxsa.iadd r<0, >, r<0, >, r<0, > // CHECK: dxsa.iadd r<0, >, r<0, >, vThreadIDInGroup<> // CHECK: dxsa.iadd r<0, >, r<0, >, vThreadIDInGroupFlattened> +// CHECK: dxsa.ld_raw r<0, >, r<0, >, u<0, vector, > +// CHECK: dxsa.add r<1, min16f, >, r<0, >, l(0x40000000) // CHECK: %[[INDEX_0:.*]] = dxsa.index.imm {imm = 0 : i32} -// CHECK: %[[OPERAND_0:.*]] = dxsa.operand %[[INDEX_0]] {mask = 32 : i32, num_components = 4 : i32, type = 0 : i32} -// CHECK: %[[INDEX_1:.*]] = dxsa.index.imm {imm = 0 : i32} -// CHECK: %[[OPERAND_1:.*]] = dxsa.operand %[[INDEX_1]] {num_components = 4 : i32, one = 0 : i32, type = 0 : i32} +// CHECK: %[[OPERAND_0:.*]] = dxsa.operand %[[INDEX_0]] {mask = 16 : i32, num_components = 4 : i32, type = 31 : i32} +// CHECK: %[[OPERAND_1:.*]] = dxsa.operand {num_components = 4 : i32, one = 0 : i32, type = 36 : i32} +// CHECK: %[[OPERAND_2:.*]] = dxsa.operand.imm {imm = dense<4> : vector<1xi32>} +// CHECK: %[[INDEX_1:.*]] = dxsa.index.imm {imm = 1 : i32} +// CHECK: %[[OPERAND_3:.*]] = dxsa.operand %[[INDEX_1]] {min_precision = 1 : i32, num_components = 4 : i32, one = 0 : i32, type = 0 : i32} +// CHECK: dxsa.instruction "store_structured" %[[OPERAND_0]], %[[OPERAND_1]], %[[OPERAND_2]], %[[OPERAND_3]] // CHECK: %[[INDEX_2:.*]] = dxsa.index.imm {imm = 0 : i32} -// CHECK: %[[OPERAND_2:.*]] = dxsa.operand %[[INDEX_2]] {num_components = 4 : i32, swizzle = dense<0> : vector<4xi32>, type = 30 : i32} -// CHECK: dxsa.instruction "ld_raw" %[[OPERAND_0]], %[[OPERAND_1]], %[[OPERAND_2]] -// CHECK: dxsa.add r<1, min16f, >, r<0, >, l(0x40000000) +// CHECK: %[[OPERAND_4:.*]] = dxsa.operand %[[INDEX_2]] {mask = 16 : i32, num_components = 4 : i32, type = 31 : i32} +// CHECK: %[[OPERAND_5:.*]] = dxsa.operand {num_components = 4 : i32, one = 0 : i32, type = 36 : i32} +// CHECK: %[[OPERAND_6:.*]] = dxsa.operand.imm {imm = dense<8> : vector<1xi32>} // CHECK: %[[INDEX_3:.*]] = dxsa.index.imm {imm = 0 : i32} -// CHECK: %[[OPERAND_3:.*]] = dxsa.operand %[[INDEX_3]] {mask = 16 : i32, num_components = 4 : i32, type = 31 : i32} -// CHECK: %[[OPERAND_4:.*]] = dxsa.operand {num_components = 4 : i32, one = 0 : i32, type = 36 : i32} -// CHECK: %[[OPERAND_5:.*]] = dxsa.operand.imm {imm = dense<4> : vector<1xi32>} -// CHECK: %[[INDEX_4:.*]] = dxsa.index.imm {imm = 1 : i32} -// CHECK: %[[OPERAND_6:.*]] = dxsa.operand %[[INDEX_4]] {min_precision = 1 : i32, num_components = 4 : i32, one = 0 : i32, type = 0 : i32} -// CHECK: dxsa.instruction "store_structured" %[[OPERAND_3]], %[[OPERAND_4]], %[[OPERAND_5]], %[[OPERAND_6]] -// CHECK: %[[INDEX_5:.*]] = dxsa.index.imm {imm = 0 : i32} -// CHECK: %[[OPERAND_7:.*]] = dxsa.operand %[[INDEX_5]] {mask = 16 : i32, num_components = 4 : i32, type = 31 : i32} -// CHECK: %[[OPERAND_8:.*]] = dxsa.operand {num_components = 4 : i32, one = 0 : i32, type = 36 : i32} -// CHECK: %[[OPERAND_9:.*]] = dxsa.operand.imm {imm = dense<8> : vector<1xi32>} -// CHECK: %[[INDEX_6:.*]] = dxsa.index.imm {imm = 0 : i32} -// CHECK: %[[OPERAND_10:.*]] = dxsa.operand %[[INDEX_6]] {num_components = 4 : i32, one = 1 : i32, type = 0 : i32} -// CHECK: dxsa.instruction "store_structured" %[[OPERAND_7]], %[[OPERAND_8]], %[[OPERAND_9]], %[[OPERAND_10]] +// CHECK: %[[OPERAND_7:.*]] = dxsa.operand %[[INDEX_3]] {num_components = 4 : i32, one = 1 : i32, type = 0 : i32} +// CHECK: dxsa.instruction "store_structured" %[[OPERAND_4]], %[[OPERAND_5]], %[[OPERAND_6]], %[[OPERAND_7]] // CHECK: dxsa.ftoi r<2, min16i, >, r<0, > -// CHECK: %[[INDEX_7:.*]] = dxsa.index.imm {imm = 0 : i32} -// CHECK: %[[OPERAND_11:.*]] = dxsa.operand %[[INDEX_7]] {mask = 16 : i32, num_components = 4 : i32, type = 31 : i32} -// CHECK: %[[OPERAND_12:.*]] = dxsa.operand {num_components = 4 : i32, one = 0 : i32, type = 36 : i32} -// CHECK: %[[OPERAND_13:.*]] = dxsa.operand.imm {imm = dense<12> : vector<1xi32>} -// CHECK: %[[INDEX_8:.*]] = dxsa.index.imm {imm = 2 : i32} -// CHECK: %[[OPERAND_14:.*]] = dxsa.operand %[[INDEX_8]] {min_precision = 4 : i32, num_components = 4 : i32, one = 0 : i32, type = 0 : i32} -// CHECK: dxsa.instruction "store_structured" %[[OPERAND_11]], %[[OPERAND_12]], %[[OPERAND_13]], %[[OPERAND_14]] +// CHECK: %[[INDEX_4:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_8:.*]] = dxsa.operand %[[INDEX_4]] {mask = 16 : i32, num_components = 4 : i32, type = 31 : i32} +// CHECK: %[[OPERAND_9:.*]] = dxsa.operand {num_components = 4 : i32, one = 0 : i32, type = 36 : i32} +// CHECK: %[[OPERAND_10:.*]] = dxsa.operand.imm {imm = dense<12> : vector<1xi32>} +// CHECK: %[[INDEX_5:.*]] = dxsa.index.imm {imm = 2 : i32} +// CHECK: %[[OPERAND_11:.*]] = dxsa.operand %[[INDEX_5]] {min_precision = 4 : i32, num_components = 4 : i32, one = 0 : i32, type = 0 : i32} +// CHECK: dxsa.instruction "store_structured" %[[OPERAND_8]], %[[OPERAND_9]], %[[OPERAND_10]], %[[OPERAND_11]] // CHECK: dxsa.sync // CHECK: dxsa.iadd r<0, >, vThreadIDInGroupFlattened>, cb<[0, 0], vector, > -// CHECK: %[[INDEX_9:.*]] = dxsa.index.imm {imm = 0 : i32} -// CHECK: %[[OPERAND_15:.*]] = dxsa.operand %[[INDEX_9]] {mask = 128 : i32, num_components = 4 : i32, type = 0 : i32} -// CHECK: %[[INDEX_10:.*]] = dxsa.index.imm {imm = 0 : i32} -// CHECK: %[[OPERAND_16:.*]] = dxsa.operand %[[INDEX_10]] {num_components = 4 : i32, one = 2 : i32, type = 0 : i32} -// CHECK: %[[OPERAND_17:.*]] = dxsa.operand.imm {imm = dense<8> : vector<1xi32>} -// CHECK: %[[INDEX_11:.*]] = dxsa.index.imm {imm = 0 : i32} -// CHECK: %[[OPERAND_18:.*]] = dxsa.operand %[[INDEX_11]] {num_components = 4 : i32, swizzle = dense<0> : vector<4xi32>, type = 31 : i32} -// CHECK: dxsa.instruction "ld_structured" %[[OPERAND_15]], %[[OPERAND_16]], %[[OPERAND_17]], %[[OPERAND_18]] +// CHECK: dxsa.ld_structured r<0, >, r<0, >, l(0x8), g<0, vector, > // CHECK: dxsa.add r<0, >, r<0, >, r<0, > -// CHECK: %[[INDEX_12:.*]] = dxsa.index.imm {imm = 2 : i32} -// CHECK: %[[OPERAND_19:.*]] = dxsa.operand %[[INDEX_12]] {mask = 16 : i32, min_precision = 4 : i32, num_components = 4 : i32, type = 0 : i32} -// CHECK: %[[INDEX_13:.*]] = dxsa.index.imm {imm = 0 : i32} -// CHECK: %[[OPERAND_20:.*]] = dxsa.operand %[[INDEX_13]] {num_components = 4 : i32, one = 2 : i32, type = 0 : i32} -// CHECK: %[[OPERAND_21:.*]] = dxsa.operand.imm {imm = dense<12> : vector<1xi32>} -// CHECK: %[[INDEX_14:.*]] = dxsa.index.imm {imm = 0 : i32} -// CHECK: %[[OPERAND_22:.*]] = dxsa.operand %[[INDEX_14]] {num_components = 4 : i32, swizzle = dense<0> : vector<4xi32>, type = 31 : i32} -// CHECK: dxsa.instruction "ld_structured" %[[OPERAND_19]], %[[OPERAND_20]], %[[OPERAND_21]], %[[OPERAND_22]] +// CHECK: dxsa.ld_structured r<2, min16i, >, r<0, >, l(0xC), g<0, vector, > // CHECK: dxsa.itof r<0, >, r<2, min16i, > // CHECK: dxsa.add r<0, >, r<0, >, r<0, > // CHECK: dxsa.sync // CHECK: dxsa.sync -// CHECK: %[[INDEX_15:.*]] = dxsa.index.imm {imm = 1 : i32} -// CHECK: %[[OPERAND_23:.*]] = dxsa.operand %[[INDEX_15]] {mask = 16 : i32, min_precision = 1 : i32, num_components = 4 : i32, type = 0 : i32} -// CHECK: %[[INDEX_16:.*]] = dxsa.index.imm {imm = 0 : i32} -// CHECK: %[[OPERAND_24:.*]] = dxsa.operand %[[INDEX_16]] {num_components = 4 : i32, one = 2 : i32, type = 0 : i32} -// CHECK: %[[OPERAND_25:.*]] = dxsa.operand.imm {imm = dense<4> : vector<1xi32>} -// CHECK: %[[INDEX_17:.*]] = dxsa.index.imm {imm = 0 : i32} -// CHECK: %[[OPERAND_26:.*]] = dxsa.operand %[[INDEX_17]] {num_components = 4 : i32, swizzle = dense<0> : vector<4xi32>, type = 31 : i32} -// CHECK: dxsa.instruction "ld_structured" %[[OPERAND_23]], %[[OPERAND_24]], %[[OPERAND_25]], %[[OPERAND_26]] +// CHECK: dxsa.ld_structured r<1, min16f, >, r<0, >, l(0x4), g<0, vector, > // CHECK: dxsa.add r<0, >, r<0, >, r<1, min16f, > -// CHECK: %[[INDEX_18:.*]] = dxsa.index.imm {imm = 0 : i32} -// CHECK: %[[OPERAND_27:.*]] = dxsa.operand %[[INDEX_18]] {mask = 16 : i32, num_components = 4 : i32, type = 30 : i32} -// CHECK: %[[INDEX_19:.*]] = dxsa.index.imm {imm = 0 : i32} -// CHECK: %[[OPERAND_28:.*]] = dxsa.operand %[[INDEX_19]] {num_components = 4 : i32, one = 0 : i32, type = 0 : i32} -// CHECK: %[[INDEX_20:.*]] = dxsa.index.imm {imm = 0 : i32} -// CHECK: %[[OPERAND_29:.*]] = dxsa.operand %[[INDEX_20]] {num_components = 4 : i32, one = 1 : i32, type = 0 : i32} -// CHECK: dxsa.instruction "store_raw" %[[OPERAND_27]], %[[OPERAND_28]], %[[OPERAND_29]] +// CHECK: %[[INDEX_6:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_12:.*]] = dxsa.operand %[[INDEX_6]] {mask = 16 : i32, num_components = 4 : i32, type = 30 : i32} +// CHECK: %[[INDEX_7:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_13:.*]] = dxsa.operand %[[INDEX_7]] {num_components = 4 : i32, one = 0 : i32, type = 0 : i32} +// CHECK: %[[INDEX_8:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_14:.*]] = dxsa.operand %[[INDEX_8]] {num_components = 4 : i32, one = 1 : i32, type = 0 : i32} +// CHECK: dxsa.instruction "store_raw" %[[OPERAND_12]], %[[OPERAND_13]], %[[OPERAND_14]] // CHECK: dxsa.ret diff --git a/mlir/test/Target/DXSA/hlsl/hs1.test b/mlir/test/Target/DXSA/hlsl/hs1.test index 228546bfa879..671265be40d6 100644 --- a/mlir/test/Target/DXSA/hlsl/hs1.test +++ b/mlir/test/Target/DXSA/hlsl/hs1.test @@ -21,16 +21,7 @@ // CHECK: dxsa.mov r<0, >, vPrim // CHECK: dxsa.ftou r<0, >, v<[r<0, >, 0], > // CHECK: dxsa.ftoi r<1>, v<[r<0, >, 0], > -// CHECK: %[[INDEX_0:.*]] = dxsa.index.imm {imm = 0 : i32} -// CHECK: %[[OPERAND_0:.*]] = dxsa.operand %[[INDEX_0]] {mask = 224 : i32, num_components = 4 : i32, type = 0 : i32} -// CHECK: %[[INDEX_1:.*]] = dxsa.index.imm {imm = 1 : i32} -// CHECK: %[[OPERAND_1:.*]] = dxsa.operand %[[INDEX_1]] {num_components = 4 : i32, swizzle = dense<[0, 1, 2, 3]> : vector<4xi32>, type = 0 : i32} -// CHECK: %[[INDEX_2:.*]] = dxsa.index.imm {imm = 0 : i32} -// CHECK: %[[INDEX_3:.*]] = dxsa.index.imm {imm = 0 : i32} -// CHECK: %[[OPERAND_2:.*]] = dxsa.operand %[[INDEX_3]] {num_components = 4 : i32, one = 1 : i32, type = 0 : i32} -// CHECK: %[[INDEX_4:.*]] = dxsa.index.rel.imm %[[OPERAND_2]] {imm = 20 : i32, op = "add"} -// CHECK: %[[OPERAND_3:.*]] = dxsa.operand %[[INDEX_2]], %[[INDEX_4]] {num_components = 4 : i32, swizzle = dense<[3, 0, 1, 2]> : vector<4xi32>, type = 7 : i32} -// CHECK: dxsa.instruction "ld" %[[OPERAND_0]], %[[OPERAND_1]], %[[OPERAND_3]] +// CHECK: dxsa.ld r<0, >, r<1>, t<[0, 20 + r<0, >], vector, > // CHECK: dxsa.add r<0, >, r<0, >, v<[r<0, >, 0], > // CHECK: dxsa.itof r<0, >, cb<[0, 0, 0], vector, > // CHECK: dxsa.add r<0, >, r<0, >, r<0, > diff --git a/mlir/test/Target/DXSA/hlsl/raw_buf1.test b/mlir/test/Target/DXSA/hlsl/raw_buf1.test index 58e200812c02..4cb6bec9adcc 100644 --- a/mlir/test/Target/DXSA/hlsl/raw_buf1.test +++ b/mlir/test/Target/DXSA/hlsl/raw_buf1.test @@ -10,177 +10,65 @@ // CHECK: dxsa.dcl_output o<0> // CHECK: dxsa.dcl_temps 16 // CHECK: dxsa.ftou r<0, >, v<0, > -// CHECK: %[[INDEX_0:.*]] = dxsa.index.imm {imm = 0 : i32} -// CHECK: %[[OPERAND_0:.*]] = dxsa.operand %[[INDEX_0]] {mask = 64 : i32, num_components = 4 : i32, type = 0 : i32} -// CHECK: %[[INDEX_1:.*]] = dxsa.index.imm {imm = 0 : i32} -// CHECK: %[[OPERAND_1:.*]] = dxsa.operand %[[INDEX_1]] {num_components = 4 : i32, one = 0 : i32, type = 0 : i32} -// CHECK: %[[INDEX_2:.*]] = dxsa.index.imm {imm = 1 : i32} -// CHECK: %[[OPERAND_2:.*]] = dxsa.operand %[[INDEX_2]] {num_components = 4 : i32, swizzle = dense<0> : vector<4xi32>, type = 30 : i32} -// CHECK: dxsa.instruction "ld_raw" %[[OPERAND_0]], %[[OPERAND_1]], %[[OPERAND_2]] +// CHECK: dxsa.ld_raw r<0, >, r<0, >, u<1, vector, > // CHECK: dxsa.add r<1, >, v<0, >, l(0x3F800000, 0x40000000, 0x40400000, 0x0) // CHECK: dxsa.ftou r<1, >, r<1, > -// CHECK: %[[INDEX_3:.*]] = dxsa.index.imm {imm = 2 : i32} -// CHECK: %[[OPERAND_3:.*]] = dxsa.operand %[[INDEX_3]] {mask = 48 : i32, num_components = 4 : i32, type = 0 : i32} -// CHECK: %[[INDEX_4:.*]] = dxsa.index.imm {imm = 1 : i32} -// CHECK: %[[OPERAND_4:.*]] = dxsa.operand %[[INDEX_4]] {num_components = 4 : i32, one = 0 : i32, type = 0 : i32} -// CHECK: %[[INDEX_5:.*]] = dxsa.index.imm {imm = 1 : i32} -// CHECK: %[[OPERAND_5:.*]] = dxsa.operand %[[INDEX_5]] {num_components = 4 : i32, swizzle = dense<[0, 1, 0, 0]> : vector<4xi32>, type = 30 : i32} -// CHECK: dxsa.instruction "ld_raw" %[[OPERAND_3]], %[[OPERAND_4]], %[[OPERAND_5]] -// CHECK: %[[INDEX_6:.*]] = dxsa.index.imm {imm = 3 : i32} -// CHECK: %[[OPERAND_6:.*]] = dxsa.operand %[[INDEX_6]] {mask = 112 : i32, num_components = 4 : i32, type = 0 : i32} -// CHECK: %[[INDEX_7:.*]] = dxsa.index.imm {imm = 1 : i32} -// CHECK: %[[OPERAND_7:.*]] = dxsa.operand %[[INDEX_7]] {num_components = 4 : i32, one = 1 : i32, type = 0 : i32} -// CHECK: %[[INDEX_8:.*]] = dxsa.index.imm {imm = 1 : i32} -// CHECK: %[[OPERAND_8:.*]] = dxsa.operand %[[INDEX_8]] {num_components = 4 : i32, swizzle = dense<[0, 1, 2, 0]> : vector<4xi32>, type = 30 : i32} -// CHECK: dxsa.instruction "ld_raw" %[[OPERAND_6]], %[[OPERAND_7]], %[[OPERAND_8]] +// CHECK: dxsa.ld_raw r<2, >, r<1, >, u<1, vector, > +// CHECK: dxsa.ld_raw r<3, >, r<1, >, u<1, vector, > // CHECK: dxsa.utof r<3, >, r<3, > -// CHECK: %[[INDEX_9:.*]] = dxsa.index.imm {imm = 4 : i32} -// CHECK: %[[OPERAND_9:.*]] = dxsa.operand %[[INDEX_9]] {mask = 240 : i32, num_components = 4 : i32, type = 0 : i32} -// CHECK: %[[INDEX_10:.*]] = dxsa.index.imm {imm = 1 : i32} -// CHECK: %[[OPERAND_10:.*]] = dxsa.operand %[[INDEX_10]] {num_components = 4 : i32, one = 2 : i32, type = 0 : i32} -// CHECK: %[[INDEX_11:.*]] = dxsa.index.imm {imm = 1 : i32} -// CHECK: %[[OPERAND_11:.*]] = dxsa.operand %[[INDEX_11]] {num_components = 4 : i32, swizzle = dense<[0, 1, 2, 3]> : vector<4xi32>, type = 30 : i32} -// CHECK: dxsa.instruction "ld_raw" %[[OPERAND_9]], %[[OPERAND_10]], %[[OPERAND_11]] +// CHECK: dxsa.ld_raw r<4>, r<1, >, u<1, vector> // CHECK: dxsa.utof r<4>, r<4> -// CHECK: %[[INDEX_12:.*]] = dxsa.index.imm {imm = 5 : i32} -// CHECK: %[[OPERAND_12:.*]] = dxsa.operand %[[INDEX_12]] {mask = 16 : i32, num_components = 4 : i32, type = 0 : i32} -// CHECK: %[[INDEX_13:.*]] = dxsa.index.imm {imm = 6 : i32} -// CHECK: %[[OPERAND_13:.*]] = dxsa.operand %[[INDEX_13]] {mask = 16 : i32, num_components = 4 : i32, type = 0 : i32} -// CHECK: %[[INDEX_14:.*]] = dxsa.index.imm {imm = 0 : i32} -// CHECK: %[[OPERAND_14:.*]] = dxsa.operand %[[INDEX_14]] {num_components = 4 : i32, one = 0 : i32, type = 0 : i32} -// CHECK: %[[INDEX_15:.*]] = dxsa.index.imm {imm = 1 : i32} -// CHECK: %[[OPERAND_15:.*]] = dxsa.operand %[[INDEX_15]] {num_components = 4 : i32, swizzle = dense<0> : vector<4xi32>, type = 30 : i32} -// CHECK: dxsa.instruction "ld_raw_s" %[[OPERAND_12]], %[[OPERAND_13]], %[[OPERAND_14]], %[[OPERAND_15]] -// CHECK: %[[INDEX_16:.*]] = dxsa.index.imm {imm = 7 : i32} -// CHECK: %[[OPERAND_16:.*]] = dxsa.operand %[[INDEX_16]] {mask = 16 : i32, num_components = 4 : i32, type = 0 : i32} -// CHECK: %[[INDEX_17:.*]] = dxsa.index.imm {imm = 8 : i32} -// CHECK: %[[OPERAND_17:.*]] = dxsa.operand %[[INDEX_17]] {mask = 16 : i32, num_components = 4 : i32, type = 0 : i32} -// CHECK: %[[INDEX_18:.*]] = dxsa.index.imm {imm = 1 : i32} -// CHECK: %[[OPERAND_18:.*]] = dxsa.operand %[[INDEX_18]] {num_components = 4 : i32, one = 0 : i32, type = 0 : i32} -// CHECK: %[[INDEX_19:.*]] = dxsa.index.imm {imm = 1 : i32} -// CHECK: %[[OPERAND_19:.*]] = dxsa.operand %[[INDEX_19]] {num_components = 4 : i32, swizzle = dense<0> : vector<4xi32>, type = 30 : i32} -// CHECK: dxsa.instruction "ld_raw_s" %[[OPERAND_16]], %[[OPERAND_17]], %[[OPERAND_18]], %[[OPERAND_19]] -// CHECK: %[[INDEX_20:.*]] = dxsa.index.imm {imm = 9 : i32} -// CHECK: %[[OPERAND_20:.*]] = dxsa.operand %[[INDEX_20]] {mask = 16 : i32, num_components = 4 : i32, type = 0 : i32} -// CHECK: %[[INDEX_21:.*]] = dxsa.index.imm {imm = 10 : i32} -// CHECK: %[[OPERAND_21:.*]] = dxsa.operand %[[INDEX_21]] {mask = 16 : i32, num_components = 4 : i32, type = 0 : i32} -// CHECK: %[[INDEX_22:.*]] = dxsa.index.imm {imm = 1 : i32} -// CHECK: %[[OPERAND_22:.*]] = dxsa.operand %[[INDEX_22]] {num_components = 4 : i32, one = 1 : i32, type = 0 : i32} -// CHECK: %[[INDEX_23:.*]] = dxsa.index.imm {imm = 1 : i32} -// CHECK: %[[OPERAND_23:.*]] = dxsa.operand %[[INDEX_23]] {num_components = 4 : i32, swizzle = dense<0> : vector<4xi32>, type = 30 : i32} -// CHECK: dxsa.instruction "ld_raw_s" %[[OPERAND_20]], %[[OPERAND_21]], %[[OPERAND_22]], %[[OPERAND_23]] -// CHECK: %[[INDEX_24:.*]] = dxsa.index.imm {imm = 11 : i32} -// CHECK: %[[OPERAND_24:.*]] = dxsa.operand %[[INDEX_24]] {mask = 16 : i32, num_components = 4 : i32, type = 0 : i32} -// CHECK: %[[INDEX_25:.*]] = dxsa.index.imm {imm = 12 : i32} -// CHECK: %[[OPERAND_25:.*]] = dxsa.operand %[[INDEX_25]] {mask = 16 : i32, num_components = 4 : i32, type = 0 : i32} -// CHECK: %[[INDEX_26:.*]] = dxsa.index.imm {imm = 1 : i32} -// CHECK: %[[OPERAND_26:.*]] = dxsa.operand %[[INDEX_26]] {num_components = 4 : i32, one = 2 : i32, type = 0 : i32} -// CHECK: %[[INDEX_27:.*]] = dxsa.index.imm {imm = 1 : i32} -// CHECK: %[[OPERAND_27:.*]] = dxsa.operand %[[INDEX_27]] {num_components = 4 : i32, swizzle = dense<0> : vector<4xi32>, type = 30 : i32} -// CHECK: dxsa.instruction "ld_raw_s" %[[OPERAND_24]], %[[OPERAND_25]], %[[OPERAND_26]], %[[OPERAND_27]] -// CHECK: %[[INDEX_28:.*]] = dxsa.index.imm {imm = 0 : i32} -// CHECK: %[[OPERAND_28:.*]] = dxsa.operand %[[INDEX_28]] {mask = 128 : i32, num_components = 4 : i32, type = 0 : i32} -// CHECK: %[[INDEX_29:.*]] = dxsa.index.imm {imm = 0 : i32} -// CHECK: %[[OPERAND_29:.*]] = dxsa.operand %[[INDEX_29]] {num_components = 4 : i32, one = 0 : i32, type = 0 : i32} -// CHECK: %[[INDEX_30:.*]] = dxsa.index.imm {imm = 0 : i32} -// CHECK: %[[OPERAND_30:.*]] = dxsa.operand %[[INDEX_30]] {num_components = 4 : i32, swizzle = dense<0> : vector<4xi32>, type = 7 : i32} -// CHECK: dxsa.instruction "ld_raw" %[[OPERAND_28]], %[[OPERAND_29]], %[[OPERAND_30]] +// CHECK: dxsa.ld_raw_s r<5, >, r<0, >, u<1, vector, >, r<6, > +// CHECK: dxsa.ld_raw_s r<7, >, r<1, >, u<1, vector, >, r<8, > +// CHECK: dxsa.ld_raw_s r<9, >, r<1, >, u<1, vector, >, r<10, > +// CHECK: dxsa.ld_raw_s r<11, >, r<1, >, u<1, vector, >, r<12, > +// CHECK: dxsa.ld_raw r<0, >, r<0, >, t<0, vector, > // CHECK: dxsa.utof r<13, min16f, >, r<0, > -// CHECK: %[[INDEX_31:.*]] = dxsa.index.imm {imm = 2 : i32} -// CHECK: %[[OPERAND_31:.*]] = dxsa.operand %[[INDEX_31]] {mask = 192 : i32, num_components = 4 : i32, type = 0 : i32} -// CHECK: %[[INDEX_32:.*]] = dxsa.index.imm {imm = 1 : i32} -// CHECK: %[[OPERAND_32:.*]] = dxsa.operand %[[INDEX_32]] {num_components = 4 : i32, one = 0 : i32, type = 0 : i32} -// CHECK: %[[INDEX_33:.*]] = dxsa.index.imm {imm = 0 : i32} -// CHECK: %[[OPERAND_33:.*]] = dxsa.operand %[[INDEX_33]] {num_components = 4 : i32, swizzle = dense<[0, 0, 0, 1]> : vector<4xi32>, type = 7 : i32} -// CHECK: dxsa.instruction "ld_raw" %[[OPERAND_31]], %[[OPERAND_32]], %[[OPERAND_33]] +// CHECK: dxsa.ld_raw r<2, >, r<1, >, t<0, vector, > // CHECK: dxsa.utof r<2>, r<2> // CHECK: dxsa.add r<2, >, r<2, >, r<13, min16f, > -// CHECK: %[[INDEX_34:.*]] = dxsa.index.imm {imm = 5 : i32} -// CHECK: %[[OPERAND_34:.*]] = dxsa.operand %[[INDEX_34]] {mask = 224 : i32, num_components = 4 : i32, type = 0 : i32} -// CHECK: %[[INDEX_35:.*]] = dxsa.index.imm {imm = 1 : i32} -// CHECK: %[[OPERAND_35:.*]] = dxsa.operand %[[INDEX_35]] {num_components = 4 : i32, one = 1 : i32, type = 0 : i32} -// CHECK: %[[INDEX_36:.*]] = dxsa.index.imm {imm = 0 : i32} -// CHECK: %[[OPERAND_36:.*]] = dxsa.operand %[[INDEX_36]] {num_components = 4 : i32, swizzle = dense<[0, 0, 1, 2]> : vector<4xi32>, type = 7 : i32} -// CHECK: dxsa.instruction "ld_raw" %[[OPERAND_34]], %[[OPERAND_35]], %[[OPERAND_36]] +// CHECK: dxsa.ld_raw r<5, >, r<1, >, t<0, vector, > // CHECK: dxsa.utof r<5, >, r<5, > // CHECK: dxsa.add r<14, >, r<2, >, r<5, > // CHECK: dxsa.add r<14, >, r<5, >, r<13, min16f, > -// CHECK: %[[INDEX_37:.*]] = dxsa.index.imm {imm = 15 : i32} -// CHECK: %[[OPERAND_37:.*]] = dxsa.operand %[[INDEX_37]] {mask = 240 : i32, num_components = 4 : i32, type = 0 : i32} -// CHECK: %[[INDEX_38:.*]] = dxsa.index.imm {imm = 1 : i32} -// CHECK: %[[OPERAND_38:.*]] = dxsa.operand %[[INDEX_38]] {num_components = 4 : i32, one = 2 : i32, type = 0 : i32} -// CHECK: %[[INDEX_39:.*]] = dxsa.index.imm {imm = 0 : i32} -// CHECK: %[[OPERAND_39:.*]] = dxsa.operand %[[INDEX_39]] {num_components = 4 : i32, swizzle = dense<[0, 1, 2, 3]> : vector<4xi32>, type = 7 : i32} -// CHECK: dxsa.instruction "ld_raw" %[[OPERAND_37]], %[[OPERAND_38]], %[[OPERAND_39]] +// CHECK: dxsa.ld_raw r<15>, r<1, >, t<0, vector> // CHECK: dxsa.utof r<15>, r<15> // CHECK: dxsa.add r<14, >, r<14, >, r<15, > // CHECK: dxsa.add r<14, >, r<13, min16f, >, r<15, > -// CHECK: %[[INDEX_40:.*]] = dxsa.index.imm {imm = 0 : i32} -// CHECK: %[[OPERAND_40:.*]] = dxsa.operand %[[INDEX_40]] {mask = 16 : i32, num_components = 4 : i32, type = 0 : i32} -// CHECK: %[[INDEX_41:.*]] = dxsa.index.imm {imm = 15 : i32} -// CHECK: %[[OPERAND_41:.*]] = dxsa.operand %[[INDEX_41]] {mask = 16 : i32, num_components = 4 : i32, type = 0 : i32} -// CHECK: %[[INDEX_42:.*]] = dxsa.index.imm {imm = 0 : i32} -// CHECK: %[[OPERAND_42:.*]] = dxsa.operand %[[INDEX_42]] {num_components = 4 : i32, one = 0 : i32, type = 0 : i32} -// CHECK: %[[INDEX_43:.*]] = dxsa.index.imm {imm = 0 : i32} -// CHECK: %[[OPERAND_43:.*]] = dxsa.operand %[[INDEX_43]] {num_components = 4 : i32, swizzle = dense<0> : vector<4xi32>, type = 7 : i32} -// CHECK: dxsa.instruction "ld_raw_s" %[[OPERAND_40]], %[[OPERAND_41]], %[[OPERAND_42]], %[[OPERAND_43]] -// CHECK: %[[INDEX_44:.*]] = dxsa.index.imm {imm = 0 : i32} -// CHECK: %[[OPERAND_44:.*]] = dxsa.operand %[[INDEX_44]] {mask = 128 : i32, num_components = 4 : i32, type = 0 : i32} -// CHECK: %[[INDEX_45:.*]] = dxsa.index.imm {imm = 15 : i32} -// CHECK: %[[OPERAND_45:.*]] = dxsa.operand %[[INDEX_45]] {num_components = 4 : i32, one = 0 : i32, type = 0 : i32} -// CHECK: dxsa.instruction "check_access_fully_mapped" %[[OPERAND_44]], %[[OPERAND_45]] +// CHECK: dxsa.ld_raw_s r<0, >, r<0, >, t<0, vector, >, r<15, > +// CHECK: %[[INDEX_0:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_0:.*]] = dxsa.operand %[[INDEX_0]] {mask = 128 : i32, num_components = 4 : i32, type = 0 : i32} +// CHECK: %[[INDEX_1:.*]] = dxsa.index.imm {imm = 15 : i32} +// CHECK: %[[OPERAND_1:.*]] = dxsa.operand %[[INDEX_1]] {num_components = 4 : i32, one = 0 : i32, type = 0 : i32} +// CHECK: dxsa.instruction "check_access_fully_mapped" %[[OPERAND_0]], %[[OPERAND_1]] // CHECK: dxsa.utof r<0, >, r<0, > // CHECK: dxsa.add r<13>, r<0, >, r<14> // CHECK: dxsa.add r<13>, r<0, >, r<13> -// CHECK: %[[INDEX_46:.*]] = dxsa.index.imm {imm = 0 : i32} -// CHECK: %[[OPERAND_46:.*]] = dxsa.operand %[[INDEX_46]] {mask = 16 : i32, num_components = 4 : i32, type = 0 : i32} -// CHECK: %[[INDEX_47:.*]] = dxsa.index.imm {imm = 1 : i32} -// CHECK: %[[OPERAND_47:.*]] = dxsa.operand %[[INDEX_47]] {mask = 16 : i32, num_components = 4 : i32, type = 0 : i32} -// CHECK: %[[INDEX_48:.*]] = dxsa.index.imm {imm = 1 : i32} -// CHECK: %[[OPERAND_48:.*]] = dxsa.operand %[[INDEX_48]] {num_components = 4 : i32, one = 0 : i32, type = 0 : i32} -// CHECK: %[[INDEX_49:.*]] = dxsa.index.imm {imm = 0 : i32} -// CHECK: %[[OPERAND_49:.*]] = dxsa.operand %[[INDEX_49]] {num_components = 4 : i32, swizzle = dense<0> : vector<4xi32>, type = 7 : i32} -// CHECK: dxsa.instruction "ld_raw_s" %[[OPERAND_46]], %[[OPERAND_47]], %[[OPERAND_48]], %[[OPERAND_49]] -// CHECK: %[[INDEX_50:.*]] = dxsa.index.imm {imm = 0 : i32} -// CHECK: %[[OPERAND_50:.*]] = dxsa.operand %[[INDEX_50]] {mask = 128 : i32, num_components = 4 : i32, type = 0 : i32} -// CHECK: %[[INDEX_51:.*]] = dxsa.index.imm {imm = 1 : i32} -// CHECK: %[[OPERAND_51:.*]] = dxsa.operand %[[INDEX_51]] {num_components = 4 : i32, one = 0 : i32, type = 0 : i32} -// CHECK: dxsa.instruction "check_access_fully_mapped" %[[OPERAND_50]], %[[OPERAND_51]] +// CHECK: dxsa.ld_raw_s r<0, >, r<1, >, t<0, vector, >, r<1, > +// CHECK: %[[INDEX_2:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_2:.*]] = dxsa.operand %[[INDEX_2]] {mask = 128 : i32, num_components = 4 : i32, type = 0 : i32} +// CHECK: %[[INDEX_3:.*]] = dxsa.index.imm {imm = 1 : i32} +// CHECK: %[[OPERAND_3:.*]] = dxsa.operand %[[INDEX_3]] {num_components = 4 : i32, one = 0 : i32, type = 0 : i32} +// CHECK: dxsa.instruction "check_access_fully_mapped" %[[OPERAND_2]], %[[OPERAND_3]] // CHECK: dxsa.utof r<0, >, r<0, > // CHECK: dxsa.add r<13, >, r<0, >, r<13, > // CHECK: dxsa.add r<13>, r<0, >, r<13> -// CHECK: %[[INDEX_52:.*]] = dxsa.index.imm {imm = 0 : i32} -// CHECK: %[[OPERAND_52:.*]] = dxsa.operand %[[INDEX_52]] {mask = 16 : i32, num_components = 4 : i32, type = 0 : i32} -// CHECK: %[[INDEX_53:.*]] = dxsa.index.imm {imm = 1 : i32} -// CHECK: %[[OPERAND_53:.*]] = dxsa.operand %[[INDEX_53]] {mask = 16 : i32, num_components = 4 : i32, type = 0 : i32} -// CHECK: %[[INDEX_54:.*]] = dxsa.index.imm {imm = 1 : i32} -// CHECK: %[[OPERAND_54:.*]] = dxsa.operand %[[INDEX_54]] {num_components = 4 : i32, one = 1 : i32, type = 0 : i32} -// CHECK: %[[INDEX_55:.*]] = dxsa.index.imm {imm = 0 : i32} -// CHECK: %[[OPERAND_55:.*]] = dxsa.operand %[[INDEX_55]] {num_components = 4 : i32, swizzle = dense<0> : vector<4xi32>, type = 7 : i32} -// CHECK: dxsa.instruction "ld_raw_s" %[[OPERAND_52]], %[[OPERAND_53]], %[[OPERAND_54]], %[[OPERAND_55]] -// CHECK: %[[INDEX_56:.*]] = dxsa.index.imm {imm = 14 : i32} -// CHECK: %[[OPERAND_56:.*]] = dxsa.operand %[[INDEX_56]] {mask = 16 : i32, num_components = 4 : i32, type = 0 : i32} -// CHECK: %[[INDEX_57:.*]] = dxsa.index.imm {imm = 15 : i32} -// CHECK: %[[OPERAND_57:.*]] = dxsa.operand %[[INDEX_57]] {mask = 16 : i32, num_components = 4 : i32, type = 0 : i32} -// CHECK: %[[INDEX_58:.*]] = dxsa.index.imm {imm = 1 : i32} -// CHECK: %[[OPERAND_58:.*]] = dxsa.operand %[[INDEX_58]] {num_components = 4 : i32, one = 2 : i32, type = 0 : i32} -// CHECK: %[[INDEX_59:.*]] = dxsa.index.imm {imm = 0 : i32} -// CHECK: %[[OPERAND_59:.*]] = dxsa.operand %[[INDEX_59]] {num_components = 4 : i32, swizzle = dense<0> : vector<4xi32>, type = 7 : i32} -// CHECK: dxsa.instruction "ld_raw_s" %[[OPERAND_56]], %[[OPERAND_57]], %[[OPERAND_58]], %[[OPERAND_59]] -// CHECK: %[[INDEX_60:.*]] = dxsa.index.imm {imm = 0 : i32} -// CHECK: %[[OPERAND_60:.*]] = dxsa.operand %[[INDEX_60]] {mask = 128 : i32, num_components = 4 : i32, type = 0 : i32} -// CHECK: %[[INDEX_61:.*]] = dxsa.index.imm {imm = 1 : i32} -// CHECK: %[[OPERAND_61:.*]] = dxsa.operand %[[INDEX_61]] {num_components = 4 : i32, one = 0 : i32, type = 0 : i32} -// CHECK: dxsa.instruction "check_access_fully_mapped" %[[OPERAND_60]], %[[OPERAND_61]] +// CHECK: dxsa.ld_raw_s r<0, >, r<1, >, t<0, vector, >, r<1, > +// CHECK: dxsa.ld_raw_s r<14, >, r<1, >, t<0, vector, >, r<15, > +// CHECK: %[[INDEX_4:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_4:.*]] = dxsa.operand %[[INDEX_4]] {mask = 128 : i32, num_components = 4 : i32, type = 0 : i32} +// CHECK: %[[INDEX_5:.*]] = dxsa.index.imm {imm = 1 : i32} +// CHECK: %[[OPERAND_5:.*]] = dxsa.operand %[[INDEX_5]] {num_components = 4 : i32, one = 0 : i32, type = 0 : i32} +// CHECK: dxsa.instruction "check_access_fully_mapped" %[[OPERAND_4]], %[[OPERAND_5]] // CHECK: dxsa.utof r<0, >, r<0, > // CHECK: dxsa.add r<13, >, r<0, >, r<13, > // CHECK: dxsa.add r<1>, r<0, >, r<13> // CHECK: dxsa.utof r<0, >, r<14, > -// CHECK: %[[INDEX_62:.*]] = dxsa.index.imm {imm = 0 : i32} -// CHECK: %[[OPERAND_62:.*]] = dxsa.operand %[[INDEX_62]] {mask = 128 : i32, num_components = 4 : i32, type = 0 : i32} -// CHECK: %[[INDEX_63:.*]] = dxsa.index.imm {imm = 15 : i32} -// CHECK: %[[OPERAND_63:.*]] = dxsa.operand %[[INDEX_63]] {num_components = 4 : i32, one = 0 : i32, type = 0 : i32} -// CHECK: dxsa.instruction "check_access_fully_mapped" %[[OPERAND_62]], %[[OPERAND_63]] +// CHECK: %[[INDEX_6:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_6:.*]] = dxsa.operand %[[INDEX_6]] {mask = 128 : i32, num_components = 4 : i32, type = 0 : i32} +// CHECK: %[[INDEX_7:.*]] = dxsa.index.imm {imm = 15 : i32} +// CHECK: %[[OPERAND_7:.*]] = dxsa.operand %[[INDEX_7]] {num_components = 4 : i32, one = 0 : i32, type = 0 : i32} +// CHECK: dxsa.instruction "check_access_fully_mapped" %[[OPERAND_6]], %[[OPERAND_7]] // CHECK: dxsa.utof r<0, >, r<0, > // CHECK: dxsa.add r<1>, r<0, >, r<1> // CHECK: dxsa.add r<1>, r<0, >, r<1> @@ -189,74 +77,74 @@ // CHECK: dxsa.add r<1, >, r<3, >, r<1, > // CHECK: dxsa.add r<1>, r<4>, r<1> // CHECK: dxsa.utof r<0, >, r<5, > -// CHECK: %[[INDEX_64:.*]] = dxsa.index.imm {imm = 0 : i32} -// CHECK: %[[OPERAND_64:.*]] = dxsa.operand %[[INDEX_64]] {mask = 64 : i32, num_components = 4 : i32, type = 0 : i32} -// CHECK: %[[INDEX_65:.*]] = dxsa.index.imm {imm = 6 : i32} -// CHECK: %[[OPERAND_65:.*]] = dxsa.operand %[[INDEX_65]] {num_components = 4 : i32, one = 0 : i32, type = 0 : i32} -// CHECK: dxsa.instruction "check_access_fully_mapped" %[[OPERAND_64]], %[[OPERAND_65]] +// CHECK: %[[INDEX_8:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_8:.*]] = dxsa.operand %[[INDEX_8]] {mask = 64 : i32, num_components = 4 : i32, type = 0 : i32} +// CHECK: %[[INDEX_9:.*]] = dxsa.index.imm {imm = 6 : i32} +// CHECK: %[[OPERAND_9:.*]] = dxsa.operand %[[INDEX_9]] {num_components = 4 : i32, one = 0 : i32, type = 0 : i32} +// CHECK: dxsa.instruction "check_access_fully_mapped" %[[OPERAND_8]], %[[OPERAND_9]] // CHECK: dxsa.utof r<0, >, r<0, > // CHECK: dxsa.add r<1>, r<0, >, r<1> // CHECK: dxsa.add r<1>, r<0, >, r<1> // CHECK: dxsa.utof r<0, >, r<7, > -// CHECK: %[[INDEX_66:.*]] = dxsa.index.imm {imm = 0 : i32} -// CHECK: %[[OPERAND_66:.*]] = dxsa.operand %[[INDEX_66]] {mask = 64 : i32, num_components = 4 : i32, type = 0 : i32} -// CHECK: %[[INDEX_67:.*]] = dxsa.index.imm {imm = 8 : i32} -// CHECK: %[[OPERAND_67:.*]] = dxsa.operand %[[INDEX_67]] {num_components = 4 : i32, one = 0 : i32, type = 0 : i32} -// CHECK: dxsa.instruction "check_access_fully_mapped" %[[OPERAND_66]], %[[OPERAND_67]] +// CHECK: %[[INDEX_10:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_10:.*]] = dxsa.operand %[[INDEX_10]] {mask = 64 : i32, num_components = 4 : i32, type = 0 : i32} +// CHECK: %[[INDEX_11:.*]] = dxsa.index.imm {imm = 8 : i32} +// CHECK: %[[OPERAND_11:.*]] = dxsa.operand %[[INDEX_11]] {num_components = 4 : i32, one = 0 : i32, type = 0 : i32} +// CHECK: dxsa.instruction "check_access_fully_mapped" %[[OPERAND_10]], %[[OPERAND_11]] // CHECK: dxsa.utof r<0, >, r<0, > // CHECK: dxsa.add r<1, >, r<0, >, r<1, > // CHECK: dxsa.add r<1>, r<0, >, r<1> // CHECK: dxsa.utof r<0, >, r<9, > -// CHECK: %[[INDEX_68:.*]] = dxsa.index.imm {imm = 0 : i32} -// CHECK: %[[OPERAND_68:.*]] = dxsa.operand %[[INDEX_68]] {mask = 64 : i32, num_components = 4 : i32, type = 0 : i32} -// CHECK: %[[INDEX_69:.*]] = dxsa.index.imm {imm = 10 : i32} -// CHECK: %[[OPERAND_69:.*]] = dxsa.operand %[[INDEX_69]] {num_components = 4 : i32, one = 0 : i32, type = 0 : i32} -// CHECK: dxsa.instruction "check_access_fully_mapped" %[[OPERAND_68]], %[[OPERAND_69]] +// CHECK: %[[INDEX_12:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_12:.*]] = dxsa.operand %[[INDEX_12]] {mask = 64 : i32, num_components = 4 : i32, type = 0 : i32} +// CHECK: %[[INDEX_13:.*]] = dxsa.index.imm {imm = 10 : i32} +// CHECK: %[[OPERAND_13:.*]] = dxsa.operand %[[INDEX_13]] {num_components = 4 : i32, one = 0 : i32, type = 0 : i32} +// CHECK: dxsa.instruction "check_access_fully_mapped" %[[OPERAND_12]], %[[OPERAND_13]] // CHECK: dxsa.utof r<0, >, r<0, > // CHECK: dxsa.add r<1, >, r<0, >, r<1, > // CHECK: dxsa.add r<1>, r<0, >, r<1> // CHECK: dxsa.utof r<0, >, r<11, > -// CHECK: %[[INDEX_70:.*]] = dxsa.index.imm {imm = 0 : i32} -// CHECK: %[[OPERAND_70:.*]] = dxsa.operand %[[INDEX_70]] {mask = 64 : i32, num_components = 4 : i32, type = 0 : i32} -// CHECK: %[[INDEX_71:.*]] = dxsa.index.imm {imm = 12 : i32} -// CHECK: %[[OPERAND_71:.*]] = dxsa.operand %[[INDEX_71]] {num_components = 4 : i32, one = 0 : i32, type = 0 : i32} -// CHECK: dxsa.instruction "check_access_fully_mapped" %[[OPERAND_70]], %[[OPERAND_71]] +// CHECK: %[[INDEX_14:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_14:.*]] = dxsa.operand %[[INDEX_14]] {mask = 64 : i32, num_components = 4 : i32, type = 0 : i32} +// CHECK: %[[INDEX_15:.*]] = dxsa.index.imm {imm = 12 : i32} +// CHECK: %[[OPERAND_15:.*]] = dxsa.operand %[[INDEX_15]] {num_components = 4 : i32, one = 0 : i32, type = 0 : i32} +// CHECK: dxsa.instruction "check_access_fully_mapped" %[[OPERAND_14]], %[[OPERAND_15]] // CHECK: dxsa.utof r<0, >, r<0, > // CHECK: dxsa.add r<1>, r<0, >, r<1> // CHECK: dxsa.add r<1>, r<0, >, r<1> // CHECK: dxsa.ftou r<0, >, r<1, > -// CHECK: %[[INDEX_72:.*]] = dxsa.index.imm {imm = 1 : i32} -// CHECK: %[[OPERAND_72:.*]] = dxsa.operand %[[INDEX_72]] {mask = 16 : i32, num_components = 4 : i32, type = 30 : i32} -// CHECK: %[[INDEX_73:.*]] = dxsa.index.imm {imm = 0 : i32} -// CHECK: %[[OPERAND_73:.*]] = dxsa.operand %[[INDEX_73]] {num_components = 4 : i32, one = 1 : i32, type = 0 : i32} -// CHECK: %[[INDEX_74:.*]] = dxsa.index.imm {imm = 0 : i32} -// CHECK: %[[OPERAND_74:.*]] = dxsa.operand %[[INDEX_74]] {num_components = 4 : i32, one = 0 : i32, type = 0 : i32} -// CHECK: dxsa.instruction "store_raw" %[[OPERAND_72]], %[[OPERAND_73]], %[[OPERAND_74]] +// CHECK: %[[INDEX_16:.*]] = dxsa.index.imm {imm = 1 : i32} +// CHECK: %[[OPERAND_16:.*]] = dxsa.operand %[[INDEX_16]] {mask = 16 : i32, num_components = 4 : i32, type = 30 : i32} +// CHECK: %[[INDEX_17:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_17:.*]] = dxsa.operand %[[INDEX_17]] {num_components = 4 : i32, one = 1 : i32, type = 0 : i32} +// CHECK: %[[INDEX_18:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_18:.*]] = dxsa.operand %[[INDEX_18]] {num_components = 4 : i32, one = 0 : i32, type = 0 : i32} +// CHECK: dxsa.instruction "store_raw" %[[OPERAND_16]], %[[OPERAND_17]], %[[OPERAND_18]] // CHECK: dxsa.add r<2, >, v<0, >, l(0x3F800000, 0x40000000, 0x40400000, 0x0) // CHECK: dxsa.ftou r<2, >, r<2, > -// CHECK: %[[INDEX_75:.*]] = dxsa.index.imm {imm = 1 : i32} -// CHECK: %[[OPERAND_75:.*]] = dxsa.operand %[[INDEX_75]] {mask = 48 : i32, num_components = 4 : i32, type = 30 : i32} -// CHECK: %[[INDEX_76:.*]] = dxsa.index.imm {imm = 2 : i32} -// CHECK: %[[OPERAND_76:.*]] = dxsa.operand %[[INDEX_76]] {num_components = 4 : i32, one = 0 : i32, type = 0 : i32} -// CHECK: %[[INDEX_77:.*]] = dxsa.index.imm {imm = 0 : i32} -// CHECK: %[[OPERAND_77:.*]] = dxsa.operand %[[INDEX_77]] {num_components = 4 : i32, swizzle = dense<[2, 3, 2, 2]> : vector<4xi32>, type = 0 : i32} -// CHECK: dxsa.instruction "store_raw" %[[OPERAND_75]], %[[OPERAND_76]], %[[OPERAND_77]] +// CHECK: %[[INDEX_19:.*]] = dxsa.index.imm {imm = 1 : i32} +// CHECK: %[[OPERAND_19:.*]] = dxsa.operand %[[INDEX_19]] {mask = 48 : i32, num_components = 4 : i32, type = 30 : i32} +// CHECK: %[[INDEX_20:.*]] = dxsa.index.imm {imm = 2 : i32} +// CHECK: %[[OPERAND_20:.*]] = dxsa.operand %[[INDEX_20]] {num_components = 4 : i32, one = 0 : i32, type = 0 : i32} +// CHECK: %[[INDEX_21:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_21:.*]] = dxsa.operand %[[INDEX_21]] {num_components = 4 : i32, swizzle = dense<[2, 3, 2, 2]> : vector<4xi32>, type = 0 : i32} +// CHECK: dxsa.instruction "store_raw" %[[OPERAND_19]], %[[OPERAND_20]], %[[OPERAND_21]] // CHECK: dxsa.ftou r<0, >, r<1, > -// CHECK: %[[INDEX_78:.*]] = dxsa.index.imm {imm = 1 : i32} -// CHECK: %[[OPERAND_78:.*]] = dxsa.operand %[[INDEX_78]] {mask = 112 : i32, num_components = 4 : i32, type = 30 : i32} -// CHECK: %[[INDEX_79:.*]] = dxsa.index.imm {imm = 2 : i32} -// CHECK: %[[OPERAND_79:.*]] = dxsa.operand %[[INDEX_79]] {num_components = 4 : i32, one = 1 : i32, type = 0 : i32} -// CHECK: %[[INDEX_80:.*]] = dxsa.index.imm {imm = 0 : i32} -// CHECK: %[[OPERAND_80:.*]] = dxsa.operand %[[INDEX_80]] {num_components = 4 : i32, swizzle = dense<[0, 1, 2, 0]> : vector<4xi32>, type = 0 : i32} -// CHECK: dxsa.instruction "store_raw" %[[OPERAND_78]], %[[OPERAND_79]], %[[OPERAND_80]] +// CHECK: %[[INDEX_22:.*]] = dxsa.index.imm {imm = 1 : i32} +// CHECK: %[[OPERAND_22:.*]] = dxsa.operand %[[INDEX_22]] {mask = 112 : i32, num_components = 4 : i32, type = 30 : i32} +// CHECK: %[[INDEX_23:.*]] = dxsa.index.imm {imm = 2 : i32} +// CHECK: %[[OPERAND_23:.*]] = dxsa.operand %[[INDEX_23]] {num_components = 4 : i32, one = 1 : i32, type = 0 : i32} +// CHECK: %[[INDEX_24:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_24:.*]] = dxsa.operand %[[INDEX_24]] {num_components = 4 : i32, swizzle = dense<[0, 1, 2, 0]> : vector<4xi32>, type = 0 : i32} +// CHECK: dxsa.instruction "store_raw" %[[OPERAND_22]], %[[OPERAND_23]], %[[OPERAND_24]] // CHECK: dxsa.ftou r<0>, r<1, > // CHECK: dxsa.mov o<0>, r<1> -// CHECK: %[[INDEX_81:.*]] = dxsa.index.imm {imm = 1 : i32} -// CHECK: %[[OPERAND_81:.*]] = dxsa.operand %[[INDEX_81]] {mask = 240 : i32, num_components = 4 : i32, type = 30 : i32} -// CHECK: %[[INDEX_82:.*]] = dxsa.index.imm {imm = 2 : i32} -// CHECK: %[[OPERAND_82:.*]] = dxsa.operand %[[INDEX_82]] {num_components = 4 : i32, one = 2 : i32, type = 0 : i32} -// CHECK: %[[INDEX_83:.*]] = dxsa.index.imm {imm = 0 : i32} -// CHECK: %[[OPERAND_83:.*]] = dxsa.operand %[[INDEX_83]] {num_components = 4 : i32, swizzle = dense<[0, 1, 2, 3]> : vector<4xi32>, type = 0 : i32} -// CHECK: dxsa.instruction "store_raw" %[[OPERAND_81]], %[[OPERAND_82]], %[[OPERAND_83]] +// CHECK: %[[INDEX_25:.*]] = dxsa.index.imm {imm = 1 : i32} +// CHECK: %[[OPERAND_25:.*]] = dxsa.operand %[[INDEX_25]] {mask = 240 : i32, num_components = 4 : i32, type = 30 : i32} +// CHECK: %[[INDEX_26:.*]] = dxsa.index.imm {imm = 2 : i32} +// CHECK: %[[OPERAND_26:.*]] = dxsa.operand %[[INDEX_26]] {num_components = 4 : i32, one = 2 : i32, type = 0 : i32} +// CHECK: %[[INDEX_27:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_27:.*]] = dxsa.operand %[[INDEX_27]] {num_components = 4 : i32, swizzle = dense<[0, 1, 2, 3]> : vector<4xi32>, type = 0 : i32} +// CHECK: dxsa.instruction "store_raw" %[[OPERAND_25]], %[[OPERAND_26]], %[[OPERAND_27]] // CHECK: dxsa.ret diff --git a/mlir/test/Target/DXSA/hlsl/srv_ms_load1.test b/mlir/test/Target/DXSA/hlsl/srv_ms_load1.test index e89c4cdb9042..a7c4e4c22960 100644 --- a/mlir/test/Target/DXSA/hlsl/srv_ms_load1.test +++ b/mlir/test/Target/DXSA/hlsl/srv_ms_load1.test @@ -11,80 +11,30 @@ // CHECK: dxsa.dcl_temps 4 // CHECK: dxsa.mov r<0, >, v<1, > // CHECK: dxsa.mov r<0, >, l(0x0, 0x0, 0x0, 0x0) -// CHECK: %[[INDEX_0:.*]] = dxsa.index.imm {imm = 0 : i32} -// CHECK: %[[OPERAND_0:.*]] = dxsa.operand %[[INDEX_0]] {mask = 112 : i32, num_components = 4 : i32, type = 0 : i32} -// CHECK: %[[INDEX_1:.*]] = dxsa.index.imm {imm = 0 : i32} -// CHECK: %[[OPERAND_1:.*]] = dxsa.operand %[[INDEX_1]] {num_components = 4 : i32, swizzle = dense<[0, 1, 2, 3]> : vector<4xi32>, type = 0 : i32} -// CHECK: %[[INDEX_2:.*]] = dxsa.index.imm {imm = 3 : i32} -// CHECK: %[[OPERAND_2:.*]] = dxsa.operand %[[INDEX_2]] {num_components = 4 : i32, swizzle = dense<[0, 1, 2, 3]> : vector<4xi32>, type = 7 : i32} -// CHECK: %[[OPERAND_3:.*]] = dxsa.operand.imm {imm = dense<0> : vector<1xi32>} -// CHECK: dxsa.instruction "ldms" %[[OPERAND_0]], %[[OPERAND_1]], %[[OPERAND_2]], %[[OPERAND_3]] +// CHECK: dxsa.ld2dms r<0, >, r<0>, t<3, vector>, l(0x0) // CHECK: dxsa.mov r<1, >, v<0, > // CHECK: dxsa.mov r<1, >, l(0x0, 0x0, 0x0, 0x0) -// CHECK: %[[INDEX_3:.*]] = dxsa.index.imm {imm = 2 : i32} -// CHECK: %[[OPERAND_4:.*]] = dxsa.operand %[[INDEX_3]] {mask = 112 : i32, num_components = 4 : i32, type = 0 : i32} -// CHECK: %[[INDEX_4:.*]] = dxsa.index.imm {imm = 1 : i32} -// CHECK: %[[OPERAND_5:.*]] = dxsa.operand %[[INDEX_4]] {num_components = 4 : i32, swizzle = dense<[0, 1, 3, 3]> : vector<4xi32>, type = 0 : i32} -// CHECK: %[[INDEX_5:.*]] = dxsa.index.imm {imm = 3 : i32} -// CHECK: %[[OPERAND_6:.*]] = dxsa.operand %[[INDEX_5]] {num_components = 4 : i32, swizzle = dense<[0, 1, 2, 3]> : vector<4xi32>, type = 7 : i32} -// CHECK: %[[INDEX_6:.*]] = dxsa.index.imm {imm = 0 : i32} -// CHECK: %[[OPERAND_7:.*]] = dxsa.operand %[[INDEX_6]] {num_components = 4 : i32, one = 2 : i32, type = 1 : i32} -// CHECK: dxsa.instruction "ldms" %[[OPERAND_4]], %[[OPERAND_5]], %[[OPERAND_6]], %[[OPERAND_7]] +// CHECK: dxsa.ld2dms r<2, >, r<1, >, t<3, vector>, v<0, > // CHECK: dxsa.add r<0, >, r<0, >, r<2, > -// CHECK: %[[INDEX_7:.*]] = dxsa.index.imm {imm = 2 : i32} -// CHECK: %[[OPERAND_8:.*]] = dxsa.operand %[[INDEX_7]] {mask = 112 : i32, num_components = 4 : i32, type = 0 : i32} -// CHECK: %[[INDEX_8:.*]] = dxsa.index.imm {imm = 1 : i32} -// CHECK: %[[OPERAND_9:.*]] = dxsa.operand %[[INDEX_8]] {num_components = 4 : i32, swizzle = dense<[0, 1, 3, 3]> : vector<4xi32>, type = 0 : i32} -// CHECK: %[[INDEX_9:.*]] = dxsa.index.imm {imm = 3 : i32} -// CHECK: %[[OPERAND_10:.*]] = dxsa.operand %[[INDEX_9]] {num_components = 4 : i32, swizzle = dense<[0, 1, 2, 3]> : vector<4xi32>, type = 7 : i32} -// CHECK: %[[INDEX_10:.*]] = dxsa.index.imm {imm = 0 : i32} -// CHECK: %[[OPERAND_11:.*]] = dxsa.operand %[[INDEX_10]] {num_components = 4 : i32, one = 2 : i32, type = 1 : i32} -// CHECK: dxsa.instruction "ldms" %[[OPERAND_8]], %[[OPERAND_9]], %[[OPERAND_10]], %[[OPERAND_11]] +// CHECK: dxsa.ld2dms r<2, >, r<1, >, t<3, vector>, v<0, >, // CHECK: dxsa.add r<0, >, r<0, >, r<2, > -// CHECK: %[[INDEX_11:.*]] = dxsa.index.imm {imm = 2 : i32} -// CHECK: %[[OPERAND_12:.*]] = dxsa.operand %[[INDEX_11]] {mask = 112 : i32, num_components = 4 : i32, type = 0 : i32} -// CHECK: %[[INDEX_12:.*]] = dxsa.index.imm {imm = 3 : i32} -// CHECK: %[[OPERAND_13:.*]] = dxsa.operand %[[INDEX_12]] {mask = 16 : i32, num_components = 4 : i32, type = 0 : i32} -// CHECK: %[[INDEX_13:.*]] = dxsa.index.imm {imm = 1 : i32} -// CHECK: %[[OPERAND_14:.*]] = dxsa.operand %[[INDEX_13]] {num_components = 4 : i32, swizzle = dense<[0, 1, 3, 3]> : vector<4xi32>, type = 0 : i32} -// CHECK: %[[INDEX_14:.*]] = dxsa.index.imm {imm = 3 : i32} -// CHECK: %[[OPERAND_15:.*]] = dxsa.operand %[[INDEX_14]] {num_components = 4 : i32, swizzle = dense<[0, 1, 2, 3]> : vector<4xi32>, type = 7 : i32} -// CHECK: %[[INDEX_15:.*]] = dxsa.index.imm {imm = 0 : i32} -// CHECK: %[[OPERAND_16:.*]] = dxsa.operand %[[INDEX_15]] {num_components = 4 : i32, one = 2 : i32, type = 1 : i32} -// CHECK: dxsa.instruction "ldms_s" %[[OPERAND_12]], %[[OPERAND_13]], %[[OPERAND_14]], %[[OPERAND_15]], %[[OPERAND_16]] +// CHECK: dxsa.ld2dms_s r<2, >, r<1, >, t<3, vector>, v<0, >, r<3, >, // CHECK: dxsa.add r<0, >, r<0, >, r<2, > -// CHECK: %[[INDEX_16:.*]] = dxsa.index.imm {imm = 0 : i32} -// CHECK: %[[OPERAND_17:.*]] = dxsa.operand %[[INDEX_16]] {mask = 128 : i32, num_components = 4 : i32, type = 0 : i32} -// CHECK: %[[INDEX_17:.*]] = dxsa.index.imm {imm = 3 : i32} -// CHECK: %[[OPERAND_18:.*]] = dxsa.operand %[[INDEX_17]] {num_components = 4 : i32, one = 0 : i32, type = 0 : i32} -// CHECK: dxsa.instruction "check_access_fully_mapped" %[[OPERAND_17]], %[[OPERAND_18]] +// CHECK: %[[INDEX_0:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_0:.*]] = dxsa.operand %[[INDEX_0]] {mask = 128 : i32, num_components = 4 : i32, type = 0 : i32} +// CHECK: %[[INDEX_1:.*]] = dxsa.index.imm {imm = 3 : i32} +// CHECK: %[[OPERAND_1:.*]] = dxsa.operand %[[INDEX_1]] {num_components = 4 : i32, one = 0 : i32, type = 0 : i32} +// CHECK: dxsa.instruction "check_access_fully_mapped" %[[OPERAND_0]], %[[OPERAND_1]] // CHECK: dxsa.utof r<0, >, r<0, > // CHECK: dxsa.add r<0, >, r<0, >, r<0, > -// CHECK: %[[INDEX_18:.*]] = dxsa.index.imm {imm = 2 : i32} -// CHECK: %[[OPERAND_19:.*]] = dxsa.operand %[[INDEX_18]] {mask = 112 : i32, num_components = 4 : i32, type = 0 : i32} -// CHECK: %[[INDEX_19:.*]] = dxsa.index.imm {imm = 3 : i32} -// CHECK: %[[OPERAND_20:.*]] = dxsa.operand %[[INDEX_19]] {mask = 16 : i32, num_components = 4 : i32, type = 0 : i32} -// CHECK: %[[INDEX_20:.*]] = dxsa.index.imm {imm = 1 : i32} -// CHECK: %[[OPERAND_21:.*]] = dxsa.operand %[[INDEX_20]] {num_components = 4 : i32, swizzle = dense<[0, 1, 3, 3]> : vector<4xi32>, type = 0 : i32} -// CHECK: %[[INDEX_21:.*]] = dxsa.index.imm {imm = 3 : i32} -// CHECK: %[[OPERAND_22:.*]] = dxsa.operand %[[INDEX_21]] {num_components = 4 : i32, swizzle = dense<[0, 1, 2, 3]> : vector<4xi32>, type = 7 : i32} -// CHECK: %[[INDEX_22:.*]] = dxsa.index.imm {imm = 0 : i32} -// CHECK: %[[OPERAND_23:.*]] = dxsa.operand %[[INDEX_22]] {num_components = 4 : i32, one = 2 : i32, type = 1 : i32} -// CHECK: dxsa.instruction "ldms_s" %[[OPERAND_19]], %[[OPERAND_20]], %[[OPERAND_21]], %[[OPERAND_22]], %[[OPERAND_23]] -// CHECK: %[[INDEX_23:.*]] = dxsa.index.imm {imm = 1 : i32} -// CHECK: %[[OPERAND_24:.*]] = dxsa.operand %[[INDEX_23]] {mask = 112 : i32, num_components = 4 : i32, type = 0 : i32} -// CHECK: %[[INDEX_24:.*]] = dxsa.index.imm {imm = 1 : i32} -// CHECK: %[[OPERAND_25:.*]] = dxsa.operand %[[INDEX_24]] {num_components = 4 : i32, swizzle = dense<[0, 1, 2, 3]> : vector<4xi32>, type = 0 : i32} -// CHECK: %[[INDEX_25:.*]] = dxsa.index.imm {imm = 3 : i32} -// CHECK: %[[OPERAND_26:.*]] = dxsa.operand %[[INDEX_25]] {num_components = 4 : i32, swizzle = dense<[0, 1, 2, 3]> : vector<4xi32>, type = 7 : i32} -// CHECK: %[[OPERAND_27:.*]] = dxsa.operand.imm {imm = dense<13> : vector<1xi32>} -// CHECK: dxsa.instruction "ldms" %[[OPERAND_24]], %[[OPERAND_25]], %[[OPERAND_26]], %[[OPERAND_27]] +// CHECK: dxsa.ld2dms_s r<2, >, r<1, >, t<3, vector>, v<0, >, r<3, > +// CHECK: dxsa.ld2dms r<1, >, r<1>, t<3, vector>, l(0xD) // CHECK: dxsa.add r<0, >, r<0, >, r<2, > -// CHECK: %[[INDEX_26:.*]] = dxsa.index.imm {imm = 0 : i32} -// CHECK: %[[OPERAND_28:.*]] = dxsa.operand %[[INDEX_26]] {mask = 128 : i32, num_components = 4 : i32, type = 0 : i32} -// CHECK: %[[INDEX_27:.*]] = dxsa.index.imm {imm = 3 : i32} -// CHECK: %[[OPERAND_29:.*]] = dxsa.operand %[[INDEX_27]] {num_components = 4 : i32, one = 0 : i32, type = 0 : i32} -// CHECK: dxsa.instruction "check_access_fully_mapped" %[[OPERAND_28]], %[[OPERAND_29]] +// CHECK: %[[INDEX_2:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_2:.*]] = dxsa.operand %[[INDEX_2]] {mask = 128 : i32, num_components = 4 : i32, type = 0 : i32} +// CHECK: %[[INDEX_3:.*]] = dxsa.index.imm {imm = 3 : i32} +// CHECK: %[[OPERAND_3:.*]] = dxsa.operand %[[INDEX_3]] {num_components = 4 : i32, one = 0 : i32, type = 0 : i32} +// CHECK: dxsa.instruction "check_access_fully_mapped" %[[OPERAND_2]], %[[OPERAND_3]] // CHECK: dxsa.utof r<0, >, r<0, > // CHECK: dxsa.add r<0, >, r<0, >, r<0, > // CHECK: dxsa.add o<0, >, r<1, >, r<0, > diff --git a/mlir/test/Target/DXSA/hlsl/srv_typed_load1.test b/mlir/test/Target/DXSA/hlsl/srv_typed_load1.test index e80ec11e3164..824991f9d600 100644 --- a/mlir/test/Target/DXSA/hlsl/srv_typed_load1.test +++ b/mlir/test/Target/DXSA/hlsl/srv_typed_load1.test @@ -10,62 +10,28 @@ // CHECK: dxsa.dcl_temps 5 // CHECK: dxsa.ftou r<0, >, v<1, > // CHECK: dxsa.mov r<0, >, l(0x0, 0x0, 0x0, 0x0) -// CHECK: %[[INDEX_0:.*]] = dxsa.index.imm {imm = 0 : i32} -// CHECK: %[[OPERAND_0:.*]] = dxsa.operand %[[INDEX_0]] {mask = 240 : i32, num_components = 4 : i32, type = 0 : i32} -// CHECK: %[[INDEX_1:.*]] = dxsa.index.imm {imm = 0 : i32} -// CHECK: %[[OPERAND_1:.*]] = dxsa.operand %[[INDEX_1]] {num_components = 4 : i32, swizzle = dense<[0, 1, 2, 3]> : vector<4xi32>, type = 0 : i32} -// CHECK: %[[INDEX_2:.*]] = dxsa.index.imm {imm = 3 : i32} -// CHECK: %[[OPERAND_2:.*]] = dxsa.operand %[[INDEX_2]] {num_components = 4 : i32, swizzle = dense<[0, 1, 2, 3]> : vector<4xi32>, type = 7 : i32} -// CHECK: dxsa.instruction "ld" %[[OPERAND_0]], %[[OPERAND_1]], %[[OPERAND_2]] +// CHECK: dxsa.ld r<0>, r<0>, t<3, vector> // CHECK: dxsa.ftoi r<1>, v<0, > -// CHECK: %[[INDEX_3:.*]] = dxsa.index.imm {imm = 2 : i32} -// CHECK: %[[OPERAND_3:.*]] = dxsa.operand %[[INDEX_3]] {mask = 240 : i32, num_components = 4 : i32, type = 0 : i32} -// CHECK: %[[INDEX_4:.*]] = dxsa.index.imm {imm = 1 : i32} -// CHECK: %[[OPERAND_4:.*]] = dxsa.operand %[[INDEX_4]] {num_components = 4 : i32, swizzle = dense<[0, 1, 3, 3]> : vector<4xi32>, type = 0 : i32} -// CHECK: %[[INDEX_5:.*]] = dxsa.index.imm {imm = 3 : i32} -// CHECK: %[[OPERAND_5:.*]] = dxsa.operand %[[INDEX_5]] {num_components = 4 : i32, swizzle = dense<[0, 1, 2, 3]> : vector<4xi32>, type = 7 : i32} -// CHECK: dxsa.instruction "ld" %[[OPERAND_3]], %[[OPERAND_4]], %[[OPERAND_5]] +// CHECK: dxsa.ld r<2>, r<1, >, t<3, vector> // CHECK: dxsa.add r<0>, r<0>, r<2> -// CHECK: %[[INDEX_6:.*]] = dxsa.index.imm {imm = 2 : i32} -// CHECK: %[[OPERAND_6:.*]] = dxsa.operand %[[INDEX_6]] {mask = 240 : i32, num_components = 4 : i32, type = 0 : i32} -// CHECK: %[[INDEX_7:.*]] = dxsa.index.imm {imm = 1 : i32} -// CHECK: %[[OPERAND_7:.*]] = dxsa.operand %[[INDEX_7]] {num_components = 4 : i32, swizzle = dense<[0, 1, 3, 3]> : vector<4xi32>, type = 0 : i32} -// CHECK: %[[INDEX_8:.*]] = dxsa.index.imm {imm = 3 : i32} -// CHECK: %[[OPERAND_8:.*]] = dxsa.operand %[[INDEX_8]] {num_components = 4 : i32, swizzle = dense<[0, 1, 2, 3]> : vector<4xi32>, type = 7 : i32} -// CHECK: dxsa.instruction "ld" %[[OPERAND_6]], %[[OPERAND_7]], %[[OPERAND_8]] +// CHECK: dxsa.ld r<2>, r<1, >, t<3, vector>, // CHECK: dxsa.add r<0>, r<0>, r<2> -// CHECK: %[[INDEX_9:.*]] = dxsa.index.imm {imm = 2 : i32} -// CHECK: %[[OPERAND_9:.*]] = dxsa.operand %[[INDEX_9]] {mask = 240 : i32, num_components = 4 : i32, type = 0 : i32} -// CHECK: %[[INDEX_10:.*]] = dxsa.index.imm {imm = 3 : i32} -// CHECK: %[[OPERAND_10:.*]] = dxsa.operand %[[INDEX_10]] {mask = 16 : i32, num_components = 4 : i32, type = 0 : i32} -// CHECK: %[[INDEX_11:.*]] = dxsa.index.imm {imm = 1 : i32} -// CHECK: %[[OPERAND_11:.*]] = dxsa.operand %[[INDEX_11]] {num_components = 4 : i32, swizzle = dense<[0, 1, 3, 3]> : vector<4xi32>, type = 0 : i32} -// CHECK: %[[INDEX_12:.*]] = dxsa.index.imm {imm = 3 : i32} -// CHECK: %[[OPERAND_12:.*]] = dxsa.operand %[[INDEX_12]] {num_components = 4 : i32, swizzle = dense<[0, 1, 2, 3]> : vector<4xi32>, type = 7 : i32} -// CHECK: dxsa.instruction "ld_s" %[[OPERAND_9]], %[[OPERAND_10]], %[[OPERAND_11]], %[[OPERAND_12]] -// CHECK: %[[INDEX_13:.*]] = dxsa.index.imm {imm = 1 : i32} -// CHECK: %[[OPERAND_13:.*]] = dxsa.operand %[[INDEX_13]] {mask = 240 : i32, num_components = 4 : i32, type = 0 : i32} -// CHECK: %[[INDEX_14:.*]] = dxsa.index.imm {imm = 4 : i32} -// CHECK: %[[OPERAND_14:.*]] = dxsa.operand %[[INDEX_14]] {mask = 16 : i32, num_components = 4 : i32, type = 0 : i32} -// CHECK: %[[INDEX_15:.*]] = dxsa.index.imm {imm = 1 : i32} -// CHECK: %[[OPERAND_15:.*]] = dxsa.operand %[[INDEX_15]] {num_components = 4 : i32, swizzle = dense<[0, 1, 2, 3]> : vector<4xi32>, type = 0 : i32} -// CHECK: %[[INDEX_16:.*]] = dxsa.index.imm {imm = 3 : i32} -// CHECK: %[[OPERAND_16:.*]] = dxsa.operand %[[INDEX_16]] {num_components = 4 : i32, swizzle = dense<[0, 1, 2, 3]> : vector<4xi32>, type = 7 : i32} -// CHECK: dxsa.instruction "ld_s" %[[OPERAND_13]], %[[OPERAND_14]], %[[OPERAND_15]], %[[OPERAND_16]] +// CHECK: dxsa.ld_s r<2>, r<1, >, t<3, vector>, r<3, >, +// CHECK: dxsa.ld_s r<1>, r<1>, t<3, vector>, r<4, > // CHECK: dxsa.add r<0>, r<0>, r<2> -// CHECK: %[[INDEX_17:.*]] = dxsa.index.imm {imm = 2 : i32} -// CHECK: %[[OPERAND_17:.*]] = dxsa.operand %[[INDEX_17]] {mask = 16 : i32, num_components = 4 : i32, type = 0 : i32} -// CHECK: %[[INDEX_18:.*]] = dxsa.index.imm {imm = 3 : i32} -// CHECK: %[[OPERAND_18:.*]] = dxsa.operand %[[INDEX_18]] {num_components = 4 : i32, one = 0 : i32, type = 0 : i32} -// CHECK: dxsa.instruction "check_access_fully_mapped" %[[OPERAND_17]], %[[OPERAND_18]] +// CHECK: %[[INDEX_0:.*]] = dxsa.index.imm {imm = 2 : i32} +// CHECK: %[[OPERAND_0:.*]] = dxsa.operand %[[INDEX_0]] {mask = 16 : i32, num_components = 4 : i32, type = 0 : i32} +// CHECK: %[[INDEX_1:.*]] = dxsa.index.imm {imm = 3 : i32} +// CHECK: %[[OPERAND_1:.*]] = dxsa.operand %[[INDEX_1]] {num_components = 4 : i32, one = 0 : i32, type = 0 : i32} +// CHECK: dxsa.instruction "check_access_fully_mapped" %[[OPERAND_0]], %[[OPERAND_1]] // CHECK: dxsa.utof r<2, >, r<2, > // CHECK: dxsa.add r<0>, r<0>, r<2, > // CHECK: dxsa.add r<0>, r<1>, r<0> -// CHECK: %[[INDEX_19:.*]] = dxsa.index.imm {imm = 1 : i32} -// CHECK: %[[OPERAND_19:.*]] = dxsa.operand %[[INDEX_19]] {mask = 16 : i32, num_components = 4 : i32, type = 0 : i32} -// CHECK: %[[INDEX_20:.*]] = dxsa.index.imm {imm = 4 : i32} -// CHECK: %[[OPERAND_20:.*]] = dxsa.operand %[[INDEX_20]] {num_components = 4 : i32, one = 0 : i32, type = 0 : i32} -// CHECK: dxsa.instruction "check_access_fully_mapped" %[[OPERAND_19]], %[[OPERAND_20]] +// CHECK: %[[INDEX_2:.*]] = dxsa.index.imm {imm = 1 : i32} +// CHECK: %[[OPERAND_2:.*]] = dxsa.operand %[[INDEX_2]] {mask = 16 : i32, num_components = 4 : i32, type = 0 : i32} +// CHECK: %[[INDEX_3:.*]] = dxsa.index.imm {imm = 4 : i32} +// CHECK: %[[OPERAND_3:.*]] = dxsa.operand %[[INDEX_3]] {num_components = 4 : i32, one = 0 : i32, type = 0 : i32} +// CHECK: dxsa.instruction "check_access_fully_mapped" %[[OPERAND_2]], %[[OPERAND_3]] // CHECK: dxsa.utof r<1, >, r<1, > // CHECK: dxsa.add o<0>, r<0>, r<1, > // CHECK: dxsa.ret diff --git a/mlir/test/Target/DXSA/hlsl/srv_typed_load2.test b/mlir/test/Target/DXSA/hlsl/srv_typed_load2.test index b607d46b62c7..ff9b4f76bff4 100644 --- a/mlir/test/Target/DXSA/hlsl/srv_typed_load2.test +++ b/mlir/test/Target/DXSA/hlsl/srv_typed_load2.test @@ -7,28 +7,14 @@ // CHECK: dxsa.dcl_input_ps constant v<0, > // CHECK: dxsa.dcl_output o<0> // CHECK: dxsa.dcl_temps 3 -// CHECK: %[[INDEX_0:.*]] = dxsa.index.imm {imm = 0 : i32} -// CHECK: %[[OPERAND_0:.*]] = dxsa.operand %[[INDEX_0]] {mask = 240 : i32, num_components = 4 : i32, type = 0 : i32} -// CHECK: %[[INDEX_1:.*]] = dxsa.index.imm {imm = 0 : i32} -// CHECK: %[[OPERAND_1:.*]] = dxsa.operand %[[INDEX_1]] {num_components = 4 : i32, swizzle = dense<0> : vector<4xi32>, type = 1 : i32} -// CHECK: %[[INDEX_2:.*]] = dxsa.index.imm {imm = 3 : i32} -// CHECK: %[[OPERAND_2:.*]] = dxsa.operand %[[INDEX_2]] {num_components = 4 : i32, swizzle = dense<[0, 1, 2, 3]> : vector<4xi32>, type = 7 : i32} -// CHECK: dxsa.instruction "ld" %[[OPERAND_0]], %[[OPERAND_1]], %[[OPERAND_2]] -// CHECK: %[[INDEX_3:.*]] = dxsa.index.imm {imm = 1 : i32} -// CHECK: %[[OPERAND_3:.*]] = dxsa.operand %[[INDEX_3]] {mask = 240 : i32, num_components = 4 : i32, type = 0 : i32} -// CHECK: %[[INDEX_4:.*]] = dxsa.index.imm {imm = 2 : i32} -// CHECK: %[[OPERAND_4:.*]] = dxsa.operand %[[INDEX_4]] {mask = 16 : i32, num_components = 4 : i32, type = 0 : i32} -// CHECK: %[[INDEX_5:.*]] = dxsa.index.imm {imm = 0 : i32} -// CHECK: %[[OPERAND_5:.*]] = dxsa.operand %[[INDEX_5]] {num_components = 4 : i32, swizzle = dense<0> : vector<4xi32>, type = 1 : i32} -// CHECK: %[[INDEX_6:.*]] = dxsa.index.imm {imm = 3 : i32} -// CHECK: %[[OPERAND_6:.*]] = dxsa.operand %[[INDEX_6]] {num_components = 4 : i32, swizzle = dense<[0, 1, 2, 3]> : vector<4xi32>, type = 7 : i32} -// CHECK: dxsa.instruction "ld_s" %[[OPERAND_3]], %[[OPERAND_4]], %[[OPERAND_5]], %[[OPERAND_6]] +// CHECK: dxsa.ld r<0>, v<0, >, t<3, vector> +// CHECK: dxsa.ld_s r<1>, v<0, >, t<3, vector>, r<2, > // CHECK: dxsa.mad r<0>, r<0>, l(0x40000000, 0x40000000, 0x40000000, 0x40000000), r<1> -// CHECK: %[[INDEX_7:.*]] = dxsa.index.imm {imm = 1 : i32} -// CHECK: %[[OPERAND_7:.*]] = dxsa.operand %[[INDEX_7]] {mask = 16 : i32, num_components = 4 : i32, type = 0 : i32} -// CHECK: %[[INDEX_8:.*]] = dxsa.index.imm {imm = 2 : i32} -// CHECK: %[[OPERAND_8:.*]] = dxsa.operand %[[INDEX_8]] {num_components = 4 : i32, one = 0 : i32, type = 0 : i32} -// CHECK: dxsa.instruction "check_access_fully_mapped" %[[OPERAND_7]], %[[OPERAND_8]] +// CHECK: %[[INDEX_0:.*]] = dxsa.index.imm {imm = 1 : i32} +// CHECK: %[[OPERAND_0:.*]] = dxsa.operand %[[INDEX_0]] {mask = 16 : i32, num_components = 4 : i32, type = 0 : i32} +// CHECK: %[[INDEX_1:.*]] = dxsa.index.imm {imm = 2 : i32} +// CHECK: %[[OPERAND_1:.*]] = dxsa.operand %[[INDEX_1]] {num_components = 4 : i32, one = 0 : i32, type = 0 : i32} +// CHECK: dxsa.instruction "check_access_fully_mapped" %[[OPERAND_0]], %[[OPERAND_1]] // CHECK: dxsa.utof r<1, >, r<1, > // CHECK: dxsa.add o<0>, r<0>, r<1, > // CHECK: dxsa.ret diff --git a/mlir/test/Target/DXSA/hlsl/struct_buf1.test b/mlir/test/Target/DXSA/hlsl/struct_buf1.test index 4cc40bd7e58e..978f1f3fa15d 100644 --- a/mlir/test/Target/DXSA/hlsl/struct_buf1.test +++ b/mlir/test/Target/DXSA/hlsl/struct_buf1.test @@ -11,249 +11,82 @@ // CHECK: dxsa.dcl_temps 22 // CHECK: dxsa.add r<0, >, v<0, >, l(0x43480000, 0x43480000, 0x0, 0x0) // CHECK: dxsa.ftoi r<0, >, r<0, > -// CHECK: %[[INDEX_0:.*]] = dxsa.index.imm {imm = 0 : i32} -// CHECK: %[[OPERAND_0:.*]] = dxsa.operand %[[INDEX_0]] {mask = 192 : i32, num_components = 4 : i32, type = 0 : i32} -// CHECK: %[[INDEX_1:.*]] = dxsa.index.imm {imm = 0 : i32} -// CHECK: %[[OPERAND_1:.*]] = dxsa.operand %[[INDEX_1]] {num_components = 4 : i32, one = 0 : i32, type = 0 : i32} -// CHECK: %[[OPERAND_2:.*]] = dxsa.operand.imm {imm = dense<0> : vector<1xi32>} -// CHECK: %[[INDEX_2:.*]] = dxsa.index.imm {imm = 1 : i32} -// CHECK: %[[OPERAND_3:.*]] = dxsa.operand %[[INDEX_2]] {num_components = 4 : i32, swizzle = dense<[0, 0, 0, 1]> : vector<4xi32>, type = 30 : i32} -// CHECK: dxsa.instruction "ld_structured" %[[OPERAND_0]], %[[OPERAND_1]], %[[OPERAND_2]], %[[OPERAND_3]] -// CHECK: %[[INDEX_3:.*]] = dxsa.index.imm {imm = 1 : i32} -// CHECK: %[[OPERAND_4:.*]] = dxsa.operand %[[INDEX_3]] {mask = 48 : i32, num_components = 4 : i32, type = 0 : i32} -// CHECK: %[[INDEX_4:.*]] = dxsa.index.imm {imm = 0 : i32} -// CHECK: %[[OPERAND_5:.*]] = dxsa.operand %[[INDEX_4]] {num_components = 4 : i32, one = 0 : i32, type = 0 : i32} -// CHECK: %[[OPERAND_6:.*]] = dxsa.operand.imm {imm = dense<8> : vector<1xi32>} -// CHECK: %[[INDEX_5:.*]] = dxsa.index.imm {imm = 1 : i32} -// CHECK: %[[OPERAND_7:.*]] = dxsa.operand %[[INDEX_5]] {num_components = 4 : i32, swizzle = dense<[0, 1, 0, 0]> : vector<4xi32>, type = 30 : i32} -// CHECK: dxsa.instruction "ld_structured" %[[OPERAND_4]], %[[OPERAND_5]], %[[OPERAND_6]], %[[OPERAND_7]] -// CHECK: %[[INDEX_6:.*]] = dxsa.index.imm {imm = 1 : i32} -// CHECK: %[[OPERAND_8:.*]] = dxsa.operand %[[INDEX_6]] {mask = 64 : i32, num_components = 4 : i32, type = 0 : i32} -// CHECK: %[[INDEX_7:.*]] = dxsa.index.imm {imm = 0 : i32} -// CHECK: %[[OPERAND_9:.*]] = dxsa.operand %[[INDEX_7]] {num_components = 4 : i32, one = 0 : i32, type = 0 : i32} -// CHECK: %[[OPERAND_10:.*]] = dxsa.operand.imm {imm = dense<16> : vector<1xi32>} -// CHECK: %[[INDEX_8:.*]] = dxsa.index.imm {imm = 1 : i32} -// CHECK: %[[OPERAND_11:.*]] = dxsa.operand %[[INDEX_8]] {num_components = 4 : i32, swizzle = dense<0> : vector<4xi32>, type = 30 : i32} -// CHECK: dxsa.instruction "ld_structured" %[[OPERAND_8]], %[[OPERAND_9]], %[[OPERAND_10]], %[[OPERAND_11]] -// CHECK: %[[INDEX_9:.*]] = dxsa.index.imm {imm = 2 : i32} -// CHECK: %[[OPERAND_12:.*]] = dxsa.operand %[[INDEX_9]] {mask = 112 : i32, num_components = 4 : i32, type = 0 : i32} -// CHECK: %[[INDEX_10:.*]] = dxsa.index.imm {imm = 0 : i32} -// CHECK: %[[OPERAND_13:.*]] = dxsa.operand %[[INDEX_10]] {num_components = 4 : i32, one = 0 : i32, type = 0 : i32} -// CHECK: %[[OPERAND_14:.*]] = dxsa.operand.imm {imm = dense<20> : vector<1xi32>} -// CHECK: %[[INDEX_11:.*]] = dxsa.index.imm {imm = 1 : i32} -// CHECK: %[[OPERAND_15:.*]] = dxsa.operand %[[INDEX_11]] {num_components = 4 : i32, swizzle = dense<[0, 1, 2, 0]> : vector<4xi32>, type = 30 : i32} -// CHECK: dxsa.instruction "ld_structured" %[[OPERAND_12]], %[[OPERAND_13]], %[[OPERAND_14]], %[[OPERAND_15]] -// CHECK: %[[INDEX_12:.*]] = dxsa.index.imm {imm = 3 : i32} -// CHECK: %[[OPERAND_16:.*]] = dxsa.operand %[[INDEX_12]] {mask = 240 : i32, num_components = 4 : i32, type = 0 : i32} -// CHECK: %[[INDEX_13:.*]] = dxsa.index.imm {imm = 0 : i32} -// CHECK: %[[OPERAND_17:.*]] = dxsa.operand %[[INDEX_13]] {num_components = 4 : i32, one = 0 : i32, type = 0 : i32} -// CHECK: %[[OPERAND_18:.*]] = dxsa.operand.imm {imm = dense<32> : vector<1xi32>} -// CHECK: %[[INDEX_14:.*]] = dxsa.index.imm {imm = 1 : i32} -// CHECK: %[[OPERAND_19:.*]] = dxsa.operand %[[INDEX_14]] {num_components = 4 : i32, swizzle = dense<[0, 1, 2, 3]> : vector<4xi32>, type = 30 : i32} -// CHECK: dxsa.instruction "ld_structured" %[[OPERAND_16]], %[[OPERAND_17]], %[[OPERAND_18]], %[[OPERAND_19]] -// CHECK: %[[INDEX_15:.*]] = dxsa.index.imm {imm = 4 : i32} -// CHECK: %[[OPERAND_20:.*]] = dxsa.operand %[[INDEX_15]] {mask = 32 : i32, num_components = 4 : i32, type = 0 : i32} -// CHECK: %[[INDEX_16:.*]] = dxsa.index.imm {imm = 0 : i32} -// CHECK: %[[OPERAND_21:.*]] = dxsa.operand %[[INDEX_16]] {num_components = 4 : i32, one = 0 : i32, type = 0 : i32} -// CHECK: %[[OPERAND_22:.*]] = dxsa.operand.imm {imm = dense<48> : vector<1xi32>} -// CHECK: %[[INDEX_17:.*]] = dxsa.index.imm {imm = 1 : i32} -// CHECK: %[[OPERAND_23:.*]] = dxsa.operand %[[INDEX_17]] {num_components = 4 : i32, swizzle = dense<0> : vector<4xi32>, type = 30 : i32} -// CHECK: dxsa.instruction "ld_structured" %[[OPERAND_20]], %[[OPERAND_21]], %[[OPERAND_22]], %[[OPERAND_23]] -// CHECK: %[[INDEX_18:.*]] = dxsa.index.imm {imm = 5 : i32} -// CHECK: %[[OPERAND_24:.*]] = dxsa.operand %[[INDEX_18]] {mask = 48 : i32, num_components = 4 : i32, type = 0 : i32} -// CHECK: %[[INDEX_19:.*]] = dxsa.index.imm {imm = 0 : i32} -// CHECK: %[[OPERAND_25:.*]] = dxsa.operand %[[INDEX_19]] {mask = 16 : i32, num_components = 4 : i32, type = 0 : i32} -// CHECK: %[[INDEX_20:.*]] = dxsa.index.imm {imm = 0 : i32} -// CHECK: %[[OPERAND_26:.*]] = dxsa.operand %[[INDEX_20]] {num_components = 4 : i32, one = 1 : i32, type = 0 : i32} -// CHECK: %[[OPERAND_27:.*]] = dxsa.operand.imm {imm = dense<0> : vector<1xi32>} -// CHECK: %[[INDEX_21:.*]] = dxsa.index.imm {imm = 1 : i32} -// CHECK: %[[OPERAND_28:.*]] = dxsa.operand %[[INDEX_21]] {num_components = 4 : i32, swizzle = dense<[0, 1, 2, 3]> : vector<4xi32>, type = 30 : i32} -// CHECK: dxsa.instruction "ld_structured_s" %[[OPERAND_24]], %[[OPERAND_25]], %[[OPERAND_26]], %[[OPERAND_27]], %[[OPERAND_28]] -// CHECK: %[[INDEX_22:.*]] = dxsa.index.imm {imm = 4 : i32} -// CHECK: %[[OPERAND_29:.*]] = dxsa.operand %[[INDEX_22]] {mask = 192 : i32, num_components = 4 : i32, type = 0 : i32} -// CHECK: %[[INDEX_23:.*]] = dxsa.index.imm {imm = 6 : i32} -// CHECK: %[[OPERAND_30:.*]] = dxsa.operand %[[INDEX_23]] {mask = 16 : i32, num_components = 4 : i32, type = 0 : i32} -// CHECK: %[[INDEX_24:.*]] = dxsa.index.imm {imm = 0 : i32} -// CHECK: %[[OPERAND_31:.*]] = dxsa.operand %[[INDEX_24]] {num_components = 4 : i32, one = 1 : i32, type = 0 : i32} -// CHECK: %[[OPERAND_32:.*]] = dxsa.operand.imm {imm = dense<0> : vector<1xi32>} -// CHECK: %[[INDEX_25:.*]] = dxsa.index.imm {imm = 1 : i32} -// CHECK: %[[OPERAND_33:.*]] = dxsa.operand %[[INDEX_25]] {num_components = 4 : i32, swizzle = dense<[0, 1, 2, 3]> : vector<4xi32>, type = 30 : i32} -// CHECK: dxsa.instruction "ld_structured_s" %[[OPERAND_29]], %[[OPERAND_30]], %[[OPERAND_31]], %[[OPERAND_32]], %[[OPERAND_33]] -// CHECK: %[[INDEX_26:.*]] = dxsa.index.imm {imm = 7 : i32} -// CHECK: %[[OPERAND_34:.*]] = dxsa.operand %[[INDEX_26]] {mask = 16 : i32, num_components = 4 : i32, type = 0 : i32} -// CHECK: %[[INDEX_27:.*]] = dxsa.index.imm {imm = 8 : i32} -// CHECK: %[[OPERAND_35:.*]] = dxsa.operand %[[INDEX_27]] {mask = 16 : i32, num_components = 4 : i32, type = 0 : i32} -// CHECK: %[[INDEX_28:.*]] = dxsa.index.imm {imm = 0 : i32} -// CHECK: %[[OPERAND_36:.*]] = dxsa.operand %[[INDEX_28]] {num_components = 4 : i32, one = 1 : i32, type = 0 : i32} -// CHECK: %[[OPERAND_37:.*]] = dxsa.operand.imm {imm = dense<16> : vector<1xi32>} -// CHECK: %[[INDEX_29:.*]] = dxsa.index.imm {imm = 1 : i32} -// CHECK: %[[OPERAND_38:.*]] = dxsa.operand %[[INDEX_29]] {num_components = 4 : i32, swizzle = dense<[0, 1, 2, 3]> : vector<4xi32>, type = 30 : i32} -// CHECK: dxsa.instruction "ld_structured_s" %[[OPERAND_34]], %[[OPERAND_35]], %[[OPERAND_36]], %[[OPERAND_37]], %[[OPERAND_38]] -// CHECK: %[[INDEX_30:.*]] = dxsa.index.imm {imm = 6 : i32} -// CHECK: %[[OPERAND_39:.*]] = dxsa.operand %[[INDEX_30]] {mask = 224 : i32, num_components = 4 : i32, type = 0 : i32} -// CHECK: %[[INDEX_31:.*]] = dxsa.index.imm {imm = 9 : i32} -// CHECK: %[[OPERAND_40:.*]] = dxsa.operand %[[INDEX_31]] {mask = 16 : i32, num_components = 4 : i32, type = 0 : i32} -// CHECK: %[[INDEX_32:.*]] = dxsa.index.imm {imm = 0 : i32} -// CHECK: %[[OPERAND_41:.*]] = dxsa.operand %[[INDEX_32]] {num_components = 4 : i32, one = 1 : i32, type = 0 : i32} -// CHECK: %[[OPERAND_42:.*]] = dxsa.operand.imm {imm = dense<16> : vector<1xi32>} -// CHECK: %[[INDEX_33:.*]] = dxsa.index.imm {imm = 1 : i32} -// CHECK: %[[OPERAND_43:.*]] = dxsa.operand %[[INDEX_33]] {num_components = 4 : i32, swizzle = dense<[0, 1, 2, 3]> : vector<4xi32>, type = 30 : i32} -// CHECK: dxsa.instruction "ld_structured_s" %[[OPERAND_39]], %[[OPERAND_40]], %[[OPERAND_41]], %[[OPERAND_42]], %[[OPERAND_43]] -// CHECK: %[[INDEX_34:.*]] = dxsa.index.imm {imm = 10 : i32} -// CHECK: %[[OPERAND_44:.*]] = dxsa.operand %[[INDEX_34]] {mask = 240 : i32, num_components = 4 : i32, type = 0 : i32} -// CHECK: %[[INDEX_35:.*]] = dxsa.index.imm {imm = 11 : i32} -// CHECK: %[[OPERAND_45:.*]] = dxsa.operand %[[INDEX_35]] {mask = 16 : i32, num_components = 4 : i32, type = 0 : i32} -// CHECK: %[[INDEX_36:.*]] = dxsa.index.imm {imm = 0 : i32} -// CHECK: %[[OPERAND_46:.*]] = dxsa.operand %[[INDEX_36]] {num_components = 4 : i32, one = 1 : i32, type = 0 : i32} -// CHECK: %[[OPERAND_47:.*]] = dxsa.operand.imm {imm = dense<32> : vector<1xi32>} -// CHECK: %[[INDEX_37:.*]] = dxsa.index.imm {imm = 1 : i32} -// CHECK: %[[OPERAND_48:.*]] = dxsa.operand %[[INDEX_37]] {num_components = 4 : i32, swizzle = dense<[0, 1, 2, 3]> : vector<4xi32>, type = 30 : i32} -// CHECK: dxsa.instruction "ld_structured_s" %[[OPERAND_44]], %[[OPERAND_45]], %[[OPERAND_46]], %[[OPERAND_47]], %[[OPERAND_48]] -// CHECK: %[[INDEX_38:.*]] = dxsa.index.imm {imm = 12 : i32} -// CHECK: %[[OPERAND_49:.*]] = dxsa.operand %[[INDEX_38]] {mask = 16 : i32, num_components = 4 : i32, type = 0 : i32} -// CHECK: %[[INDEX_39:.*]] = dxsa.index.imm {imm = 13 : i32} -// CHECK: %[[OPERAND_50:.*]] = dxsa.operand %[[INDEX_39]] {mask = 16 : i32, num_components = 4 : i32, type = 0 : i32} -// CHECK: %[[INDEX_40:.*]] = dxsa.index.imm {imm = 0 : i32} -// CHECK: %[[OPERAND_51:.*]] = dxsa.operand %[[INDEX_40]] {num_components = 4 : i32, one = 1 : i32, type = 0 : i32} -// CHECK: %[[OPERAND_52:.*]] = dxsa.operand.imm {imm = dense<48> : vector<1xi32>} -// CHECK: %[[INDEX_41:.*]] = dxsa.index.imm {imm = 1 : i32} -// CHECK: %[[OPERAND_53:.*]] = dxsa.operand %[[INDEX_41]] {num_components = 4 : i32, swizzle = dense<0> : vector<4xi32>, type = 30 : i32} -// CHECK: dxsa.instruction "ld_structured_s" %[[OPERAND_49]], %[[OPERAND_50]], %[[OPERAND_51]], %[[OPERAND_52]], %[[OPERAND_53]] +// CHECK: dxsa.ld_structured r<0, >, r<0, >, l(0x0), u<1, vector, > +// CHECK: dxsa.ld_structured r<1, >, r<0, >, l(0x8), u<1, vector, > +// CHECK: dxsa.ld_structured r<1, >, r<0, >, l(0x10), u<1, vector, > +// CHECK: dxsa.ld_structured r<2, >, r<0, >, l(0x14), u<1, vector, > +// CHECK: dxsa.ld_structured r<3>, r<0, >, l(0x20), u<1, vector> +// CHECK: dxsa.ld_structured r<4, >, r<0, >, l(0x30), u<1, vector, > +// CHECK: dxsa.ld_structured_s r<5, >, r<0, >, l(0x0), u<1, vector>, r<0, > +// CHECK: dxsa.ld_structured_s r<4, >, r<0, >, l(0x0), u<1, vector>, r<6, > +// CHECK: dxsa.ld_structured_s r<7, >, r<0, >, l(0x10), u<1, vector>, r<8, > +// CHECK: dxsa.ld_structured_s r<6, >, r<0, >, l(0x10), u<1, vector>, r<9, > +// CHECK: dxsa.ld_structured_s r<10>, r<0, >, l(0x20), u<1, vector>, r<11, > +// CHECK: dxsa.ld_structured_s r<12, >, r<0, >, l(0x30), u<1, vector, >, r<13, > // CHECK: dxsa.mov r<14, >, l(0x0) // CHECK: dxsa.ftou r<1, >, v<0, > // CHECK: dxsa.ineg r<5, >, r<1, > // CHECK: dxsa.ult r<7, >, r<1, >, l(0x0, 0x1, 0x2, 0x3) // CHECK: dxsa.and r<5, >, r<5, >, r<7, > // CHECK: dxsa.ftoi r<8, >, v<0, > -// CHECK: %[[INDEX_42:.*]] = dxsa.index.imm {imm = 15 : i32} -// CHECK: %[[OPERAND_54:.*]] = dxsa.operand %[[INDEX_42]] {mask = 240 : i32, num_components = 4 : i32, type = 0 : i32} -// CHECK: %[[INDEX_43:.*]] = dxsa.index.imm {imm = 8 : i32} -// CHECK: %[[OPERAND_55:.*]] = dxsa.operand %[[INDEX_43]] {num_components = 4 : i32, one = 1 : i32, type = 0 : i32} -// CHECK: %[[OPERAND_56:.*]] = dxsa.operand.imm {imm = dense<32> : vector<1xi32>} -// CHECK: %[[INDEX_44:.*]] = dxsa.index.imm {imm = 0 : i32} -// CHECK: %[[OPERAND_57:.*]] = dxsa.operand %[[INDEX_44]] {num_components = 4 : i32, swizzle = dense<[3, 0, 1, 2]> : vector<4xi32>, type = 7 : i32} -// CHECK: dxsa.instruction "ld_structured" %[[OPERAND_54]], %[[OPERAND_55]], %[[OPERAND_56]], %[[OPERAND_57]] +// CHECK: dxsa.ld_structured r<15>, r<8, >, l(0x20), t<0, vector, > // CHECK: dxsa.mov r<16, >, r<15, > -// CHECK: %[[INDEX_45:.*]] = dxsa.index.imm {imm = 16 : i32} -// CHECK: %[[OPERAND_58:.*]] = dxsa.operand %[[INDEX_45]] {mask = 112 : i32, num_components = 4 : i32, type = 0 : i32} -// CHECK: %[[INDEX_46:.*]] = dxsa.index.imm {imm = 8 : i32} -// CHECK: %[[OPERAND_59:.*]] = dxsa.operand %[[INDEX_46]] {num_components = 4 : i32, one = 1 : i32, type = 0 : i32} -// CHECK: %[[OPERAND_60:.*]] = dxsa.operand.imm {imm = dense<20> : vector<1xi32>} -// CHECK: %[[INDEX_47:.*]] = dxsa.index.imm {imm = 0 : i32} -// CHECK: %[[OPERAND_61:.*]] = dxsa.operand %[[INDEX_47]] {num_components = 4 : i32, swizzle = dense<[0, 1, 2, 0]> : vector<4xi32>, type = 7 : i32} -// CHECK: dxsa.instruction "ld_structured" %[[OPERAND_58]], %[[OPERAND_59]], %[[OPERAND_60]], %[[OPERAND_61]] +// CHECK: dxsa.ld_structured r<16, >, r<8, >, l(0x14), t<0, vector, > // CHECK: dxsa.and r<9, >, r<5, >, r<16, > // CHECK: dxsa.and r<11, >, r<7, >, r<16, > // CHECK: dxsa.or r<9, >, r<9, >, r<11, > // CHECK: dxsa.iadd r<5, >, r<1, >, l(0xFFFFFFFD) // CHECK: dxsa.ishl r<1, >, r<1, >, l(0x3) // CHECK: dxsa.iadd r<1, >, r<1, >, l(0x14) -// CHECK: %[[INDEX_48:.*]] = dxsa.index.imm {imm = 5 : i32} -// CHECK: %[[OPERAND_62:.*]] = dxsa.operand %[[INDEX_48]] {mask = 128 : i32, num_components = 4 : i32, type = 0 : i32} -// CHECK: %[[INDEX_49:.*]] = dxsa.index.imm {imm = 7 : i32} -// CHECK: %[[OPERAND_63:.*]] = dxsa.operand %[[INDEX_49]] {num_components = 4 : i32, one = 2 : i32, type = 0 : i32} -// CHECK: %[[OPERAND_64:.*]] = dxsa.operand.imm {imm = dense<0> : vector<1xi32>} -// CHECK: %[[INDEX_50:.*]] = dxsa.index.imm {imm = 5 : i32} -// CHECK: %[[OPERAND_65:.*]] = dxsa.operand %[[INDEX_50]] {num_components = 4 : i32, one = 3 : i32, type = 0 : i32} -// CHECK: dxsa.instruction "movc" %[[OPERAND_62]], %[[OPERAND_63]], %[[OPERAND_64]], %[[OPERAND_65]] +// CHECK: %[[INDEX_0:.*]] = dxsa.index.imm {imm = 5 : i32} +// CHECK: %[[OPERAND_0:.*]] = dxsa.operand %[[INDEX_0]] {mask = 128 : i32, num_components = 4 : i32, type = 0 : i32} +// CHECK: %[[INDEX_1:.*]] = dxsa.index.imm {imm = 7 : i32} +// CHECK: %[[OPERAND_1:.*]] = dxsa.operand %[[INDEX_1]] {num_components = 4 : i32, one = 2 : i32, type = 0 : i32} +// CHECK: %[[OPERAND_2:.*]] = dxsa.operand.imm {imm = dense<0> : vector<1xi32>} +// CHECK: %[[INDEX_2:.*]] = dxsa.index.imm {imm = 5 : i32} +// CHECK: %[[OPERAND_3:.*]] = dxsa.operand %[[INDEX_2]] {num_components = 4 : i32, one = 3 : i32, type = 0 : i32} +// CHECK: dxsa.instruction "movc" %[[OPERAND_0]], %[[OPERAND_1]], %[[OPERAND_2]], %[[OPERAND_3]] // CHECK: dxsa.and r<11, >, r<15, >, r<5, > // CHECK: dxsa.or r<9, >, r<9, >, r<11, > // CHECK: dxsa.ieq r<7, >, r<7, >, l(0x0) -// CHECK: %[[INDEX_51:.*]] = dxsa.index.imm {imm = 15 : i32} -// CHECK: %[[OPERAND_66:.*]] = dxsa.operand %[[INDEX_51]] {mask = 32 : i32, num_components = 4 : i32, type = 0 : i32} -// CHECK: %[[INDEX_52:.*]] = dxsa.index.imm {imm = 8 : i32} -// CHECK: %[[OPERAND_67:.*]] = dxsa.operand %[[INDEX_52]] {num_components = 4 : i32, one = 1 : i32, type = 0 : i32} -// CHECK: %[[OPERAND_68:.*]] = dxsa.operand.imm {imm = dense<48> : vector<1xi32>} -// CHECK: %[[INDEX_53:.*]] = dxsa.index.imm {imm = 0 : i32} -// CHECK: %[[OPERAND_69:.*]] = dxsa.operand %[[INDEX_53]] {num_components = 4 : i32, swizzle = dense<0> : vector<4xi32>, type = 7 : i32} -// CHECK: dxsa.instruction "ld_structured" %[[OPERAND_66]], %[[OPERAND_67]], %[[OPERAND_68]], %[[OPERAND_69]] +// CHECK: dxsa.ld_structured r<15, >, r<8, >, l(0x30), t<0, vector, > // CHECK: dxsa.and r<11, >, r<7, >, r<15, > // CHECK: dxsa.or r<9, >, r<9, >, r<11, > // CHECK: dxsa.itof r<9, >, r<9, > // CHECK: dxsa.mov r<15, >, l(0x0) -// CHECK: %[[INDEX_54:.*]] = dxsa.index.imm {imm = 15 : i32} -// CHECK: %[[OPERAND_70:.*]] = dxsa.operand %[[INDEX_54]] {mask = 48 : i32, num_components = 4 : i32, type = 0 : i32} -// CHECK: %[[INDEX_55:.*]] = dxsa.index.imm {imm = 8 : i32} -// CHECK: %[[OPERAND_71:.*]] = dxsa.operand %[[INDEX_55]] {num_components = 4 : i32, one = 1 : i32, type = 0 : i32} -// CHECK: %[[OPERAND_72:.*]] = dxsa.operand.imm {imm = dense<0> : vector<1xi32>} -// CHECK: %[[INDEX_56:.*]] = dxsa.index.imm {imm = 0 : i32} -// CHECK: %[[OPERAND_73:.*]] = dxsa.operand %[[INDEX_56]] {num_components = 4 : i32, swizzle = dense<[0, 1, 0, 0]> : vector<4xi32>, type = 7 : i32} -// CHECK: dxsa.instruction "ld_structured" %[[OPERAND_70]], %[[OPERAND_71]], %[[OPERAND_72]], %[[OPERAND_73]] -// CHECK: %[[INDEX_57:.*]] = dxsa.index.imm {imm = 11 : i32} -// CHECK: %[[OPERAND_74:.*]] = dxsa.operand %[[INDEX_57]] {mask = 224 : i32, num_components = 4 : i32, type = 0 : i32} -// CHECK: %[[INDEX_58:.*]] = dxsa.index.imm {imm = 8 : i32} -// CHECK: %[[OPERAND_75:.*]] = dxsa.operand %[[INDEX_58]] {num_components = 4 : i32, one = 1 : i32, type = 0 : i32} -// CHECK: %[[OPERAND_76:.*]] = dxsa.operand.imm {imm = dense<8> : vector<1xi32>} -// CHECK: %[[INDEX_59:.*]] = dxsa.index.imm {imm = 0 : i32} -// CHECK: %[[OPERAND_77:.*]] = dxsa.operand %[[INDEX_59]] {num_components = 4 : i32, swizzle = dense<[0, 0, 1, 2]> : vector<4xi32>, type = 7 : i32} -// CHECK: dxsa.instruction "ld_structured" %[[OPERAND_74]], %[[OPERAND_75]], %[[OPERAND_76]], %[[OPERAND_77]] +// CHECK: dxsa.ld_structured r<15, >, r<8, >, l(0x0), t<0, vector, > +// CHECK: dxsa.ld_structured r<11, >, r<8, >, l(0x8), t<0, vector, > // CHECK: dxsa.add r<14, >, r<11, >, r<15, > // CHECK: dxsa.add r<15, >, r<9, >, r<14, > // CHECK: dxsa.mov r<15, >, r<14, > -// CHECK: %[[INDEX_60:.*]] = dxsa.index.imm {imm = 16 : i32} -// CHECK: %[[OPERAND_78:.*]] = dxsa.operand %[[INDEX_60]] {mask = 240 : i32, num_components = 4 : i32, type = 0 : i32} -// CHECK: %[[INDEX_61:.*]] = dxsa.index.imm {imm = 17 : i32} -// CHECK: %[[OPERAND_79:.*]] = dxsa.operand %[[INDEX_61]] {mask = 16 : i32, num_components = 4 : i32, type = 0 : i32} -// CHECK: %[[INDEX_62:.*]] = dxsa.index.imm {imm = 8 : i32} -// CHECK: %[[OPERAND_80:.*]] = dxsa.operand %[[INDEX_62]] {num_components = 4 : i32, one = 2 : i32, type = 0 : i32} -// CHECK: %[[OPERAND_81:.*]] = dxsa.operand.imm {imm = dense<0> : vector<1xi32>} -// CHECK: %[[INDEX_63:.*]] = dxsa.index.imm {imm = 0 : i32} -// CHECK: %[[OPERAND_82:.*]] = dxsa.operand %[[INDEX_63]] {num_components = 4 : i32, swizzle = dense<[0, 1, 2, 3]> : vector<4xi32>, type = 7 : i32} -// CHECK: dxsa.instruction "ld_structured_s" %[[OPERAND_78]], %[[OPERAND_79]], %[[OPERAND_80]], %[[OPERAND_81]], %[[OPERAND_82]] +// CHECK: dxsa.ld_structured_s r<16>, r<8, >, l(0x0), t<0, vector>, r<17, > // CHECK: dxsa.add r<14, >, r<15, >, r<16, > -// CHECK: %[[INDEX_64:.*]] = dxsa.index.imm {imm = 7 : i32} -// CHECK: %[[OPERAND_83:.*]] = dxsa.operand %[[INDEX_64]] {mask = 128 : i32, num_components = 4 : i32, type = 0 : i32} -// CHECK: %[[INDEX_65:.*]] = dxsa.index.imm {imm = 17 : i32} -// CHECK: %[[OPERAND_84:.*]] = dxsa.operand %[[INDEX_65]] {num_components = 4 : i32, one = 0 : i32, type = 0 : i32} -// CHECK: dxsa.instruction "check_access_fully_mapped" %[[OPERAND_83]], %[[OPERAND_84]] +// CHECK: %[[INDEX_3:.*]] = dxsa.index.imm {imm = 7 : i32} +// CHECK: %[[OPERAND_4:.*]] = dxsa.operand %[[INDEX_3]] {mask = 128 : i32, num_components = 4 : i32, type = 0 : i32} +// CHECK: %[[INDEX_4:.*]] = dxsa.index.imm {imm = 17 : i32} +// CHECK: %[[OPERAND_5:.*]] = dxsa.operand %[[INDEX_4]] {num_components = 4 : i32, one = 0 : i32, type = 0 : i32} +// CHECK: dxsa.instruction "check_access_fully_mapped" %[[OPERAND_4]], %[[OPERAND_5]] // CHECK: dxsa.mov r<16, >, r<16, > -// CHECK: %[[INDEX_66:.*]] = dxsa.index.imm {imm = 17 : i32} -// CHECK: %[[OPERAND_85:.*]] = dxsa.operand %[[INDEX_66]] {mask = 240 : i32, num_components = 4 : i32, type = 0 : i32} -// CHECK: %[[INDEX_67:.*]] = dxsa.index.imm {imm = 18 : i32} -// CHECK: %[[OPERAND_86:.*]] = dxsa.operand %[[INDEX_67]] {mask = 16 : i32, num_components = 4 : i32, type = 0 : i32} -// CHECK: %[[INDEX_68:.*]] = dxsa.index.imm {imm = 8 : i32} -// CHECK: %[[OPERAND_87:.*]] = dxsa.operand %[[INDEX_68]] {num_components = 4 : i32, one = 2 : i32, type = 0 : i32} -// CHECK: %[[OPERAND_88:.*]] = dxsa.operand.imm {imm = dense<16> : vector<1xi32>} -// CHECK: %[[INDEX_69:.*]] = dxsa.index.imm {imm = 0 : i32} -// CHECK: %[[OPERAND_89:.*]] = dxsa.operand %[[INDEX_69]] {num_components = 4 : i32, swizzle = dense<[0, 1, 2, 3]> : vector<4xi32>, type = 7 : i32} -// CHECK: dxsa.instruction "ld_structured_s" %[[OPERAND_85]], %[[OPERAND_86]], %[[OPERAND_87]], %[[OPERAND_88]], %[[OPERAND_89]] -// CHECK: %[[INDEX_70:.*]] = dxsa.index.imm {imm = 8 : i32} -// CHECK: %[[OPERAND_90:.*]] = dxsa.operand %[[INDEX_70]] {mask = 32 : i32, num_components = 4 : i32, type = 0 : i32} -// CHECK: %[[INDEX_71:.*]] = dxsa.index.imm {imm = 18 : i32} -// CHECK: %[[OPERAND_91:.*]] = dxsa.operand %[[INDEX_71]] {num_components = 4 : i32, one = 0 : i32, type = 0 : i32} -// CHECK: dxsa.instruction "check_access_fully_mapped" %[[OPERAND_90]], %[[OPERAND_91]] +// CHECK: dxsa.ld_structured_s r<17>, r<8, >, l(0x10), t<0, vector>, r<18, > +// CHECK: %[[INDEX_5:.*]] = dxsa.index.imm {imm = 8 : i32} +// CHECK: %[[OPERAND_6:.*]] = dxsa.operand %[[INDEX_5]] {mask = 32 : i32, num_components = 4 : i32, type = 0 : i32} +// CHECK: %[[INDEX_6:.*]] = dxsa.index.imm {imm = 18 : i32} +// CHECK: %[[OPERAND_7:.*]] = dxsa.operand %[[INDEX_6]] {num_components = 4 : i32, one = 0 : i32, type = 0 : i32} +// CHECK: dxsa.instruction "check_access_fully_mapped" %[[OPERAND_6]], %[[OPERAND_7]] // CHECK: dxsa.and r<7, >, r<7, >, r<8, > -// CHECK: %[[INDEX_72:.*]] = dxsa.index.imm {imm = 18 : i32} -// CHECK: %[[OPERAND_92:.*]] = dxsa.operand %[[INDEX_72]] {mask = 240 : i32, num_components = 4 : i32, type = 0 : i32} -// CHECK: %[[INDEX_73:.*]] = dxsa.index.imm {imm = 19 : i32} -// CHECK: %[[OPERAND_93:.*]] = dxsa.operand %[[INDEX_73]] {mask = 16 : i32, num_components = 4 : i32, type = 0 : i32} -// CHECK: %[[INDEX_74:.*]] = dxsa.index.imm {imm = 8 : i32} -// CHECK: %[[OPERAND_94:.*]] = dxsa.operand %[[INDEX_74]] {num_components = 4 : i32, one = 2 : i32, type = 0 : i32} -// CHECK: %[[OPERAND_95:.*]] = dxsa.operand.imm {imm = dense<32> : vector<1xi32>} -// CHECK: %[[INDEX_75:.*]] = dxsa.index.imm {imm = 0 : i32} -// CHECK: %[[OPERAND_96:.*]] = dxsa.operand %[[INDEX_75]] {num_components = 4 : i32, swizzle = dense<[0, 1, 2, 3]> : vector<4xi32>, type = 7 : i32} -// CHECK: dxsa.instruction "ld_structured_s" %[[OPERAND_92]], %[[OPERAND_93]], %[[OPERAND_94]], %[[OPERAND_95]], %[[OPERAND_96]] -// CHECK: %[[INDEX_76:.*]] = dxsa.index.imm {imm = 20 : i32} -// CHECK: %[[OPERAND_97:.*]] = dxsa.operand %[[INDEX_76]] {mask = 16 : i32, num_components = 4 : i32, type = 0 : i32} -// CHECK: %[[INDEX_77:.*]] = dxsa.index.imm {imm = 21 : i32} -// CHECK: %[[OPERAND_98:.*]] = dxsa.operand %[[INDEX_77]] {mask = 16 : i32, num_components = 4 : i32, type = 0 : i32} -// CHECK: %[[INDEX_78:.*]] = dxsa.index.imm {imm = 8 : i32} -// CHECK: %[[OPERAND_99:.*]] = dxsa.operand %[[INDEX_78]] {num_components = 4 : i32, one = 2 : i32, type = 0 : i32} -// CHECK: %[[OPERAND_100:.*]] = dxsa.operand.imm {imm = dense<48> : vector<1xi32>} -// CHECK: %[[INDEX_79:.*]] = dxsa.index.imm {imm = 0 : i32} -// CHECK: %[[OPERAND_101:.*]] = dxsa.operand %[[INDEX_79]] {num_components = 4 : i32, swizzle = dense<0> : vector<4xi32>, type = 7 : i32} -// CHECK: dxsa.instruction "ld_structured_s" %[[OPERAND_97]], %[[OPERAND_98]], %[[OPERAND_99]], %[[OPERAND_100]], %[[OPERAND_101]] -// CHECK: %[[INDEX_80:.*]] = dxsa.index.imm {imm = 8 : i32} -// CHECK: %[[OPERAND_102:.*]] = dxsa.operand %[[INDEX_80]] {mask = 32 : i32, num_components = 4 : i32, type = 0 : i32} -// CHECK: %[[INDEX_81:.*]] = dxsa.index.imm {imm = 19 : i32} -// CHECK: %[[OPERAND_103:.*]] = dxsa.operand %[[INDEX_81]] {num_components = 4 : i32, one = 0 : i32, type = 0 : i32} -// CHECK: dxsa.instruction "check_access_fully_mapped" %[[OPERAND_102]], %[[OPERAND_103]] +// CHECK: dxsa.ld_structured_s r<18>, r<8, >, l(0x20), t<0, vector>, r<19, > +// CHECK: dxsa.ld_structured_s r<20, >, r<8, >, l(0x30), t<0, vector, >, r<21, > +// CHECK: %[[INDEX_7:.*]] = dxsa.index.imm {imm = 8 : i32} +// CHECK: %[[OPERAND_8:.*]] = dxsa.operand %[[INDEX_7]] {mask = 32 : i32, num_components = 4 : i32, type = 0 : i32} +// CHECK: %[[INDEX_8:.*]] = dxsa.index.imm {imm = 19 : i32} +// CHECK: %[[OPERAND_9:.*]] = dxsa.operand %[[INDEX_8]] {num_components = 4 : i32, one = 0 : i32, type = 0 : i32} +// CHECK: dxsa.instruction "check_access_fully_mapped" %[[OPERAND_8]], %[[OPERAND_9]] // CHECK: dxsa.and r<7, >, r<7, >, r<8, > -// CHECK: %[[INDEX_82:.*]] = dxsa.index.imm {imm = 8 : i32} -// CHECK: %[[OPERAND_104:.*]] = dxsa.operand %[[INDEX_82]] {mask = 32 : i32, num_components = 4 : i32, type = 0 : i32} -// CHECK: %[[INDEX_83:.*]] = dxsa.index.imm {imm = 21 : i32} -// CHECK: %[[OPERAND_105:.*]] = dxsa.operand %[[INDEX_83]] {num_components = 4 : i32, one = 0 : i32, type = 0 : i32} -// CHECK: dxsa.instruction "check_access_fully_mapped" %[[OPERAND_104]], %[[OPERAND_105]] +// CHECK: %[[INDEX_9:.*]] = dxsa.index.imm {imm = 8 : i32} +// CHECK: %[[OPERAND_10:.*]] = dxsa.operand %[[INDEX_9]] {mask = 32 : i32, num_components = 4 : i32, type = 0 : i32} +// CHECK: %[[INDEX_10:.*]] = dxsa.index.imm {imm = 21 : i32} +// CHECK: %[[OPERAND_11:.*]] = dxsa.operand %[[INDEX_10]] {num_components = 4 : i32, one = 0 : i32, type = 0 : i32} +// CHECK: dxsa.instruction "check_access_fully_mapped" %[[OPERAND_10]], %[[OPERAND_11]] // CHECK: dxsa.and r<7, >, r<7, >, r<8, > // CHECK: dxsa.utof r<7, >, r<7, > // CHECK: dxsa.add r<8, >, r<7, >, r<14, > @@ -293,141 +126,93 @@ // CHECK: dxsa.add r<3, >, r<0, >, r<14, > // CHECK: dxsa.mov r<3, >, r<14, > // CHECK: dxsa.add r<3, >, r<5, >, r<3, > -// CHECK: %[[INDEX_84:.*]] = dxsa.index.imm {imm = 0 : i32} -// CHECK: %[[OPERAND_106:.*]] = dxsa.operand %[[INDEX_84]] {mask = 16 : i32, num_components = 4 : i32, type = 0 : i32} -// CHECK: %[[INDEX_85:.*]] = dxsa.index.imm {imm = 0 : i32} -// CHECK: %[[OPERAND_107:.*]] = dxsa.operand %[[INDEX_85]] {num_components = 4 : i32, one = 0 : i32, type = 0 : i32} -// CHECK: dxsa.instruction "check_access_fully_mapped" %[[OPERAND_106]], %[[OPERAND_107]] -// CHECK: %[[OPERAND_108:.*]] = dxsa.operand {num_components = 0 : i32, type = 13 : i32} -// CHECK: %[[INDEX_86:.*]] = dxsa.index.imm {imm = 2 : i32} -// CHECK: %[[OPERAND_109:.*]] = dxsa.operand %[[INDEX_86]] {mask = 16 : i32, num_components = 4 : i32, type = 0 : i32} -// CHECK: %[[INDEX_87:.*]] = dxsa.index.imm {imm = 0 : i32} -// CHECK: %[[OPERAND_110:.*]] = dxsa.operand %[[INDEX_87]] {num_components = 4 : i32, one = 1 : i32, type = 0 : i32} -// CHECK: %[[OPERAND_111:.*]] = dxsa.operand.imm {imm = dense<16> : vector<1xi32>} -// CHECK: %[[INDEX_88:.*]] = dxsa.index.imm {imm = 1 : i32} -// CHECK: %[[OPERAND_112:.*]] = dxsa.operand %[[INDEX_88]] {num_components = 4 : i32, swizzle = dense<[0, 1, 2, 3]> : vector<4xi32>, type = 30 : i32} -// CHECK: dxsa.instruction "ld_structured_s" %[[OPERAND_108]], %[[OPERAND_109]], %[[OPERAND_110]], %[[OPERAND_111]], %[[OPERAND_112]] -// CHECK: %[[INDEX_89:.*]] = dxsa.index.imm {imm = 0 : i32} -// CHECK: %[[OPERAND_113:.*]] = dxsa.operand %[[INDEX_89]] {mask = 64 : i32, num_components = 4 : i32, type = 0 : i32} -// CHECK: %[[INDEX_90:.*]] = dxsa.index.imm {imm = 2 : i32} -// CHECK: %[[OPERAND_114:.*]] = dxsa.operand %[[INDEX_90]] {num_components = 4 : i32, one = 0 : i32, type = 0 : i32} -// CHECK: dxsa.instruction "check_access_fully_mapped" %[[OPERAND_113]], %[[OPERAND_114]] +// CHECK: %[[INDEX_11:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_12:.*]] = dxsa.operand %[[INDEX_11]] {mask = 16 : i32, num_components = 4 : i32, type = 0 : i32} +// CHECK: %[[INDEX_12:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_13:.*]] = dxsa.operand %[[INDEX_12]] {num_components = 4 : i32, one = 0 : i32, type = 0 : i32} +// CHECK: dxsa.instruction "check_access_fully_mapped" %[[OPERAND_12]], %[[OPERAND_13]] +// CHECK: dxsa.ld_structured_s null, r<0, >, l(0x10), u<1, vector>, r<2, > +// CHECK: %[[INDEX_13:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_14:.*]] = dxsa.operand %[[INDEX_13]] {mask = 64 : i32, num_components = 4 : i32, type = 0 : i32} +// CHECK: %[[INDEX_14:.*]] = dxsa.index.imm {imm = 2 : i32} +// CHECK: %[[OPERAND_15:.*]] = dxsa.operand %[[INDEX_14]] {num_components = 4 : i32, one = 0 : i32, type = 0 : i32} +// CHECK: dxsa.instruction "check_access_fully_mapped" %[[OPERAND_14]], %[[OPERAND_15]] // CHECK: dxsa.and r<0, >, r<0, >, r<0, > -// CHECK: %[[OPERAND_115:.*]] = dxsa.operand {num_components = 0 : i32, type = 13 : i32} -// CHECK: %[[INDEX_91:.*]] = dxsa.index.imm {imm = 2 : i32} -// CHECK: %[[OPERAND_116:.*]] = dxsa.operand %[[INDEX_91]] {mask = 16 : i32, num_components = 4 : i32, type = 0 : i32} -// CHECK: %[[INDEX_92:.*]] = dxsa.index.imm {imm = 0 : i32} -// CHECK: %[[OPERAND_117:.*]] = dxsa.operand %[[INDEX_92]] {num_components = 4 : i32, one = 1 : i32, type = 0 : i32} -// CHECK: %[[OPERAND_118:.*]] = dxsa.operand.imm {imm = dense<32> : vector<1xi32>} -// CHECK: %[[INDEX_93:.*]] = dxsa.index.imm {imm = 1 : i32} -// CHECK: %[[OPERAND_119:.*]] = dxsa.operand %[[INDEX_93]] {num_components = 4 : i32, swizzle = dense<[0, 1, 2, 3]> : vector<4xi32>, type = 30 : i32} -// CHECK: dxsa.instruction "ld_structured_s" %[[OPERAND_115]], %[[OPERAND_116]], %[[OPERAND_117]], %[[OPERAND_118]], %[[OPERAND_119]] -// CHECK: %[[OPERAND_120:.*]] = dxsa.operand {num_components = 0 : i32, type = 13 : i32} -// CHECK: %[[INDEX_94:.*]] = dxsa.index.imm {imm = 4 : i32} -// CHECK: %[[OPERAND_121:.*]] = dxsa.operand %[[INDEX_94]] {mask = 16 : i32, num_components = 4 : i32, type = 0 : i32} -// CHECK: %[[INDEX_95:.*]] = dxsa.index.imm {imm = 0 : i32} -// CHECK: %[[OPERAND_122:.*]] = dxsa.operand %[[INDEX_95]] {num_components = 4 : i32, one = 1 : i32, type = 0 : i32} -// CHECK: %[[OPERAND_123:.*]] = dxsa.operand.imm {imm = dense<48> : vector<1xi32>} -// CHECK: %[[INDEX_96:.*]] = dxsa.index.imm {imm = 1 : i32} -// CHECK: %[[OPERAND_124:.*]] = dxsa.operand %[[INDEX_96]] {num_components = 4 : i32, swizzle = dense<0> : vector<4xi32>, type = 30 : i32} -// CHECK: dxsa.instruction "ld_structured_s" %[[OPERAND_120]], %[[OPERAND_121]], %[[OPERAND_122]], %[[OPERAND_123]], %[[OPERAND_124]] -// CHECK: %[[INDEX_97:.*]] = dxsa.index.imm {imm = 0 : i32} -// CHECK: %[[OPERAND_125:.*]] = dxsa.operand %[[INDEX_97]] {mask = 64 : i32, num_components = 4 : i32, type = 0 : i32} -// CHECK: %[[INDEX_98:.*]] = dxsa.index.imm {imm = 4 : i32} -// CHECK: %[[OPERAND_126:.*]] = dxsa.operand %[[INDEX_98]] {num_components = 4 : i32, one = 0 : i32, type = 0 : i32} -// CHECK: dxsa.instruction "check_access_fully_mapped" %[[OPERAND_125]], %[[OPERAND_126]] -// CHECK: %[[INDEX_99:.*]] = dxsa.index.imm {imm = 0 : i32} -// CHECK: %[[OPERAND_127:.*]] = dxsa.operand %[[INDEX_99]] {mask = 128 : i32, num_components = 4 : i32, type = 0 : i32} -// CHECK: %[[INDEX_100:.*]] = dxsa.index.imm {imm = 2 : i32} -// CHECK: %[[OPERAND_128:.*]] = dxsa.operand %[[INDEX_100]] {num_components = 4 : i32, one = 0 : i32, type = 0 : i32} -// CHECK: dxsa.instruction "check_access_fully_mapped" %[[OPERAND_127]], %[[OPERAND_128]] +// CHECK: dxsa.ld_structured_s null, r<0, >, l(0x20), u<1, vector>, r<2, > +// CHECK: dxsa.ld_structured_s null, r<0, >, l(0x30), u<1, vector, >, r<4, > +// CHECK: %[[INDEX_15:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_16:.*]] = dxsa.operand %[[INDEX_15]] {mask = 64 : i32, num_components = 4 : i32, type = 0 : i32} +// CHECK: %[[INDEX_16:.*]] = dxsa.index.imm {imm = 4 : i32} +// CHECK: %[[OPERAND_17:.*]] = dxsa.operand %[[INDEX_16]] {num_components = 4 : i32, one = 0 : i32, type = 0 : i32} +// CHECK: dxsa.instruction "check_access_fully_mapped" %[[OPERAND_16]], %[[OPERAND_17]] +// CHECK: %[[INDEX_17:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_18:.*]] = dxsa.operand %[[INDEX_17]] {mask = 128 : i32, num_components = 4 : i32, type = 0 : i32} +// CHECK: %[[INDEX_18:.*]] = dxsa.index.imm {imm = 2 : i32} +// CHECK: %[[OPERAND_19:.*]] = dxsa.operand %[[INDEX_18]] {num_components = 4 : i32, one = 0 : i32, type = 0 : i32} +// CHECK: dxsa.instruction "check_access_fully_mapped" %[[OPERAND_18]], %[[OPERAND_19]] // CHECK: dxsa.and r<0, >, r<0, >, r<0, > // CHECK: dxsa.and r<0, >, r<0, >, r<0, > // CHECK: dxsa.utof r<0, >, r<0, > // CHECK: dxsa.add r<3>, r<0, >, r<3> // CHECK: dxsa.mov r<4, >, r<4, > -// CHECK: %[[INDEX_101:.*]] = dxsa.index.imm {imm = 0 : i32} -// CHECK: %[[OPERAND_129:.*]] = dxsa.operand %[[INDEX_101]] {mask = 16 : i32, num_components = 4 : i32, type = 0 : i32} -// CHECK: %[[INDEX_102:.*]] = dxsa.index.imm {imm = 6 : i32} -// CHECK: %[[OPERAND_130:.*]] = dxsa.operand %[[INDEX_102]] {num_components = 4 : i32, one = 0 : i32, type = 0 : i32} -// CHECK: dxsa.instruction "check_access_fully_mapped" %[[OPERAND_129]], %[[OPERAND_130]] +// CHECK: %[[INDEX_19:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_20:.*]] = dxsa.operand %[[INDEX_19]] {mask = 16 : i32, num_components = 4 : i32, type = 0 : i32} +// CHECK: %[[INDEX_20:.*]] = dxsa.index.imm {imm = 6 : i32} +// CHECK: %[[OPERAND_21:.*]] = dxsa.operand %[[INDEX_20]] {num_components = 4 : i32, one = 0 : i32, type = 0 : i32} +// CHECK: dxsa.instruction "check_access_fully_mapped" %[[OPERAND_20]], %[[OPERAND_21]] // CHECK: dxsa.mov r<4, >, r<7, > -// CHECK: %[[INDEX_103:.*]] = dxsa.index.imm {imm = 0 : i32} -// CHECK: %[[OPERAND_131:.*]] = dxsa.operand %[[INDEX_103]] {mask = 64 : i32, num_components = 4 : i32, type = 0 : i32} -// CHECK: %[[INDEX_104:.*]] = dxsa.index.imm {imm = 8 : i32} -// CHECK: %[[OPERAND_132:.*]] = dxsa.operand %[[INDEX_104]] {num_components = 4 : i32, one = 0 : i32, type = 0 : i32} -// CHECK: dxsa.instruction "check_access_fully_mapped" %[[OPERAND_131]], %[[OPERAND_132]] +// CHECK: %[[INDEX_21:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_22:.*]] = dxsa.operand %[[INDEX_21]] {mask = 64 : i32, num_components = 4 : i32, type = 0 : i32} +// CHECK: %[[INDEX_22:.*]] = dxsa.index.imm {imm = 8 : i32} +// CHECK: %[[OPERAND_23:.*]] = dxsa.operand %[[INDEX_22]] {num_components = 4 : i32, one = 0 : i32, type = 0 : i32} +// CHECK: dxsa.instruction "check_access_fully_mapped" %[[OPERAND_22]], %[[OPERAND_23]] // CHECK: dxsa.and r<0, >, r<0, >, r<0, > // CHECK: dxsa.add r<3, >, r<3, >, r<4, > -// CHECK: %[[OPERAND_133:.*]] = dxsa.operand {num_components = 0 : i32, type = 13 : i32} -// CHECK: %[[INDEX_105:.*]] = dxsa.index.imm {imm = 2 : i32} -// CHECK: %[[OPERAND_134:.*]] = dxsa.operand %[[INDEX_105]] {mask = 16 : i32, num_components = 4 : i32, type = 0 : i32} -// CHECK: %[[INDEX_106:.*]] = dxsa.index.imm {imm = 0 : i32} -// CHECK: %[[OPERAND_135:.*]] = dxsa.operand %[[INDEX_106]] {num_components = 4 : i32, one = 1 : i32, type = 0 : i32} -// CHECK: %[[OPERAND_136:.*]] = dxsa.operand.imm {imm = dense<32> : vector<1xi32>} -// CHECK: %[[INDEX_107:.*]] = dxsa.index.imm {imm = 1 : i32} -// CHECK: %[[OPERAND_137:.*]] = dxsa.operand %[[INDEX_107]] {num_components = 4 : i32, swizzle = dense<[0, 1, 2, 3]> : vector<4xi32>, type = 30 : i32} -// CHECK: dxsa.instruction "ld_structured_s" %[[OPERAND_133]], %[[OPERAND_134]], %[[OPERAND_135]], %[[OPERAND_136]], %[[OPERAND_137]] -// CHECK: %[[INDEX_108:.*]] = dxsa.index.imm {imm = 0 : i32} -// CHECK: %[[OPERAND_138:.*]] = dxsa.operand %[[INDEX_108]] {mask = 64 : i32, num_components = 4 : i32, type = 0 : i32} -// CHECK: %[[INDEX_109:.*]] = dxsa.index.imm {imm = 2 : i32} -// CHECK: %[[OPERAND_139:.*]] = dxsa.operand %[[INDEX_109]] {num_components = 4 : i32, one = 0 : i32, type = 0 : i32} -// CHECK: dxsa.instruction "check_access_fully_mapped" %[[OPERAND_138]], %[[OPERAND_139]] +// CHECK: dxsa.ld_structured_s null, r<0, >, l(0x20), u<1, vector>, r<2, > +// CHECK: %[[INDEX_23:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_24:.*]] = dxsa.operand %[[INDEX_23]] {mask = 64 : i32, num_components = 4 : i32, type = 0 : i32} +// CHECK: %[[INDEX_24:.*]] = dxsa.index.imm {imm = 2 : i32} +// CHECK: %[[OPERAND_25:.*]] = dxsa.operand %[[INDEX_24]] {num_components = 4 : i32, one = 0 : i32, type = 0 : i32} +// CHECK: dxsa.instruction "check_access_fully_mapped" %[[OPERAND_24]], %[[OPERAND_25]] // CHECK: dxsa.and r<0, >, r<0, >, r<0, > -// CHECK: %[[OPERAND_140:.*]] = dxsa.operand {num_components = 0 : i32, type = 13 : i32} -// CHECK: %[[INDEX_110:.*]] = dxsa.index.imm {imm = 2 : i32} -// CHECK: %[[OPERAND_141:.*]] = dxsa.operand %[[INDEX_110]] {mask = 16 : i32, num_components = 4 : i32, type = 0 : i32} -// CHECK: %[[INDEX_111:.*]] = dxsa.index.imm {imm = 0 : i32} -// CHECK: %[[OPERAND_142:.*]] = dxsa.operand %[[INDEX_111]] {num_components = 4 : i32, one = 1 : i32, type = 0 : i32} -// CHECK: %[[OPERAND_143:.*]] = dxsa.operand.imm {imm = dense<48> : vector<1xi32>} -// CHECK: %[[INDEX_112:.*]] = dxsa.index.imm {imm = 1 : i32} -// CHECK: %[[OPERAND_144:.*]] = dxsa.operand %[[INDEX_112]] {num_components = 4 : i32, swizzle = dense<0> : vector<4xi32>, type = 30 : i32} -// CHECK: dxsa.instruction "ld_structured_s" %[[OPERAND_140]], %[[OPERAND_141]], %[[OPERAND_142]], %[[OPERAND_143]], %[[OPERAND_144]] -// CHECK: %[[OPERAND_145:.*]] = dxsa.operand {num_components = 0 : i32, type = 13 : i32} -// CHECK: %[[INDEX_113:.*]] = dxsa.index.imm {imm = 4 : i32} -// CHECK: %[[OPERAND_146:.*]] = dxsa.operand %[[INDEX_113]] {mask = 16 : i32, num_components = 4 : i32, type = 0 : i32} -// CHECK: %[[INDEX_114:.*]] = dxsa.index.imm {imm = 0 : i32} -// CHECK: %[[OPERAND_147:.*]] = dxsa.operand %[[INDEX_114]] {num_components = 4 : i32, one = 1 : i32, type = 0 : i32} -// CHECK: %[[OPERAND_148:.*]] = dxsa.operand.imm {imm = dense<0> : vector<1xi32>} -// CHECK: %[[INDEX_115:.*]] = dxsa.index.imm {imm = 1 : i32} -// CHECK: %[[OPERAND_149:.*]] = dxsa.operand %[[INDEX_115]] {num_components = 4 : i32, swizzle = dense<[0, 1, 2, 3]> : vector<4xi32>, type = 30 : i32} -// CHECK: dxsa.instruction "ld_structured_s" %[[OPERAND_145]], %[[OPERAND_146]], %[[OPERAND_147]], %[[OPERAND_148]], %[[OPERAND_149]] -// CHECK: %[[INDEX_116:.*]] = dxsa.index.imm {imm = 0 : i32} -// CHECK: %[[OPERAND_150:.*]] = dxsa.operand %[[INDEX_116]] {mask = 32 : i32, num_components = 4 : i32, type = 0 : i32} -// CHECK: %[[INDEX_117:.*]] = dxsa.index.imm {imm = 4 : i32} -// CHECK: %[[OPERAND_151:.*]] = dxsa.operand %[[INDEX_117]] {num_components = 4 : i32, one = 0 : i32, type = 0 : i32} -// CHECK: dxsa.instruction "check_access_fully_mapped" %[[OPERAND_150]], %[[OPERAND_151]] -// CHECK: %[[INDEX_118:.*]] = dxsa.index.imm {imm = 0 : i32} -// CHECK: %[[OPERAND_152:.*]] = dxsa.operand %[[INDEX_118]] {mask = 64 : i32, num_components = 4 : i32, type = 0 : i32} -// CHECK: %[[INDEX_119:.*]] = dxsa.index.imm {imm = 2 : i32} -// CHECK: %[[OPERAND_153:.*]] = dxsa.operand %[[INDEX_119]] {num_components = 4 : i32, one = 0 : i32, type = 0 : i32} -// CHECK: dxsa.instruction "check_access_fully_mapped" %[[OPERAND_152]], %[[OPERAND_153]] +// CHECK: dxsa.ld_structured_s null, r<0, >, l(0x30), u<1, vector, >, r<2, > +// CHECK: dxsa.ld_structured_s null, r<0, >, l(0x0), u<1, vector>, r<4, > +// CHECK: %[[INDEX_25:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_26:.*]] = dxsa.operand %[[INDEX_25]] {mask = 32 : i32, num_components = 4 : i32, type = 0 : i32} +// CHECK: %[[INDEX_26:.*]] = dxsa.index.imm {imm = 4 : i32} +// CHECK: %[[OPERAND_27:.*]] = dxsa.operand %[[INDEX_26]] {num_components = 4 : i32, one = 0 : i32, type = 0 : i32} +// CHECK: dxsa.instruction "check_access_fully_mapped" %[[OPERAND_26]], %[[OPERAND_27]] +// CHECK: %[[INDEX_27:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_28:.*]] = dxsa.operand %[[INDEX_27]] {mask = 64 : i32, num_components = 4 : i32, type = 0 : i32} +// CHECK: %[[INDEX_28:.*]] = dxsa.index.imm {imm = 2 : i32} +// CHECK: %[[OPERAND_29:.*]] = dxsa.operand %[[INDEX_28]] {num_components = 4 : i32, one = 0 : i32, type = 0 : i32} +// CHECK: dxsa.instruction "check_access_fully_mapped" %[[OPERAND_28]], %[[OPERAND_29]] // CHECK: dxsa.and r<0, >, r<0, >, r<0, > // CHECK: dxsa.utof r<0, >, r<0, > // CHECK: dxsa.add r<3>, r<0, >, r<3> -// CHECK: %[[INDEX_120:.*]] = dxsa.index.imm {imm = 0 : i32} -// CHECK: %[[OPERAND_154:.*]] = dxsa.operand %[[INDEX_120]] {mask = 16 : i32, num_components = 4 : i32, type = 0 : i32} -// CHECK: %[[INDEX_121:.*]] = dxsa.index.imm {imm = 9 : i32} -// CHECK: %[[OPERAND_155:.*]] = dxsa.operand %[[INDEX_121]] {num_components = 4 : i32, one = 0 : i32, type = 0 : i32} -// CHECK: dxsa.instruction "check_access_fully_mapped" %[[OPERAND_154]], %[[OPERAND_155]] +// CHECK: %[[INDEX_29:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_30:.*]] = dxsa.operand %[[INDEX_29]] {mask = 16 : i32, num_components = 4 : i32, type = 0 : i32} +// CHECK: %[[INDEX_30:.*]] = dxsa.index.imm {imm = 9 : i32} +// CHECK: %[[OPERAND_31:.*]] = dxsa.operand %[[INDEX_30]] {num_components = 4 : i32, one = 0 : i32, type = 0 : i32} +// CHECK: dxsa.instruction "check_access_fully_mapped" %[[OPERAND_30]], %[[OPERAND_31]] // CHECK: dxsa.and r<0, >, r<0, >, r<0, > // CHECK: dxsa.mov r<6, >, r<10, > // CHECK: dxsa.and r<0, >, r<5, >, r<6, > // CHECK: dxsa.or r<0, >, r<1, >, r<0, > // CHECK: dxsa.or r<0, >, r<0, >, r<2, > // CHECK: dxsa.mov r<12, >, r<10, > -// CHECK: %[[INDEX_122:.*]] = dxsa.index.imm {imm = 0 : i32} -// CHECK: %[[OPERAND_156:.*]] = dxsa.operand %[[INDEX_122]] {mask = 128 : i32, num_components = 4 : i32, type = 0 : i32} -// CHECK: %[[INDEX_123:.*]] = dxsa.index.imm {imm = 11 : i32} -// CHECK: %[[OPERAND_157:.*]] = dxsa.operand %[[INDEX_123]] {num_components = 4 : i32, one = 0 : i32, type = 0 : i32} -// CHECK: dxsa.instruction "check_access_fully_mapped" %[[OPERAND_156]], %[[OPERAND_157]] +// CHECK: %[[INDEX_31:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_32:.*]] = dxsa.operand %[[INDEX_31]] {mask = 128 : i32, num_components = 4 : i32, type = 0 : i32} +// CHECK: %[[INDEX_32:.*]] = dxsa.index.imm {imm = 11 : i32} +// CHECK: %[[OPERAND_33:.*]] = dxsa.operand %[[INDEX_32]] {num_components = 4 : i32, one = 0 : i32, type = 0 : i32} +// CHECK: dxsa.instruction "check_access_fully_mapped" %[[OPERAND_32]], %[[OPERAND_33]] // CHECK: dxsa.and r<0, >, r<0, >, r<0, > // CHECK: dxsa.and r<1, >, r<7, >, r<12, > -// CHECK: %[[INDEX_124:.*]] = dxsa.index.imm {imm = 0 : i32} -// CHECK: %[[OPERAND_158:.*]] = dxsa.operand %[[INDEX_124]] {mask = 128 : i32, num_components = 4 : i32, type = 0 : i32} -// CHECK: %[[INDEX_125:.*]] = dxsa.index.imm {imm = 13 : i32} -// CHECK: %[[OPERAND_159:.*]] = dxsa.operand %[[INDEX_125]] {num_components = 4 : i32, one = 0 : i32, type = 0 : i32} -// CHECK: dxsa.instruction "check_access_fully_mapped" %[[OPERAND_158]], %[[OPERAND_159]] +// CHECK: %[[INDEX_33:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_34:.*]] = dxsa.operand %[[INDEX_33]] {mask = 128 : i32, num_components = 4 : i32, type = 0 : i32} +// CHECK: %[[INDEX_34:.*]] = dxsa.index.imm {imm = 13 : i32} +// CHECK: %[[OPERAND_35:.*]] = dxsa.operand %[[INDEX_34]] {num_components = 4 : i32, one = 0 : i32, type = 0 : i32} +// CHECK: dxsa.instruction "check_access_fully_mapped" %[[OPERAND_34]], %[[OPERAND_35]] // CHECK: dxsa.and r<0, >, r<0, >, r<0, > // CHECK: dxsa.utof r<0, >, r<0, > // CHECK: dxsa.or r<0, >, r<0, >, r<1, > @@ -436,32 +221,32 @@ // CHECK: dxsa.add r<0>, r<0, >, r<3> // CHECK: dxsa.mul r<1, >, v<0, >, l(0x40400000) // CHECK: dxsa.ftou r<1, >, r<1, > -// CHECK: %[[INDEX_126:.*]] = dxsa.index.imm {imm = 1 : i32} -// CHECK: %[[OPERAND_160:.*]] = dxsa.operand %[[INDEX_126]] {mask = 48 : i32, num_components = 4 : i32, type = 30 : i32} -// CHECK: %[[INDEX_127:.*]] = dxsa.index.imm {imm = 1 : i32} -// CHECK: %[[OPERAND_161:.*]] = dxsa.operand %[[INDEX_127]] {num_components = 4 : i32, one = 0 : i32, type = 0 : i32} -// CHECK: %[[OPERAND_162:.*]] = dxsa.operand.imm {imm = dense<0> : vector<1xi32>} -// CHECK: %[[INDEX_128:.*]] = dxsa.index.imm {imm = 0 : i32} -// CHECK: %[[OPERAND_163:.*]] = dxsa.operand %[[INDEX_128]] {num_components = 4 : i32, swizzle = dense<[0, 1, 0, 0]> : vector<4xi32>, type = 0 : i32} -// CHECK: dxsa.instruction "store_structured" %[[OPERAND_160]], %[[OPERAND_161]], %[[OPERAND_162]], %[[OPERAND_163]] -// CHECK: %[[INDEX_129:.*]] = dxsa.index.imm {imm = 1 : i32} -// CHECK: %[[OPERAND_164:.*]] = dxsa.operand %[[INDEX_129]] {mask = 112 : i32, num_components = 4 : i32, type = 30 : i32} -// CHECK: %[[INDEX_130:.*]] = dxsa.index.imm {imm = 1 : i32} -// CHECK: %[[OPERAND_165:.*]] = dxsa.operand %[[INDEX_130]] {num_components = 4 : i32, one = 0 : i32, type = 0 : i32} -// CHECK: %[[OPERAND_166:.*]] = dxsa.operand.imm {imm = dense<8> : vector<1xi32>} -// CHECK: %[[INDEX_131:.*]] = dxsa.index.imm {imm = 0 : i32} -// CHECK: %[[OPERAND_167:.*]] = dxsa.operand %[[INDEX_131]] {num_components = 4 : i32, swizzle = dense<[0, 1, 2, 0]> : vector<4xi32>, type = 0 : i32} -// CHECK: dxsa.instruction "store_structured" %[[OPERAND_164]], %[[OPERAND_165]], %[[OPERAND_166]], %[[OPERAND_167]] +// CHECK: %[[INDEX_35:.*]] = dxsa.index.imm {imm = 1 : i32} +// CHECK: %[[OPERAND_36:.*]] = dxsa.operand %[[INDEX_35]] {mask = 48 : i32, num_components = 4 : i32, type = 30 : i32} +// CHECK: %[[INDEX_36:.*]] = dxsa.index.imm {imm = 1 : i32} +// CHECK: %[[OPERAND_37:.*]] = dxsa.operand %[[INDEX_36]] {num_components = 4 : i32, one = 0 : i32, type = 0 : i32} +// CHECK: %[[OPERAND_38:.*]] = dxsa.operand.imm {imm = dense<0> : vector<1xi32>} +// CHECK: %[[INDEX_37:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_39:.*]] = dxsa.operand %[[INDEX_37]] {num_components = 4 : i32, swizzle = dense<[0, 1, 0, 0]> : vector<4xi32>, type = 0 : i32} +// CHECK: dxsa.instruction "store_structured" %[[OPERAND_36]], %[[OPERAND_37]], %[[OPERAND_38]], %[[OPERAND_39]] +// CHECK: %[[INDEX_38:.*]] = dxsa.index.imm {imm = 1 : i32} +// CHECK: %[[OPERAND_40:.*]] = dxsa.operand %[[INDEX_38]] {mask = 112 : i32, num_components = 4 : i32, type = 30 : i32} +// CHECK: %[[INDEX_39:.*]] = dxsa.index.imm {imm = 1 : i32} +// CHECK: %[[OPERAND_41:.*]] = dxsa.operand %[[INDEX_39]] {num_components = 4 : i32, one = 0 : i32, type = 0 : i32} +// CHECK: %[[OPERAND_42:.*]] = dxsa.operand.imm {imm = dense<8> : vector<1xi32>} +// CHECK: %[[INDEX_40:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_43:.*]] = dxsa.operand %[[INDEX_40]] {num_components = 4 : i32, swizzle = dense<[0, 1, 2, 0]> : vector<4xi32>, type = 0 : i32} +// CHECK: dxsa.instruction "store_structured" %[[OPERAND_40]], %[[OPERAND_41]], %[[OPERAND_42]], %[[OPERAND_43]] // CHECK: dxsa.ftoi r<1, >, r<0, > // CHECK: dxsa.mov o<0>, r<0> -// CHECK: %[[INDEX_132:.*]] = dxsa.index.imm {imm = 1 : i32} -// CHECK: %[[OPERAND_168:.*]] = dxsa.operand %[[INDEX_132]] {mask = 48 : i32, num_components = 4 : i32, type = 30 : i32} -// CHECK: %[[INDEX_133:.*]] = dxsa.index.imm {imm = 1 : i32} -// CHECK: %[[OPERAND_169:.*]] = dxsa.operand %[[INDEX_133]] {num_components = 4 : i32, one = 0 : i32, type = 0 : i32} -// CHECK: %[[INDEX_134:.*]] = dxsa.index.imm {imm = 1 : i32} -// CHECK: %[[OPERAND_170:.*]] = dxsa.operand %[[INDEX_134]] {num_components = 4 : i32, one = 3 : i32, type = 0 : i32} -// CHECK: %[[INDEX_135:.*]] = dxsa.index.imm {imm = 1 : i32} -// CHECK: %[[OPERAND_171:.*]] = dxsa.operand %[[INDEX_135]] {num_components = 4 : i32, swizzle = dense<[1, 2, 1, 1]> : vector<4xi32>, type = 0 : i32} -// CHECK: dxsa.instruction "store_structured" %[[OPERAND_168]], %[[OPERAND_169]], %[[OPERAND_170]], %[[OPERAND_171]] +// CHECK: %[[INDEX_41:.*]] = dxsa.index.imm {imm = 1 : i32} +// CHECK: %[[OPERAND_44:.*]] = dxsa.operand %[[INDEX_41]] {mask = 48 : i32, num_components = 4 : i32, type = 30 : i32} +// CHECK: %[[INDEX_42:.*]] = dxsa.index.imm {imm = 1 : i32} +// CHECK: %[[OPERAND_45:.*]] = dxsa.operand %[[INDEX_42]] {num_components = 4 : i32, one = 0 : i32, type = 0 : i32} +// CHECK: %[[INDEX_43:.*]] = dxsa.index.imm {imm = 1 : i32} +// CHECK: %[[OPERAND_46:.*]] = dxsa.operand %[[INDEX_43]] {num_components = 4 : i32, one = 3 : i32, type = 0 : i32} +// CHECK: %[[INDEX_44:.*]] = dxsa.index.imm {imm = 1 : i32} +// CHECK: %[[OPERAND_47:.*]] = dxsa.operand %[[INDEX_44]] {num_components = 4 : i32, swizzle = dense<[1, 2, 1, 1]> : vector<4xi32>, type = 0 : i32} +// CHECK: dxsa.instruction "store_structured" %[[OPERAND_44]], %[[OPERAND_45]], %[[OPERAND_46]], %[[OPERAND_47]] // CHECK: dxsa.ret diff --git a/mlir/test/Target/DXSA/hlsl/uav_raw1.test b/mlir/test/Target/DXSA/hlsl/uav_raw1.test index 77bd5ef9095c..cc45e516e06d 100644 --- a/mlir/test/Target/DXSA/hlsl/uav_raw1.test +++ b/mlir/test/Target/DXSA/hlsl/uav_raw1.test @@ -8,37 +8,24 @@ // CHECK: dxsa.dcl_input_ps constant v<0, > // CHECK: dxsa.dcl_output o<0> // CHECK: dxsa.dcl_temps 2 -// CHECK: %[[INDEX_0:.*]] = dxsa.index.imm {imm = 0 : i32} -// CHECK: %[[OPERAND_0:.*]] = dxsa.operand %[[INDEX_0]] {mask = 16 : i32, num_components = 4 : i32, type = 0 : i32} -// CHECK: %[[INDEX_1:.*]] = dxsa.index.imm {imm = 0 : i32} -// CHECK: %[[OPERAND_1:.*]] = dxsa.operand %[[INDEX_1]] {num_components = 4 : i32, one = 0 : i32, type = 1 : i32} -// CHECK: %[[INDEX_2:.*]] = dxsa.index.imm {imm = 3 : i32} -// CHECK: %[[OPERAND_2:.*]] = dxsa.operand %[[INDEX_2]] {num_components = 4 : i32, swizzle = dense<0> : vector<4xi32>, type = 30 : i32} -// CHECK: dxsa.instruction "ld_raw" %[[OPERAND_0]], %[[OPERAND_1]], %[[OPERAND_2]] +// CHECK: dxsa.ld_raw r<0, >, v<0, >, u<3, vector, > // CHECK: dxsa.utof r<0, >, r<0, > -// CHECK: %[[OPERAND_3:.*]] = dxsa.operand {num_components = 0 : i32, type = 13 : i32} -// CHECK: %[[INDEX_3:.*]] = dxsa.index.imm {imm = 1 : i32} -// CHECK: %[[OPERAND_4:.*]] = dxsa.operand %[[INDEX_3]] {mask = 16 : i32, num_components = 4 : i32, type = 0 : i32} -// CHECK: %[[INDEX_4:.*]] = dxsa.index.imm {imm = 0 : i32} -// CHECK: %[[OPERAND_5:.*]] = dxsa.operand %[[INDEX_4]] {num_components = 4 : i32, one = 0 : i32, type = 1 : i32} -// CHECK: %[[INDEX_5:.*]] = dxsa.index.imm {imm = 3 : i32} -// CHECK: %[[OPERAND_6:.*]] = dxsa.operand %[[INDEX_5]] {num_components = 4 : i32, swizzle = dense<0> : vector<4xi32>, type = 30 : i32} -// CHECK: dxsa.instruction "ld_raw_s" %[[OPERAND_3]], %[[OPERAND_4]], %[[OPERAND_5]], %[[OPERAND_6]] -// CHECK: %[[INDEX_6:.*]] = dxsa.index.imm {imm = 0 : i32} -// CHECK: %[[OPERAND_7:.*]] = dxsa.operand %[[INDEX_6]] {mask = 32 : i32, num_components = 4 : i32, type = 0 : i32} -// CHECK: %[[INDEX_7:.*]] = dxsa.index.imm {imm = 1 : i32} -// CHECK: %[[OPERAND_8:.*]] = dxsa.operand %[[INDEX_7]] {num_components = 4 : i32, one = 0 : i32, type = 0 : i32} -// CHECK: dxsa.instruction "check_access_fully_mapped" %[[OPERAND_7]], %[[OPERAND_8]] +// CHECK: dxsa.ld_raw_s null, v<0, >, u<3, vector, >, r<1, > +// CHECK: %[[INDEX_0:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_0:.*]] = dxsa.operand %[[INDEX_0]] {mask = 32 : i32, num_components = 4 : i32, type = 0 : i32} +// CHECK: %[[INDEX_1:.*]] = dxsa.index.imm {imm = 1 : i32} +// CHECK: %[[OPERAND_1:.*]] = dxsa.operand %[[INDEX_1]] {num_components = 4 : i32, one = 0 : i32, type = 0 : i32} +// CHECK: dxsa.instruction "check_access_fully_mapped" %[[OPERAND_0]], %[[OPERAND_1]] // CHECK: dxsa.utof r<0, >, r<0, > // CHECK: dxsa.mad r<0>, r<0, >, l(0x40000000, 0x40000000, 0x40000000, 0x40000000), r<0, > // CHECK: dxsa.ftou r<1, >, r<0, > // CHECK: dxsa.mov o<0>, r<0> -// CHECK: %[[INDEX_8:.*]] = dxsa.index.imm {imm = 3 : i32} -// CHECK: %[[OPERAND_9:.*]] = dxsa.operand %[[INDEX_8]] {mask = 240 : i32, num_components = 4 : i32, type = 30 : i32} -// CHECK: %[[INDEX_9:.*]] = dxsa.index.imm {imm = 0 : i32} -// CHECK: %[[OPERAND_10:.*]] = dxsa.operand %[[INDEX_9]] {num_components = 4 : i32, one = 1 : i32, type = 1 : i32} -// CHECK: %[[INDEX_10:.*]] = dxsa.index.imm {imm = 1 : i32} -// CHECK: %[[OPERAND_11:.*]] = dxsa.operand %[[INDEX_10]] {num_components = 4 : i32, swizzle = dense<0> : vector<4xi32>, type = 0 : i32} -// CHECK: dxsa.instruction "store_raw" %[[OPERAND_9]], %[[OPERAND_10]], %[[OPERAND_11]] +// CHECK: %[[INDEX_2:.*]] = dxsa.index.imm {imm = 3 : i32} +// CHECK: %[[OPERAND_2:.*]] = dxsa.operand %[[INDEX_2]] {mask = 240 : i32, num_components = 4 : i32, type = 30 : i32} +// CHECK: %[[INDEX_3:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_3:.*]] = dxsa.operand %[[INDEX_3]] {num_components = 4 : i32, one = 1 : i32, type = 1 : i32} +// CHECK: %[[INDEX_4:.*]] = dxsa.index.imm {imm = 1 : i32} +// CHECK: %[[OPERAND_4:.*]] = dxsa.operand %[[INDEX_4]] {num_components = 4 : i32, swizzle = dense<0> : vector<4xi32>, type = 0 : i32} +// CHECK: dxsa.instruction "store_raw" %[[OPERAND_2]], %[[OPERAND_3]], %[[OPERAND_4]] // CHECK: dxsa.ret diff --git a/mlir/test/Target/DXSA/hlsl/uav_typed_load_store1.test b/mlir/test/Target/DXSA/hlsl/uav_typed_load_store1.test index 56050a610391..37ad4e1dd9c9 100644 --- a/mlir/test/Target/DXSA/hlsl/uav_typed_load_store1.test +++ b/mlir/test/Target/DXSA/hlsl/uav_typed_load_store1.test @@ -8,43 +8,24 @@ // CHECK: dxsa.dcl_input_ps constant v<0, > // CHECK: dxsa.dcl_output o<0> // CHECK: dxsa.dcl_temps 2 -// CHECK: %[[INDEX_0:.*]] = dxsa.index.imm {imm = 0 : i32} -// CHECK: %[[OPERAND_0:.*]] = dxsa.operand %[[INDEX_0]] {mask = 240 : i32, num_components = 4 : i32, type = 0 : i32} -// CHECK: %[[INDEX_1:.*]] = dxsa.index.imm {imm = 0 : i32} -// CHECK: %[[OPERAND_1:.*]] = dxsa.operand %[[INDEX_1]] {num_components = 4 : i32, swizzle = dense<[2, 3, 3, 3]> : vector<4xi32>, type = 1 : i32} -// CHECK: %[[INDEX_2:.*]] = dxsa.index.imm {imm = 3 : i32} -// CHECK: %[[OPERAND_2:.*]] = dxsa.operand %[[INDEX_2]] {num_components = 4 : i32, swizzle = dense<[0, 1, 2, 3]> : vector<4xi32>, type = 30 : i32} -// CHECK: dxsa.instruction "ld_uav_typed" %[[OPERAND_0]], %[[OPERAND_1]], %[[OPERAND_2]] -// CHECK: %[[INDEX_3:.*]] = dxsa.index.imm {imm = 1 : i32} -// CHECK: %[[OPERAND_3:.*]] = dxsa.operand %[[INDEX_3]] {mask = 240 : i32, num_components = 4 : i32, type = 0 : i32} -// CHECK: %[[INDEX_4:.*]] = dxsa.index.imm {imm = 0 : i32} -// CHECK: %[[OPERAND_4:.*]] = dxsa.operand %[[INDEX_4]] {num_components = 4 : i32, swizzle = dense<[0, 1, 1, 1]> : vector<4xi32>, type = 1 : i32} -// CHECK: %[[INDEX_5:.*]] = dxsa.index.imm {imm = 3 : i32} -// CHECK: %[[OPERAND_5:.*]] = dxsa.operand %[[INDEX_5]] {num_components = 4 : i32, swizzle = dense<[0, 1, 2, 3]> : vector<4xi32>, type = 30 : i32} -// CHECK: dxsa.instruction "ld_uav_typed" %[[OPERAND_3]], %[[OPERAND_4]], %[[OPERAND_5]] +// CHECK: dxsa.ld_uav_typed r<0>, v<0, >, u<3, vector> +// CHECK: dxsa.ld_uav_typed r<1>, v<0, >, u<3, vector> // CHECK: dxsa.add r<0>, r<0>, r<1> -// CHECK: %[[OPERAND_6:.*]] = dxsa.operand {num_components = 0 : i32, type = 13 : i32} -// CHECK: %[[INDEX_6:.*]] = dxsa.index.imm {imm = 1 : i32} -// CHECK: %[[OPERAND_7:.*]] = dxsa.operand %[[INDEX_6]] {mask = 16 : i32, num_components = 4 : i32, type = 0 : i32} -// CHECK: %[[INDEX_7:.*]] = dxsa.index.imm {imm = 0 : i32} -// CHECK: %[[OPERAND_8:.*]] = dxsa.operand %[[INDEX_7]] {num_components = 4 : i32, swizzle = dense<[0, 1, 1, 1]> : vector<4xi32>, type = 1 : i32} -// CHECK: %[[INDEX_8:.*]] = dxsa.index.imm {imm = 3 : i32} -// CHECK: %[[OPERAND_9:.*]] = dxsa.operand %[[INDEX_8]] {num_components = 4 : i32, swizzle = dense<[0, 1, 2, 3]> : vector<4xi32>, type = 30 : i32} -// CHECK: dxsa.instruction "ld_uav_typed_s" %[[OPERAND_6]], %[[OPERAND_7]], %[[OPERAND_8]], %[[OPERAND_9]] -// CHECK: %[[INDEX_9:.*]] = dxsa.index.imm {imm = 1 : i32} -// CHECK: %[[OPERAND_10:.*]] = dxsa.operand %[[INDEX_9]] {mask = 16 : i32, num_components = 4 : i32, type = 0 : i32} -// CHECK: %[[INDEX_10:.*]] = dxsa.index.imm {imm = 1 : i32} -// CHECK: %[[OPERAND_11:.*]] = dxsa.operand %[[INDEX_10]] {num_components = 4 : i32, one = 0 : i32, type = 0 : i32} -// CHECK: dxsa.instruction "check_access_fully_mapped" %[[OPERAND_10]], %[[OPERAND_11]] +// CHECK: dxsa.ld_uav_typed_s null, v<0, >, u<3, vector>, r<1, > +// CHECK: %[[INDEX_0:.*]] = dxsa.index.imm {imm = 1 : i32} +// CHECK: %[[OPERAND_0:.*]] = dxsa.operand %[[INDEX_0]] {mask = 16 : i32, num_components = 4 : i32, type = 0 : i32} +// CHECK: %[[INDEX_1:.*]] = dxsa.index.imm {imm = 1 : i32} +// CHECK: %[[OPERAND_1:.*]] = dxsa.operand %[[INDEX_1]] {num_components = 4 : i32, one = 0 : i32, type = 0 : i32} +// CHECK: dxsa.instruction "check_access_fully_mapped" %[[OPERAND_0]], %[[OPERAND_1]] // CHECK: dxsa.utof r<1, >, r<1, > // CHECK: dxsa.mad r<0>, r<1, >, l(0x40000000, 0x40000000, 0x40000000, 0x40000000), r<0> -// CHECK: %[[INDEX_11:.*]] = dxsa.index.imm {imm = 3 : i32} -// CHECK: %[[OPERAND_12:.*]] = dxsa.operand %[[INDEX_11]] {mask = 240 : i32, num_components = 4 : i32, type = 30 : i32} -// CHECK: %[[INDEX_12:.*]] = dxsa.index.imm {imm = 0 : i32} -// CHECK: %[[OPERAND_13:.*]] = dxsa.operand %[[INDEX_12]] {num_components = 4 : i32, swizzle = dense<[2, 3, 3, 3]> : vector<4xi32>, type = 1 : i32} -// CHECK: %[[INDEX_13:.*]] = dxsa.index.imm {imm = 0 : i32} -// CHECK: %[[OPERAND_14:.*]] = dxsa.operand %[[INDEX_13]] {num_components = 4 : i32, swizzle = dense<[0, 1, 2, 3]> : vector<4xi32>, type = 0 : i32} -// CHECK: dxsa.instruction "store_uav_typed" %[[OPERAND_12]], %[[OPERAND_13]], %[[OPERAND_14]] +// CHECK: %[[INDEX_2:.*]] = dxsa.index.imm {imm = 3 : i32} +// CHECK: %[[OPERAND_2:.*]] = dxsa.operand %[[INDEX_2]] {mask = 240 : i32, num_components = 4 : i32, type = 30 : i32} +// CHECK: %[[INDEX_3:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_3:.*]] = dxsa.operand %[[INDEX_3]] {num_components = 4 : i32, swizzle = dense<[2, 3, 3, 3]> : vector<4xi32>, type = 1 : i32} +// CHECK: %[[INDEX_4:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_4:.*]] = dxsa.operand %[[INDEX_4]] {num_components = 4 : i32, swizzle = dense<[0, 1, 2, 3]> : vector<4xi32>, type = 0 : i32} +// CHECK: dxsa.instruction "store_uav_typed" %[[OPERAND_2]], %[[OPERAND_3]], %[[OPERAND_4]] // CHECK: dxsa.mov o<0>, r<0> // CHECK: dxsa.ret diff --git a/mlir/test/Target/DXSA/hlsl/uav_typed_load_store2.test b/mlir/test/Target/DXSA/hlsl/uav_typed_load_store2.test index 9aa085034040..2b5b5f67ff1d 100644 --- a/mlir/test/Target/DXSA/hlsl/uav_typed_load_store2.test +++ b/mlir/test/Target/DXSA/hlsl/uav_typed_load_store2.test @@ -8,58 +8,31 @@ // CHECK: dxsa.dcl_input_ps constant v<0, > // CHECK: dxsa.dcl_output o<0, > // CHECK: dxsa.dcl_temps 5 -// CHECK: %[[INDEX_0:.*]] = dxsa.index.imm {imm = 0 : i32} -// CHECK: %[[OPERAND_0:.*]] = dxsa.operand %[[INDEX_0]] {mask = 112 : i32, min_precision = 4 : i32, num_components = 4 : i32, type = 0 : i32} -// CHECK: %[[INDEX_1:.*]] = dxsa.index.imm {imm = 0 : i32} -// CHECK: %[[OPERAND_1:.*]] = dxsa.operand %[[INDEX_1]] {num_components = 4 : i32, swizzle = dense<1> : vector<4xi32>, type = 1 : i32} -// CHECK: %[[INDEX_2:.*]] = dxsa.index.imm {imm = 3 : i32} -// CHECK: %[[OPERAND_2:.*]] = dxsa.operand %[[INDEX_2]] {num_components = 4 : i32, swizzle = dense<[0, 1, 2, 3]> : vector<4xi32>, type = 30 : i32} -// CHECK: dxsa.instruction "ld_uav_typed" %[[OPERAND_0]], %[[OPERAND_1]], %[[OPERAND_2]] -// CHECK: %[[INDEX_3:.*]] = dxsa.index.imm {imm = 1 : i32} -// CHECK: %[[OPERAND_3:.*]] = dxsa.operand %[[INDEX_3]] {mask = 112 : i32, min_precision = 4 : i32, num_components = 4 : i32, type = 0 : i32} -// CHECK: %[[INDEX_4:.*]] = dxsa.index.imm {imm = 0 : i32} -// CHECK: %[[OPERAND_4:.*]] = dxsa.operand %[[INDEX_4]] {num_components = 4 : i32, swizzle = dense<0> : vector<4xi32>, type = 1 : i32} -// CHECK: %[[INDEX_5:.*]] = dxsa.index.imm {imm = 3 : i32} -// CHECK: %[[OPERAND_5:.*]] = dxsa.operand %[[INDEX_5]] {num_components = 4 : i32, swizzle = dense<[0, 1, 2, 3]> : vector<4xi32>, type = 30 : i32} -// CHECK: dxsa.instruction "ld_uav_typed" %[[OPERAND_3]], %[[OPERAND_4]], %[[OPERAND_5]] +// CHECK: dxsa.ld_uav_typed r<0, min16i, >, v<0, >, u<3, vector> +// CHECK: dxsa.ld_uav_typed r<1, min16i, >, v<0, >, u<3, vector> // CHECK: dxsa.iadd r<2, >, r<0, min16i, >, r<1, min16i, > -// CHECK: %[[OPERAND_6:.*]] = dxsa.operand {num_components = 0 : i32, type = 13 : i32} -// CHECK: %[[INDEX_6:.*]] = dxsa.index.imm {imm = 3 : i32} -// CHECK: %[[OPERAND_7:.*]] = dxsa.operand %[[INDEX_6]] {mask = 16 : i32, num_components = 4 : i32, type = 0 : i32} -// CHECK: %[[INDEX_7:.*]] = dxsa.index.imm {imm = 0 : i32} -// CHECK: %[[OPERAND_8:.*]] = dxsa.operand %[[INDEX_7]] {num_components = 4 : i32, swizzle = dense<1> : vector<4xi32>, type = 1 : i32} -// CHECK: %[[INDEX_8:.*]] = dxsa.index.imm {imm = 3 : i32} -// CHECK: %[[OPERAND_9:.*]] = dxsa.operand %[[INDEX_8]] {num_components = 4 : i32, swizzle = dense<[3, 1, 2, 0]> : vector<4xi32>, type = 30 : i32} -// CHECK: dxsa.instruction "ld_uav_typed_s" %[[OPERAND_6]], %[[OPERAND_7]], %[[OPERAND_8]], %[[OPERAND_9]] -// CHECK: %[[INDEX_9:.*]] = dxsa.index.imm {imm = 0 : i32} -// CHECK: %[[OPERAND_10:.*]] = dxsa.operand %[[INDEX_9]] {mask = 112 : i32, min_precision = 4 : i32, num_components = 4 : i32, type = 0 : i32} -// CHECK: %[[INDEX_10:.*]] = dxsa.index.imm {imm = 4 : i32} -// CHECK: %[[OPERAND_11:.*]] = dxsa.operand %[[INDEX_10]] {mask = 16 : i32, num_components = 4 : i32, type = 0 : i32} -// CHECK: %[[INDEX_11:.*]] = dxsa.index.imm {imm = 0 : i32} -// CHECK: %[[OPERAND_12:.*]] = dxsa.operand %[[INDEX_11]] {num_components = 4 : i32, swizzle = dense<0> : vector<4xi32>, type = 1 : i32} -// CHECK: %[[INDEX_12:.*]] = dxsa.index.imm {imm = 3 : i32} -// CHECK: %[[OPERAND_13:.*]] = dxsa.operand %[[INDEX_12]] {num_components = 4 : i32, swizzle = dense<[3, 1, 2, 0]> : vector<4xi32>, type = 30 : i32} -// CHECK: dxsa.instruction "ld_uav_typed_s" %[[OPERAND_10]], %[[OPERAND_11]], %[[OPERAND_12]], %[[OPERAND_13]] -// CHECK: %[[INDEX_13:.*]] = dxsa.index.imm {imm = 2 : i32} -// CHECK: %[[OPERAND_14:.*]] = dxsa.operand %[[INDEX_13]] {mask = 128 : i32, num_components = 4 : i32, type = 0 : i32} -// CHECK: %[[INDEX_14:.*]] = dxsa.index.imm {imm = 3 : i32} -// CHECK: %[[OPERAND_15:.*]] = dxsa.operand %[[INDEX_14]] {num_components = 4 : i32, one = 0 : i32, type = 0 : i32} -// CHECK: dxsa.instruction "check_access_fully_mapped" %[[OPERAND_14]], %[[OPERAND_15]] +// CHECK: dxsa.ld_uav_typed_s null, v<0, >, u<3, vector, >, r<3, > +// CHECK: dxsa.ld_uav_typed_s r<0, min16i, >, v<0, >, u<3, vector, >, r<4, > +// CHECK: %[[INDEX_0:.*]] = dxsa.index.imm {imm = 2 : i32} +// CHECK: %[[OPERAND_0:.*]] = dxsa.operand %[[INDEX_0]] {mask = 128 : i32, num_components = 4 : i32, type = 0 : i32} +// CHECK: %[[INDEX_1:.*]] = dxsa.index.imm {imm = 3 : i32} +// CHECK: %[[OPERAND_1:.*]] = dxsa.operand %[[INDEX_1]] {num_components = 4 : i32, one = 0 : i32, type = 0 : i32} +// CHECK: dxsa.instruction "check_access_fully_mapped" %[[OPERAND_0]], %[[OPERAND_1]] // CHECK: dxsa.iadd r<2, >, r<2, >, r<2, > -// CHECK: %[[INDEX_15:.*]] = dxsa.index.imm {imm = 2 : i32} -// CHECK: %[[OPERAND_16:.*]] = dxsa.operand %[[INDEX_15]] {mask = 128 : i32, num_components = 4 : i32, type = 0 : i32} -// CHECK: %[[INDEX_16:.*]] = dxsa.index.imm {imm = 4 : i32} -// CHECK: %[[OPERAND_17:.*]] = dxsa.operand %[[INDEX_16]] {num_components = 4 : i32, one = 0 : i32, type = 0 : i32} -// CHECK: dxsa.instruction "check_access_fully_mapped" %[[OPERAND_16]], %[[OPERAND_17]] +// CHECK: %[[INDEX_2:.*]] = dxsa.index.imm {imm = 2 : i32} +// CHECK: %[[OPERAND_2:.*]] = dxsa.operand %[[INDEX_2]] {mask = 128 : i32, num_components = 4 : i32, type = 0 : i32} +// CHECK: %[[INDEX_3:.*]] = dxsa.index.imm {imm = 4 : i32} +// CHECK: %[[OPERAND_3:.*]] = dxsa.operand %[[INDEX_3]] {num_components = 4 : i32, one = 0 : i32, type = 0 : i32} +// CHECK: dxsa.instruction "check_access_fully_mapped" %[[OPERAND_2]], %[[OPERAND_3]] // CHECK: dxsa.iadd r<2, >, r<0, min16i, >, r<2, > // CHECK: dxsa.iadd r<2, >, r<2, >, r<2, > -// CHECK: %[[INDEX_17:.*]] = dxsa.index.imm {imm = 3 : i32} -// CHECK: %[[OPERAND_18:.*]] = dxsa.operand %[[INDEX_17]] {mask = 240 : i32, num_components = 4 : i32, type = 30 : i32} -// CHECK: %[[INDEX_18:.*]] = dxsa.index.imm {imm = 0 : i32} -// CHECK: %[[OPERAND_19:.*]] = dxsa.operand %[[INDEX_18]] {num_components = 4 : i32, swizzle = dense<1> : vector<4xi32>, type = 1 : i32} -// CHECK: %[[INDEX_19:.*]] = dxsa.index.imm {imm = 2 : i32} -// CHECK: %[[OPERAND_20:.*]] = dxsa.operand %[[INDEX_19]] {num_components = 4 : i32, swizzle = dense<[0, 1, 2, 0]> : vector<4xi32>, type = 0 : i32} -// CHECK: dxsa.instruction "store_uav_typed" %[[OPERAND_18]], %[[OPERAND_19]], %[[OPERAND_20]] +// CHECK: %[[INDEX_4:.*]] = dxsa.index.imm {imm = 3 : i32} +// CHECK: %[[OPERAND_4:.*]] = dxsa.operand %[[INDEX_4]] {mask = 240 : i32, num_components = 4 : i32, type = 30 : i32} +// CHECK: %[[INDEX_5:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_5:.*]] = dxsa.operand %[[INDEX_5]] {num_components = 4 : i32, swizzle = dense<1> : vector<4xi32>, type = 1 : i32} +// CHECK: %[[INDEX_6:.*]] = dxsa.index.imm {imm = 2 : i32} +// CHECK: %[[OPERAND_6:.*]] = dxsa.operand %[[INDEX_6]] {num_components = 4 : i32, swizzle = dense<[0, 1, 2, 0]> : vector<4xi32>, type = 0 : i32} +// CHECK: dxsa.instruction "store_uav_typed" %[[OPERAND_4]], %[[OPERAND_5]], %[[OPERAND_6]] // CHECK: dxsa.mov o<0, >, r<2, > // CHECK: dxsa.ret diff --git a/mlir/test/Target/DXSA/ld.test b/mlir/test/Target/DXSA/ld.test new file mode 100644 index 000000000000..8153135d52c8 --- /dev/null +++ b/mlir/test/Target/DXSA/ld.test @@ -0,0 +1,26 @@ +// RUN: mlir-translate --import-dxsa-hex %s | FileCheck %s +// RUN: mlir-translate --import-dxsa-hex %s | mlir-opt --verify-roundtrip + +// CHECK: dxsa.ld r<0>, r<0>, t<3, vector> + +0x8900002d, 0x800000c2, 0x00155543, 0x001000f2, +0x00000000, 0x00100e46, 0x00000000, 0x00107e46, +0x00000003 + +// CHECK: dxsa.ld r<2>, r<1, >, t<3, vector>, + +0x8a00002d, 0x8000f601, 0x800000c2, 0x00155543, +0x001000f2, 0x00000002, 0x00100f46, 0x00000001, +0x00107e46, 0x00000003 + +// CHECK: dxsa.ld_s r<2>, r<1, >, t<3, vector>, r<3, >, + +0x8c0000df, 0x8000f601, 0x800000c2, 0x00155543, +0x001000f2, 0x00000002, 0x00100012, 0x00000003, +0x00100f46, 0x00000001, 0x00107e46, 0x00000003 + +// CHECK: dxsa.ld_s r<1>, r<1>, t<3, vector>, r<4, > + +0x8b0000df, 0x800000c2, 0x00155543, 0x001000f2, +0x00000001, 0x00100012, 0x00000004, 0x00100e46, +0x00000001, 0x00107e46, 0x00000003 diff --git a/mlir/test/Target/DXSA/ld2dms.test b/mlir/test/Target/DXSA/ld2dms.test new file mode 100644 index 000000000000..2e331eee9cdf --- /dev/null +++ b/mlir/test/Target/DXSA/ld2dms.test @@ -0,0 +1,40 @@ +// RUN: mlir-translate --import-dxsa-hex %s | FileCheck %s +// RUN: mlir-translate --import-dxsa-hex %s | mlir-opt --verify-roundtrip + +// CHECK: dxsa.ld2dms r<0, >, r<0>, t<3, vector>, l(0x0) + +0x8b00002e, 0x80000102, 0x00155543, 0x00100072, +0x00000000, 0x00100e46, 0x00000000, 0x00107e46, +0x00000003, 0x00004001, 0x00000000 + +// CHECK: dxsa.ld2dms r<2, >, r<1, >, t<3, vector>, v<0, > + +0x8b00002e, 0x80000102, 0x00155543, 0x00100072, +0x00000002, 0x00100f46, 0x00000001, 0x00107e46, +0x00000003, 0x0010102a, 0x00000000 + +// CHECK: dxsa.ld2dms r<2, >, r<1, >, t<3, vector>, v<0, >, + +0x8c00002e, 0x8000f601, 0x80000102, 0x00155543, +0x00100072, 0x00000002, 0x00100f46, 0x00000001, +0x00107e46, 0x00000003, 0x0010102a, 0x00000000 + +// CHECK: dxsa.ld2dms_s r<2, >, r<1, >, t<3, vector>, v<0, >, r<3, >, + +0x8e0000e0, 0x8000f601, 0x80000102, 0x00155543, +0x00100072, 0x00000002, 0x00100012, 0x00000003, +0x00100f46, 0x00000001, 0x00107e46, 0x00000003, +0x0010102a, 0x00000000 + +// CHECK: dxsa.ld2dms_s r<2, >, r<1, >, t<3, vector>, v<0, >, r<3, > + +0x8d0000e0, 0x80000102, 0x00155543, 0x00100072, +0x00000002, 0x00100012, 0x00000003, 0x00100f46, +0x00000001, 0x00107e46, 0x00000003, 0x0010102a, +0x00000000 + +// CHECK: dxsa.ld2dms r<1, >, r<1>, t<3, vector>, l(0xD) + +0x8b00002e, 0x80000102, 0x00155543, 0x00100072, +0x00000001, 0x00100e46, 0x00000001, 0x00107e46, +0x00000003, 0x00004001, 0x0000000d diff --git a/mlir/test/Target/DXSA/ld_raw.test b/mlir/test/Target/DXSA/ld_raw.test new file mode 100644 index 000000000000..ae5faa8d6956 --- /dev/null +++ b/mlir/test/Target/DXSA/ld_raw.test @@ -0,0 +1,19 @@ +// RUN: mlir-translate --import-dxsa-hex %s | FileCheck %s +// RUN: mlir-translate --import-dxsa-hex %s | mlir-opt --verify-roundtrip + +// CHECK: dxsa.ld_raw r<0, >, r<0, >, g<0, vector, > + +0x070000a5, 0x00100052, 0x00000000, 0x0010000a, +0x00000000, 0x0011f726, 0x00000000 + +// CHECK: dxsa.ld_raw r<0, >, r<0, >, u<0, vector, > + +0x890000a5, 0x800002c2, 0x00199983, 0x00100022, +0x00000000, 0x0010000a, 0x00000000, 0x0011e006, +0x00000000 + +// CHECK: dxsa.ld_raw_s r<5, >, r<0, >, u<1, vector, >, r<6, > + +0x8b0000e2, 0x800002c2, 0x00199983, 0x00100012, +0x00000005, 0x00100012, 0x00000006, 0x0010000a, +0x00000000, 0x0011e006, 0x00000001 diff --git a/mlir/test/Target/DXSA/ld_structured.test b/mlir/test/Target/DXSA/ld_structured.test new file mode 100644 index 000000000000..d31b225e65ad --- /dev/null +++ b/mlir/test/Target/DXSA/ld_structured.test @@ -0,0 +1,27 @@ +// RUN: mlir-translate --import-dxsa-hex %s | FileCheck %s +// RUN: mlir-translate --import-dxsa-hex %s | mlir-opt --verify-roundtrip + +// CHECK: dxsa.ld_structured r<0, >, r<0, >, l(0x8), g<0, vector, > + +0x090000a7, 0x00100082, 0x00000000, 0x0010002a, +0x00000000, 0x00004001, 0x00000008, 0x0011f006, +0x00000000 + +// CHECK: dxsa.ld_structured r<2, min16i, >, r<0, >, l(0xC), g<0, vector, > + +0x0a0000a7, 0x80100012, 0x00010001, 0x00000002, +0x0010002a, 0x00000000, 0x00004001, 0x0000000c, +0x0011f006, 0x00000000 + +// CHECK: dxsa.ld_structured r<1, min16f, >, r<0, >, l(0x4), g<0, vector, > + +0x0a0000a7, 0x80100012, 0x00004001, 0x00000001, +0x0010002a, 0x00000000, 0x00004001, 0x00000004, +0x0011f006, 0x00000000 + +// CHECK: dxsa.ld_structured_s r<5, >, r<0, >, l(0x0), u<1, vector>, r<0, > + +0x8d0000e3, 0x8001a302, 0x00199983, 0x00100032, +0x00000005, 0x00100012, 0x00000000, 0x0010001a, +0x00000000, 0x00004001, 0x00000000, 0x0011ee46, +0x00000001 diff --git a/mlir/test/Target/DXSA/ld_uav_typed.test b/mlir/test/Target/DXSA/ld_uav_typed.test new file mode 100644 index 000000000000..e5e04f80a16d --- /dev/null +++ b/mlir/test/Target/DXSA/ld_uav_typed.test @@ -0,0 +1,27 @@ +// RUN: mlir-translate --import-dxsa-hex %s | FileCheck %s +// RUN: mlir-translate --import-dxsa-hex %s | mlir-opt --verify-roundtrip + +// CHECK: dxsa.ld_uav_typed r<0, min16i, >, v<0, >, u<3, vector> + +0x8a0000a3, 0x80000042, 0x000cccc3, 0x80100072, +0x00010001, 0x00000000, 0x00101556, 0x00000000, +0x0011ee46, 0x00000003 + +// CHECK: dxsa.ld_uav_typed r<1, min16i, >, v<0, >, u<3, vector> + +0x8a0000a3, 0x80000042, 0x000cccc3, 0x80100072, +0x00010001, 0x00000001, 0x00101006, 0x00000000, +0x0011ee46, 0x00000003 + +// CHECK: dxsa.ld_uav_typed_s null, v<0, >, u<3, vector, >, r<3, > + +0x8a0000e1, 0x80000042, 0x000cccc3, 0x0000d000, +0x00100012, 0x00000003, 0x00101556, 0x00000000, +0x0011e276, 0x00000003 + +// CHECK: dxsa.ld_uav_typed_s r<0, min16i, >, v<0, >, u<3, vector, >, r<4, > + +0x8c0000e1, 0x80000042, 0x000cccc3, 0x80100072, +0x00010001, 0x00000000, 0x00100012, 0x00000004, +0x00101006, 0x00000000, 0x0011e276, 0x00000003 +