From 540066b4bb821987876a81c9d3f6b6f177e0f6e8 Mon Sep 17 00:00:00 2001 From: Andrew Savonichev Date: Thu, 2 Jul 2026 16:42:25 +0900 Subject: [PATCH] [dxsa][mlir] Port LIT tests from dxilconv dxilconv tool has a LIT test suite that covers most instructions. These original tests are DXBC container binaries, but the current mlir-translate tool cannot translate from them directly - it needs only the content of SHEX section. The tests are generated by extracting shader binaries from DXBC containers. LIT checks are auto-generated by MLIR utils/generate-test-checks.py script. The checks reflect the current state of the compiler, and it is expected they will change once we enable more instructions. Tests in hlsl directory are from: https://github.com/microsoft/DirectXShaderCompiler/tree/main/projects/dxilconv/test/dxbc2dxil Tests in asm directory are from: https://github.com/microsoft/DirectXShaderCompiler/tree/main/projects/dxilconv/test/dxbc2dxil-asm --- mlir/test/Target/DXSA/asm/call2.test | 37 +++ mlir/test/Target/DXSA/asm/cs3.test | 42 +++ mlir/test/Target/DXSA/asm/cyclecounter.test | 11 + mlir/test/Target/DXSA/asm/hs3.test | 93 +++++++ mlir/test/Target/DXSA/asm/indexabletemp4.test | 19 ++ mlir/test/Target/DXSA/asm/indexabletemp6.test | 21 ++ mlir/test/Target/DXSA/asm/inputs/call2.shex | Bin 0 -> 356 bytes mlir/test/Target/DXSA/asm/inputs/cs3.shex | Bin 0 -> 324 bytes .../Target/DXSA/asm/inputs/cyclecounter.shex | Bin 0 -> 92 bytes mlir/test/Target/DXSA/asm/inputs/hs3.shex | Bin 0 -> 1300 bytes .../DXSA/asm/inputs/indexabletemp4.shex | Bin 0 -> 260 bytes .../DXSA/asm/inputs/indexabletemp6.shex | Bin 0 -> 372 bytes mlir/test/Target/DXSA/hlsl/abs1.test | 10 + mlir/test/Target/DXSA/hlsl/abs2.test | 10 + mlir/test/Target/DXSA/hlsl/atomics.test | 51 ++++ mlir/test/Target/DXSA/hlsl/bad_ftoi.test | 11 + mlir/test/Target/DXSA/hlsl/binary1.test | 17 ++ mlir/test/Target/DXSA/hlsl/bool1.test | 20 ++ mlir/test/Target/DXSA/hlsl/bool2.test | 19 ++ mlir/test/Target/DXSA/hlsl/bufinfo.test | 28 ++ mlir/test/Target/DXSA/hlsl/calc_lod.test | 19 ++ mlir/test/Target/DXSA/hlsl/call1.test | 34 +++ mlir/test/Target/DXSA/hlsl/call3.test | 52 ++++ mlir/test/Target/DXSA/hlsl/cast1.test | 10 + mlir/test/Target/DXSA/hlsl/cast2.test | 10 + mlir/test/Target/DXSA/hlsl/cast3.test | 10 + mlir/test/Target/DXSA/hlsl/cast4.test | 10 + mlir/test/Target/DXSA/hlsl/cast5.test | 10 + mlir/test/Target/DXSA/hlsl/cast6.test | 10 + mlir/test/Target/DXSA/hlsl/cbuffer1.50.test | 10 + mlir/test/Target/DXSA/hlsl/cbuffer1.51.test | 10 + mlir/test/Target/DXSA/hlsl/cbuffer2.50.test | 10 + mlir/test/Target/DXSA/hlsl/cbuffer2.51.test | 10 + mlir/test/Target/DXSA/hlsl/cbuffer3.50.test | 15 ++ mlir/test/Target/DXSA/hlsl/cbuffer3.51.test | 16 ++ mlir/test/Target/DXSA/hlsl/cmp1.test | 11 + mlir/test/Target/DXSA/hlsl/constoperand1.test | 9 + mlir/test/Target/DXSA/hlsl/cs1.test | 30 +++ mlir/test/Target/DXSA/hlsl/cs2.test | 84 ++++++ mlir/test/Target/DXSA/hlsl/cs4.test | 59 ++++ mlir/test/Target/DXSA/hlsl/cs5.test | 84 ++++++ mlir/test/Target/DXSA/hlsl/derivatives.test | 22 ++ mlir/test/Target/DXSA/hlsl/discard.test | 19 ++ mlir/test/Target/DXSA/hlsl/dot1.test | 16 ++ mlir/test/Target/DXSA/hlsl/double1.test | 18 ++ mlir/test/Target/DXSA/hlsl/double2.test | 19 ++ mlir/test/Target/DXSA/hlsl/double3.test | 23 ++ mlir/test/Target/DXSA/hlsl/double4.test | 18 ++ mlir/test/Target/DXSA/hlsl/double5.test | 27 ++ mlir/test/Target/DXSA/hlsl/double6.test | 40 +++ mlir/test/Target/DXSA/hlsl/ds1.test | 45 ++++ mlir/test/Target/DXSA/hlsl/empty.test | 7 + mlir/test/Target/DXSA/hlsl/eval.test | 33 +++ mlir/test/Target/DXSA/hlsl/f32f16.test | 15 ++ mlir/test/Target/DXSA/hlsl/gather.test | 44 +++ mlir/test/Target/DXSA/hlsl/gather_cmp.test | 44 +++ mlir/test/Target/DXSA/hlsl/gather_po.test | 80 ++++++ mlir/test/Target/DXSA/hlsl/gather_po_cmp.test | 80 ++++++ mlir/test/Target/DXSA/hlsl/getdim.test | 61 +++++ mlir/test/Target/DXSA/hlsl/gs1.test | 34 +++ mlir/test/Target/DXSA/hlsl/gs2.test | 61 +++++ mlir/test/Target/DXSA/hlsl/half_rcp.test | 12 + mlir/test/Target/DXSA/hlsl/hs1.test | 84 ++++++ mlir/test/Target/DXSA/hlsl/hs2.test | 77 ++++++ mlir/test/Target/DXSA/hlsl/icb1.test | 20 ++ mlir/test/Target/DXSA/hlsl/if1.test | 21 ++ mlir/test/Target/DXSA/hlsl/if2.test | 19 ++ mlir/test/Target/DXSA/hlsl/if3.test | 19 ++ mlir/test/Target/DXSA/hlsl/if4.test | 25 ++ mlir/test/Target/DXSA/hlsl/if5.test | 29 ++ .../Target/DXSA/hlsl/indexableinput1.test | 20 ++ .../Target/DXSA/hlsl/indexableinput2.test | 26 ++ .../Target/DXSA/hlsl/indexableoutput1.test | 12 + .../test/Target/DXSA/hlsl/indexabletemp1.test | 23 ++ .../test/Target/DXSA/hlsl/indexabletemp2.test | 27 ++ .../test/Target/DXSA/hlsl/indexabletemp3.test | 18 ++ .../test/Target/DXSA/hlsl/indexabletemp5.test | 18 ++ mlir/test/Target/DXSA/hlsl/input1.test | 45 ++++ mlir/test/Target/DXSA/hlsl/input2.test | 45 ++++ mlir/test/Target/DXSA/hlsl/input3.test | 16 ++ mlir/test/Target/DXSA/hlsl/inputs/abs1.shex | Bin 0 -> 64 bytes mlir/test/Target/DXSA/hlsl/inputs/abs2.shex | Bin 0 -> 72 bytes .../test/Target/DXSA/hlsl/inputs/atomics.shex | Bin 0 -> 1204 bytes .../Target/DXSA/hlsl/inputs/bad_ftoi.shex | Bin 0 -> 100 bytes .../test/Target/DXSA/hlsl/inputs/binary1.shex | Bin 0 -> 212 bytes mlir/test/Target/DXSA/hlsl/inputs/bool1.shex | Bin 0 -> 136 bytes mlir/test/Target/DXSA/hlsl/inputs/bool2.shex | Bin 0 -> 124 bytes .../test/Target/DXSA/hlsl/inputs/bufinfo.shex | Bin 0 -> 488 bytes .../Target/DXSA/hlsl/inputs/calc_lod.shex | Bin 0 -> 272 bytes mlir/test/Target/DXSA/hlsl/inputs/call1.shex | Bin 0 -> 280 bytes mlir/test/Target/DXSA/hlsl/inputs/call3.shex | Bin 0 -> 456 bytes mlir/test/Target/DXSA/hlsl/inputs/cast1.shex | Bin 0 -> 60 bytes mlir/test/Target/DXSA/hlsl/inputs/cast2.shex | Bin 0 -> 60 bytes mlir/test/Target/DXSA/hlsl/inputs/cast3.shex | Bin 0 -> 60 bytes mlir/test/Target/DXSA/hlsl/inputs/cast4.shex | Bin 0 -> 60 bytes mlir/test/Target/DXSA/hlsl/inputs/cast5.shex | Bin 0 -> 68 bytes mlir/test/Target/DXSA/hlsl/inputs/cast6.shex | Bin 0 -> 68 bytes .../Target/DXSA/hlsl/inputs/cbuffer1.50.shex | Bin 0 -> 68 bytes .../Target/DXSA/hlsl/inputs/cbuffer1.51.shex | Bin 0 -> 84 bytes .../Target/DXSA/hlsl/inputs/cbuffer2.50.shex | Bin 0 -> 68 bytes .../Target/DXSA/hlsl/inputs/cbuffer2.51.shex | Bin 0 -> 84 bytes .../Target/DXSA/hlsl/inputs/cbuffer3.50.shex | Bin 0 -> 156 bytes .../Target/DXSA/hlsl/inputs/cbuffer3.51.shex | Bin 0 -> 232 bytes mlir/test/Target/DXSA/hlsl/inputs/cmp1.shex | Bin 0 -> 80 bytes .../DXSA/hlsl/inputs/constoperand1.shex | Bin 0 -> 64 bytes mlir/test/Target/DXSA/hlsl/inputs/cs1.shex | Bin 0 -> 308 bytes mlir/test/Target/DXSA/hlsl/inputs/cs2.shex | Bin 0 -> 736 bytes mlir/test/Target/DXSA/hlsl/inputs/cs4.shex | Bin 0 -> 728 bytes mlir/test/Target/DXSA/hlsl/inputs/cs5.shex | Bin 0 -> 736 bytes .../Target/DXSA/hlsl/inputs/derivatives.shex | Bin 0 -> 320 bytes .../test/Target/DXSA/hlsl/inputs/discard.shex | Bin 0 -> 160 bytes mlir/test/Target/DXSA/hlsl/inputs/dot1.shex | Bin 0 -> 200 bytes .../test/Target/DXSA/hlsl/inputs/double1.shex | Bin 0 -> 260 bytes .../test/Target/DXSA/hlsl/inputs/double2.shex | Bin 0 -> 296 bytes .../test/Target/DXSA/hlsl/inputs/double3.shex | Bin 0 -> 364 bytes .../test/Target/DXSA/hlsl/inputs/double4.shex | Bin 0 -> 216 bytes .../test/Target/DXSA/hlsl/inputs/double5.shex | Bin 0 -> 412 bytes .../test/Target/DXSA/hlsl/inputs/double6.shex | Bin 0 -> 876 bytes mlir/test/Target/DXSA/hlsl/inputs/ds1.shex | Bin 0 -> 752 bytes mlir/test/Target/DXSA/hlsl/inputs/empty.shex | Bin 0 -> 16 bytes mlir/test/Target/DXSA/hlsl/inputs/eval.shex | Bin 0 -> 584 bytes mlir/test/Target/DXSA/hlsl/inputs/f32f16.shex | Bin 0 -> 148 bytes mlir/test/Target/DXSA/hlsl/inputs/gather.shex | Bin 0 -> 680 bytes .../Target/DXSA/hlsl/inputs/gather_cmp.shex | Bin 0 -> 720 bytes .../Target/DXSA/hlsl/inputs/gather_po.shex | Bin 0 -> 1312 bytes .../DXSA/hlsl/inputs/gather_po_cmp.shex | Bin 0 -> 1408 bytes mlir/test/Target/DXSA/hlsl/inputs/getdim.shex | Bin 0 -> 1296 bytes mlir/test/Target/DXSA/hlsl/inputs/gs1.shex | Bin 0 -> 524 bytes mlir/test/Target/DXSA/hlsl/inputs/gs2.shex | Bin 0 -> 848 bytes .../Target/DXSA/hlsl/inputs/half_rcp.shex | Bin 0 -> 112 bytes mlir/test/Target/DXSA/hlsl/inputs/hs1.shex | Bin 0 -> 996 bytes mlir/test/Target/DXSA/hlsl/inputs/hs2.shex | Bin 0 -> 1032 bytes mlir/test/Target/DXSA/hlsl/inputs/icb1.shex | Bin 0 -> 348 bytes mlir/test/Target/DXSA/hlsl/inputs/if1.shex | Bin 0 -> 156 bytes mlir/test/Target/DXSA/hlsl/inputs/if2.shex | Bin 0 -> 148 bytes mlir/test/Target/DXSA/hlsl/inputs/if3.shex | Bin 0 -> 164 bytes mlir/test/Target/DXSA/hlsl/inputs/if4.shex | Bin 0 -> 212 bytes mlir/test/Target/DXSA/hlsl/inputs/if5.shex | Bin 0 -> 228 bytes .../DXSA/hlsl/inputs/indexableinput1.shex | Bin 0 -> 220 bytes .../DXSA/hlsl/inputs/indexableinput2.shex | Bin 0 -> 312 bytes .../DXSA/hlsl/inputs/indexableoutput1.shex | Bin 0 -> 96 bytes .../DXSA/hlsl/inputs/indexabletemp1.shex | Bin 0 -> 404 bytes .../DXSA/hlsl/inputs/indexabletemp2.shex | Bin 0 -> 516 bytes .../DXSA/hlsl/inputs/indexabletemp3.shex | Bin 0 -> 228 bytes .../DXSA/hlsl/inputs/indexabletemp5.shex | Bin 0 -> 256 bytes mlir/test/Target/DXSA/hlsl/inputs/input1.shex | Bin 0 -> 788 bytes mlir/test/Target/DXSA/hlsl/inputs/input2.shex | Bin 0 -> 788 bytes mlir/test/Target/DXSA/hlsl/inputs/input3.shex | Bin 0 -> 180 bytes .../Target/DXSA/hlsl/inputs/interface1.shex | Bin 0 -> 576 bytes .../Target/DXSA/hlsl/inputs/liveness1.shex | Bin 0 -> 220 bytes mlir/test/Target/DXSA/hlsl/inputs/loop1.shex | Bin 0 -> 216 bytes mlir/test/Target/DXSA/hlsl/inputs/loop2.shex | Bin 0 -> 304 bytes mlir/test/Target/DXSA/hlsl/inputs/loop3.shex | Bin 0 -> 536 bytes mlir/test/Target/DXSA/hlsl/inputs/loop4.shex | Bin 0 -> 468 bytes mlir/test/Target/DXSA/hlsl/inputs/loop5.shex | Bin 0 -> 364 bytes .../Target/DXSA/hlsl/inputs/minprec1.shex | Bin 0 -> 112 bytes .../Target/DXSA/hlsl/inputs/minprec2.shex | Bin 0 -> 68 bytes .../Target/DXSA/hlsl/inputs/minprec3.shex | Bin 0 -> 188 bytes .../Target/DXSA/hlsl/inputs/minprec4.shex | Bin 0 -> 112 bytes .../Target/DXSA/hlsl/inputs/minprec5.shex | Bin 0 -> 76 bytes .../Target/DXSA/hlsl/inputs/minprec6.shex | Bin 0 -> 252 bytes .../Target/DXSA/hlsl/inputs/minprec7.shex | Bin 0 -> 104 bytes mlir/test/Target/DXSA/hlsl/inputs/neg1.shex | Bin 0 -> 64 bytes mlir/test/Target/DXSA/hlsl/inputs/neg2.shex | Bin 0 -> 60 bytes .../test/Target/DXSA/hlsl/inputs/negabs1.shex | Bin 0 -> 64 bytes .../Target/DXSA/hlsl/inputs/nonuniform1.shex | Bin 0 -> 360 bytes .../test/Target/DXSA/hlsl/inputs/output1.shex | Bin 0 -> 260 bytes .../test/Target/DXSA/hlsl/inputs/output2.shex | Bin 0 -> 164 bytes .../test/Target/DXSA/hlsl/inputs/output3.shex | Bin 0 -> 148 bytes .../test/Target/DXSA/hlsl/inputs/output4.shex | Bin 0 -> 188 bytes .../Target/DXSA/hlsl/inputs/passthrough1.shex | Bin 0 -> 64 bytes .../Target/DXSA/hlsl/inputs/passthrough2.shex | Bin 0 -> 60 bytes .../Target/DXSA/hlsl/inputs/precise1.shex | Bin 0 -> 236 bytes .../Target/DXSA/hlsl/inputs/raw_buf1.shex | Bin 0 -> 2312 bytes mlir/test/Target/DXSA/hlsl/inputs/rcp1.shex | Bin 0 -> 60 bytes .../DXSA/hlsl/inputs/redundantinput1.shex | Bin 0 -> 72 bytes .../test/Target/DXSA/hlsl/inputs/sample1.shex | Bin 0 -> 168 bytes .../test/Target/DXSA/hlsl/inputs/sample2.shex | Bin 0 -> 168 bytes .../test/Target/DXSA/hlsl/inputs/sample3.shex | Bin 0 -> 604 bytes .../Target/DXSA/hlsl/inputs/sample_b1.shex | Bin 0 -> 644 bytes .../Target/DXSA/hlsl/inputs/sample_cmp1.shex | Bin 0 -> 712 bytes .../Target/DXSA/hlsl/inputs/sample_cmp2.shex | Bin 0 -> 580 bytes .../Target/DXSA/hlsl/inputs/sample_grad1.shex | Bin 0 -> 684 bytes .../Target/DXSA/hlsl/inputs/sample_l1.shex | Bin 0 -> 840 bytes .../Target/DXSA/hlsl/inputs/samplecount.shex | Bin 0 -> 76 bytes .../Target/DXSA/hlsl/inputs/samplepos.shex | Bin 0 -> 432 bytes .../Target/DXSA/hlsl/inputs/saturate1.shex | Bin 0 -> 60 bytes mlir/test/Target/DXSA/hlsl/inputs/shift1.shex | Bin 0 -> 380 bytes mlir/test/Target/DXSA/hlsl/inputs/sincos.shex | Bin 0 -> 188 bytes mlir/test/Target/DXSA/hlsl/inputs/snorm1.shex | Bin 0 -> 208 bytes .../Target/DXSA/hlsl/inputs/srv_ms_load1.shex | Bin 0 -> 756 bytes .../DXSA/hlsl/inputs/srv_typed_load1.shex | Bin 0 -> 600 bytes .../DXSA/hlsl/inputs/srv_typed_load2.shex | Bin 0 -> 260 bytes .../Target/DXSA/hlsl/inputs/struct_buf1.shex | Bin 0 -> 4392 bytes mlir/test/Target/DXSA/hlsl/inputs/sub1.shex | Bin 0 -> 400 bytes .../test/Target/DXSA/hlsl/inputs/switch1.shex | Bin 0 -> 196 bytes .../test/Target/DXSA/hlsl/inputs/switch2.shex | Bin 0 -> 304 bytes .../test/Target/DXSA/hlsl/inputs/switch3.shex | Bin 0 -> 384 bytes .../Target/DXSA/hlsl/inputs/swizzle1.shex | Bin 0 -> 168 bytes mlir/test/Target/DXSA/hlsl/inputs/temp1.shex | Bin 0 -> 128 bytes mlir/test/Target/DXSA/hlsl/inputs/temp2.shex | Bin 0 -> 128 bytes .../DXSA/hlsl/inputs/uav_counter_dec.shex | Bin 0 -> 60 bytes .../DXSA/hlsl/inputs/uav_counter_inc.shex | Bin 0 -> 60 bytes .../Target/DXSA/hlsl/inputs/uav_raw1.shex | Bin 0 -> 324 bytes .../hlsl/inputs/uav_typed_load_store1.shex | Bin 0 -> 352 bytes .../hlsl/inputs/uav_typed_load_store2.shex | Bin 0 -> 456 bytes .../test/Target/DXSA/hlsl/inputs/ubfeu16.shex | Bin 0 -> 224 bytes mlir/test/Target/DXSA/hlsl/interface1.test | 32 +++ mlir/test/Target/DXSA/hlsl/liveness1.test | 21 ++ mlir/test/Target/DXSA/hlsl/loop1.test | 21 ++ mlir/test/Target/DXSA/hlsl/loop2.test | 29 ++ mlir/test/Target/DXSA/hlsl/loop3.test | 48 ++++ mlir/test/Target/DXSA/hlsl/loop4.test | 46 ++++ mlir/test/Target/DXSA/hlsl/loop5.test | 34 +++ mlir/test/Target/DXSA/hlsl/minprec1.test | 12 + mlir/test/Target/DXSA/hlsl/minprec2.test | 10 + mlir/test/Target/DXSA/hlsl/minprec3.test | 21 ++ mlir/test/Target/DXSA/hlsl/minprec4.test | 12 + mlir/test/Target/DXSA/hlsl/minprec5.test | 10 + mlir/test/Target/DXSA/hlsl/minprec6.test | 23 ++ mlir/test/Target/DXSA/hlsl/minprec7.test | 12 + mlir/test/Target/DXSA/hlsl/neg1.test | 10 + mlir/test/Target/DXSA/hlsl/neg2.test | 10 + mlir/test/Target/DXSA/hlsl/negabs1.test | 10 + mlir/test/Target/DXSA/hlsl/nonuniform1.test | 48 ++++ mlir/test/Target/DXSA/hlsl/output1.test | 21 ++ mlir/test/Target/DXSA/hlsl/output2.test | 17 ++ mlir/test/Target/DXSA/hlsl/output3.test | 16 ++ mlir/test/Target/DXSA/hlsl/output4.test | 16 ++ mlir/test/Target/DXSA/hlsl/passthrough1.test | 10 + mlir/test/Target/DXSA/hlsl/passthrough2.test | 10 + mlir/test/Target/DXSA/hlsl/precise1.test | 17 ++ mlir/test/Target/DXSA/hlsl/raw_buf1.test | 150 +++++++++++ mlir/test/Target/DXSA/hlsl/rcp1.test | 10 + .../Target/DXSA/hlsl/redundantinput1.test | 10 + mlir/test/Target/DXSA/hlsl/sample1.test | 15 ++ mlir/test/Target/DXSA/hlsl/sample2.test | 15 ++ mlir/test/Target/DXSA/hlsl/sample3.test | 35 +++ mlir/test/Target/DXSA/hlsl/sample_b1.test | 35 +++ mlir/test/Target/DXSA/hlsl/sample_cmp1.test | 38 +++ mlir/test/Target/DXSA/hlsl/sample_cmp2.test | 31 +++ mlir/test/Target/DXSA/hlsl/sample_grad1.test | 35 +++ mlir/test/Target/DXSA/hlsl/sample_l1.test | 42 +++ mlir/test/Target/DXSA/hlsl/samplecount.test | 13 + mlir/test/Target/DXSA/hlsl/samplepos.test | 34 +++ mlir/test/Target/DXSA/hlsl/saturate1.test | 10 + mlir/test/Target/DXSA/hlsl/shift1.test | 23 ++ mlir/test/Target/DXSA/hlsl/sincos.test | 15 ++ mlir/test/Target/DXSA/hlsl/snorm1.test | 16 ++ mlir/test/Target/DXSA/hlsl/srv_ms_load1.test | 42 +++ .../Target/DXSA/hlsl/srv_typed_load1.test | 38 +++ .../Target/DXSA/hlsl/srv_typed_load2.test | 21 ++ mlir/test/Target/DXSA/hlsl/struct_buf1.test | 252 ++++++++++++++++++ mlir/test/Target/DXSA/hlsl/sub1.test | 38 +++ mlir/test/Target/DXSA/hlsl/switch1.test | 25 ++ mlir/test/Target/DXSA/hlsl/switch2.test | 36 +++ mlir/test/Target/DXSA/hlsl/switch3.test | 46 ++++ mlir/test/Target/DXSA/hlsl/swizzle1.test | 15 ++ mlir/test/Target/DXSA/hlsl/temp1.test | 13 + mlir/test/Target/DXSA/hlsl/temp2.test | 13 + .../Target/DXSA/hlsl/uav_counter_dec.test | 10 + .../Target/DXSA/hlsl/uav_counter_inc.test | 10 + mlir/test/Target/DXSA/hlsl/uav_raw1.test | 31 +++ .../DXSA/hlsl/uav_typed_load_store1.test | 31 +++ .../DXSA/hlsl/uav_typed_load_store2.test | 38 +++ mlir/test/Target/DXSA/hlsl/ubfeu16.test | 14 + 266 files changed, 3880 insertions(+) create mode 100644 mlir/test/Target/DXSA/asm/call2.test create mode 100644 mlir/test/Target/DXSA/asm/cs3.test create mode 100644 mlir/test/Target/DXSA/asm/cyclecounter.test create mode 100644 mlir/test/Target/DXSA/asm/hs3.test create mode 100644 mlir/test/Target/DXSA/asm/indexabletemp4.test create mode 100644 mlir/test/Target/DXSA/asm/indexabletemp6.test create mode 100644 mlir/test/Target/DXSA/asm/inputs/call2.shex create mode 100644 mlir/test/Target/DXSA/asm/inputs/cs3.shex create mode 100644 mlir/test/Target/DXSA/asm/inputs/cyclecounter.shex create mode 100644 mlir/test/Target/DXSA/asm/inputs/hs3.shex create mode 100644 mlir/test/Target/DXSA/asm/inputs/indexabletemp4.shex create mode 100644 mlir/test/Target/DXSA/asm/inputs/indexabletemp6.shex create mode 100644 mlir/test/Target/DXSA/hlsl/abs1.test create mode 100644 mlir/test/Target/DXSA/hlsl/abs2.test create mode 100644 mlir/test/Target/DXSA/hlsl/atomics.test create mode 100644 mlir/test/Target/DXSA/hlsl/bad_ftoi.test create mode 100644 mlir/test/Target/DXSA/hlsl/binary1.test create mode 100644 mlir/test/Target/DXSA/hlsl/bool1.test create mode 100644 mlir/test/Target/DXSA/hlsl/bool2.test create mode 100644 mlir/test/Target/DXSA/hlsl/bufinfo.test create mode 100644 mlir/test/Target/DXSA/hlsl/calc_lod.test create mode 100644 mlir/test/Target/DXSA/hlsl/call1.test create mode 100644 mlir/test/Target/DXSA/hlsl/call3.test create mode 100644 mlir/test/Target/DXSA/hlsl/cast1.test create mode 100644 mlir/test/Target/DXSA/hlsl/cast2.test create mode 100644 mlir/test/Target/DXSA/hlsl/cast3.test create mode 100644 mlir/test/Target/DXSA/hlsl/cast4.test create mode 100644 mlir/test/Target/DXSA/hlsl/cast5.test create mode 100644 mlir/test/Target/DXSA/hlsl/cast6.test create mode 100644 mlir/test/Target/DXSA/hlsl/cbuffer1.50.test create mode 100644 mlir/test/Target/DXSA/hlsl/cbuffer1.51.test create mode 100644 mlir/test/Target/DXSA/hlsl/cbuffer2.50.test create mode 100644 mlir/test/Target/DXSA/hlsl/cbuffer2.51.test create mode 100644 mlir/test/Target/DXSA/hlsl/cbuffer3.50.test create mode 100644 mlir/test/Target/DXSA/hlsl/cbuffer3.51.test create mode 100644 mlir/test/Target/DXSA/hlsl/cmp1.test create mode 100644 mlir/test/Target/DXSA/hlsl/constoperand1.test create mode 100644 mlir/test/Target/DXSA/hlsl/cs1.test create mode 100644 mlir/test/Target/DXSA/hlsl/cs2.test create mode 100644 mlir/test/Target/DXSA/hlsl/cs4.test create mode 100644 mlir/test/Target/DXSA/hlsl/cs5.test create mode 100644 mlir/test/Target/DXSA/hlsl/derivatives.test create mode 100644 mlir/test/Target/DXSA/hlsl/discard.test create mode 100644 mlir/test/Target/DXSA/hlsl/dot1.test create mode 100644 mlir/test/Target/DXSA/hlsl/double1.test create mode 100644 mlir/test/Target/DXSA/hlsl/double2.test create mode 100644 mlir/test/Target/DXSA/hlsl/double3.test create mode 100644 mlir/test/Target/DXSA/hlsl/double4.test create mode 100644 mlir/test/Target/DXSA/hlsl/double5.test create mode 100644 mlir/test/Target/DXSA/hlsl/double6.test create mode 100644 mlir/test/Target/DXSA/hlsl/ds1.test create mode 100644 mlir/test/Target/DXSA/hlsl/empty.test create mode 100644 mlir/test/Target/DXSA/hlsl/eval.test create mode 100644 mlir/test/Target/DXSA/hlsl/f32f16.test create mode 100644 mlir/test/Target/DXSA/hlsl/gather.test create mode 100644 mlir/test/Target/DXSA/hlsl/gather_cmp.test create mode 100644 mlir/test/Target/DXSA/hlsl/gather_po.test create mode 100644 mlir/test/Target/DXSA/hlsl/gather_po_cmp.test create mode 100644 mlir/test/Target/DXSA/hlsl/getdim.test create mode 100644 mlir/test/Target/DXSA/hlsl/gs1.test create mode 100644 mlir/test/Target/DXSA/hlsl/gs2.test create mode 100644 mlir/test/Target/DXSA/hlsl/half_rcp.test create mode 100644 mlir/test/Target/DXSA/hlsl/hs1.test create mode 100644 mlir/test/Target/DXSA/hlsl/hs2.test create mode 100644 mlir/test/Target/DXSA/hlsl/icb1.test create mode 100644 mlir/test/Target/DXSA/hlsl/if1.test create mode 100644 mlir/test/Target/DXSA/hlsl/if2.test create mode 100644 mlir/test/Target/DXSA/hlsl/if3.test create mode 100644 mlir/test/Target/DXSA/hlsl/if4.test create mode 100644 mlir/test/Target/DXSA/hlsl/if5.test create mode 100644 mlir/test/Target/DXSA/hlsl/indexableinput1.test create mode 100644 mlir/test/Target/DXSA/hlsl/indexableinput2.test create mode 100644 mlir/test/Target/DXSA/hlsl/indexableoutput1.test create mode 100644 mlir/test/Target/DXSA/hlsl/indexabletemp1.test create mode 100644 mlir/test/Target/DXSA/hlsl/indexabletemp2.test create mode 100644 mlir/test/Target/DXSA/hlsl/indexabletemp3.test create mode 100644 mlir/test/Target/DXSA/hlsl/indexabletemp5.test create mode 100644 mlir/test/Target/DXSA/hlsl/input1.test create mode 100644 mlir/test/Target/DXSA/hlsl/input2.test create mode 100644 mlir/test/Target/DXSA/hlsl/input3.test create mode 100644 mlir/test/Target/DXSA/hlsl/inputs/abs1.shex create mode 100644 mlir/test/Target/DXSA/hlsl/inputs/abs2.shex create mode 100644 mlir/test/Target/DXSA/hlsl/inputs/atomics.shex create mode 100644 mlir/test/Target/DXSA/hlsl/inputs/bad_ftoi.shex create mode 100644 mlir/test/Target/DXSA/hlsl/inputs/binary1.shex create mode 100644 mlir/test/Target/DXSA/hlsl/inputs/bool1.shex create mode 100644 mlir/test/Target/DXSA/hlsl/inputs/bool2.shex create mode 100644 mlir/test/Target/DXSA/hlsl/inputs/bufinfo.shex create mode 100644 mlir/test/Target/DXSA/hlsl/inputs/calc_lod.shex create mode 100644 mlir/test/Target/DXSA/hlsl/inputs/call1.shex create mode 100644 mlir/test/Target/DXSA/hlsl/inputs/call3.shex create mode 100644 mlir/test/Target/DXSA/hlsl/inputs/cast1.shex create mode 100644 mlir/test/Target/DXSA/hlsl/inputs/cast2.shex create mode 100644 mlir/test/Target/DXSA/hlsl/inputs/cast3.shex create mode 100644 mlir/test/Target/DXSA/hlsl/inputs/cast4.shex create mode 100644 mlir/test/Target/DXSA/hlsl/inputs/cast5.shex create mode 100644 mlir/test/Target/DXSA/hlsl/inputs/cast6.shex create mode 100644 mlir/test/Target/DXSA/hlsl/inputs/cbuffer1.50.shex create mode 100644 mlir/test/Target/DXSA/hlsl/inputs/cbuffer1.51.shex create mode 100644 mlir/test/Target/DXSA/hlsl/inputs/cbuffer2.50.shex create mode 100644 mlir/test/Target/DXSA/hlsl/inputs/cbuffer2.51.shex create mode 100644 mlir/test/Target/DXSA/hlsl/inputs/cbuffer3.50.shex create mode 100644 mlir/test/Target/DXSA/hlsl/inputs/cbuffer3.51.shex create mode 100644 mlir/test/Target/DXSA/hlsl/inputs/cmp1.shex create mode 100644 mlir/test/Target/DXSA/hlsl/inputs/constoperand1.shex create mode 100644 mlir/test/Target/DXSA/hlsl/inputs/cs1.shex create mode 100644 mlir/test/Target/DXSA/hlsl/inputs/cs2.shex create mode 100644 mlir/test/Target/DXSA/hlsl/inputs/cs4.shex create mode 100644 mlir/test/Target/DXSA/hlsl/inputs/cs5.shex create mode 100644 mlir/test/Target/DXSA/hlsl/inputs/derivatives.shex create mode 100644 mlir/test/Target/DXSA/hlsl/inputs/discard.shex create mode 100644 mlir/test/Target/DXSA/hlsl/inputs/dot1.shex create mode 100644 mlir/test/Target/DXSA/hlsl/inputs/double1.shex create mode 100644 mlir/test/Target/DXSA/hlsl/inputs/double2.shex create mode 100644 mlir/test/Target/DXSA/hlsl/inputs/double3.shex create mode 100644 mlir/test/Target/DXSA/hlsl/inputs/double4.shex create mode 100644 mlir/test/Target/DXSA/hlsl/inputs/double5.shex create mode 100644 mlir/test/Target/DXSA/hlsl/inputs/double6.shex create mode 100644 mlir/test/Target/DXSA/hlsl/inputs/ds1.shex create mode 100644 mlir/test/Target/DXSA/hlsl/inputs/empty.shex create mode 100644 mlir/test/Target/DXSA/hlsl/inputs/eval.shex create mode 100644 mlir/test/Target/DXSA/hlsl/inputs/f32f16.shex create mode 100644 mlir/test/Target/DXSA/hlsl/inputs/gather.shex create mode 100644 mlir/test/Target/DXSA/hlsl/inputs/gather_cmp.shex create mode 100644 mlir/test/Target/DXSA/hlsl/inputs/gather_po.shex create mode 100644 mlir/test/Target/DXSA/hlsl/inputs/gather_po_cmp.shex create mode 100644 mlir/test/Target/DXSA/hlsl/inputs/getdim.shex create mode 100644 mlir/test/Target/DXSA/hlsl/inputs/gs1.shex create mode 100644 mlir/test/Target/DXSA/hlsl/inputs/gs2.shex create mode 100644 mlir/test/Target/DXSA/hlsl/inputs/half_rcp.shex create mode 100644 mlir/test/Target/DXSA/hlsl/inputs/hs1.shex create mode 100644 mlir/test/Target/DXSA/hlsl/inputs/hs2.shex create mode 100644 mlir/test/Target/DXSA/hlsl/inputs/icb1.shex create mode 100644 mlir/test/Target/DXSA/hlsl/inputs/if1.shex create mode 100644 mlir/test/Target/DXSA/hlsl/inputs/if2.shex create mode 100644 mlir/test/Target/DXSA/hlsl/inputs/if3.shex create mode 100644 mlir/test/Target/DXSA/hlsl/inputs/if4.shex create mode 100644 mlir/test/Target/DXSA/hlsl/inputs/if5.shex create mode 100644 mlir/test/Target/DXSA/hlsl/inputs/indexableinput1.shex create mode 100644 mlir/test/Target/DXSA/hlsl/inputs/indexableinput2.shex create mode 100644 mlir/test/Target/DXSA/hlsl/inputs/indexableoutput1.shex create mode 100644 mlir/test/Target/DXSA/hlsl/inputs/indexabletemp1.shex create mode 100644 mlir/test/Target/DXSA/hlsl/inputs/indexabletemp2.shex create mode 100644 mlir/test/Target/DXSA/hlsl/inputs/indexabletemp3.shex create mode 100644 mlir/test/Target/DXSA/hlsl/inputs/indexabletemp5.shex create mode 100644 mlir/test/Target/DXSA/hlsl/inputs/input1.shex create mode 100644 mlir/test/Target/DXSA/hlsl/inputs/input2.shex create mode 100644 mlir/test/Target/DXSA/hlsl/inputs/input3.shex create mode 100644 mlir/test/Target/DXSA/hlsl/inputs/interface1.shex create mode 100644 mlir/test/Target/DXSA/hlsl/inputs/liveness1.shex create mode 100644 mlir/test/Target/DXSA/hlsl/inputs/loop1.shex create mode 100644 mlir/test/Target/DXSA/hlsl/inputs/loop2.shex create mode 100644 mlir/test/Target/DXSA/hlsl/inputs/loop3.shex create mode 100644 mlir/test/Target/DXSA/hlsl/inputs/loop4.shex create mode 100644 mlir/test/Target/DXSA/hlsl/inputs/loop5.shex create mode 100644 mlir/test/Target/DXSA/hlsl/inputs/minprec1.shex create mode 100644 mlir/test/Target/DXSA/hlsl/inputs/minprec2.shex create mode 100644 mlir/test/Target/DXSA/hlsl/inputs/minprec3.shex create mode 100644 mlir/test/Target/DXSA/hlsl/inputs/minprec4.shex create mode 100644 mlir/test/Target/DXSA/hlsl/inputs/minprec5.shex create mode 100644 mlir/test/Target/DXSA/hlsl/inputs/minprec6.shex create mode 100644 mlir/test/Target/DXSA/hlsl/inputs/minprec7.shex create mode 100644 mlir/test/Target/DXSA/hlsl/inputs/neg1.shex create mode 100644 mlir/test/Target/DXSA/hlsl/inputs/neg2.shex create mode 100644 mlir/test/Target/DXSA/hlsl/inputs/negabs1.shex create mode 100644 mlir/test/Target/DXSA/hlsl/inputs/nonuniform1.shex create mode 100644 mlir/test/Target/DXSA/hlsl/inputs/output1.shex create mode 100644 mlir/test/Target/DXSA/hlsl/inputs/output2.shex create mode 100644 mlir/test/Target/DXSA/hlsl/inputs/output3.shex create mode 100644 mlir/test/Target/DXSA/hlsl/inputs/output4.shex create mode 100644 mlir/test/Target/DXSA/hlsl/inputs/passthrough1.shex create mode 100644 mlir/test/Target/DXSA/hlsl/inputs/passthrough2.shex create mode 100644 mlir/test/Target/DXSA/hlsl/inputs/precise1.shex create mode 100644 mlir/test/Target/DXSA/hlsl/inputs/raw_buf1.shex create mode 100644 mlir/test/Target/DXSA/hlsl/inputs/rcp1.shex create mode 100644 mlir/test/Target/DXSA/hlsl/inputs/redundantinput1.shex create mode 100644 mlir/test/Target/DXSA/hlsl/inputs/sample1.shex create mode 100644 mlir/test/Target/DXSA/hlsl/inputs/sample2.shex create mode 100644 mlir/test/Target/DXSA/hlsl/inputs/sample3.shex create mode 100644 mlir/test/Target/DXSA/hlsl/inputs/sample_b1.shex create mode 100644 mlir/test/Target/DXSA/hlsl/inputs/sample_cmp1.shex create mode 100644 mlir/test/Target/DXSA/hlsl/inputs/sample_cmp2.shex create mode 100644 mlir/test/Target/DXSA/hlsl/inputs/sample_grad1.shex create mode 100644 mlir/test/Target/DXSA/hlsl/inputs/sample_l1.shex create mode 100644 mlir/test/Target/DXSA/hlsl/inputs/samplecount.shex create mode 100644 mlir/test/Target/DXSA/hlsl/inputs/samplepos.shex create mode 100644 mlir/test/Target/DXSA/hlsl/inputs/saturate1.shex create mode 100644 mlir/test/Target/DXSA/hlsl/inputs/shift1.shex create mode 100644 mlir/test/Target/DXSA/hlsl/inputs/sincos.shex create mode 100644 mlir/test/Target/DXSA/hlsl/inputs/snorm1.shex create mode 100644 mlir/test/Target/DXSA/hlsl/inputs/srv_ms_load1.shex create mode 100644 mlir/test/Target/DXSA/hlsl/inputs/srv_typed_load1.shex create mode 100644 mlir/test/Target/DXSA/hlsl/inputs/srv_typed_load2.shex create mode 100644 mlir/test/Target/DXSA/hlsl/inputs/struct_buf1.shex create mode 100644 mlir/test/Target/DXSA/hlsl/inputs/sub1.shex create mode 100644 mlir/test/Target/DXSA/hlsl/inputs/switch1.shex create mode 100644 mlir/test/Target/DXSA/hlsl/inputs/switch2.shex create mode 100644 mlir/test/Target/DXSA/hlsl/inputs/switch3.shex create mode 100644 mlir/test/Target/DXSA/hlsl/inputs/swizzle1.shex create mode 100644 mlir/test/Target/DXSA/hlsl/inputs/temp1.shex create mode 100644 mlir/test/Target/DXSA/hlsl/inputs/temp2.shex create mode 100644 mlir/test/Target/DXSA/hlsl/inputs/uav_counter_dec.shex create mode 100644 mlir/test/Target/DXSA/hlsl/inputs/uav_counter_inc.shex create mode 100644 mlir/test/Target/DXSA/hlsl/inputs/uav_raw1.shex create mode 100644 mlir/test/Target/DXSA/hlsl/inputs/uav_typed_load_store1.shex create mode 100644 mlir/test/Target/DXSA/hlsl/inputs/uav_typed_load_store2.shex create mode 100644 mlir/test/Target/DXSA/hlsl/inputs/ubfeu16.shex create mode 100644 mlir/test/Target/DXSA/hlsl/interface1.test create mode 100644 mlir/test/Target/DXSA/hlsl/liveness1.test create mode 100644 mlir/test/Target/DXSA/hlsl/loop1.test create mode 100644 mlir/test/Target/DXSA/hlsl/loop2.test create mode 100644 mlir/test/Target/DXSA/hlsl/loop3.test create mode 100644 mlir/test/Target/DXSA/hlsl/loop4.test create mode 100644 mlir/test/Target/DXSA/hlsl/loop5.test create mode 100644 mlir/test/Target/DXSA/hlsl/minprec1.test create mode 100644 mlir/test/Target/DXSA/hlsl/minprec2.test create mode 100644 mlir/test/Target/DXSA/hlsl/minprec3.test create mode 100644 mlir/test/Target/DXSA/hlsl/minprec4.test create mode 100644 mlir/test/Target/DXSA/hlsl/minprec5.test create mode 100644 mlir/test/Target/DXSA/hlsl/minprec6.test create mode 100644 mlir/test/Target/DXSA/hlsl/minprec7.test create mode 100644 mlir/test/Target/DXSA/hlsl/neg1.test create mode 100644 mlir/test/Target/DXSA/hlsl/neg2.test create mode 100644 mlir/test/Target/DXSA/hlsl/negabs1.test create mode 100644 mlir/test/Target/DXSA/hlsl/nonuniform1.test create mode 100644 mlir/test/Target/DXSA/hlsl/output1.test create mode 100644 mlir/test/Target/DXSA/hlsl/output2.test create mode 100644 mlir/test/Target/DXSA/hlsl/output3.test create mode 100644 mlir/test/Target/DXSA/hlsl/output4.test create mode 100644 mlir/test/Target/DXSA/hlsl/passthrough1.test create mode 100644 mlir/test/Target/DXSA/hlsl/passthrough2.test create mode 100644 mlir/test/Target/DXSA/hlsl/precise1.test create mode 100644 mlir/test/Target/DXSA/hlsl/raw_buf1.test create mode 100644 mlir/test/Target/DXSA/hlsl/rcp1.test create mode 100644 mlir/test/Target/DXSA/hlsl/redundantinput1.test create mode 100644 mlir/test/Target/DXSA/hlsl/sample1.test create mode 100644 mlir/test/Target/DXSA/hlsl/sample2.test create mode 100644 mlir/test/Target/DXSA/hlsl/sample3.test create mode 100644 mlir/test/Target/DXSA/hlsl/sample_b1.test create mode 100644 mlir/test/Target/DXSA/hlsl/sample_cmp1.test create mode 100644 mlir/test/Target/DXSA/hlsl/sample_cmp2.test create mode 100644 mlir/test/Target/DXSA/hlsl/sample_grad1.test create mode 100644 mlir/test/Target/DXSA/hlsl/sample_l1.test create mode 100644 mlir/test/Target/DXSA/hlsl/samplecount.test create mode 100644 mlir/test/Target/DXSA/hlsl/samplepos.test create mode 100644 mlir/test/Target/DXSA/hlsl/saturate1.test create mode 100644 mlir/test/Target/DXSA/hlsl/shift1.test create mode 100644 mlir/test/Target/DXSA/hlsl/sincos.test create mode 100644 mlir/test/Target/DXSA/hlsl/snorm1.test create mode 100644 mlir/test/Target/DXSA/hlsl/srv_ms_load1.test create mode 100644 mlir/test/Target/DXSA/hlsl/srv_typed_load1.test create mode 100644 mlir/test/Target/DXSA/hlsl/srv_typed_load2.test create mode 100644 mlir/test/Target/DXSA/hlsl/struct_buf1.test create mode 100644 mlir/test/Target/DXSA/hlsl/sub1.test create mode 100644 mlir/test/Target/DXSA/hlsl/switch1.test create mode 100644 mlir/test/Target/DXSA/hlsl/switch2.test create mode 100644 mlir/test/Target/DXSA/hlsl/switch3.test create mode 100644 mlir/test/Target/DXSA/hlsl/swizzle1.test create mode 100644 mlir/test/Target/DXSA/hlsl/temp1.test create mode 100644 mlir/test/Target/DXSA/hlsl/temp2.test create mode 100644 mlir/test/Target/DXSA/hlsl/uav_counter_dec.test create mode 100644 mlir/test/Target/DXSA/hlsl/uav_counter_inc.test create mode 100644 mlir/test/Target/DXSA/hlsl/uav_raw1.test create mode 100644 mlir/test/Target/DXSA/hlsl/uav_typed_load_store1.test create mode 100644 mlir/test/Target/DXSA/hlsl/uav_typed_load_store2.test create mode 100644 mlir/test/Target/DXSA/hlsl/ubfeu16.test diff --git a/mlir/test/Target/DXSA/asm/call2.test b/mlir/test/Target/DXSA/asm/call2.test new file mode 100644 index 000000000000..9bc015d2b9ad --- /dev/null +++ b/mlir/test/Target/DXSA/asm/call2.test @@ -0,0 +1,37 @@ +// RUN: mlir-translate --import-dxsa-bin %S/inputs/call2.shex | FileCheck %s +// NOTE: Assertions have been autogenerated by utils/generate-test-checks.py + + +// CHECK-LABEL: dxsa.dcl_global_flags +// CHECK: dxsa.dcl_input_ps linear v<0, > +// CHECK: dxsa.dcl_input_ps constant v<1, > +// CHECK: dxsa.dcl_output o<0, > +// CHECK: dxsa.dcl_temps 1 +// CHECK: dxsa.mov r<0, >, v<1, > +// CHECK: dxsa.call label<0> +// CHECK: dxsa.callc_nz r<0, >, label<0> +// CHECK: %[[INDEX_0:.*]] = dxsa.index.imm {imm = 1 : i32} +// CHECK: %[[OPERAND_0:.*]] = dxsa.operand %[[INDEX_0]] {num_components = 4 : i32, one = 0 : i32, type = 1 : i32} +// CHECK: dxsa.instruction "switch" %[[OPERAND_0]] +// CHECK: dxsa.case l(0x1) +// CHECK: dxsa.call label<2> +// CHECK: dxsa.callc_nz r<0, >, label<1> +// CHECK: dxsa.break +// CHECK: dxsa.default +// CHECK: dxsa.callc_nz r<0, >, label<2> +// CHECK: dxsa.break +// CHECK: dxsa.case l(0x2) +// CHECK: dxsa.break +// CHECK: dxsa.endswitch +// CHECK: dxsa.add o<0, >, r<0, >, l(0x3F800000) +// CHECK: dxsa.ret +// CHECK: dxsa.label label<0> +// CHECK: dxsa.mov r<0, >, l(0x40A00000) +// CHECK: dxsa.ret +// CHECK: dxsa.label label<1> +// CHECK: dxsa.mov r<0, >, v<0, > +// CHECK: dxsa.ret +// CHECK: dxsa.label label<2> +// CHECK: dxsa.mov r<0, >, l(0x40400000) +// CHECK: dxsa.ret + diff --git a/mlir/test/Target/DXSA/asm/cs3.test b/mlir/test/Target/DXSA/asm/cs3.test new file mode 100644 index 000000000000..91ffb8cc1011 --- /dev/null +++ b/mlir/test/Target/DXSA/asm/cs3.test @@ -0,0 +1,42 @@ +// RUN: mlir-translate --import-dxsa-bin %S/inputs/cs3.shex | FileCheck %s +// NOTE: Assertions have been autogenerated by utils/generate-test-checks.py + + +// CHECK-LABEL: dxsa.dcl_global_flags +// CHECK: dxsa.dcl_constant_buffer , +// CHECK: dxsa.dcl_input vThreadIDInGroup<> +// CHECK: dxsa.dcl_temps 3 +// CHECK: dxsa.dcl_tgsm_raw g<0>, 1024 +// CHECK: dxsa.dcl_thread_group +// CHECK: dxsa.ishl r<0, >, vThreadIDInGroup<>, l(0x2) +// CHECK: %[[INDEX_0:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_0:.*]] = dxsa.operand %[[INDEX_0]] {mask = 48 : i32, num_components = 4 : i32, type = 31 : i32} +// CHECK: %[[INDEX_1:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_1:.*]] = dxsa.operand %[[INDEX_1]] {num_components = 4 : i32, one = 0 : i32, type = 0 : i32} +// CHECK: %[[INDEX_2:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[INDEX_3:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_2:.*]] = dxsa.operand %[[INDEX_2]], %[[INDEX_3]] {num_components = 4 : i32, swizzle = dense<[3, 2, 1, 0]> : vector<4xi32>, type = 8 : i32} +// CHECK: dxsa.instruction "store_raw" %[[OPERAND_0]], %[[OPERAND_1]], %[[OPERAND_2]] +// CHECK: dxsa.sync +// CHECK: dxsa.sync +// CHECK: dxsa.sync +// CHECK: dxsa.sync +// CHECK: dxsa.sync +// CHECK: dxsa.sync +// CHECK: dxsa.sync +// CHECK: dxsa.sync +// CHECK: dxsa.sync +// CHECK: dxsa.sync +// CHECK: %[[INDEX_4:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_3:.*]] = dxsa.operand %[[INDEX_4]] {mask = 80 : i32, num_components = 4 : i32, type = 0 : i32} +// CHECK: %[[INDEX_5:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_4:.*]] = dxsa.operand %[[INDEX_5]] {num_components = 4 : i32, one = 0 : i32, type = 0 : i32} +// CHECK: %[[INDEX_6:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_5:.*]] = dxsa.operand %[[INDEX_6]] {num_components = 4 : i32, swizzle = dense<[2, 0, 3, 1]> : vector<4xi32>, type = 31 : i32} +// CHECK: dxsa.instruction "ld_raw" %[[OPERAND_3]], %[[OPERAND_4]], %[[OPERAND_5]] +// CHECK: dxsa.imm_atomic_iadd r<2, >, g<0>, r<1, >, vThreadIDInGroup<> +// CHECK: dxsa.atomic_or g<0>, r<1, >, vThreadIDInGroup<> +// CHECK: dxsa.atomic_cmp_store g<0>, r<1, >, vThreadIDInGroup<>, vThreadIDInGroup<> +// CHECK: dxsa.imm_atomic_cmp_exch r<1, >, g<0>, r<1, >, vThreadIDInGroup<>, vThreadIDInGroup<> +// CHECK: dxsa.ret + diff --git a/mlir/test/Target/DXSA/asm/cyclecounter.test b/mlir/test/Target/DXSA/asm/cyclecounter.test new file mode 100644 index 000000000000..696f82ed6d2f --- /dev/null +++ b/mlir/test/Target/DXSA/asm/cyclecounter.test @@ -0,0 +1,11 @@ +// RUN: mlir-translate --import-dxsa-bin %S/inputs/cyclecounter.shex | FileCheck %s +// NOTE: Assertions have been autogenerated by utils/generate-test-checks.py + + +// CHECK-LABEL: dxsa.dcl_temps 1 +// CHECK: dxsa.dcl_output o<0> +// CHECK: dxsa.dcl_input cycleCounter<> +// CHECK: dxsa.mov r<0>, l(0x0) +// CHECK: dxsa.mov r<0, >, cycleCounter<> +// CHECK: dxsa.mov o<0>, r<0> + diff --git a/mlir/test/Target/DXSA/asm/hs3.test b/mlir/test/Target/DXSA/asm/hs3.test new file mode 100644 index 000000000000..64f8bec917e3 --- /dev/null +++ b/mlir/test/Target/DXSA/asm/hs3.test @@ -0,0 +1,93 @@ +// RUN: mlir-translate --import-dxsa-bin %S/inputs/hs3.shex | FileCheck %s +// NOTE: Assertions have been autogenerated by utils/generate-test-checks.py + + +// CHECK-LABEL: dxsa.hs_decls +// CHECK: dxsa.dcl_input_control_point_count 4 +// CHECK: dxsa.dcl_output_control_point_count 32 +// CHECK: dxsa.dcl_tessellator_domain domain_quad +// CHECK: dxsa.dcl_tessellator_partitioning partitioning_fractional_odd +// CHECK: dxsa.dcl_tessellator_output_primitive output_triangle_cw +// CHECK: dxsa.dcl_hs_max_tessfactor 6.400000e+01 +// CHECK: dxsa.hs_control_point_phase +// CHECK: dxsa.dcl_input v<[4, 0]> +// CHECK: dxsa.dcl_input v<[4, 1], > +// CHECK: dxsa.dcl_input v<[4, 2], > +// CHECK: dxsa.dcl_input vOutputControlPointID +// CHECK: dxsa.dcl_input vPrim +// CHECK: dxsa.dcl_output o<0> +// CHECK: dxsa.dcl_output o<1, > +// CHECK: dxsa.dcl_output o<2, > +// CHECK: dxsa.dcl_temps 1 +// CHECK: dxsa.udiv null, r<0, >, vOutputControlPointID, l(0x4) +// CHECK: dxsa.mov o<0>, v<[r<0, >, 0]> +// CHECK: dxsa.mov o<1, >, v<[r<0, >, 1], > +// CHECK: dxsa.mov o<2, >, v<[r<0, >, 2], > +// CHECK: dxsa.hs_fork_phase +// CHECK: dxsa.dcl_input vicp<[4, 0]> +// CHECK: dxsa.dcl_input vicp<[4, 1], > +// CHECK: dxsa.dcl_input vicp<[4, 2], > +// CHECK: dxsa.dcl_input vocp<[32, 0]> +// CHECK: dxsa.dcl_input vocp<[32, 1], > +// CHECK: dxsa.dcl_input vocp<[32, 2], > +// CHECK: dxsa.dcl_hs_fork_phase_instance_count 4 +// CHECK: dxsa.dcl_input vForkInstanceID +// CHECK: dxsa.dcl_input vPrim +// CHECK: dxsa.dcl_index_range o<0>, 4 +// CHECK: dxsa.dcl_temps 1 +// CHECK: dxsa.dcl_indexable_temp x<0>[4], 1 +// CHECK: dxsa.dcl_output_siv o<0, >, +// CHECK: dxsa.dcl_output_siv o<1, >, +// CHECK: dxsa.dcl_output_siv o<2, >, +// CHECK: dxsa.dcl_output_siv o<3, >, +// CHECK: dxsa.mov x<[0, 0], >, l(0x40000000) +// CHECK: dxsa.mov x<[0, 1], >, l(0x40800000) +// CHECK: dxsa.mov x<[0, 2], >, l(0x41700000) +// CHECK: dxsa.mov x<[0, 3], >, l(0x40C00000) +// CHECK: dxsa.mov r<0, >, vForkInstanceID +// CHECK: dxsa.mov o>, >, x<[0, r<0, >], > +// CHECK: dxsa.hs_fork_phase +// CHECK: dxsa.dcl_input vicp<[4, 0]> +// CHECK: dxsa.dcl_input vicp<[4, 1], > +// CHECK: dxsa.dcl_input vicp<[4, 2], > +// CHECK: dxsa.dcl_input vocp<[32, 0]> +// CHECK: dxsa.dcl_input vocp<[32, 1], > +// CHECK: dxsa.dcl_input vocp<[32, 2], > +// CHECK: dxsa.dcl_hs_fork_phase_instance_count 4 +// CHECK: dxsa.dcl_input vForkInstanceID +// CHECK: dxsa.dcl_input vPrim +// CHECK: dxsa.dcl_index_range o<0>, 4 +// CHECK: dxsa.dcl_temps 1 +// CHECK: dxsa.dcl_indexable_temp x<0>[4], 1 +// CHECK: dxsa.dcl_output o<0, > +// CHECK: dxsa.dcl_output o<1, > +// CHECK: dxsa.dcl_output o<2, > +// CHECK: dxsa.dcl_output o<3, > +// CHECK: dxsa.mov x<[0, 0], >, l(0x41400000) +// CHECK: dxsa.mov x<[0, 1], >, l(0x42000000) +// CHECK: dxsa.mov x<[0, 2], >, l(0x41700000) +// CHECK: dxsa.mov x<[0, 3], >, l(0x40A00000) +// CHECK: dxsa.mov r<0, >, vForkInstanceID +// CHECK: dxsa.mov o>, >, x<[0, r<0, >], > +// CHECK: dxsa.hs_join_phase +// CHECK: dxsa.dcl_input vicp<[4, 0]> +// CHECK: dxsa.dcl_input vicp<[4, 1], > +// CHECK: dxsa.dcl_input vicp<[4, 2], > +// CHECK: dxsa.dcl_input vocp<[32, 0]> +// CHECK: dxsa.dcl_input vocp<[32, 1], > +// CHECK: dxsa.dcl_input vocp<[32, 2], > +// CHECK: dxsa.dcl_input vpc<0, > +// CHECK: dxsa.dcl_input vpc<1, > +// CHECK: dxsa.dcl_input vpc<2, > +// CHECK: dxsa.dcl_input vpc<3, > +// CHECK: dxsa.dcl_index_range vpc<0>, 4 +// CHECK: dxsa.dcl_output_siv o<4, >, +// CHECK: dxsa.dcl_output_siv o<5, >, +// CHECK: dxsa.dcl_output o<4, > +// CHECK: dxsa.dcl_output o<5, > +// CHECK: dxsa.dcl_input vPrim +// CHECK: dxsa.mov o<4, >, l(0x41400000) +// CHECK: dxsa.mov o<5, >, l(0x40C00000) +// CHECK: dxsa.mov o<4, >, l(0x0) +// CHECK: dxsa.mov o<5, >, l(0x0) + diff --git a/mlir/test/Target/DXSA/asm/indexabletemp4.test b/mlir/test/Target/DXSA/asm/indexabletemp4.test new file mode 100644 index 000000000000..61ab0a2240e1 --- /dev/null +++ b/mlir/test/Target/DXSA/asm/indexabletemp4.test @@ -0,0 +1,19 @@ +// RUN: mlir-translate --import-dxsa-bin %S/inputs/indexabletemp4.shex | FileCheck %s +// NOTE: Assertions have been autogenerated by utils/generate-test-checks.py + + +// CHECK-LABEL: dxsa.dcl_global_flags +// CHECK: dxsa.dcl_constant_buffer , +// CHECK: dxsa.dcl_input_ps constant v<1, > +// CHECK: dxsa.dcl_input_ps constant v<1, > +// CHECK: dxsa.dcl_output o<0, > +// CHECK: dxsa.dcl_temps 1 +// CHECK: dxsa.dcl_indexable_temp x<0>[4], 2 +// CHECK: dxsa.mov r<0, >, v<1, > +// CHECK: dxsa.mov x<[0, 0], >, cb<[0, r<0, >], vector, > +// CHECK: dxsa.mov x<[0, 1], >, cb<[0, 4 + r<0, >], vector, > +// CHECK: dxsa.mov r<0, >, v<1, > +// CHECK: dxsa.mov x<[0, 1], >, r<0, > +// CHECK: dxsa.mov o<0, >, x<[0, 77 + x<[0, 1], >], > +// CHECK: dxsa.ret + diff --git a/mlir/test/Target/DXSA/asm/indexabletemp6.test b/mlir/test/Target/DXSA/asm/indexabletemp6.test new file mode 100644 index 000000000000..28580c33c879 --- /dev/null +++ b/mlir/test/Target/DXSA/asm/indexabletemp6.test @@ -0,0 +1,21 @@ +// RUN: mlir-translate --import-dxsa-bin %S/inputs/indexabletemp6.shex | FileCheck %s +// NOTE: Assertions have been autogenerated by utils/generate-test-checks.py + + +// CHECK-LABEL: dxsa.dcl_global_flags +// CHECK: dxsa.dcl_constant_buffer , +// CHECK: dxsa.dcl_input_ps constant v<1, > +// CHECK: dxsa.dcl_input_ps constant v<1, > +// CHECK: dxsa.dcl_output o<0, min16f, > +// CHECK: dxsa.dcl_temps 1 +// CHECK: dxsa.dcl_indexable_temp x<0>[4] +// CHECK: dxsa.mov r<0, >, v<1, > +// CHECK: dxsa.mov x<[0, 0], >, cb<[0, 4 + r<0, >], vector, > +// CHECK: dxsa.mov r<0, >, x<[0, 0], > +// CHECK: dxsa.mov x<[0, 0], min16f, >, cb<[0, r<0, >], vector, min16f, > +// CHECK: dxsa.mov x<[0, 1], min16f, >, cb<[0, 4 + r<0, >], vector, min16f, > +// CHECK: dxsa.mov r<0, >, v<1, > +// CHECK: dxsa.add x<[0, r<0, >], min16f, >, x<[0, r<0, >], min16f, >, r<0, min16f, > +// CHECK: dxsa.mov o<0, min16f, >, x<[0, r<0, >], min16f, > +// CHECK: dxsa.ret + diff --git a/mlir/test/Target/DXSA/asm/inputs/call2.shex b/mlir/test/Target/DXSA/asm/inputs/call2.shex new file mode 100644 index 0000000000000000000000000000000000000000..e0fe124cfbac3496004e6f986cad99c129b6be98 GIT binary patch literal 356 zcmZWku?oUK41L%3wA^%b5jr`Gv!mYRU?7mZ_wtfF0lb*s z9%0I8hn(2~Q;&9L9az6X{HXW`Xau_eafV{|QFR@4SQLxsVye7h5Avyc?pTL{&EMu4 z`pVqs=42P~keI@q94C6=%**N?zuT4k+1)C?4AoaPOYs`}*EI5jgxARK If1k4XtTcBLkpKVy literal 0 HcmV?d00001 diff --git a/mlir/test/Target/DXSA/asm/inputs/cs3.shex b/mlir/test/Target/DXSA/asm/inputs/cs3.shex new file mode 100644 index 0000000000000000000000000000000000000000..979c550dcb062987cd513ea67ed67d2d81bb4c3c GIT binary patch literal 324 zcmZ{gEe^s!5QV=jf2FFR2&#$zil9)WszDYMC@ev811`V?5GW7?Nk}j~6AsIpv^4}a z`F3~q&CI^tlp1qj>*H2XO%9PFaAFPKF7nuDttdW8=hZUVb{sWp!4swrpx!3b4u-08 zajsp!9~X5&p+EMKvhtCIxGWN}=!m|UiIGUfL@aS25yW6~!9uvj( ejzC_n^7iZerk>yDUFBQN6Pni3di=|o>Z?BU1t1du literal 0 HcmV?d00001 diff --git a/mlir/test/Target/DXSA/asm/inputs/cyclecounter.shex b/mlir/test/Target/DXSA/asm/inputs/cyclecounter.shex new file mode 100644 index 0000000000000000000000000000000000000000..3f883fb28ba45fe3776aba9a973d0286c9e43102 GIT binary patch literal 92 zcmWGwU|Q@)H$I430Cx5VsQ>@~ literal 0 HcmV?d00001 diff --git a/mlir/test/Target/DXSA/asm/inputs/hs3.shex b/mlir/test/Target/DXSA/asm/inputs/hs3.shex new file mode 100644 index 0000000000000000000000000000000000000000..f817cea934d42183b1444d12a2c6652ee656c946 GIT binary patch literal 1300 zcmdT@OHKko6s%?jHTc6>xiSMMAS_%Xi7bhG7rHU(4$%W}1QP!{j=&K-f@hf%Sk>K+ zX%eF=7j`nC>iv4E=5dA$rw+IS++zv%1m~U);a>Q>@_7Rqz-%~W{sPFWc8MI}i1#Ds z2#8N3XOnmXmoEG+fh!=Z%C>J7?h~s|cuK6E8}=wR1~%~t6bSW>bKHOzFn7$H%^4jn z(26xo`JBxiwd9-|IhkuHEcL&kf5X!}7(jyhyzv zjou8_JgYs%Fs=XH@2ui`3KO zE}ri6&N9Iub@j9lUg5qN7H# +// CHECK: dxsa.dcl_input_ps linear v<0, > +// CHECK: dxsa.dcl_output o<0> +// CHECK: dxsa.mov o<0>, |v<0, >| +// CHECK: dxsa.ret + diff --git a/mlir/test/Target/DXSA/hlsl/abs2.test b/mlir/test/Target/DXSA/hlsl/abs2.test new file mode 100644 index 000000000000..af85fa8cad72 --- /dev/null +++ b/mlir/test/Target/DXSA/hlsl/abs2.test @@ -0,0 +1,10 @@ +// RUN: mlir-translate --import-dxsa-bin %S/inputs/abs2.shex | FileCheck %s +// NOTE: Assertions have been autogenerated by utils/generate-test-checks.py + + +// CHECK-LABEL: dxsa.dcl_global_flags +// CHECK: dxsa.dcl_input_ps constant v<0, > +// CHECK: dxsa.dcl_output o<0> +// CHECK: dxsa.imax o<0>, -v<0, >, v<0, > +// CHECK: dxsa.ret + diff --git a/mlir/test/Target/DXSA/hlsl/atomics.test b/mlir/test/Target/DXSA/hlsl/atomics.test new file mode 100644 index 000000000000..0c3751c84187 --- /dev/null +++ b/mlir/test/Target/DXSA/hlsl/atomics.test @@ -0,0 +1,51 @@ +// RUN: mlir-translate --import-dxsa-bin %S/inputs/atomics.shex | FileCheck %s +// NOTE: Assertions have been autogenerated by utils/generate-test-checks.py + + +// CHECK-LABEL: dxsa.dcl_global_flags +// CHECK: dxsa.dcl_uav_typed , +// CHECK: dxsa.dcl_uav_raw +// CHECK: dxsa.dcl_uav_raw +// CHECK: dxsa.dcl_uav_typed , +// CHECK: dxsa.dcl_uav_typed , +// CHECK: dxsa.dcl_uav_typed , +// CHECK: dxsa.dcl_uav_typed , +// CHECK: dxsa.dcl_input_ps constant v<0> +// CHECK: dxsa.dcl_output o<0> +// CHECK: dxsa.dcl_temps 2 +// CHECK: dxsa.atomic_iadd u<[0, 0]>, v<0, >, v<0, > +// CHECK: dxsa.atomic_umin u<[0, 0]>, v<0, >, v<0, > +// CHECK: dxsa.atomic_umax u<[0, 0]>, v<0, >, v<0, > +// CHECK: dxsa.atomic_and u<[0, 0]>, v<0, >, v<0, > +// CHECK: dxsa.atomic_or u<[0, 0]>, v<0, >, v<0, > +// CHECK: dxsa.atomic_xor u<[0, 0]>, v<0, >, v<0, > +// CHECK: dxsa.imm_atomic_iadd r<0, >, u<[0, 0]>, v<0, >, v<0, > +// CHECK: dxsa.iadd r<0, >, r<0, >, v<0, > +// CHECK: dxsa.atomic_iadd u<[3, 30]>, v<0, >, r<0, > +// CHECK: dxsa.atomic_iadd u<[4, 31]>, v<0, >, r<0, > +// CHECK: dxsa.atomic_iadd u<[5, 32]>, v<0, >, r<0, > +// CHECK: %[[INDEX_0:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_0:.*]] = dxsa.operand %[[INDEX_0]] {mask = 32 : i32, num_components = 4 : i32, type = 0 : i32} +// CHECK: %[[OPERAND_1:.*]] = dxsa.operand.imm {imm = dense<30> : vector<1xi32>} +// CHECK: %[[OPERAND_2:.*]] = dxsa.operand.imm {imm = dense<2> : vector<1xi32>} +// CHECK: %[[INDEX_1:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_3:.*]] = dxsa.operand %[[INDEX_1]] {num_components = 4 : i32, one = 0 : i32, type = 1 : i32} +// CHECK: %[[OPERAND_4:.*]] = dxsa.operand.imm {imm = dense<1> : vector<1xi32>} +// CHECK: dxsa.instruction "bfi" %[[OPERAND_0]], %[[OPERAND_1]], %[[OPERAND_2]], %[[OPERAND_3]], %[[OPERAND_4]] +// CHECK: dxsa.atomic_iadd u<[6, 33 + r<0, >]>, v<0, >, r<0, > +// CHECK: dxsa.imm_atomic_cmp_exch r<0, >, u<[0, 0]>, v<0, >, v<0, >, r<0, > +// CHECK: dxsa.imm_atomic_iadd r<0, >, u<[1, 1]>, v<0, >, v<0, > +// CHECK: dxsa.iadd r<0, >, v<0, >, l(0xE) +// CHECK: dxsa.imm_atomic_iadd r<0, >, u<[2, 2 + r<0, >]>, v<0, >, v<0, > +// CHECK: dxsa.imm_atomic_umin r<0, >, u<[1, 1]>, v<0, >, v<0, > +// CHECK: dxsa.imm_atomic_umax r<0, >, u<[1, 1]>, v<0, >, v<0, > +// CHECK: dxsa.imm_atomic_and r<0, >, u<[1, 1]>, v<0, >, v<0, > +// CHECK: dxsa.imm_atomic_or r<0, >, u<[1, 1]>, v<0, >, v<0, > +// CHECK: dxsa.imm_atomic_xor r<0, >, u<[1, 1]>, v<0, >, v<0, > +// CHECK: dxsa.imm_atomic_exch r<1, >, u<[1, 1]>, v<0, >, r<0, > +// CHECK: dxsa.iadd r<0, >, r<0, >, r<1, > +// CHECK: dxsa.imm_atomic_cmp_exch r<1, >, u<[1, 1]>, v<0, >, v<0, >, r<0, > +// CHECK: dxsa.iadd r<0, >, r<0, >, r<1, > +// CHECK: dxsa.utof o<0>, r<0, > +// CHECK: dxsa.ret + diff --git a/mlir/test/Target/DXSA/hlsl/bad_ftoi.test b/mlir/test/Target/DXSA/hlsl/bad_ftoi.test new file mode 100644 index 000000000000..dfd01667850d --- /dev/null +++ b/mlir/test/Target/DXSA/hlsl/bad_ftoi.test @@ -0,0 +1,11 @@ +// RUN: mlir-translate --import-dxsa-bin %S/inputs/bad_ftoi.shex | FileCheck %s +// NOTE: Assertions have been autogenerated by utils/generate-test-checks.py + + +// CHECK-LABEL: dxsa.dcl_global_flags +// CHECK: dxsa.dcl_output o<0> +// CHECK: dxsa.ftou o<0, >, l(0x7F7FFFFF) +// CHECK: dxsa.ftou o<0, >, l(0xFF7FFFFF) +// CHECK: dxsa.ftoi o<0, >, l(0x7F7FFFFF, 0xFF7FFFFF, 0x0, 0x0) +// CHECK: dxsa.ret + diff --git a/mlir/test/Target/DXSA/hlsl/binary1.test b/mlir/test/Target/DXSA/hlsl/binary1.test new file mode 100644 index 000000000000..a7d8778e1c66 --- /dev/null +++ b/mlir/test/Target/DXSA/hlsl/binary1.test @@ -0,0 +1,17 @@ +// RUN: mlir-translate --import-dxsa-bin %S/inputs/binary1.shex | FileCheck %s +// NOTE: Assertions have been autogenerated by utils/generate-test-checks.py + + +// CHECK-LABEL: dxsa.dcl_global_flags +// CHECK: dxsa.dcl_input_ps linear v<0, > +// CHECK: dxsa.dcl_input_ps linear v<0, > +// CHECK: dxsa.dcl_input_ps linear v<0, > +// CHECK: dxsa.dcl_output o<0, > +// CHECK: dxsa.dcl_temps 1 +// CHECK: dxsa.add r<0, >, v<0, >, v<0, > +// CHECK: dxsa.div r<0, >, r<0, >, v<0, > +// CHECK: dxsa.mul r<0, >, r<0, >, v<0, > +// CHECK: dxsa.max r<0, >, r<0, >, v<0, > +// CHECK: dxsa.min o<0, >, r<0, >, v<0, > +// CHECK: dxsa.ret + diff --git a/mlir/test/Target/DXSA/hlsl/bool1.test b/mlir/test/Target/DXSA/hlsl/bool1.test new file mode 100644 index 000000000000..c0afeabf534d --- /dev/null +++ b/mlir/test/Target/DXSA/hlsl/bool1.test @@ -0,0 +1,20 @@ +// RUN: mlir-translate --import-dxsa-bin %S/inputs/bool1.shex | FileCheck %s +// NOTE: Assertions have been autogenerated by utils/generate-test-checks.py + + +// CHECK-LABEL: dxsa.dcl_global_flags +// CHECK: dxsa.dcl_input_ps constant v<0, > +// CHECK: dxsa.dcl_output o<0, > +// CHECK: dxsa.dcl_temps 1 +// CHECK: dxsa.firstbit_hi r<0, >, v<0, > +// CHECK: dxsa.iadd r<0, >, -r<0, >, l(0x1F) +// CHECK: %[[INDEX_0:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_0:.*]] = dxsa.operand %[[INDEX_0]] {mask = 16 : i32, num_components = 4 : i32, type = 2 : i32} +// CHECK: %[[INDEX_1:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_1:.*]] = dxsa.operand %[[INDEX_1]] {num_components = 4 : i32, one = 0 : i32, type = 1 : i32} +// CHECK: %[[INDEX_2:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_2:.*]] = dxsa.operand %[[INDEX_2]] {num_components = 4 : i32, one = 0 : i32, type = 0 : i32} +// CHECK: %[[OPERAND_3:.*]] = dxsa.operand.imm {imm = dense<-1> : vector<1xi32>} +// CHECK: dxsa.instruction "movc" %[[OPERAND_0]], %[[OPERAND_1]], %[[OPERAND_2]], %[[OPERAND_3]] +// CHECK: dxsa.ret + diff --git a/mlir/test/Target/DXSA/hlsl/bool2.test b/mlir/test/Target/DXSA/hlsl/bool2.test new file mode 100644 index 000000000000..8e001271f55d --- /dev/null +++ b/mlir/test/Target/DXSA/hlsl/bool2.test @@ -0,0 +1,19 @@ +// RUN: mlir-translate --import-dxsa-bin %S/inputs/bool2.shex | FileCheck %s +// NOTE: Assertions have been autogenerated by utils/generate-test-checks.py + + +// CHECK-LABEL: dxsa.dcl_global_flags +// CHECK: dxsa.dcl_input_ps linear v<0, > +// CHECK: dxsa.dcl_input_ps linear v<0, > +// CHECK: dxsa.dcl_output o<0, > +// CHECK: dxsa.dcl_temps 1 +// CHECK: dxsa.lt r<0, >, v<0, >, v<0, > +// CHECK: %[[INDEX_0:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_0:.*]] = dxsa.operand %[[INDEX_0]] {mask = 16 : i32, num_components = 4 : i32, type = 2 : i32} +// CHECK: %[[INDEX_1:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_1:.*]] = dxsa.operand %[[INDEX_1]] {num_components = 4 : i32, one = 0 : i32, type = 0 : i32} +// CHECK: %[[OPERAND_2:.*]] = dxsa.operand.imm {imm = dense<0> : vector<1xi32>} +// CHECK: %[[OPERAND_3:.*]] = dxsa.operand.imm {imm = dense<1065353216> : vector<1xi32>} +// CHECK: dxsa.instruction "movc" %[[OPERAND_0]], %[[OPERAND_1]], %[[OPERAND_2]], %[[OPERAND_3]] +// CHECK: dxsa.ret + diff --git a/mlir/test/Target/DXSA/hlsl/bufinfo.test b/mlir/test/Target/DXSA/hlsl/bufinfo.test new file mode 100644 index 000000000000..440fe0276e04 --- /dev/null +++ b/mlir/test/Target/DXSA/hlsl/bufinfo.test @@ -0,0 +1,28 @@ +// RUN: mlir-translate --import-dxsa-bin %S/inputs/bufinfo.shex | FileCheck %s +// NOTE: Assertions have been autogenerated by utils/generate-test-checks.py + + +// CHECK-LABEL: dxsa.dcl_global_flags +// CHECK: dxsa.dcl_resource_structured +// CHECK: dxsa.dcl_resource_raw +// CHECK: dxsa.dcl_resource , , +// CHECK: dxsa.dcl_uav_structured +// CHECK: dxsa.dcl_uav_raw +// CHECK: dxsa.dcl_uav_typed , +// CHECK: dxsa.dcl_output o<0, > +// CHECK: dxsa.dcl_temps 1 +// CHECK: dxsa.unknown +// CHECK: dxsa.iadd r<0, >, r<0, >, l(0x34) +// CHECK: dxsa.unknown +// CHECK: dxsa.iadd r<0, >, r<0, >, r<0, > +// CHECK: dxsa.iadd r<0, >, r<0, >, l(0x34) +// CHECK: dxsa.unknown +// CHECK: dxsa.iadd r<0, >, r<0, >, r<0, > +// CHECK: dxsa.unknown +// CHECK: dxsa.iadd r<0, >, r<0, >, r<0, > +// CHECK: dxsa.unknown +// CHECK: dxsa.iadd r<0, >, r<0, >, r<0, > +// CHECK: dxsa.unknown +// CHECK: dxsa.iadd o<0, >, r<0, >, r<0, > +// CHECK: dxsa.ret + diff --git a/mlir/test/Target/DXSA/hlsl/calc_lod.test b/mlir/test/Target/DXSA/hlsl/calc_lod.test new file mode 100644 index 000000000000..dd017850f0ed --- /dev/null +++ b/mlir/test/Target/DXSA/hlsl/calc_lod.test @@ -0,0 +1,19 @@ +// RUN: mlir-translate --import-dxsa-bin %S/inputs/calc_lod.shex | FileCheck %s +// NOTE: Assertions have been autogenerated by utils/generate-test-checks.py + + +// CHECK-LABEL: dxsa.dcl_global_flags +// CHECK: dxsa.dcl_sampler +// CHECK: dxsa.dcl_resource , , +// CHECK: dxsa.dcl_resource , , +// CHECK: dxsa.dcl_resource , , +// CHECK: dxsa.dcl_input_ps linear v<0, > +// CHECK: dxsa.dcl_output o<0> +// CHECK: dxsa.dcl_temps 1 +// CHECK: dxsa.lod r<0, >, v<0, >, t<0, vector, >, s<0> +// CHECK: dxsa.lod r<0, >, v<0, >, t<1, vector, >, s<0> +// CHECK: dxsa.add r<0, >, r<0, >, r<0, > +// CHECK: dxsa.lod r<0, >, v<0, >, t<2, vector, >, s<0> +// CHECK: dxsa.add o<0>, r<0, >, r<0, > +// CHECK: dxsa.ret + diff --git a/mlir/test/Target/DXSA/hlsl/call1.test b/mlir/test/Target/DXSA/hlsl/call1.test new file mode 100644 index 000000000000..72e988eca748 --- /dev/null +++ b/mlir/test/Target/DXSA/hlsl/call1.test @@ -0,0 +1,34 @@ +// RUN: mlir-translate --import-dxsa-bin %S/inputs/call1.shex | FileCheck %s +// NOTE: Assertions have been autogenerated by utils/generate-test-checks.py + + +// CHECK-LABEL: dxsa.dcl_global_flags +// CHECK: dxsa.dcl_input_ps linear v<0, > +// CHECK: dxsa.dcl_input_ps constant v<1, > +// CHECK: dxsa.dcl_output o<0, > +// CHECK: dxsa.dcl_temps 1 +// CHECK: %[[INDEX_0:.*]] = dxsa.index.imm {imm = 1 : i32} +// CHECK: %[[OPERAND_0:.*]] = dxsa.operand %[[INDEX_0]] {num_components = 4 : i32, one = 0 : i32, type = 1 : i32} +// CHECK: dxsa.instruction "switch" %[[OPERAND_0]] +// CHECK: dxsa.case l(0x1) +// CHECK: dxsa.call label<0> +// CHECK: dxsa.break +// CHECK: dxsa.case l(0x2) +// CHECK: dxsa.call label<1> +// CHECK: dxsa.break +// CHECK: dxsa.default +// CHECK: dxsa.call label<2> +// CHECK: dxsa.break +// CHECK: dxsa.endswitch +// CHECK: dxsa.mov o<0, >, r<0, > +// CHECK: dxsa.ret +// CHECK: dxsa.label label<0> +// CHECK: dxsa.mov r<0, >, l(0x40A00000) +// CHECK: dxsa.ret +// CHECK: dxsa.label label<1> +// CHECK: dxsa.mov r<0, >, v<0, > +// CHECK: dxsa.ret +// CHECK: dxsa.label label<2> +// CHECK: dxsa.mov r<0, >, l(0x40400000) +// CHECK: dxsa.ret + diff --git a/mlir/test/Target/DXSA/hlsl/call3.test b/mlir/test/Target/DXSA/hlsl/call3.test new file mode 100644 index 000000000000..34890016700b --- /dev/null +++ b/mlir/test/Target/DXSA/hlsl/call3.test @@ -0,0 +1,52 @@ +// RUN: mlir-translate --import-dxsa-bin %S/inputs/call3.shex | FileCheck %s +// NOTE: Assertions have been autogenerated by utils/generate-test-checks.py + + +// CHECK-LABEL: dxsa.dcl_global_flags +// CHECK: dxsa.dcl_input_ps linear v<0, > +// CHECK: dxsa.dcl_input_ps constant v<1, > +// CHECK: dxsa.dcl_output o<0, > +// CHECK: dxsa.dcl_temps 1 +// CHECK: %[[INDEX_0:.*]] = dxsa.index.imm {imm = 1 : i32} +// CHECK: %[[OPERAND_0:.*]] = dxsa.operand %[[INDEX_0]] {num_components = 4 : i32, one = 1 : i32, type = 1 : i32} +// CHECK: dxsa.instruction "if" %[[OPERAND_0]] +// CHECK: dxsa.mov o<0, >, v<0, > +// CHECK: dxsa.ret +// CHECK: dxsa.endif +// CHECK: %[[INDEX_1:.*]] = dxsa.index.imm {imm = 1 : i32} +// CHECK: %[[OPERAND_1:.*]] = dxsa.operand %[[INDEX_1]] {num_components = 4 : i32, one = 0 : i32, type = 1 : i32} +// CHECK: dxsa.instruction "switch" %[[OPERAND_1]] +// CHECK: dxsa.case l(0x1) +// CHECK: dxsa.call label<0> +// CHECK: dxsa.break +// CHECK: dxsa.case l(0x2) +// CHECK: dxsa.call label<1> +// CHECK: dxsa.break +// CHECK: dxsa.default +// CHECK: dxsa.call label<2> +// CHECK: dxsa.break +// CHECK: dxsa.endswitch +// CHECK: dxsa.mov o<0, >, r<0, > +// CHECK: %[[INDEX_2:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_2:.*]] = dxsa.operand %[[INDEX_2]] {num_components = 4 : i32, one = 2 : i32, type = 0 : i32} +// CHECK: dxsa.instruction "retc" %[[OPERAND_2]] +// CHECK: dxsa.mov o<0, >, r<0, > +// CHECK: dxsa.ret +// CHECK: dxsa.label label<0> +// CHECK: %[[INDEX_3:.*]] = dxsa.index.imm {imm = 1 : i32} +// CHECK: %[[OPERAND_3:.*]] = dxsa.operand %[[INDEX_3]] {num_components = 4 : i32, one = 1 : i32, type = 1 : i32} +// CHECK: dxsa.instruction "if" %[[OPERAND_3]] +// CHECK: dxsa.mov r<0, >, v<0, > +// CHECK: dxsa.mov r<0, >, l(0xFFFFFFFF) +// CHECK: dxsa.ret +// CHECK: dxsa.endif +// CHECK: dxsa.mov r<0, >, l(0x0, 0x40A00000, 0x0, 0x0) +// CHECK: dxsa.ret +// CHECK: dxsa.label label<1> +// CHECK: dxsa.mov r<0, >, v<0, > +// CHECK: dxsa.mov r<0, >, l(0x0) +// CHECK: dxsa.ret +// CHECK: dxsa.label label<2> +// CHECK: dxsa.mov r<0, >, l(0x0, 0x40400000, 0x0, 0x0) +// CHECK: dxsa.ret + diff --git a/mlir/test/Target/DXSA/hlsl/cast1.test b/mlir/test/Target/DXSA/hlsl/cast1.test new file mode 100644 index 000000000000..f3bbc4ffd707 --- /dev/null +++ b/mlir/test/Target/DXSA/hlsl/cast1.test @@ -0,0 +1,10 @@ +// RUN: mlir-translate --import-dxsa-bin %S/inputs/cast1.shex | FileCheck %s +// NOTE: Assertions have been autogenerated by utils/generate-test-checks.py + + +// CHECK-LABEL: dxsa.dcl_global_flags +// CHECK: dxsa.dcl_input_ps constant v<0, > +// CHECK: dxsa.dcl_output o<0, > +// CHECK: dxsa.itof o<0, >, v<0, > +// CHECK: dxsa.ret + diff --git a/mlir/test/Target/DXSA/hlsl/cast2.test b/mlir/test/Target/DXSA/hlsl/cast2.test new file mode 100644 index 000000000000..357b94849c59 --- /dev/null +++ b/mlir/test/Target/DXSA/hlsl/cast2.test @@ -0,0 +1,10 @@ +// RUN: mlir-translate --import-dxsa-bin %S/inputs/cast2.shex | FileCheck %s +// NOTE: Assertions have been autogenerated by utils/generate-test-checks.py + + +// CHECK-LABEL: dxsa.dcl_global_flags +// CHECK: dxsa.dcl_input_ps constant v<0, > +// CHECK: dxsa.dcl_output o<0, > +// CHECK: dxsa.utof o<0, >, v<0, > +// CHECK: dxsa.ret + diff --git a/mlir/test/Target/DXSA/hlsl/cast3.test b/mlir/test/Target/DXSA/hlsl/cast3.test new file mode 100644 index 000000000000..686293c0bc48 --- /dev/null +++ b/mlir/test/Target/DXSA/hlsl/cast3.test @@ -0,0 +1,10 @@ +// RUN: mlir-translate --import-dxsa-bin %S/inputs/cast3.shex | FileCheck %s +// NOTE: Assertions have been autogenerated by utils/generate-test-checks.py + + +// CHECK-LABEL: dxsa.dcl_global_flags +// CHECK: dxsa.dcl_input_ps linear v<0, > +// CHECK: dxsa.dcl_output o<0, > +// CHECK: dxsa.ftoi o<0, >, v<0, > +// CHECK: dxsa.ret + diff --git a/mlir/test/Target/DXSA/hlsl/cast4.test b/mlir/test/Target/DXSA/hlsl/cast4.test new file mode 100644 index 000000000000..133dd29f1f45 --- /dev/null +++ b/mlir/test/Target/DXSA/hlsl/cast4.test @@ -0,0 +1,10 @@ +// RUN: mlir-translate --import-dxsa-bin %S/inputs/cast4.shex | FileCheck %s +// NOTE: Assertions have been autogenerated by utils/generate-test-checks.py + + +// CHECK-LABEL: dxsa.dcl_global_flags +// CHECK: dxsa.dcl_input_ps linear v<0, > +// CHECK: dxsa.dcl_output o<0, > +// CHECK: dxsa.ftou o<0, >, v<0, > +// CHECK: dxsa.ret + diff --git a/mlir/test/Target/DXSA/hlsl/cast5.test b/mlir/test/Target/DXSA/hlsl/cast5.test new file mode 100644 index 000000000000..d36083886c75 --- /dev/null +++ b/mlir/test/Target/DXSA/hlsl/cast5.test @@ -0,0 +1,10 @@ +// RUN: mlir-translate --import-dxsa-bin %S/inputs/cast5.shex | FileCheck %s +// NOTE: Assertions have been autogenerated by utils/generate-test-checks.py + + +// CHECK-LABEL: dxsa.dcl_global_flags +// CHECK: dxsa.dcl_input_ps linear v<0, min16f, > +// CHECK: dxsa.dcl_output o<0, > +// CHECK: dxsa.mov o<0, >, v<0, min16f, > +// CHECK: dxsa.ret + diff --git a/mlir/test/Target/DXSA/hlsl/cast6.test b/mlir/test/Target/DXSA/hlsl/cast6.test new file mode 100644 index 000000000000..147719154651 --- /dev/null +++ b/mlir/test/Target/DXSA/hlsl/cast6.test @@ -0,0 +1,10 @@ +// RUN: mlir-translate --import-dxsa-bin %S/inputs/cast6.shex | FileCheck %s +// NOTE: Assertions have been autogenerated by utils/generate-test-checks.py + + +// CHECK-LABEL: dxsa.dcl_global_flags +// CHECK: dxsa.dcl_input_ps linear v<0, > +// CHECK: dxsa.dcl_output o<0, min16f, > +// CHECK: dxsa.mov o<0, min16f, >, v<0, > +// CHECK: dxsa.ret + diff --git a/mlir/test/Target/DXSA/hlsl/cbuffer1.50.test b/mlir/test/Target/DXSA/hlsl/cbuffer1.50.test new file mode 100644 index 000000000000..049d243d39b5 --- /dev/null +++ b/mlir/test/Target/DXSA/hlsl/cbuffer1.50.test @@ -0,0 +1,10 @@ +// RUN: mlir-translate --import-dxsa-bin %S/inputs/cbuffer1.50.shex | FileCheck %s +// NOTE: Assertions have been autogenerated by utils/generate-test-checks.py + + +// CHECK-LABEL: dxsa.dcl_global_flags +// CHECK: dxsa.dcl_constant_buffer , +// CHECK: dxsa.dcl_output o<0> +// CHECK: dxsa.mov o<0>, cb<[5, 0], vector> +// CHECK: dxsa.ret + diff --git a/mlir/test/Target/DXSA/hlsl/cbuffer1.51.test b/mlir/test/Target/DXSA/hlsl/cbuffer1.51.test new file mode 100644 index 000000000000..7170c2ad31ef --- /dev/null +++ b/mlir/test/Target/DXSA/hlsl/cbuffer1.51.test @@ -0,0 +1,10 @@ +// RUN: mlir-translate --import-dxsa-bin %S/inputs/cbuffer1.51.shex | FileCheck %s +// NOTE: Assertions have been autogenerated by utils/generate-test-checks.py + + +// CHECK-LABEL: dxsa.dcl_global_flags +// CHECK: dxsa.dcl_constant_buffer , +// CHECK: dxsa.dcl_output o<0> +// CHECK: dxsa.mov o<0>, cb<[0, 5, 0], vector> +// CHECK: dxsa.ret + diff --git a/mlir/test/Target/DXSA/hlsl/cbuffer2.50.test b/mlir/test/Target/DXSA/hlsl/cbuffer2.50.test new file mode 100644 index 000000000000..7c17012e83c0 --- /dev/null +++ b/mlir/test/Target/DXSA/hlsl/cbuffer2.50.test @@ -0,0 +1,10 @@ +// RUN: mlir-translate --import-dxsa-bin %S/inputs/cbuffer2.50.shex | FileCheck %s +// NOTE: Assertions have been autogenerated by utils/generate-test-checks.py + + +// CHECK-LABEL: dxsa.dcl_global_flags +// CHECK: dxsa.dcl_constant_buffer , +// CHECK: dxsa.dcl_output o<0> +// CHECK: dxsa.mov o<0>, cb<[0, 0], vector, > +// CHECK: dxsa.ret + diff --git a/mlir/test/Target/DXSA/hlsl/cbuffer2.51.test b/mlir/test/Target/DXSA/hlsl/cbuffer2.51.test new file mode 100644 index 000000000000..2dd4bd626346 --- /dev/null +++ b/mlir/test/Target/DXSA/hlsl/cbuffer2.51.test @@ -0,0 +1,10 @@ +// RUN: mlir-translate --import-dxsa-bin %S/inputs/cbuffer2.51.shex | FileCheck %s +// NOTE: Assertions have been autogenerated by utils/generate-test-checks.py + + +// CHECK-LABEL: dxsa.dcl_global_flags +// CHECK: dxsa.dcl_constant_buffer , +// CHECK: dxsa.dcl_output o<0> +// CHECK: dxsa.mov o<0>, cb<[0, 0, 0], vector, > +// CHECK: dxsa.ret + diff --git a/mlir/test/Target/DXSA/hlsl/cbuffer3.50.test b/mlir/test/Target/DXSA/hlsl/cbuffer3.50.test new file mode 100644 index 000000000000..d35334c8f624 --- /dev/null +++ b/mlir/test/Target/DXSA/hlsl/cbuffer3.50.test @@ -0,0 +1,15 @@ +// RUN: mlir-translate --import-dxsa-bin %S/inputs/cbuffer3.50.shex | FileCheck %s +// NOTE: Assertions have been autogenerated by utils/generate-test-checks.py + + +// CHECK-LABEL: dxsa.dcl_global_flags +// CHECK: dxsa.dcl_constant_buffer , +// CHECK: dxsa.dcl_constant_buffer , +// CHECK: dxsa.dcl_input_ps constant v<0, > +// CHECK: dxsa.dcl_output o<0> +// CHECK: dxsa.dcl_temps 1 +// CHECK: dxsa.mov r<0, >, v<0, > +// CHECK: dxsa.mov r<0, >, cb<[1, r<0, >], vector, > +// CHECK: dxsa.mov o<0>, cb<[0, r<0, >], vector, > +// CHECK: dxsa.ret + diff --git a/mlir/test/Target/DXSA/hlsl/cbuffer3.51.test b/mlir/test/Target/DXSA/hlsl/cbuffer3.51.test new file mode 100644 index 000000000000..a937b74d0036 --- /dev/null +++ b/mlir/test/Target/DXSA/hlsl/cbuffer3.51.test @@ -0,0 +1,16 @@ +// RUN: mlir-translate --import-dxsa-bin %S/inputs/cbuffer3.51.shex | FileCheck %s +// NOTE: Assertions have been autogenerated by utils/generate-test-checks.py + + +// CHECK-LABEL: dxsa.dcl_global_flags +// CHECK: dxsa.dcl_constant_buffer , +// CHECK: dxsa.dcl_constant_buffer , +// CHECK: dxsa.dcl_input_ps constant v<0, > +// CHECK: dxsa.dcl_output o<0> +// CHECK: dxsa.dcl_temps 1 +// CHECK: dxsa.iadd r<0, >, v<0, >, l(0xC) +// CHECK: dxsa.mov r<0, >, v<0, > +// CHECK: dxsa.mov r<0, >, cb<[0, 17 + r<0, >, r<0, >], vector, > +// CHECK: dxsa.mov o<0>, cb<[1, 77 + r<0, >, r<0, >], vector, > +// CHECK: dxsa.ret + diff --git a/mlir/test/Target/DXSA/hlsl/cmp1.test b/mlir/test/Target/DXSA/hlsl/cmp1.test new file mode 100644 index 000000000000..b3bee3308858 --- /dev/null +++ b/mlir/test/Target/DXSA/hlsl/cmp1.test @@ -0,0 +1,11 @@ +// RUN: mlir-translate --import-dxsa-bin %S/inputs/cmp1.shex | FileCheck %s +// NOTE: Assertions have been autogenerated by utils/generate-test-checks.py + + +// CHECK-LABEL: dxsa.dcl_global_flags +// CHECK: dxsa.dcl_input_ps linear v<0, > +// CHECK: dxsa.dcl_input_ps linear v<0, > +// CHECK: dxsa.dcl_output o<0, > +// CHECK: dxsa.eq o<0, >, v<0, >, v<0, > +// CHECK: dxsa.ret + diff --git a/mlir/test/Target/DXSA/hlsl/constoperand1.test b/mlir/test/Target/DXSA/hlsl/constoperand1.test new file mode 100644 index 000000000000..0a45cb657e32 --- /dev/null +++ b/mlir/test/Target/DXSA/hlsl/constoperand1.test @@ -0,0 +1,9 @@ +// RUN: mlir-translate --import-dxsa-bin %S/inputs/constoperand1.shex | FileCheck %s +// NOTE: Assertions have been autogenerated by utils/generate-test-checks.py + + +// CHECK-LABEL: dxsa.dcl_global_flags +// CHECK: dxsa.dcl_output_siv o<0>, +// CHECK: dxsa.mov o<0>, l(0x40400000, 0x0, 0x3F000000, 0x3DFCD35B) +// CHECK: dxsa.ret + diff --git a/mlir/test/Target/DXSA/hlsl/cs1.test b/mlir/test/Target/DXSA/hlsl/cs1.test new file mode 100644 index 000000000000..5e4c5fab5332 --- /dev/null +++ b/mlir/test/Target/DXSA/hlsl/cs1.test @@ -0,0 +1,30 @@ +// RUN: mlir-translate --import-dxsa-bin %S/inputs/cs1.shex | FileCheck %s +// NOTE: Assertions have been autogenerated by utils/generate-test-checks.py + + +// CHECK-LABEL: dxsa.dcl_global_flags +// CHECK: dxsa.dcl_uav_raw +// CHECK: dxsa.dcl_input vThreadIDInGroupFlattened +// CHECK: dxsa.dcl_input vThreadGroupID<> +// CHECK: dxsa.dcl_input vThreadIDInGroup<> +// CHECK: dxsa.dcl_input vThreadID<> +// CHECK: dxsa.dcl_temps 1 +// CHECK: dxsa.dcl_thread_group +// CHECK: dxsa.ishl r<0, >, vThreadID<>, l(0x7) +// CHECK: dxsa.ishl r<0, >, vThreadGroupID<>, l(0xA) +// CHECK: dxsa.iadd r<0, >, r<0, >, r<0, > +// CHECK: dxsa.iadd r<0, >, r<0, >, vThreadIDInGroup<> +// CHECK: dxsa.iadd r<0, >, r<0, >, vThreadIDInGroupFlattened> +// CHECK: dxsa.unknown +// CHECK: dxsa.add r<0, >, r<0, >, l(0x40400000) +// CHECK: dxsa.sync +// CHECK: %[[INDEX_0:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_0:.*]] = dxsa.operand %[[INDEX_0]] {mask = 16 : i32, num_components = 4 : i32, type = 30 : i32} +// CHECK: %[[INDEX_1:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_1:.*]] = dxsa.operand %[[INDEX_1]] {num_components = 4 : i32, one = 0 : i32, type = 0 : i32} +// CHECK: %[[INDEX_2:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_2:.*]] = dxsa.operand %[[INDEX_2]] {num_components = 4 : i32, one = 1 : i32, type = 0 : i32} +// CHECK: dxsa.instruction "store_raw" %[[OPERAND_0]], %[[OPERAND_1]], %[[OPERAND_2]] +// CHECK: dxsa.sync +// CHECK: dxsa.ret + diff --git a/mlir/test/Target/DXSA/hlsl/cs2.test b/mlir/test/Target/DXSA/hlsl/cs2.test new file mode 100644 index 000000000000..eb98472de409 --- /dev/null +++ b/mlir/test/Target/DXSA/hlsl/cs2.test @@ -0,0 +1,84 @@ +// RUN: mlir-translate --import-dxsa-bin %S/inputs/cs2.shex | FileCheck %s +// NOTE: Assertions have been autogenerated by utils/generate-test-checks.py + + +// CHECK-LABEL: dxsa.dcl_global_flags +// CHECK: dxsa.dcl_constant_buffer , +// CHECK: dxsa.dcl_uav_raw +// CHECK: dxsa.dcl_input vThreadIDInGroupFlattened +// CHECK: dxsa.dcl_input vThreadGroupID<> +// CHECK: dxsa.dcl_input vThreadIDInGroup<> +// CHECK: dxsa.dcl_input vThreadID<> +// CHECK: dxsa.dcl_temps 3 +// CHECK: dxsa.dcl_tgsm_structured g<0>, 16, 384 +// CHECK: dxsa.dcl_thread_group +// CHECK: dxsa.ishl r<0, >, vThreadID<>, l(0x7) +// CHECK: dxsa.ishl r<0, >, vThreadGroupID<>, l(0xA) +// CHECK: dxsa.iadd r<0, >, r<0, >, r<0, > +// CHECK: dxsa.iadd r<0, >, r<0, >, vThreadIDInGroup<> +// CHECK: dxsa.iadd r<0, >, r<0, >, vThreadIDInGroupFlattened> +// CHECK: dxsa.unknown +// CHECK: dxsa.add r<1, min16f, >, r<0, >, l(0x40000000) +// CHECK: %[[INDEX_0:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_0:.*]] = dxsa.operand %[[INDEX_0]] {mask = 16 : i32, num_components = 4 : i32, type = 31 : i32} +// CHECK: %[[OPERAND_1:.*]] = dxsa.operand {num_components = 4 : i32, one = 0 : i32, type = 36 : i32} +// CHECK: %[[OPERAND_2:.*]] = dxsa.operand.imm {imm = dense<4> : vector<1xi32>} +// CHECK: %[[INDEX_1:.*]] = dxsa.index.imm {imm = 1 : i32} +// CHECK: %[[OPERAND_3:.*]] = dxsa.operand %[[INDEX_1]] {min_precision = 1 : i32, num_components = 4 : i32, one = 0 : i32, type = 0 : i32} +// CHECK: dxsa.instruction "store_structured" %[[OPERAND_0]], %[[OPERAND_1]], %[[OPERAND_2]], %[[OPERAND_3]] +// CHECK: %[[INDEX_2:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_4:.*]] = dxsa.operand %[[INDEX_2]] {mask = 16 : i32, num_components = 4 : i32, type = 31 : i32} +// CHECK: %[[OPERAND_5:.*]] = dxsa.operand {num_components = 4 : i32, one = 0 : i32, type = 36 : i32} +// CHECK: %[[OPERAND_6:.*]] = dxsa.operand.imm {imm = dense<8> : vector<1xi32>} +// CHECK: %[[INDEX_3:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_7:.*]] = dxsa.operand %[[INDEX_3]] {num_components = 4 : i32, one = 1 : i32, type = 0 : i32} +// CHECK: dxsa.instruction "store_structured" %[[OPERAND_4]], %[[OPERAND_5]], %[[OPERAND_6]], %[[OPERAND_7]] +// CHECK: dxsa.ftoi r<2, min16i, >, r<0, > +// CHECK: %[[INDEX_4:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_8:.*]] = dxsa.operand %[[INDEX_4]] {mask = 16 : i32, num_components = 4 : i32, type = 31 : i32} +// CHECK: %[[OPERAND_9:.*]] = dxsa.operand {num_components = 4 : i32, one = 0 : i32, type = 36 : i32} +// CHECK: %[[OPERAND_10:.*]] = dxsa.operand.imm {imm = dense<12> : vector<1xi32>} +// CHECK: %[[INDEX_5:.*]] = dxsa.index.imm {imm = 2 : i32} +// CHECK: %[[OPERAND_11:.*]] = dxsa.operand %[[INDEX_5]] {min_precision = 4 : i32, num_components = 4 : i32, one = 0 : i32, type = 0 : i32} +// CHECK: dxsa.instruction "store_structured" %[[OPERAND_8]], %[[OPERAND_9]], %[[OPERAND_10]], %[[OPERAND_11]] +// CHECK: dxsa.sync +// CHECK: dxsa.iadd r<0, >, vThreadIDInGroupFlattened>, cb<[0, 0], vector, > +// CHECK: %[[INDEX_6:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_12:.*]] = dxsa.operand %[[INDEX_6]] {mask = 128 : i32, num_components = 4 : i32, type = 0 : i32} +// CHECK: %[[INDEX_7:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_13:.*]] = dxsa.operand %[[INDEX_7]] {num_components = 4 : i32, one = 2 : i32, type = 0 : i32} +// CHECK: %[[OPERAND_14:.*]] = dxsa.operand.imm {imm = dense<8> : vector<1xi32>} +// CHECK: %[[INDEX_8:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_15:.*]] = dxsa.operand %[[INDEX_8]] {num_components = 4 : i32, swizzle = dense<0> : vector<4xi32>, type = 31 : i32} +// CHECK: dxsa.instruction "ld_structured" %[[OPERAND_12]], %[[OPERAND_13]], %[[OPERAND_14]], %[[OPERAND_15]] +// CHECK: dxsa.add r<0, >, r<0, >, r<0, > +// CHECK: %[[INDEX_9:.*]] = dxsa.index.imm {imm = 2 : i32} +// CHECK: %[[OPERAND_16:.*]] = dxsa.operand %[[INDEX_9]] {mask = 16 : i32, min_precision = 4 : i32, num_components = 4 : i32, type = 0 : i32} +// CHECK: %[[INDEX_10:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_17:.*]] = dxsa.operand %[[INDEX_10]] {num_components = 4 : i32, one = 2 : i32, type = 0 : i32} +// CHECK: %[[OPERAND_18:.*]] = dxsa.operand.imm {imm = dense<12> : vector<1xi32>} +// CHECK: %[[INDEX_11:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_19:.*]] = dxsa.operand %[[INDEX_11]] {num_components = 4 : i32, swizzle = dense<0> : vector<4xi32>, type = 31 : i32} +// CHECK: dxsa.instruction "ld_structured" %[[OPERAND_16]], %[[OPERAND_17]], %[[OPERAND_18]], %[[OPERAND_19]] +// CHECK: dxsa.itof r<0, >, r<2, min16i, > +// CHECK: dxsa.add r<0, >, r<0, >, r<0, > +// CHECK: dxsa.sync +// CHECK: dxsa.sync +// CHECK: %[[INDEX_12:.*]] = dxsa.index.imm {imm = 1 : i32} +// CHECK: %[[OPERAND_20:.*]] = dxsa.operand %[[INDEX_12]] {mask = 16 : i32, min_precision = 1 : i32, num_components = 4 : i32, type = 0 : i32} +// CHECK: %[[INDEX_13:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_21:.*]] = dxsa.operand %[[INDEX_13]] {num_components = 4 : i32, one = 2 : i32, type = 0 : i32} +// CHECK: %[[OPERAND_22:.*]] = dxsa.operand.imm {imm = dense<4> : vector<1xi32>} +// CHECK: %[[INDEX_14:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_23:.*]] = dxsa.operand %[[INDEX_14]] {num_components = 4 : i32, swizzle = dense<0> : vector<4xi32>, type = 31 : i32} +// CHECK: dxsa.instruction "ld_structured" %[[OPERAND_20]], %[[OPERAND_21]], %[[OPERAND_22]], %[[OPERAND_23]] +// CHECK: dxsa.add r<0, >, r<0, >, r<1, min16f, > +// CHECK: %[[INDEX_15:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_24:.*]] = dxsa.operand %[[INDEX_15]] {mask = 16 : i32, num_components = 4 : i32, type = 30 : i32} +// CHECK: %[[INDEX_16:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_25:.*]] = dxsa.operand %[[INDEX_16]] {num_components = 4 : i32, one = 0 : i32, type = 0 : i32} +// CHECK: %[[INDEX_17:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_26:.*]] = dxsa.operand %[[INDEX_17]] {num_components = 4 : i32, one = 1 : i32, type = 0 : i32} +// CHECK: dxsa.instruction "store_raw" %[[OPERAND_24]], %[[OPERAND_25]], %[[OPERAND_26]] +// CHECK: dxsa.ret + diff --git a/mlir/test/Target/DXSA/hlsl/cs4.test b/mlir/test/Target/DXSA/hlsl/cs4.test new file mode 100644 index 000000000000..291fc13e8caa --- /dev/null +++ b/mlir/test/Target/DXSA/hlsl/cs4.test @@ -0,0 +1,59 @@ +// RUN: mlir-translate --import-dxsa-bin %S/inputs/cs4.shex | FileCheck %s +// NOTE: Assertions have been autogenerated by utils/generate-test-checks.py + + +// CHECK-LABEL: dxsa.dcl_global_flags +// CHECK: dxsa.dcl_constant_buffer , +// CHECK: dxsa.dcl_uav_raw +// CHECK: dxsa.dcl_input vThreadIDInGroupFlattened +// CHECK: dxsa.dcl_input vThreadGroupID<> +// CHECK: dxsa.dcl_input vThreadIDInGroup<> +// CHECK: dxsa.dcl_input vThreadID<> +// CHECK: dxsa.dcl_temps 3 +// CHECK: dxsa.dcl_tgsm_structured g<0>, 20, 384 +// CHECK: dxsa.dcl_thread_group +// CHECK: dxsa.ishl r<0, >, vThreadID<>, l(0x7) +// CHECK: dxsa.ishl r<0, >, vThreadGroupID<>, l(0xA) +// CHECK: dxsa.iadd r<0, >, r<0, >, r<0, > +// CHECK: dxsa.iadd r<0, >, r<0, >, vThreadIDInGroup<> +// CHECK: dxsa.iadd r<0, >, r<0, >, vThreadIDInGroupFlattened> +// CHECK: dxsa.unknown +// CHECK: dxsa.ftou r<0, >, r<0, > +// CHECK: %[[INDEX_0:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_0:.*]] = dxsa.operand %[[INDEX_0]] {mask = 16 : i32, num_components = 4 : i32, type = 31 : i32} +// CHECK: %[[OPERAND_1:.*]] = dxsa.operand {num_components = 4 : i32, one = 0 : i32, type = 36 : i32} +// CHECK: %[[OPERAND_2:.*]] = dxsa.operand.imm {imm = dense<16> : vector<1xi32>} +// CHECK: %[[INDEX_1:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_3:.*]] = dxsa.operand %[[INDEX_1]] {num_components = 4 : i32, one = 2 : i32, type = 0 : i32} +// CHECK: dxsa.instruction "store_structured" %[[OPERAND_0]], %[[OPERAND_1]], %[[OPERAND_2]], %[[OPERAND_3]] +// CHECK: dxsa.mov r<1, >, vThreadIDInGroupFlattened> +// CHECK: dxsa.mov r<1, >, l(0x10) +// CHECK: dxsa.imm_atomic_iadd r<2, >, g<0>, r<1, >, vThreadID<> +// CHECK: dxsa.atomic_or g<0>, r<1, >, vThreadID<> +// CHECK: dxsa.utof r<0, >, r<2, > +// CHECK: dxsa.add r<0, >, r<0, >, r<0, > +// CHECK: dxsa.atomic_cmp_store g<0>, r<1, >, vThreadGroupID<>, vThreadID<> +// CHECK: dxsa.imm_atomic_cmp_exch r<1, >, g<0>, r<1, >, vThreadGroupID<>, vThreadID<> +// CHECK: dxsa.sync +// CHECK: dxsa.utof r<0, >, r<1, > +// CHECK: dxsa.add r<0, >, r<0, >, r<0, > +// CHECK: dxsa.iadd r<0, >, vThreadIDInGroupFlattened>, cb<[0, 0], vector, > +// CHECK: %[[INDEX_2:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_4:.*]] = dxsa.operand %[[INDEX_2]] {mask = 64 : i32, num_components = 4 : i32, type = 0 : i32} +// CHECK: %[[INDEX_3:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_5:.*]] = dxsa.operand %[[INDEX_3]] {num_components = 4 : i32, one = 2 : i32, type = 0 : i32} +// CHECK: %[[OPERAND_6:.*]] = dxsa.operand.imm {imm = dense<16> : vector<1xi32>} +// CHECK: %[[INDEX_4:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_7:.*]] = dxsa.operand %[[INDEX_4]] {num_components = 4 : i32, swizzle = dense<0> : vector<4xi32>, type = 31 : i32} +// CHECK: dxsa.instruction "ld_structured" %[[OPERAND_4]], %[[OPERAND_5]], %[[OPERAND_6]], %[[OPERAND_7]] +// CHECK: dxsa.utof r<0, >, r<0, > +// CHECK: dxsa.add r<0, >, r<0, >, r<0, > +// CHECK: %[[INDEX_5:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_8:.*]] = dxsa.operand %[[INDEX_5]] {mask = 16 : i32, num_components = 4 : i32, type = 30 : i32} +// CHECK: %[[INDEX_6:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_9:.*]] = dxsa.operand %[[INDEX_6]] {num_components = 4 : i32, one = 0 : i32, type = 0 : i32} +// CHECK: %[[INDEX_7:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_10:.*]] = dxsa.operand %[[INDEX_7]] {num_components = 4 : i32, one = 1 : i32, type = 0 : i32} +// CHECK: dxsa.instruction "store_raw" %[[OPERAND_8]], %[[OPERAND_9]], %[[OPERAND_10]] +// CHECK: dxsa.ret + diff --git a/mlir/test/Target/DXSA/hlsl/cs5.test b/mlir/test/Target/DXSA/hlsl/cs5.test new file mode 100644 index 000000000000..21b251f8bd07 --- /dev/null +++ b/mlir/test/Target/DXSA/hlsl/cs5.test @@ -0,0 +1,84 @@ +// RUN: mlir-translate --import-dxsa-bin %S/inputs/cs5.shex | FileCheck %s +// NOTE: Assertions have been autogenerated by utils/generate-test-checks.py + + +// CHECK-LABEL: dxsa.dcl_global_flags +// CHECK: dxsa.dcl_constant_buffer , +// CHECK: dxsa.dcl_uav_raw +// CHECK: dxsa.dcl_input vThreadIDInGroupFlattened +// CHECK: dxsa.dcl_input vThreadGroupID<> +// CHECK: dxsa.dcl_input vThreadIDInGroup<> +// CHECK: dxsa.dcl_input vThreadID<> +// CHECK: dxsa.dcl_temps 3 +// CHECK: dxsa.dcl_tgsm_structured g<0>, 16, 384 +// CHECK: dxsa.dcl_thread_group +// CHECK: dxsa.ishl r<0, >, vThreadID<>, l(0x7) +// CHECK: dxsa.ishl r<0, >, vThreadGroupID<>, l(0xA) +// CHECK: dxsa.iadd r<0, >, r<0, >, r<0, > +// CHECK: dxsa.iadd r<0, >, r<0, >, vThreadIDInGroup<> +// CHECK: dxsa.iadd r<0, >, r<0, >, vThreadIDInGroupFlattened> +// CHECK: dxsa.unknown +// CHECK: dxsa.add r<1, min16f, >, r<0, >, l(0x40000000) +// CHECK: %[[INDEX_0:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_0:.*]] = dxsa.operand %[[INDEX_0]] {mask = 16 : i32, num_components = 4 : i32, type = 31 : i32} +// CHECK: %[[OPERAND_1:.*]] = dxsa.operand {num_components = 4 : i32, one = 0 : i32, type = 36 : i32} +// CHECK: %[[OPERAND_2:.*]] = dxsa.operand.imm {imm = dense<4> : vector<1xi32>} +// CHECK: %[[INDEX_1:.*]] = dxsa.index.imm {imm = 1 : i32} +// CHECK: %[[OPERAND_3:.*]] = dxsa.operand %[[INDEX_1]] {min_precision = 1 : i32, num_components = 4 : i32, one = 0 : i32, type = 0 : i32} +// CHECK: dxsa.instruction "store_structured" %[[OPERAND_0]], %[[OPERAND_1]], %[[OPERAND_2]], %[[OPERAND_3]] +// CHECK: %[[INDEX_2:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_4:.*]] = dxsa.operand %[[INDEX_2]] {mask = 16 : i32, num_components = 4 : i32, type = 31 : i32} +// CHECK: %[[OPERAND_5:.*]] = dxsa.operand {num_components = 4 : i32, one = 0 : i32, type = 36 : i32} +// CHECK: %[[OPERAND_6:.*]] = dxsa.operand.imm {imm = dense<8> : vector<1xi32>} +// CHECK: %[[INDEX_3:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_7:.*]] = dxsa.operand %[[INDEX_3]] {num_components = 4 : i32, one = 1 : i32, type = 0 : i32} +// CHECK: dxsa.instruction "store_structured" %[[OPERAND_4]], %[[OPERAND_5]], %[[OPERAND_6]], %[[OPERAND_7]] +// CHECK: dxsa.ftoi r<2, min16i, >, r<0, > +// CHECK: %[[INDEX_4:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_8:.*]] = dxsa.operand %[[INDEX_4]] {mask = 16 : i32, num_components = 4 : i32, type = 31 : i32} +// CHECK: %[[OPERAND_9:.*]] = dxsa.operand {num_components = 4 : i32, one = 0 : i32, type = 36 : i32} +// CHECK: %[[OPERAND_10:.*]] = dxsa.operand.imm {imm = dense<12> : vector<1xi32>} +// CHECK: %[[INDEX_5:.*]] = dxsa.index.imm {imm = 2 : i32} +// CHECK: %[[OPERAND_11:.*]] = dxsa.operand %[[INDEX_5]] {min_precision = 4 : i32, num_components = 4 : i32, one = 0 : i32, type = 0 : i32} +// CHECK: dxsa.instruction "store_structured" %[[OPERAND_8]], %[[OPERAND_9]], %[[OPERAND_10]], %[[OPERAND_11]] +// CHECK: dxsa.sync +// CHECK: dxsa.iadd r<0, >, vThreadIDInGroupFlattened>, cb<[0, 0], vector, > +// CHECK: %[[INDEX_6:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_12:.*]] = dxsa.operand %[[INDEX_6]] {mask = 128 : i32, num_components = 4 : i32, type = 0 : i32} +// CHECK: %[[INDEX_7:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_13:.*]] = dxsa.operand %[[INDEX_7]] {num_components = 4 : i32, one = 2 : i32, type = 0 : i32} +// CHECK: %[[OPERAND_14:.*]] = dxsa.operand.imm {imm = dense<8> : vector<1xi32>} +// CHECK: %[[INDEX_8:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_15:.*]] = dxsa.operand %[[INDEX_8]] {num_components = 4 : i32, swizzle = dense<0> : vector<4xi32>, type = 31 : i32} +// CHECK: dxsa.instruction "ld_structured" %[[OPERAND_12]], %[[OPERAND_13]], %[[OPERAND_14]], %[[OPERAND_15]] +// CHECK: dxsa.add r<0, >, r<0, >, r<0, > +// CHECK: %[[INDEX_9:.*]] = dxsa.index.imm {imm = 2 : i32} +// CHECK: %[[OPERAND_16:.*]] = dxsa.operand %[[INDEX_9]] {mask = 16 : i32, min_precision = 4 : i32, num_components = 4 : i32, type = 0 : i32} +// CHECK: %[[INDEX_10:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_17:.*]] = dxsa.operand %[[INDEX_10]] {num_components = 4 : i32, one = 2 : i32, type = 0 : i32} +// CHECK: %[[OPERAND_18:.*]] = dxsa.operand.imm {imm = dense<12> : vector<1xi32>} +// CHECK: %[[INDEX_11:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_19:.*]] = dxsa.operand %[[INDEX_11]] {num_components = 4 : i32, swizzle = dense<0> : vector<4xi32>, type = 31 : i32} +// CHECK: dxsa.instruction "ld_structured" %[[OPERAND_16]], %[[OPERAND_17]], %[[OPERAND_18]], %[[OPERAND_19]] +// CHECK: dxsa.itof r<0, >, r<2, min16i, > +// CHECK: dxsa.add r<0, >, r<0, >, r<0, > +// CHECK: dxsa.sync +// CHECK: dxsa.sync +// CHECK: %[[INDEX_12:.*]] = dxsa.index.imm {imm = 1 : i32} +// CHECK: %[[OPERAND_20:.*]] = dxsa.operand %[[INDEX_12]] {mask = 16 : i32, min_precision = 1 : i32, num_components = 4 : i32, type = 0 : i32} +// CHECK: %[[INDEX_13:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_21:.*]] = dxsa.operand %[[INDEX_13]] {num_components = 4 : i32, one = 2 : i32, type = 0 : i32} +// CHECK: %[[OPERAND_22:.*]] = dxsa.operand.imm {imm = dense<4> : vector<1xi32>} +// CHECK: %[[INDEX_14:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_23:.*]] = dxsa.operand %[[INDEX_14]] {num_components = 4 : i32, swizzle = dense<0> : vector<4xi32>, type = 31 : i32} +// CHECK: dxsa.instruction "ld_structured" %[[OPERAND_20]], %[[OPERAND_21]], %[[OPERAND_22]], %[[OPERAND_23]] +// CHECK: dxsa.add r<0, >, r<0, >, r<1, min16f, > +// CHECK: %[[INDEX_15:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_24:.*]] = dxsa.operand %[[INDEX_15]] {mask = 16 : i32, num_components = 4 : i32, type = 30 : i32} +// CHECK: %[[INDEX_16:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_25:.*]] = dxsa.operand %[[INDEX_16]] {num_components = 4 : i32, one = 0 : i32, type = 0 : i32} +// CHECK: %[[INDEX_17:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_26:.*]] = dxsa.operand %[[INDEX_17]] {num_components = 4 : i32, one = 1 : i32, type = 0 : i32} +// CHECK: dxsa.instruction "store_raw" %[[OPERAND_24]], %[[OPERAND_25]], %[[OPERAND_26]] +// CHECK: dxsa.ret + diff --git a/mlir/test/Target/DXSA/hlsl/derivatives.test b/mlir/test/Target/DXSA/hlsl/derivatives.test new file mode 100644 index 000000000000..c107066cf2b5 --- /dev/null +++ b/mlir/test/Target/DXSA/hlsl/derivatives.test @@ -0,0 +1,22 @@ +// RUN: mlir-translate --import-dxsa-bin %S/inputs/derivatives.shex | FileCheck %s +// NOTE: Assertions have been autogenerated by utils/generate-test-checks.py + + +// CHECK-LABEL: dxsa.dcl_global_flags +// CHECK: dxsa.dcl_input_ps linear v<0> +// CHECK: dxsa.dcl_input_ps linear v<1> +// CHECK: dxsa.dcl_output o<0> +// CHECK: dxsa.dcl_temps 2 +// CHECK: dxsa.deriv_rtx_coarse r<0>, v<1> +// CHECK: dxsa.deriv_rty_coarse r<1>, v<1> +// CHECK: dxsa.add r<0>, r<0>, r<1> +// CHECK: dxsa.deriv_rtx_coarse r<1>, v<0> +// CHECK: dxsa.add r<0>, r<0>, r<1> +// CHECK: dxsa.deriv_rty_coarse r<1>, v<0> +// CHECK: dxsa.add r<0>, r<0>, r<1> +// CHECK: dxsa.deriv_rtx_fine r<1>, v<0> +// CHECK: dxsa.add r<0>, r<0>, r<1> +// CHECK: dxsa.deriv_rty_fine r<1>, v<0> +// CHECK: dxsa.add o<0>, r<0>, r<1> +// CHECK: dxsa.ret + diff --git a/mlir/test/Target/DXSA/hlsl/discard.test b/mlir/test/Target/DXSA/hlsl/discard.test new file mode 100644 index 000000000000..ebd4898f78b0 --- /dev/null +++ b/mlir/test/Target/DXSA/hlsl/discard.test @@ -0,0 +1,19 @@ +// RUN: mlir-translate --import-dxsa-bin %S/inputs/discard.shex | FileCheck %s +// NOTE: Assertions have been autogenerated by utils/generate-test-checks.py + + +// CHECK-LABEL: dxsa.dcl_global_flags +// CHECK: dxsa.dcl_input_ps linear v<0, > +// CHECK: dxsa.dcl_output o<0> +// CHECK: dxsa.dcl_temps 1 +// CHECK: dxsa.lt r<0, >, l(0x3E99999A), v<0, > +// CHECK: %[[INDEX_0:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_0:.*]] = dxsa.operand %[[INDEX_0]] {num_components = 4 : i32, one = 0 : i32, type = 0 : i32} +// CHECK: dxsa.instruction "discard" %[[OPERAND_0]] +// CHECK: dxsa.ne r<0, >, v<0, >, l(0x0) +// CHECK: %[[INDEX_1:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_1:.*]] = dxsa.operand %[[INDEX_1]] {num_components = 4 : i32, one = 0 : i32, type = 0 : i32} +// CHECK: dxsa.instruction "discard" %[[OPERAND_1]] +// CHECK: dxsa.mov o<0>, l(0x0, 0x0, 0x0, 0x0) +// CHECK: dxsa.ret + diff --git a/mlir/test/Target/DXSA/hlsl/dot1.test b/mlir/test/Target/DXSA/hlsl/dot1.test new file mode 100644 index 000000000000..0a09055aa3d0 --- /dev/null +++ b/mlir/test/Target/DXSA/hlsl/dot1.test @@ -0,0 +1,16 @@ +// RUN: mlir-translate --import-dxsa-bin %S/inputs/dot1.shex | FileCheck %s +// NOTE: Assertions have been autogenerated by utils/generate-test-checks.py + + +// CHECK-LABEL: dxsa.dcl_global_flags +// CHECK: dxsa.dcl_input_ps linear v<0> +// CHECK: dxsa.dcl_input_ps linear v<1> +// CHECK: dxsa.dcl_output o<0, > +// CHECK: dxsa.dcl_temps 1 +// CHECK: dxsa.dp4 r<0, >, v<0>, v<1> +// CHECK: dxsa.dp3 r<0, >, v<0, >, v<1, > +// CHECK: dxsa.add r<0, >, r<0, >, r<0, > +// CHECK: dxsa.dp2 r<0, >, v<0, >, v<1, > +// CHECK: dxsa.add o<0, >, r<0, >, r<0, > +// CHECK: dxsa.ret + diff --git a/mlir/test/Target/DXSA/hlsl/double1.test b/mlir/test/Target/DXSA/hlsl/double1.test new file mode 100644 index 000000000000..de2f29f5664b --- /dev/null +++ b/mlir/test/Target/DXSA/hlsl/double1.test @@ -0,0 +1,18 @@ +// RUN: mlir-translate --import-dxsa-bin %S/inputs/double1.shex | FileCheck %s +// NOTE: Assertions have been autogenerated by utils/generate-test-checks.py + + +// CHECK-LABEL: dxsa.dcl_global_flags +// CHECK: dxsa.dcl_input_ps constant v<0, > +// CHECK: dxsa.dcl_input_ps constant v<0, > +// CHECK: dxsa.dcl_output o<0, > +// CHECK: dxsa.dcl_temps 1 +// CHECK: dxsa.mov r<0>, v<0> +// CHECK: dxsa.ddiv r<0, >, r<0, >, r<0, > +// CHECK: dxsa.dadd r<0, >, r<0, >, d(0x0, 0x60000000C0116666) +// CHECK: dxsa.dmin r<0, >, r<0, >, d(0x800000003FFC51EB, 0x0) +// CHECK: dxsa.dmax r<0, >, r<0, >, r<0, > +// CHECK: dxsa.dmov r<0, >, |r<0, >| +// CHECK: dxsa.mov o<0, >, r<0, > +// CHECK: dxsa.ret + diff --git a/mlir/test/Target/DXSA/hlsl/double2.test b/mlir/test/Target/DXSA/hlsl/double2.test new file mode 100644 index 000000000000..2d974af7ffc7 --- /dev/null +++ b/mlir/test/Target/DXSA/hlsl/double2.test @@ -0,0 +1,19 @@ +// RUN: mlir-translate --import-dxsa-bin %S/inputs/double2.shex | FileCheck %s +// NOTE: Assertions have been autogenerated by utils/generate-test-checks.py + + +// CHECK-LABEL: dxsa.dcl_global_flags +// CHECK: dxsa.dcl_constant_buffer , +// CHECK: dxsa.dcl_input_ps constant v<0, > +// CHECK: dxsa.dcl_input_ps constant v<0, > +// CHECK: dxsa.dcl_output o<0, > +// CHECK: dxsa.dcl_temps 1 +// CHECK: dxsa.mov r<0>, v<0> +// CHECK: dxsa.ddiv r<0, >, r<0, >, r<0, > +// CHECK: dxsa.dadd r<0, >, r<0, >, d(0x0, 0x60000000C0116666) +// CHECK: dxsa.dmin r<0, >, r<0, >, d(0x800000003FFC51EB, 0x0) +// CHECK: dxsa.dmax r<0, >, r<0, >, r<0, > +// CHECK: dxsa.dmovc r<0, >, cb<[0, 0], vector, >, |r<0, >|, r<0, > +// CHECK: dxsa.mov o<0, >, r<0, > +// CHECK: dxsa.ret + diff --git a/mlir/test/Target/DXSA/hlsl/double3.test b/mlir/test/Target/DXSA/hlsl/double3.test new file mode 100644 index 000000000000..0ebab3a58356 --- /dev/null +++ b/mlir/test/Target/DXSA/hlsl/double3.test @@ -0,0 +1,23 @@ +// RUN: mlir-translate --import-dxsa-bin %S/inputs/double3.shex | FileCheck %s +// NOTE: Assertions have been autogenerated by utils/generate-test-checks.py + + +// CHECK-LABEL: dxsa.dcl_global_flags +// CHECK: dxsa.dcl_input_ps constant v<0, > +// CHECK: dxsa.dcl_input_ps constant v<0, > +// CHECK: dxsa.dcl_input_ps constant v<1, > +// CHECK: dxsa.dcl_output o<0, > +// CHECK: dxsa.dcl_temps 2 +// CHECK: dxsa.mov r<0>, v<0> +// CHECK: dxsa.deq r<1, >, r<0, >, r<0, > +// CHECK: dxsa.mov r<1, >, v<1, > +// CHECK: dxsa.dne r<1, >, r<0, >, r<1, > +// CHECK: dxsa.and r<1, >, r<1, >, r<1, > +// CHECK: dxsa.dlt r<1, >, r<0, >, r<1, > +// CHECK: dxsa.dmul r<0, >, r<0, >, r<1, > +// CHECK: dxsa.dadd r<0, >, r<0, >, r<0, > +// CHECK: dxsa.dlt r<0, >, r<0, >, r<0, > +// CHECK: dxsa.and r<0, >, r<1, >, r<1, > +// CHECK: dxsa.and o<0, >, r<0, >, r<0, > +// CHECK: dxsa.ret + diff --git a/mlir/test/Target/DXSA/hlsl/double4.test b/mlir/test/Target/DXSA/hlsl/double4.test new file mode 100644 index 000000000000..6b61ff4078d3 --- /dev/null +++ b/mlir/test/Target/DXSA/hlsl/double4.test @@ -0,0 +1,18 @@ +// RUN: mlir-translate --import-dxsa-bin %S/inputs/double4.shex | FileCheck %s +// NOTE: Assertions have been autogenerated by utils/generate-test-checks.py + + +// CHECK-LABEL: dxsa.dcl_global_flags +// CHECK: dxsa.dcl_input_ps constant v<0> +// CHECK: dxsa.dcl_input_ps constant v<1> +// CHECK: dxsa.dcl_input_ps constant v<2> +// CHECK: dxsa.dcl_output o<0> +// CHECK: dxsa.dcl_temps 3 +// CHECK: dxsa.mov r<0>, v<1> +// CHECK: dxsa.mov r<1>, v<2> +// CHECK: dxsa.mov r<2>, v<0> +// CHECK: dxsa.dfma r<0>, r<2>, r<0>, r<1> +// CHECK: dxsa.dadd_sat r<0>, r<2>, r<0> +// CHECK: dxsa.mov o<0>, r<0, > +// CHECK: dxsa.ret + diff --git a/mlir/test/Target/DXSA/hlsl/double5.test b/mlir/test/Target/DXSA/hlsl/double5.test new file mode 100644 index 000000000000..ee61b253a80c --- /dev/null +++ b/mlir/test/Target/DXSA/hlsl/double5.test @@ -0,0 +1,27 @@ +// RUN: mlir-translate --import-dxsa-bin %S/inputs/double5.shex | FileCheck %s +// NOTE: Assertions have been autogenerated by utils/generate-test-checks.py + + +// CHECK-LABEL: dxsa.dcl_global_flags +// CHECK: dxsa.dcl_input_ps constant v<0, > +// CHECK: dxsa.dcl_input_ps constant v<1, > +// CHECK: dxsa.dcl_input_ps constant v<2, > +// CHECK: dxsa.dcl_output o<0> +// CHECK: dxsa.dcl_temps 2 +// CHECK: dxsa.mov r<0, >, v<0, > +// CHECK: dxsa.dtof r<0, >, r<0, > +// CHECK: dxsa.ftod r<0, >, r<0, > +// CHECK: dxsa.mov r<0, >, v<1, > +// CHECK: dxsa.dtoi r<0, >, r<0, > +// CHECK: dxsa.itod r<0, >, r<0, > +// CHECK: dxsa.dadd r<1, >, r<0, >, r<0, > +// CHECK: dxsa.dadd r<1, >, r<0, >, r<1, > +// CHECK: dxsa.dadd r<0, >, r<0, >, r<1, > +// CHECK: dxsa.dadd r<0, >, r<0, >, r<0, > +// CHECK: dxsa.mov r<0, >, v<2, > +// CHECK: dxsa.dtou r<0, >, r<0, > +// CHECK: dxsa.utod r<0, >, r<0, > +// CHECK: dxsa.dadd r<0, >, r<0, >, r<0, > +// CHECK: dxsa.mov o<0>, r<0, > +// CHECK: dxsa.ret + diff --git a/mlir/test/Target/DXSA/hlsl/double6.test b/mlir/test/Target/DXSA/hlsl/double6.test new file mode 100644 index 000000000000..9de645e889cc --- /dev/null +++ b/mlir/test/Target/DXSA/hlsl/double6.test @@ -0,0 +1,40 @@ +// RUN: mlir-translate --import-dxsa-bin %S/inputs/double6.shex | FileCheck %s +// NOTE: Assertions have been autogenerated by utils/generate-test-checks.py + + +// CHECK-LABEL: dxsa.dcl_global_flags +// CHECK: dxsa.dcl_constant_buffer , +// CHECK: dxsa.dcl_input_ps constant v<0, > +// CHECK: dxsa.dcl_input_ps constant v<1, > +// CHECK: dxsa.dcl_input_ps constant v<2, > +// CHECK: dxsa.dcl_output o<0> +// CHECK: dxsa.dcl_temps 2 +// CHECK: dxsa.dcl_indexable_temp x<0>[6] +// CHECK: dxsa.dcl_indexable_temp x<1>[4] +// CHECK: dxsa.dmov x<[0, 0], >, d(0x40200000, 0x0) +// CHECK: dxsa.dmov x<[0, 1], >, d(0x3FF00000, 0x0) +// CHECK: dxsa.dmov x<[0, 2], >, d(0x40000000, 0x0) +// CHECK: dxsa.dmov x<[0, 3], >, d(0x40000000400C7AE1, 0x0) +// CHECK: dxsa.dmov x<[0, 4], >, d(0x401C0000, 0x0) +// CHECK: dxsa.dmov x<[0, 5], >, d(0x40408000, 0x0) +// CHECK: dxsa.dmov x<[1, 0], >, d(0x3FF00000, 0x0) +// CHECK: dxsa.dmov x<[1, 1], >, d(0x40000000, 0x0) +// CHECK: dxsa.dmov x<[1, 2], >, d(0x40000000400C7AE1, 0x0) +// CHECK: dxsa.dmov x<[1, 3], >, d(0x401C0000, 0x0) +// CHECK: dxsa.mov r<0, >, cb<[0, 0], vector, > +// CHECK: dxsa.dmov r<0, >, x<[1, r<0, >], > +// CHECK: dxsa.dadd r<0, >, r<0, >, cb<[0, 1 + r<0, >], vector, > +// CHECK: dxsa.dmov r<1, >, x<[0, r<0, >], > +// CHECK: dxsa.dadd r<0, >, r<0, >, r<1, > +// CHECK: dxsa.mov r<1, >, v<0, > +// CHECK: dxsa.mov r<1, >, v<1, > +// CHECK: dxsa.dadd r<1, >, r<1, >, r<1, > +// CHECK: dxsa.mov r<1, >, v<2, > +// CHECK: dxsa.dadd r<1, >, r<1, >, r<1, > +// CHECK: dxsa.dadd r<0, >, r<0, >, r<1, > +// CHECK: dxsa.dmov x<[1, r<0, >], >, r<0, > +// CHECK: dxsa.dmov r<0, >, x<[1, r<0, >], > +// CHECK: dxsa.dadd r<0, >, r<0, >, r<0, > +// CHECK: dxsa.mov o<0>, r<0, > +// CHECK: dxsa.ret + diff --git a/mlir/test/Target/DXSA/hlsl/ds1.test b/mlir/test/Target/DXSA/hlsl/ds1.test new file mode 100644 index 000000000000..d339764ba2a4 --- /dev/null +++ b/mlir/test/Target/DXSA/hlsl/ds1.test @@ -0,0 +1,45 @@ +// RUN: mlir-translate --import-dxsa-bin %S/inputs/ds1.shex | FileCheck %s +// NOTE: Assertions have been autogenerated by utils/generate-test-checks.py + + +// CHECK-LABEL: dxsa.dcl_input_control_point_count 16 +// CHECK: dxsa.dcl_tessellator_domain domain_quad +// CHECK: dxsa.dcl_global_flags +// CHECK: dxsa.dcl_constant_buffer , +// CHECK: dxsa.dcl_input_siv vpc<0, >, +// CHECK: dxsa.dcl_input_siv vpc<1, >, +// CHECK: dxsa.dcl_input_siv vpc<2, >, +// CHECK: dxsa.dcl_input_siv vpc<3, >, +// CHECK: dxsa.dcl_input_siv vpc<4, >, +// CHECK: dxsa.dcl_input_siv vpc<5, >, +// CHECK: dxsa.dcl_input vpc<6> +// CHECK: dxsa.dcl_input vpc<7, > +// CHECK: dxsa.dcl_input vpc<8, > +// CHECK: dxsa.dcl_input vpc<9, > +// CHECK: dxsa.dcl_input vDomain<> +// CHECK: dxsa.dcl_input vicp<[16, 0], > +// CHECK: dxsa.dcl_output_siv o<0>, +// CHECK: dxsa.dcl_temps 2 +// CHECK: dxsa.dcl_index_range vpc<7, >, 3 +// CHECK: dxsa.mov r<0>, l(0x0, 0x0, 0x0, 0x0) +// CHECK: dxsa.mov r<1, >, l(0x0) +// CHECK: dxsa.loop +// CHECK: dxsa.ige r<1, >, r<1, >, l(0x10) +// CHECK: %[[INDEX_0:.*]] = dxsa.index.imm {imm = 1 : i32} +// CHECK: %[[OPERAND_0:.*]] = dxsa.operand %[[INDEX_0]] {num_components = 4 : i32, one = 1 : i32, type = 0 : i32} +// CHECK: dxsa.instruction "breakc" %[[OPERAND_0]] +// CHECK: dxsa.add r<0>, r<0>, vicp<[r<1, >, 0], > +// CHECK: dxsa.iadd r<1, >, r<1, >, l(0x1) +// CHECK: dxsa.endloop +// CHECK: dxsa.add r<0>, r<0>, vpc<0, > +// CHECK: dxsa.mad r<0>, vpc<1, >, l(0x40000000, 0x40000000, 0x40000000, 0x40000000), r<0> +// CHECK: dxsa.mad r<0>, vpc<2, >, l(0x40400000, 0x40400000, 0x40400000, 0x40400000), r<0> +// CHECK: dxsa.mad r<0>, vpc<3, >, l(0x40800000, 0x40800000, 0x40800000, 0x40800000), r<0> +// CHECK: dxsa.add r<1, >, vpc<4, >, vpc<5, > +// CHECK: dxsa.add r<0>, r<0>, r<1, > +// CHECK: dxsa.mov r<1, >, cb<[0, 0], vector, > +// CHECK: dxsa.add r<1>, vpc<6, >, vpc<7 + r<1, >, > +// CHECK: dxsa.add r<0>, r<0>, r<1> +// CHECK: dxsa.mul o<0>, r<0>, vDomain<> +// CHECK: dxsa.ret + diff --git a/mlir/test/Target/DXSA/hlsl/empty.test b/mlir/test/Target/DXSA/hlsl/empty.test new file mode 100644 index 000000000000..94619b7eb743 --- /dev/null +++ b/mlir/test/Target/DXSA/hlsl/empty.test @@ -0,0 +1,7 @@ +// RUN: mlir-translate --import-dxsa-bin %S/inputs/empty.shex | FileCheck %s +// NOTE: Assertions have been autogenerated by utils/generate-test-checks.py + + +// CHECK-LABEL: dxsa.dcl_global_flags +// CHECK: dxsa.ret + diff --git a/mlir/test/Target/DXSA/hlsl/eval.test b/mlir/test/Target/DXSA/hlsl/eval.test new file mode 100644 index 000000000000..ab50b27416ed --- /dev/null +++ b/mlir/test/Target/DXSA/hlsl/eval.test @@ -0,0 +1,33 @@ +// RUN: mlir-translate --import-dxsa-bin %S/inputs/eval.shex | FileCheck %s +// NOTE: Assertions have been autogenerated by utils/generate-test-checks.py + + +// CHECK-LABEL: dxsa.dcl_global_flags +// CHECK: dxsa.dcl_input_ps linear v<0> +// CHECK: dxsa.dcl_input_ps constant v<1, > +// CHECK: dxsa.dcl_input_ps linear v<2> +// CHECK: dxsa.dcl_input_ps linear v<3> +// CHECK: dxsa.dcl_input_ps linear v<4> +// CHECK: dxsa.dcl_input_ps linear v<5> +// CHECK: dxsa.dcl_input_ps linear v<6> +// CHECK: dxsa.dcl_input_ps linear v<7> +// CHECK: dxsa.dcl_output o<0> +// CHECK: dxsa.dcl_temps 3 +// CHECK: dxsa.dcl_index_range v<2>, 6 +// CHECK: dxsa.eval_sample_index r<0>, v<0>, v<1, > +// CHECK: dxsa.eval_sample_index r<1>, v<0>, l(0x3) +// CHECK: dxsa.add r<0>, r<0>, r<1> +// CHECK: dxsa.eval_centroid r<1>, v<0> +// CHECK: dxsa.add r<0>, r<0>, r<1> +// CHECK: dxsa.eval_snapped r<1>, v<0>, l(0xFFFFFFFE, 0x5, 0x0, 0x0) +// CHECK: dxsa.add r<0>, r<0>, r<1> +// CHECK: dxsa.mov r<1, >, v<1, > +// CHECK: dxsa.eval_sample_index r<1>, v<2 + r<1, >, >, v<1, > +// CHECK: dxsa.add r<0>, r<0>, r<1> +// CHECK: dxsa.mov r<1, >, v<1, > +// CHECK: dxsa.eval_centroid r<2>, v<2 + r<1, >> +// CHECK: dxsa.eval_snapped r<1>, v<2 + r<1, >>, l(0xFFFFFFFE, 0x5, 0x0, 0x0) +// CHECK: dxsa.add r<0>, r<0>, r<2> +// CHECK: dxsa.add o<0>, r<1>, r<0> +// CHECK: dxsa.ret + diff --git a/mlir/test/Target/DXSA/hlsl/f32f16.test b/mlir/test/Target/DXSA/hlsl/f32f16.test new file mode 100644 index 000000000000..5e2acbd6cf58 --- /dev/null +++ b/mlir/test/Target/DXSA/hlsl/f32f16.test @@ -0,0 +1,15 @@ +// RUN: mlir-translate --import-dxsa-bin %S/inputs/f32f16.shex | FileCheck %s +// NOTE: Assertions have been autogenerated by utils/generate-test-checks.py + + +// CHECK-LABEL: dxsa.dcl_global_flags +// CHECK: dxsa.dcl_input_ps linear v<0, > +// CHECK: dxsa.dcl_input_ps constant v<1, > +// CHECK: dxsa.dcl_output o<0> +// CHECK: dxsa.dcl_temps 2 +// CHECK: dxsa.f32tof16 r<0>, v<0, > +// CHECK: dxsa.utof r<0>, r<0> +// CHECK: dxsa.f16tof32 r<1>, v<1, > +// CHECK: dxsa.add o<0>, r<0>, r<1> +// CHECK: dxsa.ret + diff --git a/mlir/test/Target/DXSA/hlsl/gather.test b/mlir/test/Target/DXSA/hlsl/gather.test new file mode 100644 index 000000000000..999cd17fa79f --- /dev/null +++ b/mlir/test/Target/DXSA/hlsl/gather.test @@ -0,0 +1,44 @@ +// RUN: mlir-translate --import-dxsa-bin %S/inputs/gather.shex | FileCheck %s +// NOTE: Assertions have been autogenerated by utils/generate-test-checks.py + + +// CHECK-LABEL: dxsa.dcl_global_flags +// CHECK: dxsa.dcl_sampler +// CHECK: dxsa.dcl_resource , , +// CHECK: dxsa.dcl_resource , , +// CHECK: dxsa.dcl_resource , , +// CHECK: dxsa.dcl_input_ps linear v<0> +// CHECK: dxsa.dcl_output o<0> +// CHECK: dxsa.dcl_temps 3 +// CHECK: dxsa.unknown +// CHECK: dxsa.unknown +// CHECK: dxsa.add r<0>, r<0>, r<1> +// CHECK: dxsa.unknown +// CHECK: dxsa.add r<0>, r<0>, r<1> +// CHECK: %[[INDEX_0:.*]] = dxsa.index.imm {imm = 1 : i32} +// CHECK: %[[OPERAND_0:.*]] = dxsa.operand %[[INDEX_0]] {mask = 16 : i32, num_components = 4 : i32, type = 0 : i32} +// CHECK: %[[INDEX_1:.*]] = dxsa.index.imm {imm = 2 : i32} +// CHECK: %[[OPERAND_1:.*]] = dxsa.operand %[[INDEX_1]] {num_components = 4 : i32, one = 0 : i32, type = 0 : i32} +// CHECK: dxsa.instruction "check_access_fully_mapped" %[[OPERAND_0]], %[[OPERAND_1]] +// CHECK: dxsa.utof r<1, >, r<1, > +// CHECK: dxsa.add r<0>, r<0>, r<1, > +// CHECK: dxsa.unknown +// CHECK: dxsa.add r<0>, r<0>, r<1> +// CHECK: %[[INDEX_2:.*]] = dxsa.index.imm {imm = 1 : i32} +// CHECK: %[[OPERAND_2:.*]] = dxsa.operand %[[INDEX_2]] {mask = 16 : i32, num_components = 4 : i32, type = 0 : i32} +// CHECK: %[[INDEX_3:.*]] = dxsa.index.imm {imm = 2 : i32} +// CHECK: %[[OPERAND_3:.*]] = dxsa.operand %[[INDEX_3]] {num_components = 4 : i32, one = 0 : i32, type = 0 : i32} +// CHECK: dxsa.instruction "check_access_fully_mapped" %[[OPERAND_2]], %[[OPERAND_3]] +// CHECK: dxsa.utof r<1, >, r<1, > +// CHECK: dxsa.add r<0>, r<0>, r<1, > +// CHECK: dxsa.unknown +// CHECK: dxsa.add r<0>, r<0>, r<1> +// CHECK: %[[INDEX_4:.*]] = dxsa.index.imm {imm = 1 : i32} +// CHECK: %[[OPERAND_4:.*]] = dxsa.operand %[[INDEX_4]] {mask = 16 : i32, num_components = 4 : i32, type = 0 : i32} +// CHECK: %[[INDEX_5:.*]] = dxsa.index.imm {imm = 2 : i32} +// CHECK: %[[OPERAND_5:.*]] = dxsa.operand %[[INDEX_5]] {num_components = 4 : i32, one = 0 : i32, type = 0 : i32} +// CHECK: dxsa.instruction "check_access_fully_mapped" %[[OPERAND_4]], %[[OPERAND_5]] +// CHECK: dxsa.utof r<1, >, r<1, > +// CHECK: dxsa.add o<0>, r<0>, r<1, > +// CHECK: dxsa.ret + diff --git a/mlir/test/Target/DXSA/hlsl/gather_cmp.test b/mlir/test/Target/DXSA/hlsl/gather_cmp.test new file mode 100644 index 000000000000..4695080f05cc --- /dev/null +++ b/mlir/test/Target/DXSA/hlsl/gather_cmp.test @@ -0,0 +1,44 @@ +// RUN: mlir-translate --import-dxsa-bin %S/inputs/gather_cmp.shex | FileCheck %s +// NOTE: Assertions have been autogenerated by utils/generate-test-checks.py + + +// CHECK-LABEL: dxsa.dcl_global_flags +// CHECK: dxsa.dcl_sampler +// CHECK: dxsa.dcl_resource , , +// CHECK: dxsa.dcl_resource , , +// CHECK: dxsa.dcl_resource , , +// CHECK: dxsa.dcl_input_ps linear v<0> +// CHECK: dxsa.dcl_output o<0> +// CHECK: dxsa.dcl_temps 3 +// CHECK: dxsa.unknown +// CHECK: dxsa.unknown +// CHECK: dxsa.add r<0>, r<0>, r<1> +// CHECK: dxsa.unknown +// CHECK: dxsa.add r<0>, r<0>, r<1> +// CHECK: %[[INDEX_0:.*]] = dxsa.index.imm {imm = 1 : i32} +// CHECK: %[[OPERAND_0:.*]] = dxsa.operand %[[INDEX_0]] {mask = 16 : i32, num_components = 4 : i32, type = 0 : i32} +// CHECK: %[[INDEX_1:.*]] = dxsa.index.imm {imm = 2 : i32} +// CHECK: %[[OPERAND_1:.*]] = dxsa.operand %[[INDEX_1]] {num_components = 4 : i32, one = 0 : i32, type = 0 : i32} +// CHECK: dxsa.instruction "check_access_fully_mapped" %[[OPERAND_0]], %[[OPERAND_1]] +// CHECK: dxsa.utof r<1, >, r<1, > +// CHECK: dxsa.add r<0>, r<0>, r<1, > +// CHECK: dxsa.unknown +// CHECK: dxsa.add r<0>, r<0>, r<1> +// CHECK: %[[INDEX_2:.*]] = dxsa.index.imm {imm = 1 : i32} +// CHECK: %[[OPERAND_2:.*]] = dxsa.operand %[[INDEX_2]] {mask = 16 : i32, num_components = 4 : i32, type = 0 : i32} +// CHECK: %[[INDEX_3:.*]] = dxsa.index.imm {imm = 2 : i32} +// CHECK: %[[OPERAND_3:.*]] = dxsa.operand %[[INDEX_3]] {num_components = 4 : i32, one = 0 : i32, type = 0 : i32} +// CHECK: dxsa.instruction "check_access_fully_mapped" %[[OPERAND_2]], %[[OPERAND_3]] +// CHECK: dxsa.utof r<1, >, r<1, > +// CHECK: dxsa.add r<0>, r<0>, r<1, > +// CHECK: dxsa.unknown +// CHECK: dxsa.add r<0>, r<0>, r<1> +// CHECK: %[[INDEX_4:.*]] = dxsa.index.imm {imm = 1 : i32} +// CHECK: %[[OPERAND_4:.*]] = dxsa.operand %[[INDEX_4]] {mask = 16 : i32, num_components = 4 : i32, type = 0 : i32} +// CHECK: %[[INDEX_5:.*]] = dxsa.index.imm {imm = 2 : i32} +// CHECK: %[[OPERAND_5:.*]] = dxsa.operand %[[INDEX_5]] {num_components = 4 : i32, one = 0 : i32, type = 0 : i32} +// CHECK: dxsa.instruction "check_access_fully_mapped" %[[OPERAND_4]], %[[OPERAND_5]] +// CHECK: dxsa.utof r<1, >, r<1, > +// CHECK: dxsa.add o<0>, r<0>, r<1, > +// CHECK: dxsa.ret + diff --git a/mlir/test/Target/DXSA/hlsl/gather_po.test b/mlir/test/Target/DXSA/hlsl/gather_po.test new file mode 100644 index 000000000000..002da4e12a56 --- /dev/null +++ b/mlir/test/Target/DXSA/hlsl/gather_po.test @@ -0,0 +1,80 @@ +// RUN: mlir-translate --import-dxsa-bin %S/inputs/gather_po.shex | FileCheck %s +// NOTE: Assertions have been autogenerated by utils/generate-test-checks.py + + +// CHECK-LABEL: dxsa.dcl_global_flags +// CHECK: dxsa.dcl_sampler +// CHECK: dxsa.dcl_resource , , +// CHECK: dxsa.dcl_resource , , +// CHECK: dxsa.dcl_input_ps linear v<0> +// CHECK: dxsa.dcl_input_ps linear v<1> +// CHECK: dxsa.dcl_output o<0> +// CHECK: dxsa.dcl_temps 6 +// CHECK: dxsa.ftoi r<0>, v<1> +// CHECK: dxsa.unknown +// CHECK: dxsa.unknown +// CHECK: dxsa.ftoi r<2>, v<0> +// CHECK: dxsa.unknown +// CHECK: dxsa.unknown +// CHECK: dxsa.unknown +// CHECK: %[[INDEX_0:.*]] = dxsa.index.imm {imm = 4 : i32} +// CHECK: %[[OPERAND_0:.*]] = dxsa.operand %[[INDEX_0]] {mask = 16 : i32, num_components = 4 : i32, type = 0 : i32} +// CHECK: %[[INDEX_1:.*]] = dxsa.index.imm {imm = 4 : i32} +// CHECK: %[[OPERAND_1:.*]] = dxsa.operand %[[INDEX_1]] {num_components = 4 : i32, one = 0 : i32, type = 0 : i32} +// CHECK: dxsa.instruction "check_access_fully_mapped" %[[OPERAND_0]], %[[OPERAND_1]] +// CHECK: dxsa.unknown +// CHECK: %[[INDEX_2:.*]] = dxsa.index.imm {imm = 4 : i32} +// CHECK: %[[OPERAND_2:.*]] = dxsa.operand %[[INDEX_2]] {mask = 32 : i32, num_components = 4 : i32, type = 0 : i32} +// CHECK: %[[INDEX_3:.*]] = dxsa.index.imm {imm = 5 : i32} +// CHECK: %[[OPERAND_3:.*]] = dxsa.operand %[[INDEX_3]] {num_components = 4 : i32, one = 0 : i32, type = 0 : i32} +// CHECK: dxsa.instruction "check_access_fully_mapped" %[[OPERAND_2]], %[[OPERAND_3]] +// CHECK: dxsa.and r<4, >, r<4, >, r<4, > +// CHECK: dxsa.unknown +// CHECK: %[[INDEX_4:.*]] = dxsa.index.imm {imm = 4 : i32} +// CHECK: %[[OPERAND_4:.*]] = dxsa.operand %[[INDEX_4]] {mask = 32 : i32, num_components = 4 : i32, type = 0 : i32} +// CHECK: %[[INDEX_5:.*]] = dxsa.index.imm {imm = 5 : i32} +// CHECK: %[[OPERAND_5:.*]] = dxsa.operand %[[INDEX_5]] {num_components = 4 : i32, one = 0 : i32, type = 0 : i32} +// CHECK: dxsa.instruction "check_access_fully_mapped" %[[OPERAND_4]], %[[OPERAND_5]] +// CHECK: dxsa.and r<4, >, r<4, >, r<4, > +// CHECK: dxsa.unknown +// CHECK: %[[INDEX_6:.*]] = dxsa.index.imm {imm = 4 : i32} +// CHECK: %[[OPERAND_6:.*]] = dxsa.operand %[[INDEX_6]] {mask = 32 : i32, num_components = 4 : i32, type = 0 : i32} +// CHECK: %[[INDEX_7:.*]] = dxsa.index.imm {imm = 5 : i32} +// CHECK: %[[OPERAND_7:.*]] = dxsa.operand %[[INDEX_7]] {num_components = 4 : i32, one = 0 : i32, type = 0 : i32} +// CHECK: dxsa.instruction "check_access_fully_mapped" %[[OPERAND_6]], %[[OPERAND_7]] +// CHECK: dxsa.and r<4, >, r<4, >, r<4, > +// CHECK: dxsa.utof r<4, >, r<4, > +// CHECK: dxsa.add r<1>, r<1>, r<3> +// CHECK: dxsa.add r<1>, r<4, >, r<1> +// CHECK: dxsa.unknown +// CHECK: dxsa.unknown +// CHECK: %[[INDEX_8:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_8:.*]] = dxsa.operand %[[INDEX_8]] {mask = 16 : i32, num_components = 4 : i32, type = 0 : i32} +// CHECK: %[[INDEX_9:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_9:.*]] = dxsa.operand %[[INDEX_9]] {num_components = 4 : i32, one = 0 : i32, type = 0 : i32} +// CHECK: dxsa.instruction "check_access_fully_mapped" %[[OPERAND_8]], %[[OPERAND_9]] +// CHECK: %[[INDEX_10:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_10:.*]] = dxsa.operand %[[INDEX_10]] {mask = 32 : i32, num_components = 4 : i32, type = 0 : i32} +// CHECK: %[[INDEX_11:.*]] = dxsa.index.imm {imm = 4 : i32} +// CHECK: %[[OPERAND_11:.*]] = dxsa.operand %[[INDEX_11]] {num_components = 4 : i32, one = 0 : i32, type = 0 : i32} +// CHECK: dxsa.instruction "check_access_fully_mapped" %[[OPERAND_10]], %[[OPERAND_11]] +// CHECK: dxsa.and r<0, >, r<0, >, r<0, > +// CHECK: dxsa.unknown +// CHECK: dxsa.unknown +// CHECK: %[[INDEX_12:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_12:.*]] = dxsa.operand %[[INDEX_12]] {mask = 32 : i32, num_components = 4 : i32, type = 0 : i32} +// CHECK: %[[INDEX_13:.*]] = dxsa.index.imm {imm = 2 : i32} +// CHECK: %[[OPERAND_13:.*]] = dxsa.operand %[[INDEX_13]] {num_components = 4 : i32, one = 0 : i32, type = 0 : i32} +// CHECK: dxsa.instruction "check_access_fully_mapped" %[[OPERAND_12]], %[[OPERAND_13]] +// CHECK: dxsa.and r<0, >, r<0, >, r<0, > +// CHECK: %[[INDEX_14:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_14:.*]] = dxsa.operand %[[INDEX_14]] {mask = 32 : i32, num_components = 4 : i32, type = 0 : i32} +// CHECK: %[[INDEX_15:.*]] = dxsa.index.imm {imm = 4 : i32} +// CHECK: %[[OPERAND_15:.*]] = dxsa.operand %[[INDEX_15]] {num_components = 4 : i32, one = 0 : i32, type = 0 : i32} +// CHECK: dxsa.instruction "check_access_fully_mapped" %[[OPERAND_14]], %[[OPERAND_15]] +// CHECK: dxsa.and r<0, >, r<0, >, r<0, > +// CHECK: dxsa.utof r<0, >, r<0, > +// CHECK: dxsa.add r<1>, r<1>, r<3> +// CHECK: dxsa.add o<0>, r<0, >, r<1> +// CHECK: dxsa.ret + diff --git a/mlir/test/Target/DXSA/hlsl/gather_po_cmp.test b/mlir/test/Target/DXSA/hlsl/gather_po_cmp.test new file mode 100644 index 000000000000..5d39d4963f35 --- /dev/null +++ b/mlir/test/Target/DXSA/hlsl/gather_po_cmp.test @@ -0,0 +1,80 @@ +// RUN: mlir-translate --import-dxsa-bin %S/inputs/gather_po_cmp.shex | FileCheck %s +// NOTE: Assertions have been autogenerated by utils/generate-test-checks.py + + +// CHECK-LABEL: dxsa.dcl_global_flags +// CHECK: dxsa.dcl_sampler +// CHECK: dxsa.dcl_resource , , +// CHECK: dxsa.dcl_resource , , +// CHECK: dxsa.dcl_input_ps linear v<0> +// CHECK: dxsa.dcl_input_ps linear v<1> +// CHECK: dxsa.dcl_output o<0> +// CHECK: dxsa.dcl_temps 6 +// CHECK: dxsa.ftoi r<0>, v<1> +// CHECK: dxsa.unknown +// CHECK: dxsa.unknown +// CHECK: dxsa.ftoi r<2>, v<0> +// CHECK: dxsa.unknown +// CHECK: dxsa.unknown +// CHECK: dxsa.unknown +// CHECK: %[[INDEX_0:.*]] = dxsa.index.imm {imm = 4 : i32} +// CHECK: %[[OPERAND_0:.*]] = dxsa.operand %[[INDEX_0]] {mask = 16 : i32, num_components = 4 : i32, type = 0 : i32} +// CHECK: %[[INDEX_1:.*]] = dxsa.index.imm {imm = 4 : i32} +// CHECK: %[[OPERAND_1:.*]] = dxsa.operand %[[INDEX_1]] {num_components = 4 : i32, one = 0 : i32, type = 0 : i32} +// CHECK: dxsa.instruction "check_access_fully_mapped" %[[OPERAND_0]], %[[OPERAND_1]] +// CHECK: dxsa.unknown +// CHECK: %[[INDEX_2:.*]] = dxsa.index.imm {imm = 4 : i32} +// CHECK: %[[OPERAND_2:.*]] = dxsa.operand %[[INDEX_2]] {mask = 32 : i32, num_components = 4 : i32, type = 0 : i32} +// CHECK: %[[INDEX_3:.*]] = dxsa.index.imm {imm = 5 : i32} +// CHECK: %[[OPERAND_3:.*]] = dxsa.operand %[[INDEX_3]] {num_components = 4 : i32, one = 0 : i32, type = 0 : i32} +// CHECK: dxsa.instruction "check_access_fully_mapped" %[[OPERAND_2]], %[[OPERAND_3]] +// CHECK: dxsa.and r<4, >, r<4, >, r<4, > +// CHECK: dxsa.unknown +// CHECK: %[[INDEX_4:.*]] = dxsa.index.imm {imm = 4 : i32} +// CHECK: %[[OPERAND_4:.*]] = dxsa.operand %[[INDEX_4]] {mask = 32 : i32, num_components = 4 : i32, type = 0 : i32} +// CHECK: %[[INDEX_5:.*]] = dxsa.index.imm {imm = 5 : i32} +// CHECK: %[[OPERAND_5:.*]] = dxsa.operand %[[INDEX_5]] {num_components = 4 : i32, one = 0 : i32, type = 0 : i32} +// CHECK: dxsa.instruction "check_access_fully_mapped" %[[OPERAND_4]], %[[OPERAND_5]] +// CHECK: dxsa.and r<4, >, r<4, >, r<4, > +// CHECK: dxsa.unknown +// CHECK: %[[INDEX_6:.*]] = dxsa.index.imm {imm = 4 : i32} +// CHECK: %[[OPERAND_6:.*]] = dxsa.operand %[[INDEX_6]] {mask = 32 : i32, num_components = 4 : i32, type = 0 : i32} +// CHECK: %[[INDEX_7:.*]] = dxsa.index.imm {imm = 5 : i32} +// CHECK: %[[OPERAND_7:.*]] = dxsa.operand %[[INDEX_7]] {num_components = 4 : i32, one = 0 : i32, type = 0 : i32} +// CHECK: dxsa.instruction "check_access_fully_mapped" %[[OPERAND_6]], %[[OPERAND_7]] +// CHECK: dxsa.and r<4, >, r<4, >, r<4, > +// CHECK: dxsa.utof r<4, >, r<4, > +// CHECK: dxsa.add r<1>, r<1>, r<3> +// CHECK: dxsa.add r<1>, r<4, >, r<1> +// CHECK: dxsa.unknown +// CHECK: dxsa.unknown +// CHECK: %[[INDEX_8:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_8:.*]] = dxsa.operand %[[INDEX_8]] {mask = 16 : i32, num_components = 4 : i32, type = 0 : i32} +// CHECK: %[[INDEX_9:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_9:.*]] = dxsa.operand %[[INDEX_9]] {num_components = 4 : i32, one = 0 : i32, type = 0 : i32} +// CHECK: dxsa.instruction "check_access_fully_mapped" %[[OPERAND_8]], %[[OPERAND_9]] +// CHECK: %[[INDEX_10:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_10:.*]] = dxsa.operand %[[INDEX_10]] {mask = 32 : i32, num_components = 4 : i32, type = 0 : i32} +// CHECK: %[[INDEX_11:.*]] = dxsa.index.imm {imm = 4 : i32} +// CHECK: %[[OPERAND_11:.*]] = dxsa.operand %[[INDEX_11]] {num_components = 4 : i32, one = 0 : i32, type = 0 : i32} +// CHECK: dxsa.instruction "check_access_fully_mapped" %[[OPERAND_10]], %[[OPERAND_11]] +// CHECK: dxsa.and r<0, >, r<0, >, r<0, > +// CHECK: dxsa.unknown +// CHECK: dxsa.unknown +// CHECK: %[[INDEX_12:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_12:.*]] = dxsa.operand %[[INDEX_12]] {mask = 32 : i32, num_components = 4 : i32, type = 0 : i32} +// CHECK: %[[INDEX_13:.*]] = dxsa.index.imm {imm = 2 : i32} +// CHECK: %[[OPERAND_13:.*]] = dxsa.operand %[[INDEX_13]] {num_components = 4 : i32, one = 0 : i32, type = 0 : i32} +// CHECK: dxsa.instruction "check_access_fully_mapped" %[[OPERAND_12]], %[[OPERAND_13]] +// CHECK: dxsa.and r<0, >, r<0, >, r<0, > +// CHECK: %[[INDEX_14:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_14:.*]] = dxsa.operand %[[INDEX_14]] {mask = 32 : i32, num_components = 4 : i32, type = 0 : i32} +// CHECK: %[[INDEX_15:.*]] = dxsa.index.imm {imm = 4 : i32} +// CHECK: %[[OPERAND_15:.*]] = dxsa.operand %[[INDEX_15]] {num_components = 4 : i32, one = 0 : i32, type = 0 : i32} +// CHECK: dxsa.instruction "check_access_fully_mapped" %[[OPERAND_14]], %[[OPERAND_15]] +// CHECK: dxsa.and r<0, >, r<0, >, r<0, > +// CHECK: dxsa.utof r<0, >, r<0, > +// CHECK: dxsa.add r<1>, r<1>, r<3> +// CHECK: dxsa.add o<0>, r<0, >, r<1> +// CHECK: dxsa.ret + diff --git a/mlir/test/Target/DXSA/hlsl/getdim.test b/mlir/test/Target/DXSA/hlsl/getdim.test new file mode 100644 index 000000000000..fdb3a198ad49 --- /dev/null +++ b/mlir/test/Target/DXSA/hlsl/getdim.test @@ -0,0 +1,61 @@ +// RUN: mlir-translate --import-dxsa-bin %S/inputs/getdim.shex | FileCheck %s +// NOTE: Assertions have been autogenerated by utils/generate-test-checks.py + + +// CHECK-LABEL: dxsa.dcl_global_flags +// CHECK: dxsa.dcl_resource , , +// CHECK: dxsa.dcl_resource , , +// CHECK: dxsa.dcl_resource , , +// CHECK: dxsa.unknown +// CHECK: dxsa.dcl_uav_typed , +// CHECK: dxsa.dcl_input_ps linear v<0, > +// CHECK: dxsa.dcl_output o<0> +// CHECK: dxsa.dcl_temps 2 +// CHECK: dxsa.ftou r<0, >, v<0, > +// CHECK: dxsa.unknown +// CHECK: dxsa.iadd r<0, >, r<0, >, r<0, > +// CHECK: dxsa.iadd r<0, >, r<0, >, r<0, > +// CHECK: dxsa.iadd r<0, >, r<0, >, r<0, > +// CHECK: dxsa.unknown +// CHECK: dxsa.iadd r<0, >, r<0, >, r<1, > +// CHECK: dxsa.iadd r<0, >, r<1, >, r<0, > +// CHECK: dxsa.iadd r<0, >, r<0, >, r<0, > +// CHECK: dxsa.utof r<0, >, r<0, > +// CHECK: dxsa.add r<0, >, r<0, >, r<0, > +// CHECK: dxsa.unknown +// CHECK: dxsa.iadd r<0, >, r<0, >, r<1, > +// CHECK: dxsa.iadd r<0, >, r<1, >, r<0, > +// CHECK: dxsa.iadd r<0, >, r<1, >, r<0, > +// CHECK: dxsa.iadd r<0, >, r<1, >, r<0, > +// CHECK: dxsa.utof r<0, >, r<0, > +// CHECK: dxsa.add r<0, >, r<0, >, r<0, > +// CHECK: dxsa.unknown +// CHECK: dxsa.iadd r<0, >, r<0, >, r<1, > +// CHECK: dxsa.iadd r<0, >, r<1, >, r<0, > +// CHECK: dxsa.iadd r<0, >, r<1, >, r<0, > +// CHECK: dxsa.iadd r<0, >, r<1, >, r<0, > +// CHECK: dxsa.utof r<0, >, r<0, > +// CHECK: dxsa.add r<0, >, r<0, >, r<0, > +// CHECK: dxsa.unknown +// CHECK: dxsa.iadd r<0, >, r<0, >, r<1, > +// CHECK: dxsa.iadd r<0, >, r<1, >, r<0, > +// CHECK: dxsa.iadd r<0, >, r<1, >, r<0, > +// CHECK: dxsa.iadd r<0, >, r<1, >, r<0, > +// CHECK: %[[INDEX_0:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_0:.*]] = dxsa.operand %[[INDEX_0]] {mask = 128 : i32, num_components = 4 : i32, type = 0 : i32} +// CHECK: %[[INDEX_1:.*]] = dxsa.index.imm {imm = 3 : i32} +// CHECK: %[[OPERAND_1:.*]] = dxsa.operand %[[INDEX_1]] {num_components = 4 : i32, one = 0 : i32, type = 7 : i32} +// CHECK: dxsa.instruction "sampleinfo" %[[OPERAND_0]], %[[OPERAND_1]] +// CHECK: dxsa.iadd r<0, >, r<0, >, r<0, > +// CHECK: dxsa.utof r<0, >, r<0, > +// CHECK: dxsa.add r<0, >, r<0, >, r<0, > +// CHECK: dxsa.unknown +// CHECK: dxsa.iadd r<0, >, r<0, >, r<1, > +// CHECK: dxsa.iadd r<0, >, r<1, >, r<0, > +// CHECK: dxsa.iadd r<0, >, r<1, >, r<0, > +// CHECK: dxsa.iadd r<0, >, r<1, >, r<0, > +// CHECK: dxsa.iadd r<0, >, r<0, >, r<0, > +// CHECK: dxsa.utof r<0, >, r<0, > +// CHECK: dxsa.add o<0>, r<0, >, r<0, > +// CHECK: dxsa.ret + diff --git a/mlir/test/Target/DXSA/hlsl/gs1.test b/mlir/test/Target/DXSA/hlsl/gs1.test new file mode 100644 index 000000000000..99c33bb5e683 --- /dev/null +++ b/mlir/test/Target/DXSA/hlsl/gs1.test @@ -0,0 +1,34 @@ +// RUN: mlir-translate --import-dxsa-bin %S/inputs/gs1.shex | FileCheck %s +// NOTE: Assertions have been autogenerated by utils/generate-test-checks.py + + +// CHECK-LABEL: dxsa.dcl_global_flags +// CHECK: dxsa.dcl_input v<[6, 0]> +// CHECK: dxsa.dcl_input v<[6, 1], > +// CHECK: dxsa.dcl_input v<[6, 2], > +// CHECK: dxsa.dcl_input v<[6, 3], > +// CHECK: dxsa.dcl_input v<[6, 4], > +// CHECK: dxsa.dcl_input_siv v<[6, 5]>, +// CHECK: dxsa.dcl_temps 1 +// CHECK: dxsa.dcl_index_range v<[6, 2], >, 3 +// CHECK: dxsa.dcl_input_primitive triangle_adj +// CHECK: dxsa.dcl_stream 0 +// CHECK: dxsa.dcl_output_topology trianglestrip +// CHECK: dxsa.dcl_output_siv o<0>, +// CHECK: dxsa.dcl_output o<1, > +// CHECK: dxsa.dcl_output_siv o<2, >, +// CHECK: dxsa.dcl_max_output_vertex_count 18 +// CHECK: dxsa.add r<0, >, v<[1, 0], >, v<[2, 1], > +// CHECK: dxsa.add r<0, >, r<0, >, v<[3, 5], > +// CHECK: dxsa.ftou r<0, >, r<0, > +// CHECK: dxsa.add r<0, >, r<0, >, v<[r<0, >, 2 + r<0, >], > +// CHECK: dxsa.ftou r<0, >, r<0, > +// CHECK: dxsa.mov o<0>, v<[r<0, >, 0]> +// CHECK: dxsa.mov o<1, >, v<[r<0, >, 1], > +// CHECK: dxsa.add r<0, >, l(0x40400000), v<[r<0, >, 0], > +// CHECK: dxsa.ftou r<0, >, r<0, > +// CHECK: dxsa.mov o<2, >, r<0, > +// CHECK: dxsa.emit_stream 0 +// CHECK: dxsa.cut_stream 0 +// CHECK: dxsa.ret + diff --git a/mlir/test/Target/DXSA/hlsl/gs2.test b/mlir/test/Target/DXSA/hlsl/gs2.test new file mode 100644 index 000000000000..484a80c83729 --- /dev/null +++ b/mlir/test/Target/DXSA/hlsl/gs2.test @@ -0,0 +1,61 @@ +// RUN: mlir-translate --import-dxsa-bin %S/inputs/gs2.shex | FileCheck %s +// NOTE: Assertions have been autogenerated by utils/generate-test-checks.py + + +// CHECK-LABEL: dxsa.dcl_global_flags +// CHECK: dxsa.dcl_constant_buffer , +// CHECK: dxsa.dcl_input v<[1, 0]> +// CHECK: dxsa.dcl_temps 2 +// CHECK: dxsa.dcl_input_primitive point +// CHECK: dxsa.dcl_stream 0 +// CHECK: dxsa.dcl_output_topology pointlist +// CHECK: dxsa.dcl_output_siv o<0>, +// CHECK: dxsa.dcl_output o<1, > +// CHECK: dxsa.dcl_stream 1 +// CHECK: dxsa.dcl_output_topology pointlist +// CHECK: dxsa.dcl_output o<0, > +// CHECK: dxsa.dcl_output o<1> +// CHECK: dxsa.dcl_output o<2> +// CHECK: dxsa.dcl_output o<3> +// CHECK: dxsa.dcl_output o<4, > +// CHECK: dxsa.dcl_stream 2 +// CHECK: dxsa.dcl_output_topology pointlist +// CHECK: dxsa.dcl_output_siv o<0>, +// CHECK: dxsa.dcl_output o<1, > +// CHECK: dxsa.dcl_max_output_vertex_count 12 +// CHECK: dxsa.ftou r<0, >, v<[0, 0], > +// CHECK: dxsa.mul r<1>, l(0x42300000, 0x42300000, 0x42300000, 0x42300000), v<[0, 0]> +// CHECK: %[[INDEX_0:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[INDEX_1:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_0:.*]] = dxsa.operand %[[INDEX_0]], %[[INDEX_1]] {num_components = 4 : i32, one = 0 : i32, type = 8 : i32} +// CHECK: dxsa.instruction "if" %[[OPERAND_0]] +// CHECK: dxsa.mov o<0>, v<[0, 0]> +// CHECK: dxsa.mov o<1, >, v<[0, 0], > +// CHECK: dxsa.emit_stream 0 +// CHECK: dxsa.cut_stream 0 +// CHECK: dxsa.mov r<0, >, r<0, > +// CHECK: dxsa.else +// CHECK: dxsa.ftou r<0, >, v<[0, 0], > +// CHECK: dxsa.mov o<0, >, r<0, > +// CHECK: dxsa.mov o<0, >, r<0, > +// CHECK: dxsa.mov o<1>, l(0x0, 0x0, 0x0, 0x0) +// CHECK: dxsa.mov o<2>, l(0x0, 0x0, 0x0, 0x0) +// CHECK: dxsa.mov o<3>, r<1> +// CHECK: dxsa.mov o<4, >, r<0, > +// CHECK: dxsa.emit_stream 1 +// CHECK: dxsa.cut_stream 1 +// CHECK: dxsa.endif +// CHECK: dxsa.mov o<0, >, r<0, > +// CHECK: dxsa.mov o<0, >, r<0, > +// CHECK: dxsa.mov o<1>, l(0x0, 0x0, 0x0, 0x0) +// CHECK: dxsa.mov o<2>, l(0x0, 0x0, 0x0, 0x0) +// CHECK: dxsa.mov o<3>, r<1> +// CHECK: dxsa.mov o<4, >, r<0, > +// CHECK: dxsa.emit_stream 1 +// CHECK: dxsa.cut_stream 1 +// CHECK: dxsa.mov o<0>, v<[0, 0]> +// CHECK: dxsa.mov o<1, >, v<[0, 0], > +// CHECK: dxsa.emit_stream 2 +// CHECK: dxsa.cut_stream 2 +// CHECK: dxsa.ret + diff --git a/mlir/test/Target/DXSA/hlsl/half_rcp.test b/mlir/test/Target/DXSA/hlsl/half_rcp.test new file mode 100644 index 000000000000..4965a532e09f --- /dev/null +++ b/mlir/test/Target/DXSA/hlsl/half_rcp.test @@ -0,0 +1,12 @@ +// RUN: mlir-translate --import-dxsa-bin %S/inputs/half_rcp.shex | FileCheck %s +// NOTE: Assertions have been autogenerated by utils/generate-test-checks.py + + +// CHECK-LABEL: dxsa.dcl_global_flags +// CHECK: dxsa.dcl_output o<0, > +// CHECK: dxsa.dcl_temps 1 +// CHECK: dxsa.mov r<0, min16f, >, l(0x3F000000) +// CHECK: dxsa.rcp r<0, min16f, >, r<0, min16f, > +// CHECK: dxsa.mov o<0, >, r<0, min16f, > +// CHECK: dxsa.ret + diff --git a/mlir/test/Target/DXSA/hlsl/hs1.test b/mlir/test/Target/DXSA/hlsl/hs1.test new file mode 100644 index 000000000000..228546bfa879 --- /dev/null +++ b/mlir/test/Target/DXSA/hlsl/hs1.test @@ -0,0 +1,84 @@ +// RUN: mlir-translate --import-dxsa-bin %S/inputs/hs1.shex | FileCheck %s +// NOTE: Assertions have been autogenerated by utils/generate-test-checks.py + + +// CHECK-LABEL: dxsa.hs_decls +// CHECK: dxsa.dcl_input_control_point_count 16 +// CHECK: dxsa.dcl_output_control_point_count 16 +// CHECK: dxsa.dcl_tessellator_domain domain_quad +// CHECK: dxsa.dcl_tessellator_partitioning partitioning_fractional_odd +// CHECK: dxsa.dcl_tessellator_output_primitive output_triangle_cw +// CHECK: dxsa.dcl_global_flags +// CHECK: dxsa.dcl_constant_buffer , +// CHECK: dxsa.dcl_constant_buffer , +// CHECK: dxsa.dcl_resource , , +// CHECK: dxsa.hs_control_point_phase +// CHECK: dxsa.dcl_input vOutputControlPointID +// CHECK: dxsa.dcl_input vPrim +// CHECK: dxsa.dcl_input v<[16, 0], > +// CHECK: dxsa.dcl_output o<0, > +// CHECK: dxsa.dcl_temps 2 +// CHECK: dxsa.mov r<0, >, vPrim +// CHECK: dxsa.ftou r<0, >, v<[r<0, >, 0], > +// CHECK: dxsa.ftoi r<1>, v<[r<0, >, 0], > +// CHECK: %[[INDEX_0:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_0:.*]] = dxsa.operand %[[INDEX_0]] {mask = 224 : i32, num_components = 4 : i32, type = 0 : i32} +// CHECK: %[[INDEX_1:.*]] = dxsa.index.imm {imm = 1 : i32} +// CHECK: %[[OPERAND_1:.*]] = dxsa.operand %[[INDEX_1]] {num_components = 4 : i32, swizzle = dense<[0, 1, 2, 3]> : vector<4xi32>, type = 0 : i32} +// CHECK: %[[INDEX_2:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[INDEX_3:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_2:.*]] = dxsa.operand %[[INDEX_3]] {num_components = 4 : i32, one = 1 : i32, type = 0 : i32} +// CHECK: %[[INDEX_4:.*]] = dxsa.index.rel.imm %[[OPERAND_2]] {imm = 20 : i32, op = "add"} +// CHECK: %[[OPERAND_3:.*]] = dxsa.operand %[[INDEX_2]], %[[INDEX_4]] {num_components = 4 : i32, swizzle = dense<[3, 0, 1, 2]> : vector<4xi32>, type = 7 : i32} +// CHECK: dxsa.instruction "ld" %[[OPERAND_0]], %[[OPERAND_1]], %[[OPERAND_3]] +// CHECK: dxsa.add r<0, >, r<0, >, v<[r<0, >, 0], > +// CHECK: dxsa.itof r<0, >, cb<[0, 0, 0], vector, > +// CHECK: dxsa.add r<0, >, r<0, >, r<0, > +// CHECK: dxsa.mov r<0, >, vOutputControlPointID +// CHECK: dxsa.add o<0, >, r<0, >, v<[r<0, >, 0], > +// CHECK: dxsa.ret +// CHECK: dxsa.hs_fork_phase +// CHECK: dxsa.dcl_input vPrim +// CHECK: dxsa.dcl_input vicp<[16, 0], > +// CHECK: dxsa.dcl_output_siv o<0, >, +// CHECK: dxsa.dcl_temps 1 +// CHECK: dxsa.mov r<0, >, vPrim +// CHECK: dxsa.mov o<0, >, vicp<[r<0, >, 0], > +// CHECK: dxsa.ret +// CHECK: dxsa.hs_fork_phase +// CHECK: dxsa.dcl_input vPrim +// CHECK: dxsa.dcl_input vicp<[16, 0], > +// CHECK: dxsa.dcl_output_siv o<1, >, +// CHECK: dxsa.dcl_temps 1 +// CHECK: dxsa.mov r<0, >, vPrim +// CHECK: dxsa.mov o<1, >, vicp<[r<0, >, 0], > +// CHECK: dxsa.ret +// CHECK: dxsa.hs_fork_phase +// CHECK: dxsa.dcl_input vPrim +// CHECK: dxsa.dcl_input vicp<[16, 0], > +// CHECK: dxsa.dcl_output_siv o<2, >, +// CHECK: dxsa.dcl_temps 1 +// CHECK: dxsa.mov r<0, >, vPrim +// CHECK: dxsa.mov o<2, >, vicp<[r<0, >, 0], > +// CHECK: dxsa.ret +// CHECK: dxsa.hs_fork_phase +// CHECK: dxsa.dcl_output_siv o<3, >, +// CHECK: dxsa.mov o<3, >, l(0x0) +// CHECK: dxsa.ret +// CHECK: dxsa.hs_fork_phase +// CHECK: dxsa.dcl_input vPrim +// CHECK: dxsa.dcl_input vicp<[16, 0], > +// CHECK: dxsa.dcl_output_siv o<4, >, +// CHECK: dxsa.dcl_temps 1 +// CHECK: dxsa.mov r<0, >, vPrim +// CHECK: dxsa.mov o<4, >, vicp<[r<0, >, 0], > +// CHECK: dxsa.ret +// CHECK: dxsa.hs_fork_phase +// CHECK: dxsa.dcl_input vPrim +// CHECK: dxsa.dcl_input vicp<[16, 0], > +// CHECK: dxsa.dcl_output_siv o<5, >, +// CHECK: dxsa.dcl_temps 1 +// CHECK: dxsa.mov r<0, >, vPrim +// CHECK: dxsa.add o<5, >, cb<[1, 2, 14], vector, >, vicp<[r<0, >, 0], > +// CHECK: dxsa.ret + diff --git a/mlir/test/Target/DXSA/hlsl/hs2.test b/mlir/test/Target/DXSA/hlsl/hs2.test new file mode 100644 index 000000000000..8eccb24f94b7 --- /dev/null +++ b/mlir/test/Target/DXSA/hlsl/hs2.test @@ -0,0 +1,77 @@ +// RUN: mlir-translate --import-dxsa-bin %S/inputs/hs2.shex | FileCheck %s +// NOTE: Assertions have been autogenerated by utils/generate-test-checks.py + + +// CHECK-LABEL: dxsa.hs_decls +// CHECK: dxsa.dcl_input_control_point_count 32 +// CHECK: dxsa.dcl_output_control_point_count 16 +// CHECK: dxsa.dcl_tessellator_domain domain_quad +// CHECK: dxsa.dcl_tessellator_partitioning partitioning_fractional_odd +// CHECK: dxsa.dcl_tessellator_output_primitive output_triangle_cw +// CHECK: dxsa.dcl_hs_max_tessfactor 3.000000e+00 +// CHECK: dxsa.dcl_global_flags +// CHECK: dxsa.hs_control_point_phase +// CHECK: dxsa.dcl_input vOutputControlPointID +// CHECK: dxsa.dcl_input vPrim +// CHECK: dxsa.dcl_input v<[32, 0]> +// CHECK: dxsa.dcl_output o<0> +// CHECK: dxsa.dcl_temps 1 +// CHECK: dxsa.mov r<0, >, vOutputControlPointID +// CHECK: dxsa.mov r<0, >, vPrim +// CHECK: dxsa.add o<0>, v<[r<0, >, 0]>, v<[r<0, >, 0]> +// CHECK: dxsa.ret +// CHECK: dxsa.hs_fork_phase +// CHECK: dxsa.dcl_hs_fork_phase_instance_count 4 +// CHECK: dxsa.dcl_input vPrim +// CHECK: dxsa.dcl_input vForkInstanceID +// CHECK: dxsa.dcl_input vicp<[32, 0], > +// CHECK: dxsa.dcl_output_siv o<0, >, +// CHECK: dxsa.dcl_output_siv o<1, >, +// CHECK: dxsa.dcl_output_siv o<2, >, +// CHECK: dxsa.dcl_output_siv o<3, >, +// CHECK: dxsa.dcl_temps 1 +// CHECK: dxsa.dcl_index_range o<0, >, 4 +// CHECK: dxsa.mov r<0, >, vPrim +// CHECK: dxsa.min r<0, >, l(0x40400000), vicp<[r<0, >, 0], > +// CHECK: dxsa.mov r<0, >, vForkInstanceID> +// CHECK: dxsa.mov o>, >, r<0, > +// CHECK: dxsa.ret +// CHECK: dxsa.hs_fork_phase +// CHECK: dxsa.dcl_input vPrim +// CHECK: dxsa.dcl_input vicp<[32, 0], > +// CHECK: dxsa.dcl_input vocp<[16, 0], > +// CHECK: dxsa.dcl_output o<6> +// CHECK: dxsa.dcl_temps 3 +// CHECK: dxsa.mov r<0>, l(0x0, 0x0, 0x0, 0x0) +// CHECK: dxsa.mov r<1, >, l(0x0) +// CHECK: dxsa.loop +// CHECK: dxsa.ige r<1, >, r<1, >, l(0x20) +// CHECK: %[[INDEX_0:.*]] = dxsa.index.imm {imm = 1 : i32} +// CHECK: %[[OPERAND_0:.*]] = dxsa.operand %[[INDEX_0]] {num_components = 4 : i32, one = 1 : i32, type = 0 : i32} +// CHECK: dxsa.instruction "breakc" %[[OPERAND_0]] +// CHECK: dxsa.mov r<1, >, vPrim +// CHECK: dxsa.mad r<1, >, vicp<[r<1, >, 0], >, vicp<[r<1, >, 0], >, vicp<[r<1, >, 0], > +// CHECK: dxsa.add r<2>, r<1, >, r<0> +// CHECK: dxsa.ushr r<1, >, r<1, >, l(0x1) +// CHECK: dxsa.add r<0>, r<2>, vocp<[r<1, >, 0], > +// CHECK: dxsa.iadd r<1, >, r<1, >, l(0x1) +// CHECK: dxsa.endloop +// CHECK: dxsa.mov o<6>, r<0> +// CHECK: dxsa.ret +// CHECK: dxsa.hs_join_phase +// CHECK: dxsa.dcl_hs_join_phase_instance_count 2 +// CHECK: dxsa.dcl_input vpc<6, > +// CHECK: dxsa.dcl_input vPrim +// CHECK: dxsa.dcl_input vJoinInstanceID +// CHECK: dxsa.dcl_input vicp<[32, 0], > +// CHECK: dxsa.dcl_output_siv o<4, >, +// CHECK: dxsa.dcl_output_siv o<5, >, +// CHECK: dxsa.dcl_temps 1 +// CHECK: dxsa.dcl_index_range o<4, >, 2 +// CHECK: dxsa.mov r<0, >, vPrim +// CHECK: dxsa.add r<0, >, vicp<[r<0, >, 0], >, vpc<6, > +// CHECK: dxsa.min r<0, >, r<0, >, l(0x40400000) +// CHECK: dxsa.mov r<0, >, vJoinInstanceID> +// CHECK: dxsa.mov o<4 + r<0, >, >, r<0, > +// CHECK: dxsa.ret + diff --git a/mlir/test/Target/DXSA/hlsl/icb1.test b/mlir/test/Target/DXSA/hlsl/icb1.test new file mode 100644 index 000000000000..7f1e4070752f --- /dev/null +++ b/mlir/test/Target/DXSA/hlsl/icb1.test @@ -0,0 +1,20 @@ +// RUN: mlir-translate --import-dxsa-bin %S/inputs/icb1.shex | FileCheck %s +// NOTE: Assertions have been autogenerated by utils/generate-test-checks.py + + +// CHECK-LABEL: dxsa.dcl_global_flags +// CHECK: dxsa.dcl_immediate_constant_buffer [1.000000e+00, 0.000000e+00, 0.000000e+00, 0.000000e+00, 0.000000e+00, 1.000000e+00, 0.000000e+00, 0.000000e+00, 0.000000e+00, 0.000000e+00, 1.000000e+00, 0.000000e+00, 0.000000e+00, 0.000000e+00, 0.000000e+00, 1.000000e+00] +// CHECK: dxsa.dcl_input_ps linear v<0> +// CHECK: dxsa.dcl_input_ps linear v<1> +// CHECK: dxsa.dcl_input_ps linear v<2> +// CHECK: dxsa.dcl_input_ps linear v<3> +// CHECK: dxsa.dcl_input_ps constant v<4, > +// CHECK: dxsa.dcl_output o<0, > +// CHECK: dxsa.dcl_temps 2 +// CHECK: dxsa.mov r<0, >, v<4, > +// CHECK: dxsa.dp4 r<1, >, v<0>, icb>, vector> +// CHECK: dxsa.dp4 r<1, >, v<1>, icb>, vector> +// CHECK: dxsa.dp4 r<1, >, v<2>, icb>, vector> +// CHECK: dxsa.dp4 r<1, >, v<3>, icb>, vector> +// CHECK: dxsa.dp4 o<0, >, r<1>, icb>, vector> +// CHECK: dxsa.ret diff --git a/mlir/test/Target/DXSA/hlsl/if1.test b/mlir/test/Target/DXSA/hlsl/if1.test new file mode 100644 index 000000000000..44286d477cac --- /dev/null +++ b/mlir/test/Target/DXSA/hlsl/if1.test @@ -0,0 +1,21 @@ +// RUN: mlir-translate --import-dxsa-bin %S/inputs/if1.shex | FileCheck %s +// NOTE: Assertions have been autogenerated by utils/generate-test-checks.py + + +// CHECK-LABEL: dxsa.dcl_global_flags +// CHECK: dxsa.dcl_input_ps linear v<0, > +// CHECK: dxsa.dcl_input_ps constant v<1, > +// CHECK: dxsa.dcl_output o<0, > +// CHECK: dxsa.dcl_temps 1 +// CHECK: dxsa.ieq r<0, >, v<1, >, l(0x1) +// CHECK: %[[INDEX_0:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_0:.*]] = dxsa.operand %[[INDEX_0]] {num_components = 4 : i32, one = 0 : i32, type = 0 : i32} +// CHECK: dxsa.instruction "if" %[[OPERAND_0]] +// CHECK: dxsa.mov o<0, >, v<0, > +// CHECK: dxsa.ret +// CHECK: dxsa.else +// CHECK: dxsa.mov o<0, >, v<0, > +// CHECK: dxsa.ret +// CHECK: dxsa.endif +// CHECK: dxsa.ret + diff --git a/mlir/test/Target/DXSA/hlsl/if2.test b/mlir/test/Target/DXSA/hlsl/if2.test new file mode 100644 index 000000000000..9fc2af1521fe --- /dev/null +++ b/mlir/test/Target/DXSA/hlsl/if2.test @@ -0,0 +1,19 @@ +// RUN: mlir-translate --import-dxsa-bin %S/inputs/if2.shex | FileCheck %s +// NOTE: Assertions have been autogenerated by utils/generate-test-checks.py + + +// CHECK-LABEL: dxsa.dcl_global_flags +// CHECK: dxsa.dcl_input_ps linear v<0, > +// CHECK: dxsa.dcl_input_ps constant v<1, > +// CHECK: dxsa.dcl_output o<0, > +// CHECK: dxsa.dcl_temps 1 +// CHECK: dxsa.ieq r<0, >, v<1, >, l(0x1) +// CHECK: %[[INDEX_0:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_0:.*]] = dxsa.operand %[[INDEX_0]] {num_components = 4 : i32, one = 0 : i32, type = 0 : i32} +// CHECK: dxsa.instruction "if" %[[OPERAND_0]] +// CHECK: dxsa.mov o<0, >, v<0, > +// CHECK: dxsa.ret +// CHECK: dxsa.endif +// CHECK: dxsa.mov o<0, >, v<0, > +// CHECK: dxsa.ret + diff --git a/mlir/test/Target/DXSA/hlsl/if3.test b/mlir/test/Target/DXSA/hlsl/if3.test new file mode 100644 index 000000000000..031772e4660b --- /dev/null +++ b/mlir/test/Target/DXSA/hlsl/if3.test @@ -0,0 +1,19 @@ +// RUN: mlir-translate --import-dxsa-bin %S/inputs/if3.shex | FileCheck %s +// NOTE: Assertions have been autogenerated by utils/generate-test-checks.py + + +// CHECK-LABEL: dxsa.dcl_global_flags +// CHECK: dxsa.dcl_input_ps linear v<0, > +// CHECK: dxsa.dcl_input_ps constant v<1, > +// CHECK: dxsa.dcl_output o<0, > +// CHECK: dxsa.dcl_temps 1 +// CHECK: dxsa.ieq r<0, >, v<1, >, l(0x1) +// CHECK: %[[INDEX_0:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_0:.*]] = dxsa.operand %[[INDEX_0]] {num_components = 4 : i32, one = 0 : i32, type = 0 : i32} +// CHECK: dxsa.instruction "if" %[[OPERAND_0]] +// CHECK: dxsa.add o<0, >, v<0, >, l(0x40A00000) +// CHECK: dxsa.else +// CHECK: dxsa.add o<0, >, v<0, >, l(0xC29A0000) +// CHECK: dxsa.endif +// CHECK: dxsa.ret + diff --git a/mlir/test/Target/DXSA/hlsl/if4.test b/mlir/test/Target/DXSA/hlsl/if4.test new file mode 100644 index 000000000000..13493c7c60bc --- /dev/null +++ b/mlir/test/Target/DXSA/hlsl/if4.test @@ -0,0 +1,25 @@ +// RUN: mlir-translate --import-dxsa-bin %S/inputs/if4.shex | FileCheck %s +// NOTE: Assertions have been autogenerated by utils/generate-test-checks.py + + +// CHECK-LABEL: dxsa.dcl_global_flags +// CHECK: dxsa.dcl_input_ps linear v<0, > +// CHECK: dxsa.dcl_input_ps constant v<1, > +// CHECK: dxsa.dcl_output o<0, > +// CHECK: dxsa.dcl_temps 1 +// CHECK: dxsa.ieq r<0, >, v<1, >, l(0x1) +// CHECK: %[[INDEX_0:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_0:.*]] = dxsa.operand %[[INDEX_0]] {num_components = 4 : i32, one = 0 : i32, type = 0 : i32} +// CHECK: dxsa.instruction "if" %[[OPERAND_0]] +// CHECK: %[[INDEX_1:.*]] = dxsa.index.imm {imm = 1 : i32} +// CHECK: %[[OPERAND_1:.*]] = dxsa.operand %[[INDEX_1]] {num_components = 4 : i32, one = 1 : i32, type = 1 : i32} +// CHECK: dxsa.instruction "if" %[[OPERAND_1]] +// CHECK: dxsa.add o<0, >, v<0, >, l(0x40A00000) +// CHECK: dxsa.else +// CHECK: dxsa.add o<0, >, v<0, >, l(0xC0000000) +// CHECK: dxsa.endif +// CHECK: dxsa.else +// CHECK: dxsa.add o<0, >, v<0, >, l(0xC29A0000) +// CHECK: dxsa.endif +// CHECK: dxsa.ret + diff --git a/mlir/test/Target/DXSA/hlsl/if5.test b/mlir/test/Target/DXSA/hlsl/if5.test new file mode 100644 index 000000000000..4ac87e32823f --- /dev/null +++ b/mlir/test/Target/DXSA/hlsl/if5.test @@ -0,0 +1,29 @@ +// RUN: mlir-translate --import-dxsa-bin %S/inputs/if5.shex | FileCheck %s +// NOTE: Assertions have been autogenerated by utils/generate-test-checks.py + + +// CHECK-LABEL: dxsa.dcl_global_flags +// CHECK: dxsa.dcl_input_ps linear v<0, > +// CHECK: dxsa.dcl_input_ps constant v<1, > +// CHECK: dxsa.dcl_output o<0, > +// CHECK: dxsa.dcl_temps 1 +// CHECK: dxsa.ieq r<0, >, v<1, >, l(0x1) +// CHECK: %[[INDEX_0:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_0:.*]] = dxsa.operand %[[INDEX_0]] {num_components = 4 : i32, one = 0 : i32, type = 0 : i32} +// CHECK: dxsa.instruction "if" %[[OPERAND_0]] +// CHECK: %[[INDEX_1:.*]] = dxsa.index.imm {imm = 1 : i32} +// CHECK: %[[OPERAND_1:.*]] = dxsa.operand %[[INDEX_1]] {num_components = 4 : i32, one = 1 : i32, type = 1 : i32} +// CHECK: dxsa.instruction "if" %[[OPERAND_1]] +// CHECK: dxsa.add o<0, >, v<0, >, l(0x40A00000) +// CHECK: dxsa.else +// CHECK: dxsa.add o<0, >, v<0, >, l(0xC0000000) +// CHECK: dxsa.endif +// CHECK: dxsa.else +// CHECK: %[[INDEX_2:.*]] = dxsa.index.imm {imm = 1 : i32} +// CHECK: %[[OPERAND_2:.*]] = dxsa.operand %[[INDEX_2]] {num_components = 4 : i32, one = 2 : i32, type = 1 : i32} +// CHECK: dxsa.instruction "if" %[[OPERAND_2]] +// CHECK: dxsa.add o<0, >, v<0, >, l(0xC29A0000) +// CHECK: dxsa.endif +// CHECK: dxsa.endif +// CHECK: dxsa.ret + diff --git a/mlir/test/Target/DXSA/hlsl/indexableinput1.test b/mlir/test/Target/DXSA/hlsl/indexableinput1.test new file mode 100644 index 000000000000..c92b1c6d4b31 --- /dev/null +++ b/mlir/test/Target/DXSA/hlsl/indexableinput1.test @@ -0,0 +1,20 @@ +// RUN: mlir-translate --import-dxsa-bin %S/inputs/indexableinput1.shex | FileCheck %s +// NOTE: Assertions have been autogenerated by utils/generate-test-checks.py + + +// CHECK-LABEL: dxsa.dcl_global_flags +// CHECK: dxsa.dcl_input_ps linear v<0, > +// CHECK: dxsa.dcl_input_ps linear v<2, > +// CHECK: dxsa.dcl_input_ps linear v<4, > +// CHECK: dxsa.dcl_input_ps linear v<5, > +// CHECK: dxsa.dcl_input_ps linear v<6, > +// CHECK: dxsa.dcl_input_ps linear v<7, > +// CHECK: dxsa.dcl_input_ps constant v<8, > +// CHECK: dxsa.dcl_output o<0, > +// CHECK: dxsa.dcl_temps 1 +// CHECK: dxsa.dcl_index_range v<4, >, 4 +// CHECK: dxsa.mov r<0, >, v<8, > +// CHECK: dxsa.add r<0, >, v<2, >, v<4 + r<0, >, > +// CHECK: dxsa.add o<0, >, r<0, >, v<0, > +// CHECK: dxsa.ret + diff --git a/mlir/test/Target/DXSA/hlsl/indexableinput2.test b/mlir/test/Target/DXSA/hlsl/indexableinput2.test new file mode 100644 index 000000000000..62b587b0b572 --- /dev/null +++ b/mlir/test/Target/DXSA/hlsl/indexableinput2.test @@ -0,0 +1,26 @@ +// RUN: mlir-translate --import-dxsa-bin %S/inputs/indexableinput2.shex | FileCheck %s +// NOTE: Assertions have been autogenerated by utils/generate-test-checks.py + + +// CHECK-LABEL: dxsa.dcl_global_flags +// CHECK: dxsa.dcl_input_ps linear v<0, > +// CHECK: dxsa.dcl_input_ps linear v<1, > +// CHECK: dxsa.dcl_input_ps linear v<2, > +// CHECK: dxsa.dcl_input_ps linear v<3, > +// CHECK: dxsa.dcl_input_ps linear v<4, > +// CHECK: dxsa.dcl_input_ps linear v<5, > +// CHECK: dxsa.dcl_input_ps linear v<6, > +// CHECK: dxsa.dcl_input_ps linear v<7, > +// CHECK: dxsa.dcl_input_ps linear v<8, > +// CHECK: dxsa.dcl_input_ps constant v<9, > +// CHECK: dxsa.dcl_input_ps_sgv v<10, >, +// CHECK: dxsa.dcl_output o<0, > +// CHECK: dxsa.dcl_temps 1 +// CHECK: dxsa.dcl_index_range v<0, >, 3 +// CHECK: dxsa.dcl_index_range v<3, >, 6 +// CHECK: dxsa.mov r<0, >, v<10, > +// CHECK: dxsa.add r<0, >, v>, >, v<2, > +// CHECK: dxsa.mov r<0, >, v<9, > +// CHECK: dxsa.add o<0, >, r<0, >, v<3 + r<0, >, > +// CHECK: dxsa.ret + diff --git a/mlir/test/Target/DXSA/hlsl/indexableoutput1.test b/mlir/test/Target/DXSA/hlsl/indexableoutput1.test new file mode 100644 index 000000000000..568b0db7a0c2 --- /dev/null +++ b/mlir/test/Target/DXSA/hlsl/indexableoutput1.test @@ -0,0 +1,12 @@ +// RUN: mlir-translate --import-dxsa-bin %S/inputs/indexableoutput1.shex | FileCheck %s +// NOTE: Assertions have been autogenerated by utils/generate-test-checks.py + + +// CHECK-LABEL: dxsa.dcl_global_flags +// CHECK: dxsa.dcl_input v<0, > +// CHECK: dxsa.dcl_output o<2> +// CHECK: dxsa.dcl_output_siv o<7>, +// CHECK: dxsa.mov o<2>, v<0, > +// CHECK: dxsa.mov o<7>, v<0, > +// CHECK: dxsa.ret + diff --git a/mlir/test/Target/DXSA/hlsl/indexabletemp1.test b/mlir/test/Target/DXSA/hlsl/indexabletemp1.test new file mode 100644 index 000000000000..3f0480308f37 --- /dev/null +++ b/mlir/test/Target/DXSA/hlsl/indexabletemp1.test @@ -0,0 +1,23 @@ +// RUN: mlir-translate --import-dxsa-bin %S/inputs/indexabletemp1.shex | FileCheck %s +// NOTE: Assertions have been autogenerated by utils/generate-test-checks.py + + +// CHECK-LABEL: dxsa.dcl_global_flags +// CHECK: dxsa.dcl_constant_buffer , +// CHECK: dxsa.dcl_input_ps constant v<1, > +// CHECK: dxsa.dcl_input_ps constant v<1, > +// CHECK: dxsa.dcl_output o<0, > +// CHECK: dxsa.dcl_temps 1 +// CHECK: dxsa.dcl_indexable_temp x<0>[6] +// CHECK: dxsa.mov r<0, >, v<1, > +// CHECK: dxsa.mov x<[0, 0], >, cb<[0, r<0, >], vector, > +// CHECK: dxsa.mov x<[0, 1], >, cb<[0, 6 + r<0, >], vector, > +// CHECK: dxsa.iadd r<0>, v<1, >, l(0x2, 0x3, 0x4, 0x5) +// CHECK: dxsa.mov x<[0, 2], >, cb<[0, r<0, >], vector, > +// CHECK: dxsa.mov x<[0, 3], >, cb<[0, r<0, >], vector, > +// CHECK: dxsa.mov x<[0, 4], >, cb<[0, r<0, >], vector, > +// CHECK: dxsa.mov x<[0, 5], >, cb<[0, r<0, >], vector, > +// CHECK: dxsa.iadd r<0, >, v<1, >, v<1, > +// CHECK: dxsa.mov o<0, >, x<[0, r<0, >], > +// CHECK: dxsa.ret + diff --git a/mlir/test/Target/DXSA/hlsl/indexabletemp2.test b/mlir/test/Target/DXSA/hlsl/indexabletemp2.test new file mode 100644 index 000000000000..09cbb944553e --- /dev/null +++ b/mlir/test/Target/DXSA/hlsl/indexabletemp2.test @@ -0,0 +1,27 @@ +// RUN: mlir-translate --import-dxsa-bin %S/inputs/indexabletemp2.shex | FileCheck %s +// NOTE: Assertions have been autogenerated by utils/generate-test-checks.py + + +// CHECK-LABEL: dxsa.dcl_global_flags +// CHECK: dxsa.dcl_constant_buffer , +// CHECK: dxsa.dcl_input_ps constant v<1, > +// CHECK: dxsa.dcl_input_ps constant v<1, > +// CHECK: dxsa.dcl_output o<0, > +// CHECK: dxsa.dcl_temps 1 +// CHECK: dxsa.dcl_indexable_temp x<0>[4] +// CHECK: dxsa.dcl_indexable_temp x<1>[2] +// CHECK: dxsa.mov r<0, >, v<1, > +// CHECK: dxsa.mov x<[0, 0], >, cb<[0, r<0, >], vector, > +// CHECK: dxsa.mov x<[0, 1], >, cb<[0, 4 + r<0, >], vector, > +// CHECK: dxsa.iadd r<0>, v<1, >, l(0x2, 0x3, 0xB, 0xD) +// CHECK: dxsa.mov x<[0, 2], >, cb<[0, r<0, >], vector, > +// CHECK: dxsa.mov x<[0, 3], >, cb<[0, r<0, >], vector, > +// CHECK: dxsa.iadd r<0, >, cb<[0, 12 + r<0, >], vector, >, cb<[0, 16 + r<0, >], vector, > +// CHECK: dxsa.iadd r<0, >, l(0xFFFFFFF3), cb<[0, 16 + r<0, >], vector, > +// CHECK: dxsa.mov x<[1, 0], >, r<0, > +// CHECK: dxsa.mov x<[1, 1], >, r<0, > +// CHECK: dxsa.mov r<0, >, v<1, > +// CHECK: dxsa.mov r<0, >, x<[1, r<0, >], > +// CHECK: dxsa.mov o<0, >, x<[0, r<0, >], > +// CHECK: dxsa.ret + diff --git a/mlir/test/Target/DXSA/hlsl/indexabletemp3.test b/mlir/test/Target/DXSA/hlsl/indexabletemp3.test new file mode 100644 index 000000000000..0ae5cd40e12c --- /dev/null +++ b/mlir/test/Target/DXSA/hlsl/indexabletemp3.test @@ -0,0 +1,18 @@ +// RUN: mlir-translate --import-dxsa-bin %S/inputs/indexabletemp3.shex | FileCheck %s +// NOTE: Assertions have been autogenerated by utils/generate-test-checks.py + + +// CHECK-LABEL: dxsa.dcl_global_flags +// CHECK: dxsa.dcl_constant_buffer , +// CHECK: dxsa.dcl_input_ps constant v<1, > +// CHECK: dxsa.dcl_input_ps constant v<1, > +// CHECK: dxsa.dcl_output o<0, > +// CHECK: dxsa.dcl_temps 1 +// CHECK: dxsa.dcl_indexable_temp x<0>[4] +// CHECK: dxsa.mov r<0, >, v<1, > +// CHECK: dxsa.mov x<[0, 0], >, cb<[0, r<0, >], vector, > +// CHECK: dxsa.mov x<[0, 1], >, cb<[0, 4 + r<0, >], vector, > +// CHECK: dxsa.mov r<0, >, v<1, > +// CHECK: dxsa.mov o<0, >, x<[0, r<0, >], > +// CHECK: dxsa.ret + diff --git a/mlir/test/Target/DXSA/hlsl/indexabletemp5.test b/mlir/test/Target/DXSA/hlsl/indexabletemp5.test new file mode 100644 index 000000000000..c823a655e371 --- /dev/null +++ b/mlir/test/Target/DXSA/hlsl/indexabletemp5.test @@ -0,0 +1,18 @@ +// RUN: mlir-translate --import-dxsa-bin %S/inputs/indexabletemp5.shex | FileCheck %s +// NOTE: Assertions have been autogenerated by utils/generate-test-checks.py + + +// CHECK-LABEL: dxsa.dcl_global_flags +// CHECK: dxsa.dcl_constant_buffer , +// CHECK: dxsa.dcl_input_ps constant v<1, > +// CHECK: dxsa.dcl_input_ps constant v<1, > +// CHECK: dxsa.dcl_output o<0, min16f, > +// CHECK: dxsa.dcl_temps 1 +// CHECK: dxsa.dcl_indexable_temp x<0>[4] +// CHECK: dxsa.mov r<0, >, v<1, > +// CHECK: dxsa.mov x<[0, 0], min16f, >, cb<[0, r<0, >], vector, min16f, > +// CHECK: dxsa.mov x<[0, 1], min16f, >, cb<[0, 4 + r<0, >], vector, min16f, > +// CHECK: dxsa.mov r<0, >, v<1, > +// CHECK: dxsa.mov o<0, min16f, >, x<[0, r<0, >], min16f, > +// CHECK: dxsa.ret + diff --git a/mlir/test/Target/DXSA/hlsl/input1.test b/mlir/test/Target/DXSA/hlsl/input1.test new file mode 100644 index 000000000000..91504ad2cf79 --- /dev/null +++ b/mlir/test/Target/DXSA/hlsl/input1.test @@ -0,0 +1,45 @@ +// RUN: mlir-translate --import-dxsa-bin %S/inputs/input1.shex | FileCheck %s +// NOTE: Assertions have been autogenerated by utils/generate-test-checks.py + + +// CHECK-LABEL: dxsa.dcl_global_flags +// CHECK: dxsa.dcl_input_ps linear v<0> +// CHECK: dxsa.dcl_input_ps constant v<1> +// CHECK: dxsa.dcl_input_ps constant v<2> +// CHECK: dxsa.dcl_input_ps linear v<3, min16f> +// CHECK: dxsa.dcl_input_ps_siv linear v<4, >, +// CHECK: dxsa.dcl_input_ps_siv linear v<4, >, +// CHECK: dxsa.dcl_input_ps constant v<5, > +// CHECK: dxsa.dcl_input_ps_sgv v<5, >, +// CHECK: dxsa.dcl_input_ps_siv constant v<5, >, +// CHECK: dxsa.dcl_input_ps_siv constant v<5, >, +// CHECK: dxsa.dcl_input_ps_siv linearNoPerspective v<6>, +// CHECK: dxsa.dcl_input_ps_sgv v<7, >, +// CHECK: dxsa.dcl_input_ps_sgv v<7, >, +// CHECK: dxsa.dcl_input vCoverage +// CHECK: dxsa.dcl_output o<0> +// CHECK: dxsa.dcl_temps 2 +// CHECK: dxsa.itof r<0>, v<1> +// CHECK: dxsa.add r<0>, r<0>, v<0> +// CHECK: dxsa.utof r<1>, v<2> +// CHECK: dxsa.add r<0>, r<0>, r<1> +// CHECK: dxsa.add r<0>, r<0>, v<3, min16f> +// CHECK: dxsa.add r<0>, r<0>, v<4, > +// CHECK: dxsa.add r<0>, r<0>, v<4, > +// CHECK: dxsa.utof r<1, >, vCoverage> +// CHECK: dxsa.add r<0>, r<0>, r<1, > +// CHECK: dxsa.utof r<1, >, v<5, > +// CHECK: dxsa.add r<0>, r<0>, r<1, > +// CHECK: dxsa.utof r<1, >, v<5, > +// CHECK: dxsa.add r<0>, r<0>, r<1, > +// CHECK: dxsa.utof r<1, >, v<5, > +// CHECK: dxsa.add r<0>, r<0>, r<1, > +// CHECK: dxsa.utof r<1, >, v<5, > +// CHECK: dxsa.add r<0>, r<0>, r<1, > +// CHECK: dxsa.add r<0>, r<0>, v<6> +// CHECK: dxsa.utof r<1, >, v<7, > +// CHECK: dxsa.add r<0>, r<0>, r<1, > +// CHECK: dxsa.and r<1, >, v<7, >, l(0x3F800000) +// CHECK: dxsa.add o<0>, r<0>, r<1, > +// CHECK: dxsa.ret + diff --git a/mlir/test/Target/DXSA/hlsl/input2.test b/mlir/test/Target/DXSA/hlsl/input2.test new file mode 100644 index 000000000000..876e05e3d2a3 --- /dev/null +++ b/mlir/test/Target/DXSA/hlsl/input2.test @@ -0,0 +1,45 @@ +// RUN: mlir-translate --import-dxsa-bin %S/inputs/input2.shex | FileCheck %s +// NOTE: Assertions have been autogenerated by utils/generate-test-checks.py + + +// CHECK-LABEL: dxsa.dcl_global_flags +// CHECK: dxsa.dcl_input_ps linear v<0> +// CHECK: dxsa.dcl_input_ps constant v<1> +// CHECK: dxsa.dcl_input_ps constant v<2> +// CHECK: dxsa.dcl_input_ps linear v<3, min16f> +// CHECK: dxsa.dcl_input_ps_siv linear v<4, >, +// CHECK: dxsa.dcl_input_ps_siv linear v<4, >, +// CHECK: dxsa.dcl_input_ps constant v<5, > +// CHECK: dxsa.dcl_input_ps_sgv v<5, >, +// CHECK: dxsa.dcl_input_ps_siv constant v<5, >, +// CHECK: dxsa.dcl_input_ps_siv constant v<5, >, +// CHECK: dxsa.dcl_input_ps_siv linearNoPerspective v<6>, +// CHECK: dxsa.dcl_input_ps_sgv v<7, >, +// CHECK: dxsa.dcl_input_ps_sgv v<7, >, +// CHECK: dxsa.dcl_input vInnerCoverage +// CHECK: dxsa.dcl_output o<0> +// CHECK: dxsa.dcl_temps 2 +// CHECK: dxsa.itof r<0>, v<1> +// CHECK: dxsa.add r<0>, r<0>, v<0> +// CHECK: dxsa.utof r<1>, v<2> +// CHECK: dxsa.add r<0>, r<0>, r<1> +// CHECK: dxsa.add r<0>, r<0>, v<3, min16f> +// CHECK: dxsa.add r<0>, r<0>, v<4, > +// CHECK: dxsa.add r<0>, r<0>, v<4, > +// CHECK: dxsa.utof r<1, >, vInnerCoverage> +// CHECK: dxsa.add r<0>, r<0>, r<1, > +// CHECK: dxsa.utof r<1, >, v<5, > +// CHECK: dxsa.add r<0>, r<0>, r<1, > +// CHECK: dxsa.utof r<1, >, v<5, > +// CHECK: dxsa.add r<0>, r<0>, r<1, > +// CHECK: dxsa.utof r<1, >, v<5, > +// CHECK: dxsa.add r<0>, r<0>, r<1, > +// CHECK: dxsa.utof r<1, >, v<5, > +// CHECK: dxsa.add r<0>, r<0>, r<1, > +// CHECK: dxsa.add r<0>, r<0>, v<6> +// CHECK: dxsa.utof r<1, >, v<7, > +// CHECK: dxsa.add r<0>, r<0>, r<1, > +// CHECK: dxsa.and r<1, >, v<7, >, l(0x3F800000) +// CHECK: dxsa.add o<0>, r<0>, r<1, > +// CHECK: dxsa.ret + diff --git a/mlir/test/Target/DXSA/hlsl/input3.test b/mlir/test/Target/DXSA/hlsl/input3.test new file mode 100644 index 000000000000..d1995f067c87 --- /dev/null +++ b/mlir/test/Target/DXSA/hlsl/input3.test @@ -0,0 +1,16 @@ +// RUN: mlir-translate --import-dxsa-bin %S/inputs/input3.shex | FileCheck %s +// NOTE: Assertions have been autogenerated by utils/generate-test-checks.py + + +// CHECK-LABEL: dxsa.dcl_global_flags +// CHECK: dxsa.dcl_input v<0> +// CHECK: dxsa.dcl_input_sgv v<1, >, +// CHECK: dxsa.dcl_input_sgv v<2, >, +// CHECK: dxsa.dcl_output_siv o<0>, +// CHECK: dxsa.dcl_temps 2 +// CHECK: dxsa.utof r<0, >, v<1, > +// CHECK: dxsa.add r<0>, r<0, >, v<0> +// CHECK: dxsa.utof r<1, >, v<2, > +// CHECK: dxsa.add o<0>, r<0>, r<1, > +// CHECK: dxsa.ret + diff --git a/mlir/test/Target/DXSA/hlsl/inputs/abs1.shex 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0000000000000000000000000000000000000000..0e1476bbd04877464158a4d1e31e329127159831 GIT binary patch literal 456 zcmWGwU|=W$;w%nE#yK1eEDR3>8JK~5V`Bz}Bn}2}&jC{pb2CsFmNH FBLKkEFb4nt literal 0 HcmV?d00001 diff --git a/mlir/test/Target/DXSA/hlsl/inputs/ubfeu16.shex b/mlir/test/Target/DXSA/hlsl/inputs/ubfeu16.shex new file mode 100644 index 0000000000000000000000000000000000000000..e38cb085a32557c0a00a5fc455c939e474a8f01e GIT binary patch literal 224 zcmWGwU|_HS;w%nE#z+PR7PmeHAdi885r|WPd?5va21W-EkAWeBfq@Cc>SAEv5n@1y zGdeIZNCU+|G%JwiYEXdd0dhfRaVa6G$B+l=`}6<*|8Sr>WOKQY^hhDG +// CHECK: dxsa.dcl_constant_buffer , +// CHECK: dxsa.unknown +// CHECK: dxsa.unknown +// CHECK: dxsa.unknown +// CHECK: dxsa.unknown +// CHECK: dxsa.unknown +// CHECK: dxsa.dcl_output o<0, > +// CHECK: dxsa.dcl_temps 2 +// CHECK: dxsa.mov r<0, >, cb<[0, 0], vector, > +// CHECK: dxsa.unknown +// CHECK: dxsa.mov o<0, >, r<0, > +// CHECK: dxsa.ret +// CHECK: dxsa.label fb<0> +// CHECK: dxsa.mov r<0, >, thisPtr>, vector, > +// CHECK: dxsa.unknown +// CHECK: dxsa.mov r<0, >, thisPtr>, vector, > +// CHECK: dxsa.mov r<1, >, thisPtr>, vector, > +// CHECK: dxsa.add r<0, >, r<0, >, cb<[r<1, >, r<0, >], vector, > +// CHECK: dxsa.ret +// CHECK: dxsa.label fb<1> +// CHECK: dxsa.mov r<0, >, thisPtr>, vector, > +// CHECK: dxsa.unknown +// CHECK: dxsa.mov r<0, >, thisPtr>, vector, > +// CHECK: dxsa.mov r<0, >, thisPtr>, vector, > +// CHECK: dxsa.mul r<0, >, r<0, >, cb<[r<0, >, r<0, >], vector, > +// CHECK: dxsa.ret + diff --git a/mlir/test/Target/DXSA/hlsl/liveness1.test b/mlir/test/Target/DXSA/hlsl/liveness1.test new file mode 100644 index 000000000000..94f2c1f59128 --- /dev/null +++ b/mlir/test/Target/DXSA/hlsl/liveness1.test @@ -0,0 +1,21 @@ +// RUN: mlir-translate --import-dxsa-bin %S/inputs/liveness1.shex | FileCheck %s +// NOTE: Assertions have been autogenerated by utils/generate-test-checks.py + + +// CHECK-LABEL: dxsa.dcl_global_flags +// CHECK: dxsa.dcl_input_ps linear v<0> +// CHECK: dxsa.dcl_input_ps constant v<1, > +// CHECK: dxsa.dcl_output o<0, > +// CHECK: dxsa.dcl_temps 1 +// CHECK: dxsa.dp2 r<0, >, v<0, >, v<0, > +// CHECK: dxsa.ieq r<0, >, v<1, >, l(0x1) +// CHECK: %[[INDEX_0:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_0:.*]] = dxsa.operand %[[INDEX_0]] {num_components = 4 : i32, one = 1 : i32, type = 0 : i32} +// CHECK: dxsa.instruction "if" %[[OPERAND_0]] +// CHECK: dxsa.add r<0, >, r<0, >, l(0x42300000) +// CHECK: dxsa.else +// CHECK: dxsa.add r<0, >, v<0, >, l(0xC29A0000) +// CHECK: dxsa.endif +// CHECK: dxsa.mul o<0, >, r<0, >, r<0, > +// CHECK: dxsa.ret + diff --git a/mlir/test/Target/DXSA/hlsl/loop1.test b/mlir/test/Target/DXSA/hlsl/loop1.test new file mode 100644 index 000000000000..ed545077bd0f --- /dev/null +++ b/mlir/test/Target/DXSA/hlsl/loop1.test @@ -0,0 +1,21 @@ +// RUN: mlir-translate --import-dxsa-bin %S/inputs/loop1.shex | FileCheck %s +// NOTE: Assertions have been autogenerated by utils/generate-test-checks.py + + +// CHECK-LABEL: dxsa.dcl_global_flags +// CHECK: dxsa.dcl_input_ps linear v<0, > +// CHECK: dxsa.dcl_input_ps constant v<1, > +// CHECK: dxsa.dcl_output o<0, > +// CHECK: dxsa.dcl_temps 1 +// CHECK: dxsa.mov r<0, >, l(0x0, 0x0, 0x0, 0x0) +// CHECK: dxsa.loop +// CHECK: dxsa.ige r<0, >, r<0, >, v<1, > +// CHECK: %[[INDEX_0:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_0:.*]] = dxsa.operand %[[INDEX_0]] {num_components = 4 : i32, one = 2 : i32, type = 0 : i32} +// CHECK: dxsa.instruction "breakc" %[[OPERAND_0]] +// CHECK: dxsa.add r<0, >, r<0, >, v<0, > +// CHECK: dxsa.iadd r<0, >, r<0, >, l(0x1) +// CHECK: dxsa.endloop +// CHECK: dxsa.mov o<0, >, r<0, > +// CHECK: dxsa.ret + diff --git a/mlir/test/Target/DXSA/hlsl/loop2.test b/mlir/test/Target/DXSA/hlsl/loop2.test new file mode 100644 index 000000000000..0ad3ce4f91eb --- /dev/null +++ b/mlir/test/Target/DXSA/hlsl/loop2.test @@ -0,0 +1,29 @@ +// RUN: mlir-translate --import-dxsa-bin %S/inputs/loop2.shex | FileCheck %s +// NOTE: Assertions have been autogenerated by utils/generate-test-checks.py + + +// CHECK-LABEL: dxsa.dcl_global_flags +// CHECK: dxsa.dcl_input_ps linear v<0, > +// CHECK: dxsa.dcl_input_ps constant v<1, > +// CHECK: dxsa.dcl_output o<0, > +// CHECK: dxsa.dcl_temps 1 +// CHECK: dxsa.mov r<0, >, l(0x0, 0x0, 0x0, 0x0) +// CHECK: dxsa.mov r<0, >, v<1, > +// CHECK: dxsa.loop +// CHECK: dxsa.ige r<0, >, r<0, >, v<1, > +// CHECK: %[[INDEX_0:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_0:.*]] = dxsa.operand %[[INDEX_0]] {num_components = 4 : i32, one = 3 : i32, type = 0 : i32} +// CHECK: dxsa.instruction "breakc" %[[OPERAND_0]] +// CHECK: %[[INDEX_1:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_1:.*]] = dxsa.operand %[[INDEX_1]] {num_components = 4 : i32, one = 2 : i32, type = 0 : i32} +// CHECK: dxsa.instruction "if" %[[OPERAND_1]] +// CHECK: dxsa.add r<0, >, r<0, >, l(0x43480000) +// CHECK: dxsa.mov r<0, >, r<0, > +// CHECK: dxsa.break +// CHECK: dxsa.endif +// CHECK: dxsa.add r<0, >, r<0, >, v<0, > +// CHECK: dxsa.iadd r<0, >, r<0, >, l(0x1) +// CHECK: dxsa.endloop +// CHECK: dxsa.mov o<0, >, r<0, > +// CHECK: dxsa.ret + diff --git a/mlir/test/Target/DXSA/hlsl/loop3.test b/mlir/test/Target/DXSA/hlsl/loop3.test new file mode 100644 index 000000000000..dc7ecc03889d --- /dev/null +++ b/mlir/test/Target/DXSA/hlsl/loop3.test @@ -0,0 +1,48 @@ +// RUN: mlir-translate --import-dxsa-bin %S/inputs/loop3.shex | FileCheck %s +// NOTE: Assertions have been autogenerated by utils/generate-test-checks.py + + +// CHECK-LABEL: dxsa.dcl_global_flags +// CHECK: dxsa.dcl_input_ps linear v<0, > +// CHECK: dxsa.dcl_input_ps constant v<1, > +// CHECK: dxsa.dcl_output o<0, > +// CHECK: dxsa.dcl_temps 3 +// CHECK: dxsa.mov r<0, >, l(0x10) +// CHECK: dxsa.mov r<1, >, v<1, > +// CHECK: dxsa.mov r<1, >, l(0x0) +// CHECK: dxsa.mov r<0, >, l(0x0) +// CHECK: dxsa.loop +// CHECK: dxsa.ige r<0, >, r<0, >, v<1, > +// CHECK: %[[INDEX_0:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_0:.*]] = dxsa.operand %[[INDEX_0]] {num_components = 4 : i32, one = 3 : i32, type = 0 : i32} +// CHECK: dxsa.instruction "breakc" %[[OPERAND_0]] +// CHECK: dxsa.ieq r<0, >, r<1, >, l(0x9) +// CHECK: %[[INDEX_1:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_1:.*]] = dxsa.operand %[[INDEX_1]] {num_components = 4 : i32, one = 3 : i32, type = 0 : i32} +// CHECK: dxsa.instruction "if" %[[OPERAND_1]] +// CHECK: dxsa.break +// CHECK: dxsa.endif +// CHECK: dxsa.mov r<1, >, r<1, > +// CHECK: dxsa.mov r<0, >, l(0x0) +// CHECK: dxsa.loop +// CHECK: dxsa.ige r<2, >, r<0, >, v<1, > +// CHECK: %[[INDEX_2:.*]] = dxsa.index.imm {imm = 2 : i32} +// CHECK: %[[OPERAND_2:.*]] = dxsa.operand %[[INDEX_2]] {num_components = 4 : i32, one = 0 : i32, type = 0 : i32} +// CHECK: dxsa.instruction "breakc" %[[OPERAND_2]] +// CHECK: dxsa.ieq r<2, >, r<1, >, l(0x10) +// CHECK: %[[INDEX_3:.*]] = dxsa.index.imm {imm = 2 : i32} +// CHECK: %[[OPERAND_3:.*]] = dxsa.operand %[[INDEX_3]] {num_components = 4 : i32, one = 0 : i32, type = 0 : i32} +// CHECK: dxsa.instruction "if" %[[OPERAND_3]] +// CHECK: dxsa.mov r<0, >, r<1, > +// CHECK: dxsa.mov r<1, >, r<0, > +// CHECK: dxsa.break +// CHECK: dxsa.endif +// CHECK: dxsa.add r<1, >, r<1, >, v<0, > +// CHECK: dxsa.iadd r<0, >, r<0, >, l(0x1) +// CHECK: dxsa.endloop +// CHECK: dxsa.mov r<1, >, r<1, > +// CHECK: dxsa.iadd r<0, >, r<0, >, l(0x1) +// CHECK: dxsa.endloop +// CHECK: dxsa.mov o<0, >, r<1, > +// CHECK: dxsa.ret + diff --git a/mlir/test/Target/DXSA/hlsl/loop4.test b/mlir/test/Target/DXSA/hlsl/loop4.test new file mode 100644 index 000000000000..0cdb48d6f9b3 --- /dev/null +++ b/mlir/test/Target/DXSA/hlsl/loop4.test @@ -0,0 +1,46 @@ +// RUN: mlir-translate --import-dxsa-bin %S/inputs/loop4.shex | FileCheck %s +// NOTE: Assertions have been autogenerated by utils/generate-test-checks.py + + +// CHECK-LABEL: dxsa.dcl_global_flags +// CHECK: dxsa.dcl_input_ps linear v<0, > +// CHECK: dxsa.dcl_input_ps constant v<1, > +// CHECK: dxsa.dcl_output o<0, > +// CHECK: dxsa.dcl_temps 3 +// CHECK: dxsa.mov r<0, >, l(0x0, 0x5, 0x7, 0x0) +// CHECK: dxsa.mov r<1, >, v<1, > +// CHECK: dxsa.mov r<1, >, l(0x0) +// CHECK: dxsa.mov r<0, >, l(0x0) +// CHECK: dxsa.loop +// CHECK: dxsa.ige r<1, >, r<1, >, v<1, > +// CHECK: %[[INDEX_0:.*]] = dxsa.index.imm {imm = 1 : i32} +// CHECK: %[[OPERAND_0:.*]] = dxsa.operand %[[INDEX_0]] {num_components = 4 : i32, one = 2 : i32, type = 0 : i32} +// CHECK: dxsa.instruction "breakc" %[[OPERAND_0]] +// CHECK: dxsa.ieq r<1, >, r<1, >, l(0x5) +// CHECK: dxsa.iadd r<0, >, r<1, >, l(0x1) +// CHECK: %[[INDEX_1:.*]] = dxsa.index.imm {imm = 2 : i32} +// CHECK: %[[OPERAND_1:.*]] = dxsa.operand %[[INDEX_1]] {mask = 48 : i32, num_components = 4 : i32, type = 0 : i32} +// CHECK: %[[INDEX_2:.*]] = dxsa.index.imm {imm = 1 : i32} +// CHECK: %[[OPERAND_2:.*]] = dxsa.operand %[[INDEX_2]] {num_components = 4 : i32, swizzle = dense<2> : vector<4xi32>, type = 0 : i32} +// CHECK: %[[INDEX_3:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_3:.*]] = dxsa.operand %[[INDEX_3]] {num_components = 4 : i32, swizzle = dense<[1, 0, 1, 1]> : vector<4xi32>, type = 0 : i32} +// CHECK: %[[INDEX_4:.*]] = dxsa.index.imm {imm = 1 : i32} +// CHECK: %[[OPERAND_4:.*]] = dxsa.operand %[[INDEX_4]] {num_components = 4 : i32, swizzle = dense<[1, 0, 1, 1]> : vector<4xi32>, type = 0 : i32} +// CHECK: dxsa.instruction "movc" %[[OPERAND_1]], %[[OPERAND_2]], %[[OPERAND_3]], %[[OPERAND_4]] +// CHECK: dxsa.mov r<1, >, r<2, > +// CHECK: %[[INDEX_5:.*]] = dxsa.index.imm {imm = 1 : i32} +// CHECK: %[[OPERAND_5:.*]] = dxsa.operand %[[INDEX_5]] {num_components = 4 : i32, one = 2 : i32, type = 0 : i32} +// CHECK: dxsa.instruction "continuec" %[[OPERAND_5]] +// CHECK: dxsa.ieq r<1, >, r<1, >, l(0x7) +// CHECK: %[[INDEX_6:.*]] = dxsa.index.imm {imm = 1 : i32} +// CHECK: %[[OPERAND_6:.*]] = dxsa.operand %[[INDEX_6]] {num_components = 4 : i32, one = 2 : i32, type = 0 : i32} +// CHECK: dxsa.instruction "if" %[[OPERAND_6]] +// CHECK: dxsa.mov r<1, >, r<0, > +// CHECK: dxsa.continue +// CHECK: dxsa.endif +// CHECK: dxsa.add r<0, >, r<0, >, v<0, > +// CHECK: dxsa.iadd r<1, >, r<1, >, l(0x1) +// CHECK: dxsa.endloop +// CHECK: dxsa.mov o<0, >, r<0, > +// CHECK: dxsa.ret + diff --git a/mlir/test/Target/DXSA/hlsl/loop5.test b/mlir/test/Target/DXSA/hlsl/loop5.test new file mode 100644 index 000000000000..031297b7b0fc --- /dev/null +++ b/mlir/test/Target/DXSA/hlsl/loop5.test @@ -0,0 +1,34 @@ +// RUN: mlir-translate --import-dxsa-bin %S/inputs/loop5.shex | FileCheck %s +// NOTE: Assertions have been autogenerated by utils/generate-test-checks.py + + +// CHECK-LABEL: dxsa.dcl_global_flags +// CHECK: dxsa.dcl_input_ps linear v<0, > +// CHECK: dxsa.dcl_input_ps constant v<1, > +// CHECK: dxsa.dcl_output o<0, > +// CHECK: dxsa.dcl_temps 1 +// CHECK: dxsa.mov r<0, >, v<1, > +// CHECK: dxsa.mov r<0, >, l(0x0, 0x0, 0x0, 0x0) +// CHECK: dxsa.loop +// CHECK: dxsa.ige r<0, >, r<0, >, v<1, > +// CHECK: %[[INDEX_0:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_0:.*]] = dxsa.operand %[[INDEX_0]] {num_components = 4 : i32, one = 3 : i32, type = 0 : i32} +// CHECK: dxsa.instruction "breakc" %[[OPERAND_0]] +// CHECK: dxsa.ieq r<0, >, r<0, >, l(0x5) +// CHECK: dxsa.mov o<0, >, r<0, > +// CHECK: %[[INDEX_1:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_1:.*]] = dxsa.operand %[[INDEX_1]] {num_components = 4 : i32, one = 3 : i32, type = 0 : i32} +// CHECK: dxsa.instruction "retc" %[[OPERAND_1]] +// CHECK: dxsa.ieq r<0, >, r<0, >, l(0x7) +// CHECK: %[[INDEX_2:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_2:.*]] = dxsa.operand %[[INDEX_2]] {num_components = 4 : i32, one = 3 : i32, type = 0 : i32} +// CHECK: dxsa.instruction "if" %[[OPERAND_2]] +// CHECK: dxsa.mov o<0, >, r<0, > +// CHECK: dxsa.ret +// CHECK: dxsa.endif +// CHECK: dxsa.add r<0, >, r<0, >, v<0, > +// CHECK: dxsa.iadd r<0, >, r<0, >, l(0x1) +// CHECK: dxsa.endloop +// CHECK: dxsa.mov o<0, >, r<0, > +// CHECK: dxsa.ret + diff --git a/mlir/test/Target/DXSA/hlsl/minprec1.test b/mlir/test/Target/DXSA/hlsl/minprec1.test new file mode 100644 index 000000000000..1976a19ac310 --- /dev/null +++ b/mlir/test/Target/DXSA/hlsl/minprec1.test @@ -0,0 +1,12 @@ +// RUN: mlir-translate --import-dxsa-bin %S/inputs/minprec1.shex | FileCheck %s +// NOTE: Assertions have been autogenerated by utils/generate-test-checks.py + + +// CHECK-LABEL: dxsa.dcl_global_flags +// CHECK: dxsa.dcl_input_ps linear v<0, min16f, > +// CHECK: dxsa.dcl_output o<0, > +// CHECK: dxsa.dcl_temps 1 +// CHECK: dxsa.add r<0, min16f, >, v<0, min16f, >, l(0x40000000) +// CHECK: dxsa.mov o<0, >, r<0, min16f, > +// CHECK: dxsa.ret + diff --git a/mlir/test/Target/DXSA/hlsl/minprec2.test b/mlir/test/Target/DXSA/hlsl/minprec2.test new file mode 100644 index 000000000000..39e1a3a3dca6 --- /dev/null +++ b/mlir/test/Target/DXSA/hlsl/minprec2.test @@ -0,0 +1,10 @@ +// RUN: mlir-translate --import-dxsa-bin %S/inputs/minprec2.shex | FileCheck %s +// NOTE: Assertions have been autogenerated by utils/generate-test-checks.py + + +// CHECK-LABEL: dxsa.dcl_global_flags +// CHECK: dxsa.dcl_input_ps linear v<0, min16f, > +// CHECK: dxsa.dcl_output o<0, > +// CHECK: dxsa.mov o<0, >, v<0, min16f, > +// CHECK: dxsa.ret + diff --git a/mlir/test/Target/DXSA/hlsl/minprec3.test b/mlir/test/Target/DXSA/hlsl/minprec3.test new file mode 100644 index 000000000000..7150d07bddfc --- /dev/null +++ b/mlir/test/Target/DXSA/hlsl/minprec3.test @@ -0,0 +1,21 @@ +// RUN: mlir-translate --import-dxsa-bin %S/inputs/minprec3.shex | FileCheck %s +// NOTE: Assertions have been autogenerated by utils/generate-test-checks.py + + +// CHECK-LABEL: dxsa.dcl_global_flags +// CHECK: dxsa.dcl_input_ps constant v<0, min16i, > +// CHECK: dxsa.dcl_output o<0, > +// CHECK: dxsa.dcl_temps 2 +// CHECK: dxsa.iadd r<0, min16i, >, v<0, min16i, >, l(0x2) +// CHECK: dxsa.ieq r<1, >, r<0, min16i, >, l(0x7) +// CHECK: %[[INDEX_0:.*]] = dxsa.index.imm {imm = 1 : i32} +// CHECK: %[[OPERAND_0:.*]] = dxsa.operand %[[INDEX_0]] {num_components = 4 : i32, one = 0 : i32, type = 0 : i32} +// CHECK: dxsa.instruction "if" %[[OPERAND_0]] +// CHECK: dxsa.mov o<0, >, l(0x4) +// CHECK: dxsa.ret +// CHECK: dxsa.else +// CHECK: dxsa.mov o<0, >, l(0x1) +// CHECK: dxsa.ret +// CHECK: dxsa.endif +// CHECK: dxsa.ret + diff --git a/mlir/test/Target/DXSA/hlsl/minprec4.test b/mlir/test/Target/DXSA/hlsl/minprec4.test new file mode 100644 index 000000000000..37654faeceaa --- /dev/null +++ b/mlir/test/Target/DXSA/hlsl/minprec4.test @@ -0,0 +1,12 @@ +// RUN: mlir-translate --import-dxsa-bin %S/inputs/minprec4.shex | FileCheck %s +// NOTE: Assertions have been autogenerated by utils/generate-test-checks.py + + +// CHECK-LABEL: dxsa.dcl_global_flags +// CHECK: dxsa.dcl_input_ps constant v<0, min16u, > +// CHECK: dxsa.dcl_output o<0, > +// CHECK: dxsa.dcl_temps 1 +// CHECK: dxsa.iadd r<0, min16u, >, v<0, min16u, >, l(0xFFFFFFFD) +// CHECK: dxsa.mov o<0, >, r<0, min16u, > +// CHECK: dxsa.ret + diff --git a/mlir/test/Target/DXSA/hlsl/minprec5.test b/mlir/test/Target/DXSA/hlsl/minprec5.test new file mode 100644 index 000000000000..82a25979ba73 --- /dev/null +++ b/mlir/test/Target/DXSA/hlsl/minprec5.test @@ -0,0 +1,10 @@ +// RUN: mlir-translate --import-dxsa-bin %S/inputs/minprec5.shex | FileCheck %s +// NOTE: Assertions have been autogenerated by utils/generate-test-checks.py + + +// CHECK-LABEL: dxsa.dcl_global_flags +// CHECK: dxsa.dcl_input_ps linear v<0, > +// CHECK: dxsa.dcl_output o<0, min16f, > +// CHECK: dxsa.add o<0, min16f, >, v<0, >, l(0x40A00000) +// CHECK: dxsa.ret + diff --git a/mlir/test/Target/DXSA/hlsl/minprec6.test b/mlir/test/Target/DXSA/hlsl/minprec6.test new file mode 100644 index 000000000000..c7a11db9bcbe --- /dev/null +++ b/mlir/test/Target/DXSA/hlsl/minprec6.test @@ -0,0 +1,23 @@ +// RUN: mlir-translate --import-dxsa-bin %S/inputs/minprec6.shex | FileCheck %s +// NOTE: Assertions have been autogenerated by utils/generate-test-checks.py + + +// CHECK-LABEL: dxsa.dcl_global_flags +// CHECK: dxsa.dcl_constant_buffer , +// CHECK: dxsa.dcl_input_ps constant v<0, min16i, > +// CHECK: dxsa.dcl_output o<0, > +// CHECK: dxsa.dcl_temps 2 +// CHECK: dxsa.iadd r<0, min16i, >, v<0, min16i, >, l(0x2) +// CHECK: dxsa.ieq r<1, >, r<0, min16i, >, cb<[0, 0], vector, min16i, > +// CHECK: %[[INDEX_0:.*]] = dxsa.index.imm {imm = 1 : i32} +// CHECK: %[[OPERAND_0:.*]] = dxsa.operand %[[INDEX_0]] {num_components = 4 : i32, one = 0 : i32, type = 0 : i32} +// CHECK: dxsa.instruction "if" %[[OPERAND_0]] +// CHECK: dxsa.iadd r<0, min16i, >, v<0, min16i, >, l(0xFFFFFFFF) +// CHECK: dxsa.mov o<0, >, r<0, min16i, > +// CHECK: dxsa.ret +// CHECK: dxsa.else +// CHECK: dxsa.mov o<0, >, l(0x1) +// CHECK: dxsa.ret +// CHECK: dxsa.endif +// CHECK: dxsa.ret + diff --git a/mlir/test/Target/DXSA/hlsl/minprec7.test b/mlir/test/Target/DXSA/hlsl/minprec7.test new file mode 100644 index 000000000000..2dda59fab041 --- /dev/null +++ b/mlir/test/Target/DXSA/hlsl/minprec7.test @@ -0,0 +1,12 @@ +// RUN: mlir-translate --import-dxsa-bin %S/inputs/minprec7.shex | FileCheck %s +// NOTE: Assertions have been autogenerated by utils/generate-test-checks.py + + +// CHECK-LABEL: dxsa.dcl_global_flags +// CHECK: dxsa.dcl_input_ps linear v<0, > +// CHECK: dxsa.dcl_output o<0, > +// CHECK: dxsa.dcl_temps 1 +// CHECK: dxsa.add r<0, min16f, >, v<0, >, l(0x40A00000) +// CHECK: dxsa.mov o<0, >, r<0, min16f, > +// CHECK: dxsa.ret + diff --git a/mlir/test/Target/DXSA/hlsl/neg1.test b/mlir/test/Target/DXSA/hlsl/neg1.test new file mode 100644 index 000000000000..cf73be85f555 --- /dev/null +++ b/mlir/test/Target/DXSA/hlsl/neg1.test @@ -0,0 +1,10 @@ +// RUN: mlir-translate --import-dxsa-bin %S/inputs/neg1.shex | FileCheck %s +// NOTE: Assertions have been autogenerated by utils/generate-test-checks.py + + +// CHECK-LABEL: dxsa.dcl_global_flags +// CHECK: dxsa.dcl_input_ps linear v<0, > +// CHECK: dxsa.dcl_output o<0> +// CHECK: dxsa.mov o<0>, -v<0, > +// CHECK: dxsa.ret + diff --git a/mlir/test/Target/DXSA/hlsl/neg2.test b/mlir/test/Target/DXSA/hlsl/neg2.test new file mode 100644 index 000000000000..e4514ed1526d --- /dev/null +++ b/mlir/test/Target/DXSA/hlsl/neg2.test @@ -0,0 +1,10 @@ +// RUN: mlir-translate --import-dxsa-bin %S/inputs/neg2.shex | FileCheck %s +// NOTE: Assertions have been autogenerated by utils/generate-test-checks.py + + +// CHECK-LABEL: dxsa.dcl_global_flags +// CHECK: dxsa.dcl_input_ps constant v<0, > +// CHECK: dxsa.dcl_output o<0> +// CHECK: dxsa.ineg o<0>, v<0, > +// CHECK: dxsa.ret + diff --git a/mlir/test/Target/DXSA/hlsl/negabs1.test b/mlir/test/Target/DXSA/hlsl/negabs1.test new file mode 100644 index 000000000000..1ddccf1c262c --- /dev/null +++ b/mlir/test/Target/DXSA/hlsl/negabs1.test @@ -0,0 +1,10 @@ +// RUN: mlir-translate --import-dxsa-bin %S/inputs/negabs1.shex | FileCheck %s +// NOTE: Assertions have been autogenerated by utils/generate-test-checks.py + + +// CHECK-LABEL: dxsa.dcl_global_flags +// CHECK: dxsa.dcl_input_ps linear v<0, > +// CHECK: dxsa.dcl_output o<0> +// CHECK: dxsa.mov o<0>, -|v<0, >| +// CHECK: dxsa.ret + diff --git a/mlir/test/Target/DXSA/hlsl/nonuniform1.test b/mlir/test/Target/DXSA/hlsl/nonuniform1.test new file mode 100644 index 000000000000..5d9d0831c076 --- /dev/null +++ b/mlir/test/Target/DXSA/hlsl/nonuniform1.test @@ -0,0 +1,48 @@ +// RUN: mlir-translate --import-dxsa-bin %S/inputs/nonuniform1.shex | FileCheck %s +// NOTE: Assertions have been autogenerated by utils/generate-test-checks.py + + +// CHECK-LABEL: dxsa.dcl_global_flags +// CHECK: dxsa.dcl_sampler +// CHECK: dxsa.dcl_resource , , +// CHECK: dxsa.dcl_input_ps constant v<0, > +// CHECK: dxsa.dcl_input_ps linear v<1, > +// CHECK: dxsa.dcl_output o<0> +// CHECK: dxsa.dcl_temps 2 +// CHECK: dxsa.itof r<0, >, v<0, > +// CHECK: dxsa.mov r<0, >, v<0, > +// CHECK: %[[INDEX_0:.*]] = dxsa.index.imm {imm = 1 : i32} +// CHECK: %[[OPERAND_0:.*]] = dxsa.operand %[[INDEX_0]] {mask = 240 : i32, num_components = 4 : i32, type = 0 : i32} +// CHECK: %[[INDEX_1:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_1:.*]] = dxsa.operand %[[INDEX_1]] {num_components = 4 : i32, swizzle = dense<0> : vector<4xi32>, type = 0 : i32} +// CHECK: %[[INDEX_2:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[INDEX_3:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_2:.*]] = dxsa.operand %[[INDEX_3]] {num_components = 4 : i32, one = 1 : i32, type = 0 : i32} +// CHECK: %[[INDEX_4:.*]] = dxsa.index.rel.imm %[[OPERAND_2]] {imm = 3 : i32, op = "add"} +// CHECK: %[[OPERAND_3:.*]] = dxsa.operand %[[INDEX_2]], %[[INDEX_4]] {non_uniform = 1 : i32, num_components = 4 : i32, swizzle = dense<[0, 1, 2, 3]> : vector<4xi32>, type = 7 : i32} +// CHECK: %[[INDEX_5:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[INDEX_6:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_4:.*]] = dxsa.operand %[[INDEX_6]] {num_components = 4 : i32, one = 1 : i32, type = 0 : i32} +// CHECK: %[[INDEX_7:.*]] = dxsa.index.rel.imm %[[OPERAND_4]] {imm = 2 : i32, op = "add"} +// CHECK: %[[OPERAND_5:.*]] = dxsa.operand %[[INDEX_5]], %[[INDEX_7]] {non_uniform = 1 : i32, num_components = 0 : i32, type = 6 : i32} +// CHECK: dxsa.instruction "sample" %[[OPERAND_0]], %[[OPERAND_1]], %[[OPERAND_3]], %[[OPERAND_5]] +// CHECK: dxsa.ftou r<0, >, v<1, > +// CHECK: dxsa.add r<0, >, v<1, >, l(0x40000000) +// CHECK: %[[INDEX_8:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_6:.*]] = dxsa.operand %[[INDEX_8]] {mask = 240 : i32, num_components = 4 : i32, type = 0 : i32} +// CHECK: %[[INDEX_9:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_7:.*]] = dxsa.operand %[[INDEX_9]] {num_components = 4 : i32, swizzle = dense<2> : vector<4xi32>, type = 0 : i32} +// CHECK: %[[INDEX_10:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[INDEX_11:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_8:.*]] = dxsa.operand %[[INDEX_11]] {num_components = 4 : i32, one = 0 : i32, type = 0 : i32} +// CHECK: %[[INDEX_12:.*]] = dxsa.index.rel.imm %[[OPERAND_8]] {imm = 3 : i32, op = "add"} +// CHECK: %[[OPERAND_9:.*]] = dxsa.operand %[[INDEX_10]], %[[INDEX_12]] {non_uniform = 1 : i32, num_components = 4 : i32, swizzle = dense<[0, 1, 2, 3]> : vector<4xi32>, type = 7 : i32} +// CHECK: %[[INDEX_13:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[INDEX_14:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_10:.*]] = dxsa.operand %[[INDEX_14]] {num_components = 4 : i32, one = 1 : i32, type = 0 : i32} +// CHECK: %[[INDEX_15:.*]] = dxsa.index.rel.imm %[[OPERAND_10]] {imm = 2 : i32, op = "add"} +// CHECK: %[[OPERAND_11:.*]] = dxsa.operand %[[INDEX_13]], %[[INDEX_15]] {num_components = 0 : i32, type = 6 : i32} +// CHECK: dxsa.instruction "sample" %[[OPERAND_6]], %[[OPERAND_7]], %[[OPERAND_9]], %[[OPERAND_11]] +// CHECK: dxsa.add o<0>, r<0>, r<1> +// CHECK: dxsa.ret + diff --git a/mlir/test/Target/DXSA/hlsl/output1.test b/mlir/test/Target/DXSA/hlsl/output1.test new file mode 100644 index 000000000000..ea1b4d8981a7 --- /dev/null +++ b/mlir/test/Target/DXSA/hlsl/output1.test @@ -0,0 +1,21 @@ +// RUN: mlir-translate --import-dxsa-bin %S/inputs/output1.shex | FileCheck %s +// NOTE: Assertions have been autogenerated by utils/generate-test-checks.py + + +// CHECK-LABEL: dxsa.dcl_global_flags +// CHECK: dxsa.dcl_input_ps linear v<0> +// CHECK: dxsa.dcl_input_ps_sgv v<1, >, +// CHECK: dxsa.dcl_input_ps_sgv v<1, >, +// CHECK: dxsa.dcl_output o<0> +// CHECK: dxsa.dcl_output o<5> +// CHECK: dxsa.dcl_output oDepth +// CHECK: dxsa.dcl_temps 2 +// CHECK: dxsa.utof r<0, >, v<1, > +// CHECK: dxsa.add r<0>, r<0, >, v<0> +// CHECK: dxsa.and r<1, >, v<1, >, l(0x3F800000) +// CHECK: dxsa.add r<0>, r<0>, r<1, > +// CHECK: dxsa.mov oDepth, r<0, > +// CHECK: dxsa.mov o<0>, r<0> +// CHECK: dxsa.mov o<5>, r<0> +// CHECK: dxsa.ret + diff --git a/mlir/test/Target/DXSA/hlsl/output2.test b/mlir/test/Target/DXSA/hlsl/output2.test new file mode 100644 index 000000000000..a3dee2349eb7 --- /dev/null +++ b/mlir/test/Target/DXSA/hlsl/output2.test @@ -0,0 +1,17 @@ +// RUN: mlir-translate --import-dxsa-bin %S/inputs/output2.shex | FileCheck %s +// NOTE: Assertions have been autogenerated by utils/generate-test-checks.py + + +// CHECK-LABEL: dxsa.dcl_global_flags +// CHECK: dxsa.dcl_input_ps linear v<0> +// CHECK: dxsa.dcl_input_ps linear v<1> +// CHECK: dxsa.dcl_output o<0> +// CHECK: dxsa.dcl_output o<5> +// CHECK: dxsa.dcl_output oDepthGE +// CHECK: dxsa.dcl_temps 1 +// CHECK: dxsa.add r<0>, v<0>, v<1> +// CHECK: dxsa.mov oDepthGE, r<0, > +// CHECK: dxsa.mov o<0>, r<0> +// CHECK: dxsa.mov o<5>, r<0> +// CHECK: dxsa.ret + diff --git a/mlir/test/Target/DXSA/hlsl/output3.test b/mlir/test/Target/DXSA/hlsl/output3.test new file mode 100644 index 000000000000..3af3981c89e5 --- /dev/null +++ b/mlir/test/Target/DXSA/hlsl/output3.test @@ -0,0 +1,16 @@ +// RUN: mlir-translate --import-dxsa-bin %S/inputs/output3.shex | FileCheck %s +// NOTE: Assertions have been autogenerated by utils/generate-test-checks.py + + +// CHECK-LABEL: dxsa.dcl_global_flags +// CHECK: dxsa.dcl_input_ps linear v<0> +// CHECK: dxsa.dcl_output o<0> +// CHECK: dxsa.dcl_output o<5> +// CHECK: dxsa.dcl_output oDepthLE +// CHECK: dxsa.dcl_output oStencilRef +// CHECK: dxsa.mov oDepthLE, v<0, > +// CHECK: dxsa.ftou oStencilRef, v<0, > +// CHECK: dxsa.mov o<0>, v<0> +// CHECK: dxsa.mov o<5>, v<0> +// CHECK: dxsa.ret + diff --git a/mlir/test/Target/DXSA/hlsl/output4.test b/mlir/test/Target/DXSA/hlsl/output4.test new file mode 100644 index 000000000000..a6da6766a655 --- /dev/null +++ b/mlir/test/Target/DXSA/hlsl/output4.test @@ -0,0 +1,16 @@ +// RUN: mlir-translate --import-dxsa-bin %S/inputs/output4.shex | FileCheck %s +// NOTE: Assertions have been autogenerated by utils/generate-test-checks.py + + +// CHECK-LABEL: dxsa.dcl_global_flags +// CHECK: dxsa.dcl_input v<0> +// CHECK: dxsa.dcl_output_siv o<0>, +// CHECK: dxsa.dcl_output_siv o<1, min16f, >, +// CHECK: dxsa.dcl_output_siv o<1, >, +// CHECK: dxsa.dcl_output_siv o<2, min16f, >, +// CHECK: dxsa.mov o<0>, v<0> +// CHECK: dxsa.mov o<1, min16f, >, v<0, > +// CHECK: dxsa.mov o<1, >, v<0, > +// CHECK: dxsa.mov o<2, min16f, >, v<0, > +// CHECK: dxsa.ret + diff --git a/mlir/test/Target/DXSA/hlsl/passthrough1.test b/mlir/test/Target/DXSA/hlsl/passthrough1.test new file mode 100644 index 000000000000..1d48cc421b7a --- /dev/null +++ b/mlir/test/Target/DXSA/hlsl/passthrough1.test @@ -0,0 +1,10 @@ +// RUN: mlir-translate --import-dxsa-bin %S/inputs/passthrough1.shex | FileCheck %s +// NOTE: Assertions have been autogenerated by utils/generate-test-checks.py + + +// CHECK-LABEL: dxsa.dcl_global_flags +// CHECK: dxsa.dcl_input v<0> +// CHECK: dxsa.dcl_output_siv o<0>, +// CHECK: dxsa.mov o<0>, v<0> +// CHECK: dxsa.ret + diff --git a/mlir/test/Target/DXSA/hlsl/passthrough2.test b/mlir/test/Target/DXSA/hlsl/passthrough2.test new file mode 100644 index 000000000000..ce8c3116a3b1 --- /dev/null +++ b/mlir/test/Target/DXSA/hlsl/passthrough2.test @@ -0,0 +1,10 @@ +// RUN: mlir-translate --import-dxsa-bin %S/inputs/passthrough2.shex | FileCheck %s +// NOTE: Assertions have been autogenerated by utils/generate-test-checks.py + + +// CHECK-LABEL: dxsa.dcl_global_flags +// CHECK: dxsa.dcl_input_ps linear v<0, > +// CHECK: dxsa.dcl_output o<0> +// CHECK: dxsa.mov o<0>, v<0, > +// CHECK: dxsa.ret + diff --git a/mlir/test/Target/DXSA/hlsl/precise1.test b/mlir/test/Target/DXSA/hlsl/precise1.test new file mode 100644 index 000000000000..5c19474e267f --- /dev/null +++ b/mlir/test/Target/DXSA/hlsl/precise1.test @@ -0,0 +1,17 @@ +// RUN: mlir-translate --import-dxsa-bin %S/inputs/precise1.shex | FileCheck %s +// NOTE: Assertions have been autogenerated by utils/generate-test-checks.py + + +// CHECK-LABEL: dxsa.dcl_global_flags +// CHECK: dxsa.dcl_constant_buffer , +// CHECK: dxsa.dcl_sampler +// CHECK: dxsa.dcl_resource , , +// CHECK: dxsa.dcl_input_ps linear v<0, > +// CHECK: dxsa.dcl_output o<0> +// CHECK: dxsa.dcl_temps 1 +// CHECK: dxsa.unknown +// CHECK: dxsa.mul precise r<0>, r<0>, cb<[0, 0], vector> +// CHECK: dxsa.mad precise r<0>, r<0>, cb<[0, 1], vector>, cb<[0, 2], vector> +// CHECK: dxsa.mov precise o<0>, -r<0> +// CHECK: dxsa.ret + diff --git a/mlir/test/Target/DXSA/hlsl/raw_buf1.test b/mlir/test/Target/DXSA/hlsl/raw_buf1.test new file mode 100644 index 000000000000..ac21e634bf5c --- /dev/null +++ b/mlir/test/Target/DXSA/hlsl/raw_buf1.test @@ -0,0 +1,150 @@ +// RUN: mlir-translate --import-dxsa-bin %S/inputs/raw_buf1.shex | FileCheck %s +// NOTE: Assertions have been autogenerated by utils/generate-test-checks.py + + +// CHECK-LABEL: dxsa.dcl_global_flags +// CHECK: dxsa.dcl_resource_raw +// CHECK: dxsa.dcl_uav_raw +// CHECK: dxsa.dcl_input_ps linear v<0, > +// CHECK: dxsa.dcl_input_ps linear v<0, > +// CHECK: dxsa.dcl_output o<0> +// CHECK: dxsa.dcl_temps 16 +// CHECK: dxsa.ftou r<0, >, v<0, > +// CHECK: dxsa.unknown +// CHECK: dxsa.add r<1, >, v<0, >, l(0x3F800000, 0x40000000, 0x40400000, 0x0) +// CHECK: dxsa.ftou r<1, >, r<1, > +// CHECK: dxsa.unknown +// CHECK: dxsa.unknown +// CHECK: dxsa.utof r<3, >, r<3, > +// CHECK: dxsa.unknown +// CHECK: dxsa.utof r<4>, r<4> +// CHECK: dxsa.unknown +// CHECK: dxsa.unknown +// CHECK: dxsa.unknown +// CHECK: dxsa.unknown +// CHECK: dxsa.unknown +// CHECK: dxsa.utof r<13, min16f, >, r<0, > +// CHECK: dxsa.unknown +// CHECK: dxsa.utof r<2>, r<2> +// CHECK: dxsa.add r<2, >, r<2, >, r<13, min16f, > +// CHECK: dxsa.unknown +// CHECK: dxsa.utof r<5, >, r<5, > +// CHECK: dxsa.add r<14, >, r<2, >, r<5, > +// CHECK: dxsa.add r<14, >, r<5, >, r<13, min16f, > +// CHECK: dxsa.unknown +// CHECK: dxsa.utof r<15>, r<15> +// CHECK: dxsa.add r<14, >, r<14, >, r<15, > +// CHECK: dxsa.add r<14, >, r<13, min16f, >, r<15, > +// CHECK: dxsa.unknown +// CHECK: %[[INDEX_0:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_0:.*]] = dxsa.operand %[[INDEX_0]] {mask = 128 : i32, num_components = 4 : i32, type = 0 : i32} +// CHECK: %[[INDEX_1:.*]] = dxsa.index.imm {imm = 15 : i32} +// CHECK: %[[OPERAND_1:.*]] = dxsa.operand %[[INDEX_1]] {num_components = 4 : i32, one = 0 : i32, type = 0 : i32} +// CHECK: dxsa.instruction "check_access_fully_mapped" %[[OPERAND_0]], %[[OPERAND_1]] +// CHECK: dxsa.utof r<0, >, r<0, > +// CHECK: dxsa.add r<13>, r<0, >, r<14> +// CHECK: dxsa.add r<13>, r<0, >, r<13> +// CHECK: dxsa.unknown +// CHECK: %[[INDEX_2:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_2:.*]] = dxsa.operand %[[INDEX_2]] {mask = 128 : i32, num_components = 4 : i32, type = 0 : i32} +// CHECK: %[[INDEX_3:.*]] = dxsa.index.imm {imm = 1 : i32} +// CHECK: %[[OPERAND_3:.*]] = dxsa.operand %[[INDEX_3]] {num_components = 4 : i32, one = 0 : i32, type = 0 : i32} +// CHECK: dxsa.instruction "check_access_fully_mapped" %[[OPERAND_2]], %[[OPERAND_3]] +// CHECK: dxsa.utof r<0, >, r<0, > +// CHECK: dxsa.add r<13, >, r<0, >, r<13, > +// CHECK: dxsa.add r<13>, r<0, >, r<13> +// CHECK: dxsa.unknown +// CHECK: dxsa.unknown +// CHECK: %[[INDEX_4:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_4:.*]] = dxsa.operand %[[INDEX_4]] {mask = 128 : i32, num_components = 4 : i32, type = 0 : i32} +// CHECK: %[[INDEX_5:.*]] = dxsa.index.imm {imm = 1 : i32} +// CHECK: %[[OPERAND_5:.*]] = dxsa.operand %[[INDEX_5]] {num_components = 4 : i32, one = 0 : i32, type = 0 : i32} +// CHECK: dxsa.instruction "check_access_fully_mapped" %[[OPERAND_4]], %[[OPERAND_5]] +// CHECK: dxsa.utof r<0, >, r<0, > +// CHECK: dxsa.add r<13, >, r<0, >, r<13, > +// CHECK: dxsa.add r<1>, r<0, >, r<13> +// CHECK: dxsa.utof r<0, >, r<14, > +// CHECK: %[[INDEX_6:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_6:.*]] = dxsa.operand %[[INDEX_6]] {mask = 128 : i32, num_components = 4 : i32, type = 0 : i32} +// CHECK: %[[INDEX_7:.*]] = dxsa.index.imm {imm = 15 : i32} +// CHECK: %[[OPERAND_7:.*]] = dxsa.operand %[[INDEX_7]] {num_components = 4 : i32, one = 0 : i32, type = 0 : i32} +// CHECK: dxsa.instruction "check_access_fully_mapped" %[[OPERAND_6]], %[[OPERAND_7]] +// CHECK: dxsa.utof r<0, >, r<0, > +// CHECK: dxsa.add r<1>, r<0, >, r<1> +// CHECK: dxsa.add r<1>, r<0, >, r<1> +// CHECK: dxsa.add r<1>, r<0, >, r<1> +// CHECK: dxsa.add r<1, >, r<2, >, r<1, > +// CHECK: dxsa.add r<1, >, r<3, >, r<1, > +// CHECK: dxsa.add r<1>, r<4>, r<1> +// CHECK: dxsa.utof r<0, >, r<5, > +// CHECK: %[[INDEX_8:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_8:.*]] = dxsa.operand %[[INDEX_8]] {mask = 64 : i32, num_components = 4 : i32, type = 0 : i32} +// CHECK: %[[INDEX_9:.*]] = dxsa.index.imm {imm = 6 : i32} +// CHECK: %[[OPERAND_9:.*]] = dxsa.operand %[[INDEX_9]] {num_components = 4 : i32, one = 0 : i32, type = 0 : i32} +// CHECK: dxsa.instruction "check_access_fully_mapped" %[[OPERAND_8]], %[[OPERAND_9]] +// CHECK: dxsa.utof r<0, >, r<0, > +// CHECK: dxsa.add r<1>, r<0, >, r<1> +// CHECK: dxsa.add r<1>, r<0, >, r<1> +// CHECK: dxsa.utof r<0, >, r<7, > +// CHECK: %[[INDEX_10:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_10:.*]] = dxsa.operand %[[INDEX_10]] {mask = 64 : i32, num_components = 4 : i32, type = 0 : i32} +// CHECK: %[[INDEX_11:.*]] = dxsa.index.imm {imm = 8 : i32} +// CHECK: %[[OPERAND_11:.*]] = dxsa.operand %[[INDEX_11]] {num_components = 4 : i32, one = 0 : i32, type = 0 : i32} +// CHECK: dxsa.instruction "check_access_fully_mapped" %[[OPERAND_10]], %[[OPERAND_11]] +// CHECK: dxsa.utof r<0, >, r<0, > +// CHECK: dxsa.add r<1, >, r<0, >, r<1, > +// CHECK: dxsa.add r<1>, r<0, >, r<1> +// CHECK: dxsa.utof r<0, >, r<9, > +// CHECK: %[[INDEX_12:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_12:.*]] = dxsa.operand %[[INDEX_12]] {mask = 64 : i32, num_components = 4 : i32, type = 0 : i32} +// CHECK: %[[INDEX_13:.*]] = dxsa.index.imm {imm = 10 : i32} +// CHECK: %[[OPERAND_13:.*]] = dxsa.operand %[[INDEX_13]] {num_components = 4 : i32, one = 0 : i32, type = 0 : i32} +// CHECK: dxsa.instruction "check_access_fully_mapped" %[[OPERAND_12]], %[[OPERAND_13]] +// CHECK: dxsa.utof r<0, >, r<0, > +// CHECK: dxsa.add r<1, >, r<0, >, r<1, > +// CHECK: dxsa.add r<1>, r<0, >, r<1> +// CHECK: dxsa.utof r<0, >, r<11, > +// CHECK: %[[INDEX_14:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_14:.*]] = dxsa.operand %[[INDEX_14]] {mask = 64 : i32, num_components = 4 : i32, type = 0 : i32} +// CHECK: %[[INDEX_15:.*]] = dxsa.index.imm {imm = 12 : i32} +// CHECK: %[[OPERAND_15:.*]] = dxsa.operand %[[INDEX_15]] {num_components = 4 : i32, one = 0 : i32, type = 0 : i32} +// CHECK: dxsa.instruction "check_access_fully_mapped" %[[OPERAND_14]], %[[OPERAND_15]] +// CHECK: dxsa.utof r<0, >, r<0, > +// CHECK: dxsa.add r<1>, r<0, >, r<1> +// CHECK: dxsa.add r<1>, r<0, >, r<1> +// CHECK: dxsa.ftou r<0, >, r<1, > +// CHECK: %[[INDEX_16:.*]] = dxsa.index.imm {imm = 1 : i32} +// CHECK: %[[OPERAND_16:.*]] = dxsa.operand %[[INDEX_16]] {mask = 16 : i32, num_components = 4 : i32, type = 30 : i32} +// CHECK: %[[INDEX_17:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_17:.*]] = dxsa.operand %[[INDEX_17]] {num_components = 4 : i32, one = 1 : i32, type = 0 : i32} +// CHECK: %[[INDEX_18:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_18:.*]] = dxsa.operand %[[INDEX_18]] {num_components = 4 : i32, one = 0 : i32, type = 0 : i32} +// CHECK: dxsa.instruction "store_raw" %[[OPERAND_16]], %[[OPERAND_17]], %[[OPERAND_18]] +// CHECK: dxsa.add r<2, >, v<0, >, l(0x3F800000, 0x40000000, 0x40400000, 0x0) +// CHECK: dxsa.ftou r<2, >, r<2, > +// CHECK: %[[INDEX_19:.*]] = dxsa.index.imm {imm = 1 : i32} +// CHECK: %[[OPERAND_19:.*]] = dxsa.operand %[[INDEX_19]] {mask = 48 : i32, num_components = 4 : i32, type = 30 : i32} +// CHECK: %[[INDEX_20:.*]] = dxsa.index.imm {imm = 2 : i32} +// CHECK: %[[OPERAND_20:.*]] = dxsa.operand %[[INDEX_20]] {num_components = 4 : i32, one = 0 : i32, type = 0 : i32} +// CHECK: %[[INDEX_21:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_21:.*]] = dxsa.operand %[[INDEX_21]] {num_components = 4 : i32, swizzle = dense<[2, 3, 2, 2]> : vector<4xi32>, type = 0 : i32} +// CHECK: dxsa.instruction "store_raw" %[[OPERAND_19]], %[[OPERAND_20]], %[[OPERAND_21]] +// CHECK: dxsa.ftou r<0, >, r<1, > +// CHECK: %[[INDEX_22:.*]] = dxsa.index.imm {imm = 1 : i32} +// CHECK: %[[OPERAND_22:.*]] = dxsa.operand %[[INDEX_22]] {mask = 112 : i32, num_components = 4 : i32, type = 30 : i32} +// CHECK: %[[INDEX_23:.*]] = dxsa.index.imm {imm = 2 : i32} +// CHECK: %[[OPERAND_23:.*]] = dxsa.operand %[[INDEX_23]] {num_components = 4 : i32, one = 1 : i32, type = 0 : i32} +// CHECK: %[[INDEX_24:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_24:.*]] = dxsa.operand %[[INDEX_24]] {num_components = 4 : i32, swizzle = dense<[0, 1, 2, 0]> : vector<4xi32>, type = 0 : i32} +// CHECK: dxsa.instruction "store_raw" %[[OPERAND_22]], %[[OPERAND_23]], %[[OPERAND_24]] +// CHECK: dxsa.ftou r<0>, r<1, > +// CHECK: dxsa.mov o<0>, r<1> +// CHECK: %[[INDEX_25:.*]] = dxsa.index.imm {imm = 1 : i32} +// CHECK: %[[OPERAND_25:.*]] = dxsa.operand %[[INDEX_25]] {mask = 240 : i32, num_components = 4 : i32, type = 30 : i32} +// CHECK: %[[INDEX_26:.*]] = dxsa.index.imm {imm = 2 : i32} +// CHECK: %[[OPERAND_26:.*]] = dxsa.operand %[[INDEX_26]] {num_components = 4 : i32, one = 2 : i32, type = 0 : i32} +// CHECK: %[[INDEX_27:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_27:.*]] = dxsa.operand %[[INDEX_27]] {num_components = 4 : i32, swizzle = dense<[0, 1, 2, 3]> : vector<4xi32>, type = 0 : i32} +// CHECK: dxsa.instruction "store_raw" %[[OPERAND_25]], %[[OPERAND_26]], %[[OPERAND_27]] +// CHECK: dxsa.ret + diff --git a/mlir/test/Target/DXSA/hlsl/rcp1.test b/mlir/test/Target/DXSA/hlsl/rcp1.test new file mode 100644 index 000000000000..4c1a1fec1445 --- /dev/null +++ b/mlir/test/Target/DXSA/hlsl/rcp1.test @@ -0,0 +1,10 @@ +// RUN: mlir-translate --import-dxsa-bin %S/inputs/rcp1.shex | FileCheck %s +// NOTE: Assertions have been autogenerated by utils/generate-test-checks.py + + +// CHECK-LABEL: dxsa.dcl_global_flags +// CHECK: dxsa.dcl_input_ps linear v<0, > +// CHECK: dxsa.dcl_output o<0, > +// CHECK: dxsa.rcp o<0, >, v<0, > +// CHECK: dxsa.ret + diff --git a/mlir/test/Target/DXSA/hlsl/redundantinput1.test b/mlir/test/Target/DXSA/hlsl/redundantinput1.test new file mode 100644 index 000000000000..f1d45aa87992 --- /dev/null +++ b/mlir/test/Target/DXSA/hlsl/redundantinput1.test @@ -0,0 +1,10 @@ +// RUN: mlir-translate --import-dxsa-bin %S/inputs/redundantinput1.shex | FileCheck %s +// NOTE: Assertions have been autogenerated by utils/generate-test-checks.py + + +// CHECK-LABEL: dxsa.dcl_global_flags +// CHECK: dxsa.dcl_input_ps linear v<0> +// CHECK: dxsa.dcl_output o<0> +// CHECK: dxsa.add o<0>, |v<0>|, v<0> +// CHECK: dxsa.ret + diff --git a/mlir/test/Target/DXSA/hlsl/sample1.test b/mlir/test/Target/DXSA/hlsl/sample1.test new file mode 100644 index 000000000000..0e443df23cac --- /dev/null +++ b/mlir/test/Target/DXSA/hlsl/sample1.test @@ -0,0 +1,15 @@ +// RUN: mlir-translate --import-dxsa-bin %S/inputs/sample1.shex | FileCheck %s +// NOTE: Assertions have been autogenerated by utils/generate-test-checks.py + + +// CHECK-LABEL: dxsa.dcl_global_flags +// CHECK: dxsa.dcl_constant_buffer , +// CHECK: dxsa.dcl_sampler +// CHECK: dxsa.dcl_resource , , +// CHECK: dxsa.dcl_input_ps linear v<0, > +// CHECK: dxsa.dcl_output o<0> +// CHECK: dxsa.dcl_temps 1 +// CHECK: dxsa.unknown +// CHECK: dxsa.add o<0>, r<0>, cb<[0, 2], vector> +// CHECK: dxsa.ret + diff --git a/mlir/test/Target/DXSA/hlsl/sample2.test b/mlir/test/Target/DXSA/hlsl/sample2.test new file mode 100644 index 000000000000..ef85bb87c782 --- /dev/null +++ b/mlir/test/Target/DXSA/hlsl/sample2.test @@ -0,0 +1,15 @@ +// RUN: mlir-translate --import-dxsa-bin %S/inputs/sample2.shex | FileCheck %s +// NOTE: Assertions have been autogenerated by utils/generate-test-checks.py + + +// CHECK-LABEL: dxsa.dcl_global_flags +// CHECK: dxsa.dcl_constant_buffer , +// CHECK: dxsa.dcl_sampler +// CHECK: dxsa.dcl_resource , , +// CHECK: dxsa.dcl_input_ps linear v<0, > +// CHECK: dxsa.dcl_output o<0, > +// CHECK: dxsa.dcl_temps 1 +// CHECK: dxsa.unknown +// CHECK: dxsa.add o<0, >, r<0, >, cb<[0, 2], vector, > +// CHECK: dxsa.ret + diff --git a/mlir/test/Target/DXSA/hlsl/sample3.test b/mlir/test/Target/DXSA/hlsl/sample3.test new file mode 100644 index 000000000000..8a14dc3a7548 --- /dev/null +++ b/mlir/test/Target/DXSA/hlsl/sample3.test @@ -0,0 +1,35 @@ +// RUN: mlir-translate --import-dxsa-bin %S/inputs/sample3.shex | FileCheck %s +// NOTE: Assertions have been autogenerated by utils/generate-test-checks.py + + +// CHECK-LABEL: dxsa.dcl_global_flags +// CHECK: dxsa.dcl_sampler +// CHECK: dxsa.dcl_resource , , +// CHECK: dxsa.dcl_input_ps linear v<0, > +// CHECK: dxsa.dcl_output o<0> +// CHECK: dxsa.dcl_temps 3 +// CHECK: dxsa.unknown +// CHECK: dxsa.unknown +// CHECK: dxsa.add r<0>, r<0>, r<1> +// CHECK: dxsa.unknown +// CHECK: dxsa.add r<0>, r<0>, r<1> +// CHECK: dxsa.unknown +// CHECK: dxsa.add r<0>, r<0>, r<1> +// CHECK: %[[INDEX_0:.*]] = dxsa.index.imm {imm = 1 : i32} +// CHECK: %[[OPERAND_0:.*]] = dxsa.operand %[[INDEX_0]] {mask = 16 : i32, num_components = 4 : i32, type = 0 : i32} +// CHECK: %[[INDEX_1:.*]] = dxsa.index.imm {imm = 2 : i32} +// CHECK: %[[OPERAND_1:.*]] = dxsa.operand %[[INDEX_1]] {num_components = 4 : i32, one = 0 : i32, type = 0 : i32} +// CHECK: dxsa.instruction "check_access_fully_mapped" %[[OPERAND_0]], %[[OPERAND_1]] +// CHECK: dxsa.utof r<1, >, r<1, > +// CHECK: dxsa.add r<0>, r<0>, r<1, > +// CHECK: dxsa.unknown +// CHECK: dxsa.add r<0>, r<0>, r<1> +// CHECK: %[[INDEX_2:.*]] = dxsa.index.imm {imm = 1 : i32} +// CHECK: %[[OPERAND_2:.*]] = dxsa.operand %[[INDEX_2]] {mask = 16 : i32, num_components = 4 : i32, type = 0 : i32} +// CHECK: %[[INDEX_3:.*]] = dxsa.index.imm {imm = 2 : i32} +// CHECK: %[[OPERAND_3:.*]] = dxsa.operand %[[INDEX_3]] {num_components = 4 : i32, one = 0 : i32, type = 0 : i32} +// CHECK: dxsa.instruction "check_access_fully_mapped" %[[OPERAND_2]], %[[OPERAND_3]] +// CHECK: dxsa.utof r<1, >, r<1, > +// CHECK: dxsa.add o<0>, r<0>, r<1, > +// CHECK: dxsa.ret + diff --git a/mlir/test/Target/DXSA/hlsl/sample_b1.test b/mlir/test/Target/DXSA/hlsl/sample_b1.test new file mode 100644 index 000000000000..f9d985eb1cc0 --- /dev/null +++ b/mlir/test/Target/DXSA/hlsl/sample_b1.test @@ -0,0 +1,35 @@ +// RUN: mlir-translate --import-dxsa-bin %S/inputs/sample_b1.shex | FileCheck %s +// NOTE: Assertions have been autogenerated by utils/generate-test-checks.py + + +// CHECK-LABEL: dxsa.dcl_global_flags +// CHECK: dxsa.dcl_sampler +// CHECK: dxsa.dcl_resource , , +// CHECK: dxsa.dcl_input_ps linear v<0, > +// CHECK: dxsa.dcl_output o<0> +// CHECK: dxsa.dcl_temps 3 +// CHECK: dxsa.unknown +// CHECK: dxsa.unknown +// CHECK: dxsa.add r<0>, r<0>, r<1> +// CHECK: dxsa.unknown +// CHECK: dxsa.add r<0>, r<0>, r<1> +// CHECK: dxsa.unknown +// CHECK: dxsa.add r<0>, r<0>, r<1> +// CHECK: %[[INDEX_0:.*]] = dxsa.index.imm {imm = 1 : i32} +// CHECK: %[[OPERAND_0:.*]] = dxsa.operand %[[INDEX_0]] {mask = 16 : i32, num_components = 4 : i32, type = 0 : i32} +// CHECK: %[[INDEX_1:.*]] = dxsa.index.imm {imm = 2 : i32} +// CHECK: %[[OPERAND_1:.*]] = dxsa.operand %[[INDEX_1]] {num_components = 4 : i32, one = 0 : i32, type = 0 : i32} +// CHECK: dxsa.instruction "check_access_fully_mapped" %[[OPERAND_0]], %[[OPERAND_1]] +// CHECK: dxsa.utof r<1, >, r<1, > +// CHECK: dxsa.add r<0>, r<0>, r<1, > +// CHECK: dxsa.unknown +// CHECK: dxsa.add r<0>, r<0>, r<1> +// CHECK: %[[INDEX_2:.*]] = dxsa.index.imm {imm = 1 : i32} +// CHECK: %[[OPERAND_2:.*]] = dxsa.operand %[[INDEX_2]] {mask = 16 : i32, num_components = 4 : i32, type = 0 : i32} +// CHECK: %[[INDEX_3:.*]] = dxsa.index.imm {imm = 2 : i32} +// CHECK: %[[OPERAND_3:.*]] = dxsa.operand %[[INDEX_3]] {num_components = 4 : i32, one = 0 : i32, type = 0 : i32} +// CHECK: dxsa.instruction "check_access_fully_mapped" %[[OPERAND_2]], %[[OPERAND_3]] +// CHECK: dxsa.utof r<1, >, r<1, > +// CHECK: dxsa.add o<0>, r<0>, r<1, > +// CHECK: dxsa.ret + diff --git a/mlir/test/Target/DXSA/hlsl/sample_cmp1.test b/mlir/test/Target/DXSA/hlsl/sample_cmp1.test new file mode 100644 index 000000000000..14772deb771e --- /dev/null +++ b/mlir/test/Target/DXSA/hlsl/sample_cmp1.test @@ -0,0 +1,38 @@ +// RUN: mlir-translate --import-dxsa-bin %S/inputs/sample_cmp1.shex | FileCheck %s +// NOTE: Assertions have been autogenerated by utils/generate-test-checks.py + + +// CHECK-LABEL: dxsa.dcl_global_flags +// CHECK: dxsa.dcl_sampler +// CHECK: dxsa.dcl_resource , , +// CHECK: dxsa.dcl_input_ps linear v<0, > +// CHECK: dxsa.dcl_output o<0> +// CHECK: dxsa.dcl_temps 4 +// CHECK: dxsa.add r<0, >, v<0, >, v<0, > +// CHECK: dxsa.ftou r<0, >, r<0, > +// CHECK: dxsa.utof r<0, >, r<0, > +// CHECK: dxsa.unknown +// CHECK: dxsa.unknown +// CHECK: dxsa.add r<0, >, r<0, >, r<0, > +// CHECK: dxsa.unknown +// CHECK: dxsa.add r<0, >, r<0, >, r<1, > +// CHECK: dxsa.unknown +// CHECK: dxsa.unknown +// CHECK: dxsa.add r<0, >, r<0, >, r<1, > +// CHECK: %[[INDEX_0:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_0:.*]] = dxsa.operand %[[INDEX_0]] {mask = 64 : i32, num_components = 4 : i32, type = 0 : i32} +// CHECK: %[[INDEX_1:.*]] = dxsa.index.imm {imm = 2 : i32} +// CHECK: %[[OPERAND_1:.*]] = dxsa.operand %[[INDEX_1]] {num_components = 4 : i32, one = 0 : i32, type = 0 : i32} +// CHECK: dxsa.instruction "check_access_fully_mapped" %[[OPERAND_0]], %[[OPERAND_1]] +// CHECK: dxsa.utof r<0, >, r<0, > +// CHECK: dxsa.add r<0, >, r<0, >, r<0, > +// CHECK: dxsa.add r<0, >, r<0, >, r<0, > +// CHECK: %[[INDEX_2:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_2:.*]] = dxsa.operand %[[INDEX_2]] {mask = 32 : i32, num_components = 4 : i32, type = 0 : i32} +// CHECK: %[[INDEX_3:.*]] = dxsa.index.imm {imm = 3 : i32} +// CHECK: %[[OPERAND_3:.*]] = dxsa.operand %[[INDEX_3]] {num_components = 4 : i32, one = 0 : i32, type = 0 : i32} +// CHECK: dxsa.instruction "check_access_fully_mapped" %[[OPERAND_2]], %[[OPERAND_3]] +// CHECK: dxsa.utof r<0, >, r<0, > +// CHECK: dxsa.add o<0>, r<0, >, r<0, > +// CHECK: dxsa.ret + diff --git a/mlir/test/Target/DXSA/hlsl/sample_cmp2.test b/mlir/test/Target/DXSA/hlsl/sample_cmp2.test new file mode 100644 index 000000000000..33ffbfe3aee2 --- /dev/null +++ b/mlir/test/Target/DXSA/hlsl/sample_cmp2.test @@ -0,0 +1,31 @@ +// RUN: mlir-translate --import-dxsa-bin %S/inputs/sample_cmp2.shex | FileCheck %s +// NOTE: Assertions have been autogenerated by utils/generate-test-checks.py + + +// CHECK-LABEL: dxsa.dcl_global_flags +// CHECK: dxsa.dcl_sampler +// CHECK: dxsa.dcl_resource , , +// CHECK: dxsa.dcl_input_ps linear v<0, > +// CHECK: dxsa.dcl_output o<0> +// CHECK: dxsa.dcl_temps 2 +// CHECK: dxsa.add r<0, >, v<0, >, v<0, > +// CHECK: dxsa.ftou r<0, >, r<0, > +// CHECK: dxsa.utof r<0, >, r<0, > +// CHECK: dxsa.unknown +// CHECK: dxsa.unknown +// CHECK: dxsa.add r<0, >, r<0, >, r<0, > +// CHECK: dxsa.unknown +// CHECK: dxsa.unknown +// CHECK: dxsa.add r<0, >, r<0, >, r<0, > +// CHECK: dxsa.add r<0, >, r<0, >, r<0, > +// CHECK: %[[INDEX_0:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_0:.*]] = dxsa.operand %[[INDEX_0]] {mask = 64 : i32, num_components = 4 : i32, type = 0 : i32} +// CHECK: %[[INDEX_1:.*]] = dxsa.index.imm {imm = 1 : i32} +// CHECK: %[[OPERAND_1:.*]] = dxsa.operand %[[INDEX_1]] {num_components = 4 : i32, one = 0 : i32, type = 0 : i32} +// CHECK: dxsa.instruction "check_access_fully_mapped" %[[OPERAND_0]], %[[OPERAND_1]] +// CHECK: dxsa.utof r<0, >, r<0, > +// CHECK: dxsa.add r<0, >, r<0, >, r<0, > +// CHECK: dxsa.add r<0, >, r<0, >, r<0, > +// CHECK: dxsa.add o<0>, r<0, >, r<0, > +// CHECK: dxsa.ret + diff --git a/mlir/test/Target/DXSA/hlsl/sample_grad1.test b/mlir/test/Target/DXSA/hlsl/sample_grad1.test new file mode 100644 index 000000000000..7a67052cfe0f --- /dev/null +++ b/mlir/test/Target/DXSA/hlsl/sample_grad1.test @@ -0,0 +1,35 @@ +// RUN: mlir-translate --import-dxsa-bin %S/inputs/sample_grad1.shex | FileCheck %s +// NOTE: Assertions have been autogenerated by utils/generate-test-checks.py + + +// CHECK-LABEL: dxsa.dcl_global_flags +// CHECK: dxsa.dcl_sampler +// CHECK: dxsa.dcl_resource , , +// CHECK: dxsa.dcl_input_ps linear v<0, > +// CHECK: dxsa.dcl_output o<0> +// CHECK: dxsa.dcl_temps 3 +// CHECK: dxsa.unknown +// CHECK: dxsa.unknown +// CHECK: dxsa.add r<0>, r<0>, r<1> +// CHECK: dxsa.unknown +// CHECK: dxsa.add r<0>, r<0>, r<1> +// CHECK: dxsa.unknown +// CHECK: dxsa.add r<0>, r<0>, r<1> +// CHECK: %[[INDEX_0:.*]] = dxsa.index.imm {imm = 1 : i32} +// CHECK: %[[OPERAND_0:.*]] = dxsa.operand %[[INDEX_0]] {mask = 16 : i32, num_components = 4 : i32, type = 0 : i32} +// CHECK: %[[INDEX_1:.*]] = dxsa.index.imm {imm = 2 : i32} +// CHECK: %[[OPERAND_1:.*]] = dxsa.operand %[[INDEX_1]] {num_components = 4 : i32, one = 0 : i32, type = 0 : i32} +// CHECK: dxsa.instruction "check_access_fully_mapped" %[[OPERAND_0]], %[[OPERAND_1]] +// CHECK: dxsa.utof r<1, >, r<1, > +// CHECK: dxsa.add r<0>, r<0>, r<1, > +// CHECK: dxsa.unknown +// CHECK: dxsa.add r<0>, r<0>, r<1> +// CHECK: %[[INDEX_2:.*]] = dxsa.index.imm {imm = 1 : i32} +// CHECK: %[[OPERAND_2:.*]] = dxsa.operand %[[INDEX_2]] {mask = 16 : i32, num_components = 4 : i32, type = 0 : i32} +// CHECK: %[[INDEX_3:.*]] = dxsa.index.imm {imm = 2 : i32} +// CHECK: %[[OPERAND_3:.*]] = dxsa.operand %[[INDEX_3]] {num_components = 4 : i32, one = 0 : i32, type = 0 : i32} +// CHECK: dxsa.instruction "check_access_fully_mapped" %[[OPERAND_2]], %[[OPERAND_3]] +// CHECK: dxsa.utof r<1, >, r<1, > +// CHECK: dxsa.add o<0>, r<0>, r<1, > +// CHECK: dxsa.ret + diff --git a/mlir/test/Target/DXSA/hlsl/sample_l1.test b/mlir/test/Target/DXSA/hlsl/sample_l1.test new file mode 100644 index 000000000000..b6a8e97e5ba2 --- /dev/null +++ b/mlir/test/Target/DXSA/hlsl/sample_l1.test @@ -0,0 +1,42 @@ +// RUN: mlir-translate --import-dxsa-bin %S/inputs/sample_l1.shex | FileCheck %s +// NOTE: Assertions have been autogenerated by utils/generate-test-checks.py + + +// CHECK-LABEL: dxsa.dcl_global_flags +// CHECK: dxsa.dcl_sampler +// CHECK: dxsa.dcl_resource , , +// CHECK: dxsa.dcl_resource , , +// CHECK: dxsa.dcl_input_ps linear v<0> +// CHECK: dxsa.dcl_output o<0> +// CHECK: dxsa.dcl_temps 3 +// CHECK: dxsa.unknown +// CHECK: dxsa.unknown +// CHECK: dxsa.add r<0>, r<0>, r<1> +// CHECK: dxsa.unknown +// CHECK: dxsa.add r<0>, r<0>, r<1> +// CHECK: dxsa.unknown +// CHECK: dxsa.add r<0>, r<0>, r<1> +// CHECK: %[[INDEX_0:.*]] = dxsa.index.imm {imm = 2 : i32} +// CHECK: %[[OPERAND_0:.*]] = dxsa.operand %[[INDEX_0]] {mask = 16 : i32, num_components = 4 : i32, type = 0 : i32} +// CHECK: %[[INDEX_1:.*]] = dxsa.index.imm {imm = 2 : i32} +// CHECK: %[[OPERAND_1:.*]] = dxsa.operand %[[INDEX_1]] {num_components = 4 : i32, one = 0 : i32, type = 0 : i32} +// CHECK: dxsa.instruction "check_access_fully_mapped" %[[OPERAND_0]], %[[OPERAND_1]] +// CHECK: dxsa.utof r<2, >, r<2, > +// CHECK: dxsa.add r<0>, r<0>, r<2, > +// CHECK: dxsa.add r<0>, r<1>, r<0> +// CHECK: dxsa.add r<0>, r<2, >, r<0> +// CHECK: dxsa.unknown +// CHECK: dxsa.mad r<0>, r<1>, l(0x40400000, 0x40400000, 0x40400000, 0x40400000), r<0> +// CHECK: dxsa.unknown +// CHECK: dxsa.add r<0>, r<0>, r<1> +// CHECK: %[[INDEX_2:.*]] = dxsa.index.imm {imm = 2 : i32} +// CHECK: %[[OPERAND_2:.*]] = dxsa.operand %[[INDEX_2]] {mask = 16 : i32, num_components = 4 : i32, type = 0 : i32} +// CHECK: %[[INDEX_3:.*]] = dxsa.index.imm {imm = 2 : i32} +// CHECK: %[[OPERAND_3:.*]] = dxsa.operand %[[INDEX_3]] {num_components = 4 : i32, one = 0 : i32, type = 0 : i32} +// CHECK: dxsa.instruction "check_access_fully_mapped" %[[OPERAND_2]], %[[OPERAND_3]] +// CHECK: dxsa.utof r<2, >, r<2, > +// CHECK: dxsa.add r<0>, r<0>, r<2, > +// CHECK: dxsa.add r<0>, r<1>, r<0> +// CHECK: dxsa.add o<0>, r<2, >, r<0> +// CHECK: dxsa.ret + diff --git a/mlir/test/Target/DXSA/hlsl/samplecount.test b/mlir/test/Target/DXSA/hlsl/samplecount.test new file mode 100644 index 000000000000..d1fd5cc87bdc --- /dev/null +++ b/mlir/test/Target/DXSA/hlsl/samplecount.test @@ -0,0 +1,13 @@ +// RUN: mlir-translate --import-dxsa-bin %S/inputs/samplecount.shex | FileCheck %s +// NOTE: Assertions have been autogenerated by utils/generate-test-checks.py + + +// CHECK-LABEL: dxsa.dcl_global_flags +// CHECK: dxsa.dcl_output o<0> +// CHECK: %[[INDEX_0:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_0:.*]] = dxsa.operand %[[INDEX_0]] {mask = 48 : i32, num_components = 4 : i32, type = 2 : i32} +// CHECK: %[[OPERAND_1:.*]] = dxsa.operand {num_components = 4 : i32, one = 0 : i32, type = 14 : i32} +// CHECK: dxsa.instruction "sampleinfo" %[[OPERAND_0]], %[[OPERAND_1]] +// CHECK: dxsa.mov o<0, >, l(0x0, 0x0, 0x0, 0x0) +// CHECK: dxsa.ret + diff --git a/mlir/test/Target/DXSA/hlsl/samplepos.test b/mlir/test/Target/DXSA/hlsl/samplepos.test new file mode 100644 index 000000000000..1803cc579e55 --- /dev/null +++ b/mlir/test/Target/DXSA/hlsl/samplepos.test @@ -0,0 +1,34 @@ +// RUN: mlir-translate --import-dxsa-bin %S/inputs/samplepos.shex | FileCheck %s +// NOTE: Assertions have been autogenerated by utils/generate-test-checks.py + + +// CHECK-LABEL: dxsa.dcl_global_flags +// CHECK: dxsa.unknown +// CHECK: dxsa.unknown +// CHECK: dxsa.dcl_input_ps linear v<0, > +// CHECK: dxsa.dcl_output o<0> +// CHECK: dxsa.dcl_output o<1> +// CHECK: dxsa.dcl_temps 2 +// CHECK: dxsa.ftoi r<0, >, v<0, > +// CHECK: dxsa.unknown +// CHECK: dxsa.unknown +// CHECK: %[[INDEX_0:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_0:.*]] = dxsa.operand %[[INDEX_0]] {mask = 96 : i32, num_components = 4 : i32, type = 0 : i32} +// CHECK: %[[OPERAND_1:.*]] = dxsa.operand {num_components = 4 : i32, swizzle = dense<[0, 0, 1, 0]> : vector<4xi32>, type = 14 : i32} +// CHECK: %[[INDEX_1:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_2:.*]] = dxsa.operand %[[INDEX_1]] {num_components = 4 : i32, one = 2 : i32, type = 0 : i32} +// CHECK: dxsa.instruction "samplepos" %[[OPERAND_0]], %[[OPERAND_1]], %[[OPERAND_2]] +// CHECK: dxsa.add r<0, >, r<0, >, r<1, > +// CHECK: %[[INDEX_2:.*]] = dxsa.index.imm {imm = 1 : i32} +// CHECK: %[[OPERAND_3:.*]] = dxsa.operand %[[INDEX_2]] {mask = 48 : i32, num_components = 4 : i32, type = 0 : i32} +// CHECK: %[[OPERAND_4:.*]] = dxsa.operand {num_components = 4 : i32, swizzle = dense<[0, 1, 0, 0]> : vector<4xi32>, type = 14 : i32} +// CHECK: %[[OPERAND_5:.*]] = dxsa.operand.imm {imm = dense<3> : vector<1xi32>} +// CHECK: dxsa.instruction "samplepos" %[[OPERAND_3]], %[[OPERAND_4]], %[[OPERAND_5]] +// CHECK: dxsa.add r<0, >, r<0, >, r<1, > +// CHECK: dxsa.add r<0, >, r<0, >, r<0, > +// CHECK: dxsa.mov o<0, >, r<0, > +// CHECK: dxsa.add o<1, >, r<0, >, l(0x40A00000, 0x40A00000, 0x0, 0x0) +// CHECK: dxsa.mov o<0, >, l(0x0, 0x0, 0x0, 0x0) +// CHECK: dxsa.mov o<1, >, l(0x0, 0x0, 0x40A00000, 0x40A00000) +// CHECK: dxsa.ret + diff --git a/mlir/test/Target/DXSA/hlsl/saturate1.test b/mlir/test/Target/DXSA/hlsl/saturate1.test new file mode 100644 index 000000000000..4eda8deaaf92 --- /dev/null +++ b/mlir/test/Target/DXSA/hlsl/saturate1.test @@ -0,0 +1,10 @@ +// RUN: mlir-translate --import-dxsa-bin %S/inputs/saturate1.shex | FileCheck %s +// NOTE: Assertions have been autogenerated by utils/generate-test-checks.py + + +// CHECK-LABEL: dxsa.dcl_global_flags +// CHECK: dxsa.dcl_input_ps linear v<0, > +// CHECK: dxsa.dcl_output o<0, > +// CHECK: dxsa.mov_sat o<0, >, v<0, > +// CHECK: dxsa.ret + diff --git a/mlir/test/Target/DXSA/hlsl/shift1.test b/mlir/test/Target/DXSA/hlsl/shift1.test new file mode 100644 index 000000000000..2ab14d38dd33 --- /dev/null +++ b/mlir/test/Target/DXSA/hlsl/shift1.test @@ -0,0 +1,23 @@ +// RUN: mlir-translate --import-dxsa-bin %S/inputs/shift1.shex | FileCheck %s +// NOTE: Assertions have been autogenerated by utils/generate-test-checks.py + + +// CHECK-LABEL: dxsa.dcl_global_flags +// CHECK: dxsa.dcl_input_ps constant v<0, > +// CHECK: dxsa.dcl_input_ps constant v<0, > +// CHECK: dxsa.dcl_input_ps constant v<0, > +// CHECK: dxsa.dcl_output o<0, > +// CHECK: dxsa.dcl_temps 1 +// CHECK: dxsa.ishl r<0, >, v<0, >, l(0x4D) +// CHECK: dxsa.ishr r<0, >, v<0, >, l(0x3) +// CHECK: dxsa.iadd r<0, >, r<0, >, r<0, > +// CHECK: dxsa.ushr r<0, >, v<0, >, l(0x8) +// CHECK: dxsa.iadd r<0, >, r<0, >, r<0, > +// CHECK: dxsa.ishl r<0, >, v<0, >, v<0, > +// CHECK: dxsa.iadd r<0, >, r<0, >, r<0, > +// CHECK: dxsa.ishr r<0, >, v<0, >, v<0, > +// CHECK: dxsa.iadd r<0, >, r<0, >, r<0, > +// CHECK: dxsa.ushr r<0, >, v<0, >, v<0, > +// CHECK: dxsa.iadd o<0, >, r<0, >, r<0, > +// CHECK: dxsa.ret + diff --git a/mlir/test/Target/DXSA/hlsl/sincos.test b/mlir/test/Target/DXSA/hlsl/sincos.test new file mode 100644 index 000000000000..de654776d531 --- /dev/null +++ b/mlir/test/Target/DXSA/hlsl/sincos.test @@ -0,0 +1,15 @@ +// RUN: mlir-translate --import-dxsa-bin %S/inputs/sincos.shex | FileCheck %s +// NOTE: Assertions have been autogenerated by utils/generate-test-checks.py + + +// CHECK-LABEL: dxsa.dcl_global_flags +// CHECK: dxsa.dcl_input v<0> +// CHECK: dxsa.dcl_output_siv o<0>, +// CHECK: dxsa.dcl_temps 3 +// CHECK: dxsa.add r<0, >, v<0, >, v<0, > +// CHECK: dxsa.sincos r<0, >, null, r<0, > +// CHECK: dxsa.sincos r<1>, r<2>, v<0> +// CHECK: dxsa.add r<1>, r<1>, r<2> +// CHECK: dxsa.add o<0>, r<0, >, r<1> +// CHECK: dxsa.ret + diff --git a/mlir/test/Target/DXSA/hlsl/snorm1.test b/mlir/test/Target/DXSA/hlsl/snorm1.test new file mode 100644 index 000000000000..7414b098059a --- /dev/null +++ b/mlir/test/Target/DXSA/hlsl/snorm1.test @@ -0,0 +1,16 @@ +// RUN: mlir-translate --import-dxsa-bin %S/inputs/snorm1.shex | FileCheck %s +// NOTE: Assertions have been autogenerated by utils/generate-test-checks.py + + +// CHECK-LABEL: dxsa.dcl_global_flags +// CHECK: dxsa.dcl_sampler +// CHECK: dxsa.dcl_resource , , +// CHECK: dxsa.dcl_resource , , +// CHECK: dxsa.dcl_input_ps linear v<0, > +// CHECK: dxsa.dcl_output o<0> +// CHECK: dxsa.dcl_temps 2 +// CHECK: dxsa.unknown +// CHECK: dxsa.unknown +// CHECK: dxsa.add o<0>, r<0>, r<1, > +// CHECK: dxsa.ret + diff --git a/mlir/test/Target/DXSA/hlsl/srv_ms_load1.test b/mlir/test/Target/DXSA/hlsl/srv_ms_load1.test new file mode 100644 index 000000000000..f18fc3cf908e --- /dev/null +++ b/mlir/test/Target/DXSA/hlsl/srv_ms_load1.test @@ -0,0 +1,42 @@ +// RUN: mlir-translate --import-dxsa-bin %S/inputs/srv_ms_load1.shex | FileCheck %s +// NOTE: Assertions have been autogenerated by utils/generate-test-checks.py + + +// CHECK-LABEL: dxsa.dcl_global_flags +// CHECK: dxsa.unknown +// CHECK: dxsa.dcl_input_ps constant v<0, > +// CHECK: dxsa.dcl_input_ps constant v<0, > +// CHECK: dxsa.dcl_input_ps constant v<1, > +// CHECK: dxsa.dcl_output o<0, > +// CHECK: dxsa.dcl_temps 4 +// CHECK: dxsa.mov r<0, >, v<1, > +// CHECK: dxsa.mov r<0, >, l(0x0, 0x0, 0x0, 0x0) +// CHECK: dxsa.unknown +// CHECK: dxsa.mov r<1, >, v<0, > +// CHECK: dxsa.mov r<1, >, l(0x0, 0x0, 0x0, 0x0) +// CHECK: dxsa.unknown +// CHECK: dxsa.add r<0, >, r<0, >, r<2, > +// CHECK: dxsa.unknown +// CHECK: dxsa.add r<0, >, r<0, >, r<2, > +// CHECK: dxsa.unknown +// CHECK: dxsa.add r<0, >, r<0, >, r<2, > +// CHECK: %[[INDEX_0:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_0:.*]] = dxsa.operand %[[INDEX_0]] {mask = 128 : i32, num_components = 4 : i32, type = 0 : i32} +// CHECK: %[[INDEX_1:.*]] = dxsa.index.imm {imm = 3 : i32} +// CHECK: %[[OPERAND_1:.*]] = dxsa.operand %[[INDEX_1]] {num_components = 4 : i32, one = 0 : i32, type = 0 : i32} +// CHECK: dxsa.instruction "check_access_fully_mapped" %[[OPERAND_0]], %[[OPERAND_1]] +// CHECK: dxsa.utof r<0, >, r<0, > +// CHECK: dxsa.add r<0, >, r<0, >, r<0, > +// CHECK: dxsa.unknown +// CHECK: dxsa.unknown +// CHECK: dxsa.add r<0, >, r<0, >, r<2, > +// CHECK: %[[INDEX_2:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_2:.*]] = dxsa.operand %[[INDEX_2]] {mask = 128 : i32, num_components = 4 : i32, type = 0 : i32} +// CHECK: %[[INDEX_3:.*]] = dxsa.index.imm {imm = 3 : i32} +// CHECK: %[[OPERAND_3:.*]] = dxsa.operand %[[INDEX_3]] {num_components = 4 : i32, one = 0 : i32, type = 0 : i32} +// CHECK: dxsa.instruction "check_access_fully_mapped" %[[OPERAND_2]], %[[OPERAND_3]] +// CHECK: dxsa.utof r<0, >, r<0, > +// CHECK: dxsa.add r<0, >, r<0, >, r<0, > +// CHECK: dxsa.add o<0, >, r<1, >, r<0, > +// CHECK: dxsa.ret + diff --git a/mlir/test/Target/DXSA/hlsl/srv_typed_load1.test b/mlir/test/Target/DXSA/hlsl/srv_typed_load1.test new file mode 100644 index 000000000000..3cae33036bcf --- /dev/null +++ b/mlir/test/Target/DXSA/hlsl/srv_typed_load1.test @@ -0,0 +1,38 @@ +// RUN: mlir-translate --import-dxsa-bin %S/inputs/srv_typed_load1.shex | FileCheck %s +// NOTE: Assertions have been autogenerated by utils/generate-test-checks.py + + +// CHECK-LABEL: dxsa.dcl_global_flags +// CHECK: dxsa.dcl_resource , , +// CHECK: dxsa.dcl_input_ps linear v<0, > +// CHECK: dxsa.dcl_input_ps linear v<1, > +// CHECK: dxsa.dcl_output o<0> +// CHECK: dxsa.dcl_temps 5 +// CHECK: dxsa.ftou r<0, >, v<1, > +// CHECK: dxsa.mov r<0, >, l(0x0, 0x0, 0x0, 0x0) +// CHECK: dxsa.unknown +// CHECK: dxsa.ftoi r<1>, v<0, > +// CHECK: dxsa.unknown +// CHECK: dxsa.add r<0>, r<0>, r<2> +// CHECK: dxsa.unknown +// CHECK: dxsa.add r<0>, r<0>, r<2> +// CHECK: dxsa.unknown +// CHECK: dxsa.unknown +// CHECK: dxsa.add r<0>, r<0>, r<2> +// CHECK: %[[INDEX_0:.*]] = dxsa.index.imm {imm = 2 : i32} +// CHECK: %[[OPERAND_0:.*]] = dxsa.operand %[[INDEX_0]] {mask = 16 : i32, num_components = 4 : i32, type = 0 : i32} +// CHECK: %[[INDEX_1:.*]] = dxsa.index.imm {imm = 3 : i32} +// CHECK: %[[OPERAND_1:.*]] = dxsa.operand %[[INDEX_1]] {num_components = 4 : i32, one = 0 : i32, type = 0 : i32} +// CHECK: dxsa.instruction "check_access_fully_mapped" %[[OPERAND_0]], %[[OPERAND_1]] +// CHECK: dxsa.utof r<2, >, r<2, > +// CHECK: dxsa.add r<0>, r<0>, r<2, > +// CHECK: dxsa.add r<0>, r<1>, r<0> +// CHECK: %[[INDEX_2:.*]] = dxsa.index.imm {imm = 1 : i32} +// CHECK: %[[OPERAND_2:.*]] = dxsa.operand %[[INDEX_2]] {mask = 16 : i32, num_components = 4 : i32, type = 0 : i32} +// CHECK: %[[INDEX_3:.*]] = dxsa.index.imm {imm = 4 : i32} +// CHECK: %[[OPERAND_3:.*]] = dxsa.operand %[[INDEX_3]] {num_components = 4 : i32, one = 0 : i32, type = 0 : i32} +// CHECK: dxsa.instruction "check_access_fully_mapped" %[[OPERAND_2]], %[[OPERAND_3]] +// CHECK: dxsa.utof r<1, >, r<1, > +// CHECK: dxsa.add o<0>, r<0>, r<1, > +// CHECK: dxsa.ret + diff --git a/mlir/test/Target/DXSA/hlsl/srv_typed_load2.test b/mlir/test/Target/DXSA/hlsl/srv_typed_load2.test new file mode 100644 index 000000000000..6ec1a6141a7c --- /dev/null +++ b/mlir/test/Target/DXSA/hlsl/srv_typed_load2.test @@ -0,0 +1,21 @@ +// RUN: mlir-translate --import-dxsa-bin %S/inputs/srv_typed_load2.shex | FileCheck %s +// NOTE: Assertions have been autogenerated by utils/generate-test-checks.py + + +// CHECK-LABEL: dxsa.dcl_global_flags +// CHECK: dxsa.dcl_resource , , +// CHECK: dxsa.dcl_input_ps constant v<0, > +// CHECK: dxsa.dcl_output o<0> +// CHECK: dxsa.dcl_temps 3 +// CHECK: dxsa.unknown +// CHECK: dxsa.unknown +// CHECK: dxsa.mad r<0>, r<0>, l(0x40000000, 0x40000000, 0x40000000, 0x40000000), r<1> +// CHECK: %[[INDEX_0:.*]] = dxsa.index.imm {imm = 1 : i32} +// CHECK: %[[OPERAND_0:.*]] = dxsa.operand %[[INDEX_0]] {mask = 16 : i32, num_components = 4 : i32, type = 0 : i32} +// CHECK: %[[INDEX_1:.*]] = dxsa.index.imm {imm = 2 : i32} +// CHECK: %[[OPERAND_1:.*]] = dxsa.operand %[[INDEX_1]] {num_components = 4 : i32, one = 0 : i32, type = 0 : i32} +// CHECK: dxsa.instruction "check_access_fully_mapped" %[[OPERAND_0]], %[[OPERAND_1]] +// CHECK: dxsa.utof r<1, >, r<1, > +// CHECK: dxsa.add o<0>, r<0>, r<1, > +// CHECK: dxsa.ret + diff --git a/mlir/test/Target/DXSA/hlsl/struct_buf1.test b/mlir/test/Target/DXSA/hlsl/struct_buf1.test new file mode 100644 index 000000000000..1b9096875cfd --- /dev/null +++ b/mlir/test/Target/DXSA/hlsl/struct_buf1.test @@ -0,0 +1,252 @@ +// RUN: mlir-translate --import-dxsa-bin %S/inputs/struct_buf1.shex | FileCheck %s +// NOTE: Assertions have been autogenerated by utils/generate-test-checks.py + + +// CHECK-LABEL: dxsa.dcl_global_flags +// CHECK: dxsa.dcl_resource_structured +// CHECK: dxsa.dcl_uav_structured +// CHECK: dxsa.dcl_input_ps linear v<0, > +// CHECK: dxsa.dcl_input_ps linear v<0, > +// CHECK: dxsa.dcl_output o<0> +// CHECK: dxsa.dcl_temps 22 +// CHECK: dxsa.add r<0, >, v<0, >, l(0x43480000, 0x43480000, 0x0, 0x0) +// CHECK: dxsa.ftoi r<0, >, r<0, > +// CHECK: dxsa.unknown +// CHECK: dxsa.unknown +// CHECK: dxsa.unknown +// CHECK: dxsa.unknown +// CHECK: dxsa.unknown +// CHECK: dxsa.unknown +// CHECK: dxsa.unknown +// CHECK: dxsa.unknown +// CHECK: dxsa.unknown +// CHECK: dxsa.unknown +// CHECK: dxsa.unknown +// CHECK: dxsa.unknown +// CHECK: dxsa.mov r<14, >, l(0x0) +// CHECK: dxsa.ftou r<1, >, v<0, > +// CHECK: dxsa.ineg r<5, >, r<1, > +// CHECK: dxsa.ult r<7, >, r<1, >, l(0x0, 0x1, 0x2, 0x3) +// CHECK: dxsa.and r<5, >, r<5, >, r<7, > +// CHECK: dxsa.ftoi r<8, >, v<0, > +// CHECK: dxsa.unknown +// CHECK: dxsa.mov r<16, >, r<15, > +// CHECK: dxsa.unknown +// CHECK: dxsa.and r<9, >, r<5, >, r<16, > +// CHECK: dxsa.and r<11, >, r<7, >, r<16, > +// CHECK: dxsa.or r<9, >, r<9, >, r<11, > +// CHECK: dxsa.iadd r<5, >, r<1, >, l(0xFFFFFFFD) +// CHECK: dxsa.ishl r<1, >, r<1, >, l(0x3) +// CHECK: dxsa.iadd r<1, >, r<1, >, l(0x14) +// CHECK: %[[INDEX_0:.*]] = dxsa.index.imm {imm = 5 : i32} +// CHECK: %[[OPERAND_0:.*]] = dxsa.operand %[[INDEX_0]] {mask = 128 : i32, num_components = 4 : i32, type = 0 : i32} +// CHECK: %[[INDEX_1:.*]] = dxsa.index.imm {imm = 7 : i32} +// CHECK: %[[OPERAND_1:.*]] = dxsa.operand %[[INDEX_1]] {num_components = 4 : i32, one = 2 : i32, type = 0 : i32} +// CHECK: %[[OPERAND_2:.*]] = dxsa.operand.imm {imm = dense<0> : vector<1xi32>} +// CHECK: %[[INDEX_2:.*]] = dxsa.index.imm {imm = 5 : i32} +// CHECK: %[[OPERAND_3:.*]] = dxsa.operand %[[INDEX_2]] {num_components = 4 : i32, one = 3 : i32, type = 0 : i32} +// CHECK: dxsa.instruction "movc" %[[OPERAND_0]], %[[OPERAND_1]], %[[OPERAND_2]], %[[OPERAND_3]] +// CHECK: dxsa.and r<11, >, r<15, >, r<5, > +// CHECK: dxsa.or r<9, >, r<9, >, r<11, > +// CHECK: dxsa.ieq r<7, >, r<7, >, l(0x0) +// CHECK: dxsa.unknown +// CHECK: dxsa.and r<11, >, r<7, >, r<15, > +// CHECK: dxsa.or r<9, >, r<9, >, r<11, > +// CHECK: dxsa.itof r<9, >, r<9, > +// CHECK: dxsa.mov r<15, >, l(0x0) +// CHECK: dxsa.unknown +// CHECK: dxsa.unknown +// CHECK: dxsa.add r<14, >, r<11, >, r<15, > +// CHECK: dxsa.add r<15, >, r<9, >, r<14, > +// CHECK: dxsa.mov r<15, >, r<14, > +// CHECK: dxsa.unknown +// CHECK: dxsa.add r<14, >, r<15, >, r<16, > +// CHECK: %[[INDEX_3:.*]] = dxsa.index.imm {imm = 7 : i32} +// CHECK: %[[OPERAND_4:.*]] = dxsa.operand %[[INDEX_3]] {mask = 128 : i32, num_components = 4 : i32, type = 0 : i32} +// CHECK: %[[INDEX_4:.*]] = dxsa.index.imm {imm = 17 : i32} +// CHECK: %[[OPERAND_5:.*]] = dxsa.operand %[[INDEX_4]] {num_components = 4 : i32, one = 0 : i32, type = 0 : i32} +// CHECK: dxsa.instruction "check_access_fully_mapped" %[[OPERAND_4]], %[[OPERAND_5]] +// CHECK: dxsa.mov r<16, >, r<16, > +// CHECK: dxsa.unknown +// CHECK: %[[INDEX_5:.*]] = dxsa.index.imm {imm = 8 : i32} +// CHECK: %[[OPERAND_6:.*]] = dxsa.operand %[[INDEX_5]] {mask = 32 : i32, num_components = 4 : i32, type = 0 : i32} +// CHECK: %[[INDEX_6:.*]] = dxsa.index.imm {imm = 18 : i32} +// CHECK: %[[OPERAND_7:.*]] = dxsa.operand %[[INDEX_6]] {num_components = 4 : i32, one = 0 : i32, type = 0 : i32} +// CHECK: dxsa.instruction "check_access_fully_mapped" %[[OPERAND_6]], %[[OPERAND_7]] +// CHECK: dxsa.and r<7, >, r<7, >, r<8, > +// CHECK: dxsa.unknown +// CHECK: dxsa.unknown +// CHECK: %[[INDEX_7:.*]] = dxsa.index.imm {imm = 8 : i32} +// CHECK: %[[OPERAND_8:.*]] = dxsa.operand %[[INDEX_7]] {mask = 32 : i32, num_components = 4 : i32, type = 0 : i32} +// CHECK: %[[INDEX_8:.*]] = dxsa.index.imm {imm = 19 : i32} +// CHECK: %[[OPERAND_9:.*]] = dxsa.operand %[[INDEX_8]] {num_components = 4 : i32, one = 0 : i32, type = 0 : i32} +// CHECK: dxsa.instruction "check_access_fully_mapped" %[[OPERAND_8]], %[[OPERAND_9]] +// CHECK: dxsa.and r<7, >, r<7, >, r<8, > +// CHECK: %[[INDEX_9:.*]] = dxsa.index.imm {imm = 8 : i32} +// CHECK: %[[OPERAND_10:.*]] = dxsa.operand %[[INDEX_9]] {mask = 32 : i32, num_components = 4 : i32, type = 0 : i32} +// CHECK: %[[INDEX_10:.*]] = dxsa.index.imm {imm = 21 : i32} +// CHECK: %[[OPERAND_11:.*]] = dxsa.operand %[[INDEX_10]] {num_components = 4 : i32, one = 0 : i32, type = 0 : i32} +// CHECK: dxsa.instruction "check_access_fully_mapped" %[[OPERAND_10]], %[[OPERAND_11]] +// CHECK: dxsa.and r<7, >, r<7, >, r<8, > +// CHECK: dxsa.utof r<7, >, r<7, > +// CHECK: dxsa.add r<8, >, r<7, >, r<14, > +// CHECK: dxsa.mul r<15, >, r<7, >, l(0x3F800000, 0x0, 0x40000000, 0x0) +// CHECK: dxsa.mov r<16, >, r<17, > +// CHECK: dxsa.add r<14, >, r<8, >, r<16, > +// CHECK: dxsa.mov r<15, >, r<14, > +// CHECK: dxsa.add r<8, >, r<15, >, r<15, > +// CHECK: dxsa.mov r<14, >, r<15, > +// CHECK: dxsa.and r<9, >, r<7, >, r<17, > +// CHECK: dxsa.mov r<17, >, r<18, > +// CHECK: dxsa.and r<11, >, r<5, >, r<17, > +// CHECK: dxsa.or r<9, >, r<9, >, r<11, > +// CHECK: dxsa.and r<11, >, r<5, >, r<18, > +// CHECK: dxsa.mov r<20, >, r<18, > +// CHECK: dxsa.and r<12, >, r<7, >, r<20, > +// CHECK: dxsa.or r<9, >, r<9, >, r<11, > +// CHECK: dxsa.or r<9, >, r<9, >, r<12, > +// CHECK: dxsa.itof r<9, >, r<9, > +// CHECK: dxsa.add r<15, >, r<8, >, r<9, > +// CHECK: dxsa.mov r<15, >, r<8, > +// CHECK: dxsa.add r<14>, r<14, >, r<15> +// CHECK: dxsa.add r<14, >, r<0, >, r<14, > +// CHECK: dxsa.add r<14, >, r<1, >, r<14, > +// CHECK: dxsa.and r<0, >, r<2, >, r<7, > +// CHECK: dxsa.and r<1, >, r<6, >, r<7, > +// CHECK: dxsa.mov r<2, >, r<3, > +// CHECK: dxsa.and r<2, >, r<2, >, r<5, > +// CHECK: dxsa.or r<0, >, r<0, >, r<2, > +// CHECK: dxsa.and r<2, >, r<3, >, r<5, > +// CHECK: dxsa.and r<2, >, r<10, >, r<5, > +// CHECK: dxsa.mov r<4, >, r<3, > +// CHECK: dxsa.and r<3, >, r<4, >, r<7, > +// CHECK: dxsa.or r<0, >, r<0, >, r<2, > +// CHECK: dxsa.or r<0, >, r<0, >, r<3, > +// CHECK: dxsa.itof r<0, >, r<0, > +// CHECK: dxsa.add r<3, >, r<0, >, r<14, > +// CHECK: dxsa.mov r<3, >, r<14, > +// CHECK: dxsa.add r<3, >, r<5, >, r<3, > +// CHECK: %[[INDEX_11:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_12:.*]] = dxsa.operand %[[INDEX_11]] {mask = 16 : i32, num_components = 4 : i32, type = 0 : i32} +// CHECK: %[[INDEX_12:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_13:.*]] = dxsa.operand %[[INDEX_12]] {num_components = 4 : i32, one = 0 : i32, type = 0 : i32} +// CHECK: dxsa.instruction "check_access_fully_mapped" %[[OPERAND_12]], %[[OPERAND_13]] +// CHECK: dxsa.unknown +// CHECK: %[[INDEX_13:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_14:.*]] = dxsa.operand %[[INDEX_13]] {mask = 64 : i32, num_components = 4 : i32, type = 0 : i32} +// CHECK: %[[INDEX_14:.*]] = dxsa.index.imm {imm = 2 : i32} +// CHECK: %[[OPERAND_15:.*]] = dxsa.operand %[[INDEX_14]] {num_components = 4 : i32, one = 0 : i32, type = 0 : i32} +// CHECK: dxsa.instruction "check_access_fully_mapped" %[[OPERAND_14]], %[[OPERAND_15]] +// CHECK: dxsa.and r<0, >, r<0, >, r<0, > +// CHECK: dxsa.unknown +// CHECK: dxsa.unknown +// CHECK: %[[INDEX_15:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_16:.*]] = dxsa.operand %[[INDEX_15]] {mask = 64 : i32, num_components = 4 : i32, type = 0 : i32} +// CHECK: %[[INDEX_16:.*]] = dxsa.index.imm {imm = 4 : i32} +// CHECK: %[[OPERAND_17:.*]] = dxsa.operand %[[INDEX_16]] {num_components = 4 : i32, one = 0 : i32, type = 0 : i32} +// CHECK: dxsa.instruction "check_access_fully_mapped" %[[OPERAND_16]], %[[OPERAND_17]] +// CHECK: %[[INDEX_17:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_18:.*]] = dxsa.operand %[[INDEX_17]] {mask = 128 : i32, num_components = 4 : i32, type = 0 : i32} +// CHECK: %[[INDEX_18:.*]] = dxsa.index.imm {imm = 2 : i32} +// CHECK: %[[OPERAND_19:.*]] = dxsa.operand %[[INDEX_18]] {num_components = 4 : i32, one = 0 : i32, type = 0 : i32} +// CHECK: dxsa.instruction "check_access_fully_mapped" %[[OPERAND_18]], %[[OPERAND_19]] +// CHECK: dxsa.and r<0, >, r<0, >, r<0, > +// CHECK: dxsa.and r<0, >, r<0, >, r<0, > +// CHECK: dxsa.utof r<0, >, r<0, > +// CHECK: dxsa.add r<3>, r<0, >, r<3> +// CHECK: dxsa.mov r<4, >, r<4, > +// CHECK: %[[INDEX_19:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_20:.*]] = dxsa.operand %[[INDEX_19]] {mask = 16 : i32, num_components = 4 : i32, type = 0 : i32} +// CHECK: %[[INDEX_20:.*]] = dxsa.index.imm {imm = 6 : i32} +// CHECK: %[[OPERAND_21:.*]] = dxsa.operand %[[INDEX_20]] {num_components = 4 : i32, one = 0 : i32, type = 0 : i32} +// CHECK: dxsa.instruction "check_access_fully_mapped" %[[OPERAND_20]], %[[OPERAND_21]] +// CHECK: dxsa.mov r<4, >, r<7, > +// CHECK: %[[INDEX_21:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_22:.*]] = dxsa.operand %[[INDEX_21]] {mask = 64 : i32, num_components = 4 : i32, type = 0 : i32} +// CHECK: %[[INDEX_22:.*]] = dxsa.index.imm {imm = 8 : i32} +// CHECK: %[[OPERAND_23:.*]] = dxsa.operand %[[INDEX_22]] {num_components = 4 : i32, one = 0 : i32, type = 0 : i32} +// CHECK: dxsa.instruction "check_access_fully_mapped" %[[OPERAND_22]], %[[OPERAND_23]] +// CHECK: dxsa.and r<0, >, r<0, >, r<0, > +// CHECK: dxsa.add r<3, >, r<3, >, r<4, > +// CHECK: dxsa.unknown +// CHECK: %[[INDEX_23:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_24:.*]] = dxsa.operand %[[INDEX_23]] {mask = 64 : i32, num_components = 4 : i32, type = 0 : i32} +// CHECK: %[[INDEX_24:.*]] = dxsa.index.imm {imm = 2 : i32} +// CHECK: %[[OPERAND_25:.*]] = dxsa.operand %[[INDEX_24]] {num_components = 4 : i32, one = 0 : i32, type = 0 : i32} +// CHECK: dxsa.instruction "check_access_fully_mapped" %[[OPERAND_24]], %[[OPERAND_25]] +// CHECK: dxsa.and r<0, >, r<0, >, r<0, > +// CHECK: dxsa.unknown +// CHECK: dxsa.unknown +// CHECK: %[[INDEX_25:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_26:.*]] = dxsa.operand %[[INDEX_25]] {mask = 32 : i32, num_components = 4 : i32, type = 0 : i32} +// CHECK: %[[INDEX_26:.*]] = dxsa.index.imm {imm = 4 : i32} +// CHECK: %[[OPERAND_27:.*]] = dxsa.operand %[[INDEX_26]] {num_components = 4 : i32, one = 0 : i32, type = 0 : i32} +// CHECK: dxsa.instruction "check_access_fully_mapped" %[[OPERAND_26]], %[[OPERAND_27]] +// CHECK: %[[INDEX_27:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_28:.*]] = dxsa.operand %[[INDEX_27]] {mask = 64 : i32, num_components = 4 : i32, type = 0 : i32} +// CHECK: %[[INDEX_28:.*]] = dxsa.index.imm {imm = 2 : i32} +// CHECK: %[[OPERAND_29:.*]] = dxsa.operand %[[INDEX_28]] {num_components = 4 : i32, one = 0 : i32, type = 0 : i32} +// CHECK: dxsa.instruction "check_access_fully_mapped" %[[OPERAND_28]], %[[OPERAND_29]] +// CHECK: dxsa.and r<0, >, r<0, >, r<0, > +// CHECK: dxsa.utof r<0, >, r<0, > +// CHECK: dxsa.add r<3>, r<0, >, r<3> +// CHECK: %[[INDEX_29:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_30:.*]] = dxsa.operand %[[INDEX_29]] {mask = 16 : i32, num_components = 4 : i32, type = 0 : i32} +// CHECK: %[[INDEX_30:.*]] = dxsa.index.imm {imm = 9 : i32} +// CHECK: %[[OPERAND_31:.*]] = dxsa.operand %[[INDEX_30]] {num_components = 4 : i32, one = 0 : i32, type = 0 : i32} +// CHECK: dxsa.instruction "check_access_fully_mapped" %[[OPERAND_30]], %[[OPERAND_31]] +// CHECK: dxsa.and r<0, >, r<0, >, r<0, > +// CHECK: dxsa.mov r<6, >, r<10, > +// CHECK: dxsa.and r<0, >, r<5, >, r<6, > +// CHECK: dxsa.or r<0, >, r<1, >, r<0, > +// CHECK: dxsa.or r<0, >, r<0, >, r<2, > +// CHECK: dxsa.mov r<12, >, r<10, > +// CHECK: %[[INDEX_31:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_32:.*]] = dxsa.operand %[[INDEX_31]] {mask = 128 : i32, num_components = 4 : i32, type = 0 : i32} +// CHECK: %[[INDEX_32:.*]] = dxsa.index.imm {imm = 11 : i32} +// CHECK: %[[OPERAND_33:.*]] = dxsa.operand %[[INDEX_32]] {num_components = 4 : i32, one = 0 : i32, type = 0 : i32} +// CHECK: dxsa.instruction "check_access_fully_mapped" %[[OPERAND_32]], %[[OPERAND_33]] +// CHECK: dxsa.and r<0, >, r<0, >, r<0, > +// CHECK: dxsa.and r<1, >, r<7, >, r<12, > +// CHECK: %[[INDEX_33:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_34:.*]] = dxsa.operand %[[INDEX_33]] {mask = 128 : i32, num_components = 4 : i32, type = 0 : i32} +// CHECK: %[[INDEX_34:.*]] = dxsa.index.imm {imm = 13 : i32} +// CHECK: %[[OPERAND_35:.*]] = dxsa.operand %[[INDEX_34]] {num_components = 4 : i32, one = 0 : i32, type = 0 : i32} +// CHECK: dxsa.instruction "check_access_fully_mapped" %[[OPERAND_34]], %[[OPERAND_35]] +// CHECK: dxsa.and r<0, >, r<0, >, r<0, > +// CHECK: dxsa.utof r<0, >, r<0, > +// CHECK: dxsa.or r<0, >, r<0, >, r<1, > +// CHECK: dxsa.itof r<0, >, r<0, > +// CHECK: dxsa.add r<3, >, r<0, >, r<3, > +// CHECK: dxsa.add r<0>, r<0, >, r<3> +// CHECK: dxsa.mul r<1, >, v<0, >, l(0x40400000) +// CHECK: dxsa.ftou r<1, >, r<1, > +// CHECK: %[[INDEX_35:.*]] = dxsa.index.imm {imm = 1 : i32} +// CHECK: %[[OPERAND_36:.*]] = dxsa.operand %[[INDEX_35]] {mask = 48 : i32, num_components = 4 : i32, type = 30 : i32} +// CHECK: %[[INDEX_36:.*]] = dxsa.index.imm {imm = 1 : i32} +// CHECK: %[[OPERAND_37:.*]] = dxsa.operand %[[INDEX_36]] {num_components = 4 : i32, one = 0 : i32, type = 0 : i32} +// CHECK: %[[OPERAND_38:.*]] = dxsa.operand.imm {imm = dense<0> : vector<1xi32>} +// CHECK: %[[INDEX_37:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_39:.*]] = dxsa.operand %[[INDEX_37]] {num_components = 4 : i32, swizzle = dense<[0, 1, 0, 0]> : vector<4xi32>, type = 0 : i32} +// CHECK: dxsa.instruction "store_structured" %[[OPERAND_36]], %[[OPERAND_37]], %[[OPERAND_38]], %[[OPERAND_39]] +// CHECK: %[[INDEX_38:.*]] = dxsa.index.imm {imm = 1 : i32} +// CHECK: %[[OPERAND_40:.*]] = dxsa.operand %[[INDEX_38]] {mask = 112 : i32, num_components = 4 : i32, type = 30 : i32} +// CHECK: %[[INDEX_39:.*]] = dxsa.index.imm {imm = 1 : i32} +// CHECK: %[[OPERAND_41:.*]] = dxsa.operand %[[INDEX_39]] {num_components = 4 : i32, one = 0 : i32, type = 0 : i32} +// CHECK: %[[OPERAND_42:.*]] = dxsa.operand.imm {imm = dense<8> : vector<1xi32>} +// CHECK: %[[INDEX_40:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_43:.*]] = dxsa.operand %[[INDEX_40]] {num_components = 4 : i32, swizzle = dense<[0, 1, 2, 0]> : vector<4xi32>, type = 0 : i32} +// CHECK: dxsa.instruction "store_structured" %[[OPERAND_40]], %[[OPERAND_41]], %[[OPERAND_42]], %[[OPERAND_43]] +// CHECK: dxsa.ftoi r<1, >, r<0, > +// CHECK: dxsa.mov o<0>, r<0> +// CHECK: %[[INDEX_41:.*]] = dxsa.index.imm {imm = 1 : i32} +// CHECK: %[[OPERAND_44:.*]] = dxsa.operand %[[INDEX_41]] {mask = 48 : i32, num_components = 4 : i32, type = 30 : i32} +// CHECK: %[[INDEX_42:.*]] = dxsa.index.imm {imm = 1 : i32} +// CHECK: %[[OPERAND_45:.*]] = dxsa.operand %[[INDEX_42]] {num_components = 4 : i32, one = 0 : i32, type = 0 : i32} +// CHECK: %[[INDEX_43:.*]] = dxsa.index.imm {imm = 1 : i32} +// CHECK: %[[OPERAND_46:.*]] = dxsa.operand %[[INDEX_43]] {num_components = 4 : i32, one = 3 : i32, type = 0 : i32} +// CHECK: %[[INDEX_44:.*]] = dxsa.index.imm {imm = 1 : i32} +// CHECK: %[[OPERAND_47:.*]] = dxsa.operand %[[INDEX_44]] {num_components = 4 : i32, swizzle = dense<[1, 2, 1, 1]> : vector<4xi32>, type = 0 : i32} +// CHECK: dxsa.instruction "store_structured" %[[OPERAND_44]], %[[OPERAND_45]], %[[OPERAND_46]], %[[OPERAND_47]] +// CHECK: dxsa.ret + diff --git a/mlir/test/Target/DXSA/hlsl/sub1.test b/mlir/test/Target/DXSA/hlsl/sub1.test new file mode 100644 index 000000000000..b1e6cfa97c7d --- /dev/null +++ b/mlir/test/Target/DXSA/hlsl/sub1.test @@ -0,0 +1,38 @@ +// RUN: mlir-translate --import-dxsa-bin %S/inputs/sub1.shex | FileCheck %s +// NOTE: Assertions have been autogenerated by utils/generate-test-checks.py + + +// CHECK-LABEL: dxsa.dcl_global_flags +// CHECK: dxsa.dcl_constant_buffer , +// CHECK: dxsa.dcl_input_ps linear v<0, > +// CHECK: dxsa.dcl_output o<0> +// CHECK: dxsa.dcl_temps 1 +// CHECK: dxsa.dcl_indexable_temp x<0>[8] +// CHECK: %[[INDEX_0:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[INDEX_1:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_0:.*]] = dxsa.operand %[[INDEX_0]], %[[INDEX_1]] {num_components = 4 : i32, one = 0 : i32, type = 8 : i32} +// CHECK: dxsa.instruction "switch" %[[OPERAND_0]] +// CHECK: dxsa.case l(0x0) +// CHECK: dxsa.call label<0> +// CHECK: dxsa.break +// CHECK: dxsa.case l(0x1) +// CHECK: dxsa.call label<1> +// CHECK: dxsa.break +// CHECK: dxsa.default +// CHECK: dxsa.call label<2> +// CHECK: dxsa.break +// CHECK: dxsa.endswitch +// CHECK: dxsa.mov r<0, >, cb<[0, 0], vector, > +// CHECK: dxsa.mov o<0>, x<[0, r<0, >]> +// CHECK: dxsa.ret +// CHECK: dxsa.label label<0> +// CHECK: dxsa.mov x<[0, 2]>, l(0x40800000, 0x40800000, 0x40800000, 0x40800000) +// CHECK: dxsa.ret +// CHECK: dxsa.label label<1> +// CHECK: dxsa.mov x<[0, 2]>, v<0, > +// CHECK: dxsa.ret +// CHECK: dxsa.label label<2> +// CHECK: dxsa.mov r<0, >, cb<[0, 0], vector, > +// CHECK: dxsa.mov x<[0, r<0, >]>, l(0x0, 0x0, 0x0, 0x0) +// CHECK: dxsa.ret + diff --git a/mlir/test/Target/DXSA/hlsl/switch1.test b/mlir/test/Target/DXSA/hlsl/switch1.test new file mode 100644 index 000000000000..1c197ed9f849 --- /dev/null +++ b/mlir/test/Target/DXSA/hlsl/switch1.test @@ -0,0 +1,25 @@ +// RUN: mlir-translate --import-dxsa-bin %S/inputs/switch1.shex | FileCheck %s +// NOTE: Assertions have been autogenerated by utils/generate-test-checks.py + + +// CHECK-LABEL: dxsa.dcl_global_flags +// CHECK: dxsa.dcl_input_ps linear v<0, > +// CHECK: dxsa.dcl_input_ps constant v<1, > +// CHECK: dxsa.dcl_output o<0, > +// CHECK: dxsa.dcl_temps 1 +// CHECK: %[[INDEX_0:.*]] = dxsa.index.imm {imm = 1 : i32} +// CHECK: %[[OPERAND_0:.*]] = dxsa.operand %[[INDEX_0]] {num_components = 4 : i32, one = 0 : i32, type = 1 : i32} +// CHECK: dxsa.instruction "switch" %[[OPERAND_0]] +// CHECK: dxsa.case l(0x1) +// CHECK: dxsa.mov r<0, >, l(0x40A00000) +// CHECK: dxsa.break +// CHECK: dxsa.case l(0x2) +// CHECK: dxsa.mov r<0, >, v<0, > +// CHECK: dxsa.break +// CHECK: dxsa.default +// CHECK: dxsa.mov r<0, >, l(0x40400000) +// CHECK: dxsa.break +// CHECK: dxsa.endswitch +// CHECK: dxsa.mov o<0, >, r<0, > +// CHECK: dxsa.ret + diff --git a/mlir/test/Target/DXSA/hlsl/switch2.test b/mlir/test/Target/DXSA/hlsl/switch2.test new file mode 100644 index 000000000000..125f566f06eb --- /dev/null +++ b/mlir/test/Target/DXSA/hlsl/switch2.test @@ -0,0 +1,36 @@ +// RUN: mlir-translate --import-dxsa-bin %S/inputs/switch2.shex | FileCheck %s +// NOTE: Assertions have been autogenerated by utils/generate-test-checks.py + + +// CHECK-LABEL: dxsa.dcl_global_flags +// CHECK: dxsa.dcl_input_ps linear v<0, > +// CHECK: dxsa.dcl_input_ps constant v<1, > +// CHECK: dxsa.dcl_output o<0, > +// CHECK: dxsa.dcl_temps 1 +// CHECK: %[[INDEX_0:.*]] = dxsa.index.imm {imm = 1 : i32} +// CHECK: %[[OPERAND_0:.*]] = dxsa.operand %[[INDEX_0]] {num_components = 4 : i32, one = 0 : i32, type = 1 : i32} +// CHECK: dxsa.instruction "switch" %[[OPERAND_0]] +// CHECK: dxsa.case l(0x1) +// CHECK: dxsa.ieq r<0, >, v<1, >, l(0xB) +// CHECK: %[[INDEX_1:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_1:.*]] = dxsa.operand %[[INDEX_1]] {num_components = 4 : i32, one = 1 : i32, type = 0 : i32} +// CHECK: dxsa.instruction "if" %[[OPERAND_1]] +// CHECK: dxsa.mov r<0, >, l(0x40A00000) +// CHECK: dxsa.break +// CHECK: dxsa.endif +// CHECK: dxsa.mov r<0, >, l(0x40B00000) +// CHECK: dxsa.break +// CHECK: dxsa.case l(0x2) +// CHECK: dxsa.ieq r<0, >, v<1, >, l(0xC) +// CHECK: %[[INDEX_2:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_2:.*]] = dxsa.operand %[[INDEX_2]] {num_components = 4 : i32, one = 1 : i32, type = 0 : i32} +// CHECK: dxsa.instruction "breakc" %[[OPERAND_2]] +// CHECK: dxsa.mov r<0, >, v<0, > +// CHECK: dxsa.break +// CHECK: dxsa.default +// CHECK: dxsa.mov r<0, >, l(0x40400000) +// CHECK: dxsa.break +// CHECK: dxsa.endswitch +// CHECK: dxsa.mov o<0, >, r<0, > +// CHECK: dxsa.ret + diff --git a/mlir/test/Target/DXSA/hlsl/switch3.test b/mlir/test/Target/DXSA/hlsl/switch3.test new file mode 100644 index 000000000000..a7be8a07519e --- /dev/null +++ b/mlir/test/Target/DXSA/hlsl/switch3.test @@ -0,0 +1,46 @@ +// RUN: mlir-translate --import-dxsa-bin %S/inputs/switch3.shex | FileCheck %s +// NOTE: Assertions have been autogenerated by utils/generate-test-checks.py + + +// CHECK-LABEL: dxsa.dcl_global_flags +// CHECK: dxsa.dcl_input_ps linear v<0, > +// CHECK: dxsa.dcl_input_ps constant v<1, > +// CHECK: dxsa.dcl_output o<0, > +// CHECK: dxsa.dcl_temps 1 +// CHECK: %[[INDEX_0:.*]] = dxsa.index.imm {imm = 1 : i32} +// CHECK: %[[OPERAND_0:.*]] = dxsa.operand %[[INDEX_0]] {num_components = 4 : i32, one = 0 : i32, type = 1 : i32} +// CHECK: dxsa.instruction "switch" %[[OPERAND_0]] +// CHECK: dxsa.case l(0x1) +// CHECK: %[[INDEX_1:.*]] = dxsa.index.imm {imm = 1 : i32} +// CHECK: %[[OPERAND_1:.*]] = dxsa.operand %[[INDEX_1]] {num_components = 4 : i32, one = 1 : i32, type = 1 : i32} +// CHECK: dxsa.instruction "switch" %[[OPERAND_1]] +// CHECK: dxsa.case l(0x14) +// CHECK: dxsa.ieq r<0, >, v<1, >, l(0x1E) +// CHECK: %[[INDEX_2:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_2:.*]] = dxsa.operand %[[INDEX_2]] {num_components = 4 : i32, one = 1 : i32, type = 0 : i32} +// CHECK: dxsa.instruction "if" %[[OPERAND_2]] +// CHECK: dxsa.mov r<0, >, l(0x40B00000) +// CHECK: dxsa.break +// CHECK: dxsa.endif +// CHECK: dxsa.ieq r<0, >, v<1, >, l(0x1F) +// CHECK: dxsa.mov r<0, >, l(0x40B66666) +// CHECK: %[[INDEX_3:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_3:.*]] = dxsa.operand %[[INDEX_3]] {num_components = 4 : i32, one = 1 : i32, type = 0 : i32} +// CHECK: dxsa.instruction "breakc" %[[OPERAND_3]] +// CHECK: dxsa.mov r<0, >, l(0x40B9999A) +// CHECK: dxsa.break +// CHECK: dxsa.default +// CHECK: dxsa.mov r<0, >, v<0, > +// CHECK: dxsa.break +// CHECK: dxsa.endswitch +// CHECK: dxsa.break +// CHECK: dxsa.case l(0x2) +// CHECK: dxsa.mov r<0, >, v<0, > +// CHECK: dxsa.break +// CHECK: dxsa.default +// CHECK: dxsa.mov r<0, >, l(0x40400000) +// CHECK: dxsa.break +// CHECK: dxsa.endswitch +// CHECK: dxsa.mov o<0, >, r<0, > +// CHECK: dxsa.ret + diff --git a/mlir/test/Target/DXSA/hlsl/swizzle1.test b/mlir/test/Target/DXSA/hlsl/swizzle1.test new file mode 100644 index 000000000000..5df120211f18 --- /dev/null +++ b/mlir/test/Target/DXSA/hlsl/swizzle1.test @@ -0,0 +1,15 @@ +// RUN: mlir-translate --import-dxsa-bin %S/inputs/swizzle1.shex | FileCheck %s +// NOTE: Assertions have been autogenerated by utils/generate-test-checks.py + + +// CHECK-LABEL: dxsa.dcl_global_flags +// CHECK: dxsa.dcl_input_ps linear v<0, > +// CHECK: dxsa.dcl_input_ps linear v<1, > +// CHECK: dxsa.dcl_input_ps linear v<2, > +// CHECK: dxsa.dcl_output o<0> +// CHECK: dxsa.dcl_temps 1 +// CHECK: dxsa.add r<0>, v<0, >, v<1, > +// CHECK: dxsa.add r<0>, r<0>, v<2, > +// CHECK: dxsa.add o<0>, r<0>, l(0x0, 0x3F800000, 0x40000000, 0x40400000) +// CHECK: dxsa.ret + diff --git a/mlir/test/Target/DXSA/hlsl/temp1.test b/mlir/test/Target/DXSA/hlsl/temp1.test new file mode 100644 index 000000000000..68ac9dd51553 --- /dev/null +++ b/mlir/test/Target/DXSA/hlsl/temp1.test @@ -0,0 +1,13 @@ +// RUN: mlir-translate --import-dxsa-bin %S/inputs/temp1.shex | FileCheck %s +// NOTE: Assertions have been autogenerated by utils/generate-test-checks.py + + +// CHECK-LABEL: dxsa.dcl_global_flags +// CHECK: dxsa.dcl_input_ps linear v<0> +// CHECK: dxsa.dcl_input_ps linear v<1> +// CHECK: dxsa.dcl_output o<0> +// CHECK: dxsa.dcl_temps 1 +// CHECK: dxsa.add r<0>, v<0>, v<1> +// CHECK: dxsa.add o<0>, r<0>, l(0x0, 0x3F800000, 0x40000000, 0x40400000) +// CHECK: dxsa.ret + diff --git a/mlir/test/Target/DXSA/hlsl/temp2.test b/mlir/test/Target/DXSA/hlsl/temp2.test new file mode 100644 index 000000000000..c2b403244759 --- /dev/null +++ b/mlir/test/Target/DXSA/hlsl/temp2.test @@ -0,0 +1,13 @@ +// RUN: mlir-translate --import-dxsa-bin %S/inputs/temp2.shex | FileCheck %s +// NOTE: Assertions have been autogenerated by utils/generate-test-checks.py + + +// CHECK-LABEL: dxsa.dcl_global_flags +// CHECK: dxsa.dcl_input_ps constant v<0> +// CHECK: dxsa.dcl_input_ps constant v<1> +// CHECK: dxsa.dcl_output o<0> +// CHECK: dxsa.dcl_temps 1 +// CHECK: dxsa.iadd r<0>, v<0>, v<1> +// CHECK: dxsa.iadd o<0>, r<0>, l(0x0, 0x1, 0x2, 0x3) +// CHECK: dxsa.ret + diff --git a/mlir/test/Target/DXSA/hlsl/uav_counter_dec.test b/mlir/test/Target/DXSA/hlsl/uav_counter_dec.test new file mode 100644 index 000000000000..15e4469b70b2 --- /dev/null +++ b/mlir/test/Target/DXSA/hlsl/uav_counter_dec.test @@ -0,0 +1,10 @@ +// RUN: mlir-translate --import-dxsa-bin %S/inputs/uav_counter_dec.shex | FileCheck %s +// NOTE: Assertions have been autogenerated by utils/generate-test-checks.py + + +// CHECK-LABEL: dxsa.dcl_global_flags +// CHECK: dxsa.dcl_uav_structured , +// CHECK: dxsa.dcl_temps 1 +// CHECK: dxsa.imm_atomic_consume r<0, >, u<0> +// CHECK: dxsa.ret + diff --git a/mlir/test/Target/DXSA/hlsl/uav_counter_inc.test b/mlir/test/Target/DXSA/hlsl/uav_counter_inc.test new file mode 100644 index 000000000000..da80965fb2f5 --- /dev/null +++ b/mlir/test/Target/DXSA/hlsl/uav_counter_inc.test @@ -0,0 +1,10 @@ +// RUN: mlir-translate --import-dxsa-bin %S/inputs/uav_counter_inc.shex | FileCheck %s +// NOTE: Assertions have been autogenerated by utils/generate-test-checks.py + + +// CHECK-LABEL: dxsa.dcl_global_flags +// CHECK: dxsa.dcl_uav_structured , +// CHECK: dxsa.dcl_temps 1 +// CHECK: dxsa.imm_atomic_alloc r<0, >, u<0> +// CHECK: dxsa.ret + diff --git a/mlir/test/Target/DXSA/hlsl/uav_raw1.test b/mlir/test/Target/DXSA/hlsl/uav_raw1.test new file mode 100644 index 000000000000..94f9725a04d1 --- /dev/null +++ b/mlir/test/Target/DXSA/hlsl/uav_raw1.test @@ -0,0 +1,31 @@ +// RUN: mlir-translate --import-dxsa-bin %S/inputs/uav_raw1.shex | FileCheck %s +// NOTE: Assertions have been autogenerated by utils/generate-test-checks.py + + +// CHECK-LABEL: dxsa.dcl_global_flags +// CHECK: dxsa.dcl_uav_raw +// CHECK: dxsa.dcl_input_ps constant v<0, > +// CHECK: dxsa.dcl_input_ps constant v<0, > +// CHECK: dxsa.dcl_output o<0> +// CHECK: dxsa.dcl_temps 2 +// CHECK: dxsa.unknown +// CHECK: dxsa.utof r<0, >, r<0, > +// CHECK: dxsa.unknown +// CHECK: %[[INDEX_0:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_0:.*]] = dxsa.operand %[[INDEX_0]] {mask = 32 : i32, num_components = 4 : i32, type = 0 : i32} +// CHECK: %[[INDEX_1:.*]] = dxsa.index.imm {imm = 1 : i32} +// CHECK: %[[OPERAND_1:.*]] = dxsa.operand %[[INDEX_1]] {num_components = 4 : i32, one = 0 : i32, type = 0 : i32} +// CHECK: dxsa.instruction "check_access_fully_mapped" %[[OPERAND_0]], %[[OPERAND_1]] +// CHECK: dxsa.utof r<0, >, r<0, > +// CHECK: dxsa.mad r<0>, r<0, >, l(0x40000000, 0x40000000, 0x40000000, 0x40000000), r<0, > +// CHECK: dxsa.ftou r<1, >, r<0, > +// CHECK: dxsa.mov o<0>, r<0> +// CHECK: %[[INDEX_2:.*]] = dxsa.index.imm {imm = 3 : i32} +// CHECK: %[[OPERAND_2:.*]] = dxsa.operand %[[INDEX_2]] {mask = 240 : i32, num_components = 4 : i32, type = 30 : i32} +// CHECK: %[[INDEX_3:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_3:.*]] = dxsa.operand %[[INDEX_3]] {num_components = 4 : i32, one = 1 : i32, type = 1 : i32} +// CHECK: %[[INDEX_4:.*]] = dxsa.index.imm {imm = 1 : i32} +// CHECK: %[[OPERAND_4:.*]] = dxsa.operand %[[INDEX_4]] {num_components = 4 : i32, swizzle = dense<0> : vector<4xi32>, type = 0 : i32} +// CHECK: dxsa.instruction "store_raw" %[[OPERAND_2]], %[[OPERAND_3]], %[[OPERAND_4]] +// CHECK: dxsa.ret + diff --git a/mlir/test/Target/DXSA/hlsl/uav_typed_load_store1.test b/mlir/test/Target/DXSA/hlsl/uav_typed_load_store1.test new file mode 100644 index 000000000000..a479e7f0c52c --- /dev/null +++ b/mlir/test/Target/DXSA/hlsl/uav_typed_load_store1.test @@ -0,0 +1,31 @@ +// RUN: mlir-translate --import-dxsa-bin %S/inputs/uav_typed_load_store1.shex | FileCheck %s +// NOTE: Assertions have been autogenerated by utils/generate-test-checks.py + + +// CHECK-LABEL: dxsa.dcl_global_flags +// CHECK: dxsa.dcl_uav_typed , +// CHECK: dxsa.dcl_input_ps constant v<0, > +// CHECK: dxsa.dcl_input_ps constant v<0, > +// CHECK: dxsa.dcl_output o<0> +// CHECK: dxsa.dcl_temps 2 +// CHECK: dxsa.unknown +// CHECK: dxsa.unknown +// CHECK: dxsa.add r<0>, r<0>, r<1> +// CHECK: dxsa.unknown +// CHECK: %[[INDEX_0:.*]] = dxsa.index.imm {imm = 1 : i32} +// CHECK: %[[OPERAND_0:.*]] = dxsa.operand %[[INDEX_0]] {mask = 16 : i32, num_components = 4 : i32, type = 0 : i32} +// CHECK: %[[INDEX_1:.*]] = dxsa.index.imm {imm = 1 : i32} +// CHECK: %[[OPERAND_1:.*]] = dxsa.operand %[[INDEX_1]] {num_components = 4 : i32, one = 0 : i32, type = 0 : i32} +// CHECK: dxsa.instruction "check_access_fully_mapped" %[[OPERAND_0]], %[[OPERAND_1]] +// CHECK: dxsa.utof r<1, >, r<1, > +// CHECK: dxsa.mad r<0>, r<1, >, l(0x40000000, 0x40000000, 0x40000000, 0x40000000), r<0> +// CHECK: %[[INDEX_2:.*]] = dxsa.index.imm {imm = 3 : i32} +// CHECK: %[[OPERAND_2:.*]] = dxsa.operand %[[INDEX_2]] {mask = 240 : i32, num_components = 4 : i32, type = 30 : i32} +// CHECK: %[[INDEX_3:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_3:.*]] = dxsa.operand %[[INDEX_3]] {num_components = 4 : i32, swizzle = dense<[2, 3, 3, 3]> : vector<4xi32>, type = 1 : i32} +// CHECK: %[[INDEX_4:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_4:.*]] = dxsa.operand %[[INDEX_4]] {num_components = 4 : i32, swizzle = dense<[0, 1, 2, 3]> : vector<4xi32>, type = 0 : i32} +// CHECK: dxsa.instruction "store_uav_typed" %[[OPERAND_2]], %[[OPERAND_3]], %[[OPERAND_4]] +// CHECK: dxsa.mov o<0>, r<0> +// CHECK: dxsa.ret + diff --git a/mlir/test/Target/DXSA/hlsl/uav_typed_load_store2.test b/mlir/test/Target/DXSA/hlsl/uav_typed_load_store2.test new file mode 100644 index 000000000000..431c092cc75a --- /dev/null +++ b/mlir/test/Target/DXSA/hlsl/uav_typed_load_store2.test @@ -0,0 +1,38 @@ +// RUN: mlir-translate --import-dxsa-bin %S/inputs/uav_typed_load_store2.shex | FileCheck %s +// NOTE: Assertions have been autogenerated by utils/generate-test-checks.py + + +// CHECK-LABEL: dxsa.dcl_global_flags +// CHECK: dxsa.dcl_uav_typed , +// CHECK: dxsa.dcl_input_ps constant v<0, > +// CHECK: dxsa.dcl_input_ps constant v<0, > +// CHECK: dxsa.dcl_output o<0, > +// CHECK: dxsa.dcl_temps 5 +// CHECK: dxsa.unknown +// CHECK: dxsa.unknown +// CHECK: dxsa.iadd r<2, >, r<0, min16i, >, r<1, min16i, > +// CHECK: dxsa.unknown +// CHECK: dxsa.unknown +// CHECK: %[[INDEX_0:.*]] = dxsa.index.imm {imm = 2 : i32} +// CHECK: %[[OPERAND_0:.*]] = dxsa.operand %[[INDEX_0]] {mask = 128 : i32, num_components = 4 : i32, type = 0 : i32} +// CHECK: %[[INDEX_1:.*]] = dxsa.index.imm {imm = 3 : i32} +// CHECK: %[[OPERAND_1:.*]] = dxsa.operand %[[INDEX_1]] {num_components = 4 : i32, one = 0 : i32, type = 0 : i32} +// CHECK: dxsa.instruction "check_access_fully_mapped" %[[OPERAND_0]], %[[OPERAND_1]] +// CHECK: dxsa.iadd r<2, >, r<2, >, r<2, > +// CHECK: %[[INDEX_2:.*]] = dxsa.index.imm {imm = 2 : i32} +// CHECK: %[[OPERAND_2:.*]] = dxsa.operand %[[INDEX_2]] {mask = 128 : i32, num_components = 4 : i32, type = 0 : i32} +// CHECK: %[[INDEX_3:.*]] = dxsa.index.imm {imm = 4 : i32} +// CHECK: %[[OPERAND_3:.*]] = dxsa.operand %[[INDEX_3]] {num_components = 4 : i32, one = 0 : i32, type = 0 : i32} +// CHECK: dxsa.instruction "check_access_fully_mapped" %[[OPERAND_2]], %[[OPERAND_3]] +// CHECK: dxsa.iadd r<2, >, r<0, min16i, >, r<2, > +// CHECK: dxsa.iadd r<2, >, r<2, >, r<2, > +// CHECK: %[[INDEX_4:.*]] = dxsa.index.imm {imm = 3 : i32} +// CHECK: %[[OPERAND_4:.*]] = dxsa.operand %[[INDEX_4]] {mask = 240 : i32, num_components = 4 : i32, type = 30 : i32} +// CHECK: %[[INDEX_5:.*]] = dxsa.index.imm {imm = 0 : i32} +// CHECK: %[[OPERAND_5:.*]] = dxsa.operand %[[INDEX_5]] {num_components = 4 : i32, swizzle = dense<1> : vector<4xi32>, type = 1 : i32} +// CHECK: %[[INDEX_6:.*]] = dxsa.index.imm {imm = 2 : i32} +// CHECK: %[[OPERAND_6:.*]] = dxsa.operand %[[INDEX_6]] {num_components = 4 : i32, swizzle = dense<[0, 1, 2, 0]> : vector<4xi32>, type = 0 : i32} +// CHECK: dxsa.instruction "store_uav_typed" %[[OPERAND_4]], %[[OPERAND_5]], %[[OPERAND_6]] +// CHECK: dxsa.mov o<0, >, r<2, > +// CHECK: dxsa.ret + diff --git a/mlir/test/Target/DXSA/hlsl/ubfeu16.test b/mlir/test/Target/DXSA/hlsl/ubfeu16.test new file mode 100644 index 000000000000..0a9e850735fc --- /dev/null +++ b/mlir/test/Target/DXSA/hlsl/ubfeu16.test @@ -0,0 +1,14 @@ +// RUN: mlir-translate --import-dxsa-bin %S/inputs/ubfeu16.shex | FileCheck %s +// NOTE: Assertions have been autogenerated by utils/generate-test-checks.py + + +// CHECK-LABEL: dxsa.dcl_global_flags +// CHECK: dxsa.dcl_constant_buffer , +// CHECK: dxsa.dcl_output o<0, min16u, > +// CHECK: dxsa.dcl_temps 1 +// CHECK: dxsa.ubfe r<0, min16u, >, l(0x1B), l(0x5), cb<[0, 0], vector, min16u, > +// CHECK: dxsa.and r<0, min16u, >, cb<[0, 0], vector, min16u, >, l(0xFFFFFFFC) +// CHECK: dxsa.xor r<0, min16u, >, r<0, min16u, >, r<0, min16u, > +// CHECK: dxsa.iadd o<0, min16u, >, r<0, min16u, >, r<0, min16u, > +// CHECK: dxsa.ret +