diff --git a/os/hal/ports/NUMICRO/LLD/GPIOv2/hal_pal_lld.c b/os/hal/ports/NUMICRO/LLD/GPIOv2/hal_pal_lld.c
index 696957c29b..b061aa1a97 100644
--- a/os/hal/ports/NUMICRO/LLD/GPIOv2/hal_pal_lld.c
+++ b/os/hal/ports/NUMICRO/LLD/GPIOv2/hal_pal_lld.c
@@ -191,26 +191,36 @@ void _pal_lld_setgroupmode(ioportid_t port,
                            ioportmask_t mask,
                            iomode_t mode) {
 
-  uint32_t nucMode = 0;
-
-  if (mode == PAL_MODE_INPUT)
-      nucMode = GPIO_MODE_INPUT;
-  else if (mode == PAL_MODE_OUTPUT_OPENDRAIN)
-      nucMode = GPIO_MODE_OPEN_DRAIN;
-  else if (mode == PAL_MODE_OUTPUT_PUSHPULL)
-      nucMode = GPIO_MODE_OUTPUT;
-  else /* mode == PAL_MODE_INPUT_PULLUP */
-      nucMode = GPIO_MODE_QUASI;
+  uint32_t nucMode;
+
+  switch (mode) {
+  case PAL_MODE_INPUT:
+  case PAL_MODE_INPUT_ANALOG:
+    nucMode = GPIO_MODE_INPUT;
+    break;
+  case PAL_MODE_OUTPUT_PUSHPULL:
+    nucMode = GPIO_MODE_OUTPUT;
+    break;
+  case PAL_MODE_OUTPUT_OPENDRAIN:
+    nucMode = GPIO_MODE_OPEN_DRAIN;
+    break;
+  case PAL_MODE_RESET:
+  case PAL_MODE_UNCONNECTED:
+  case PAL_MODE_INPUT_PULLUP:
+    /* Quasi-bidirectional mode drives the pin low while DOUT is 0. */
+    port->DOUT |= (uint32_t)(uint16_t)mask;
+    nucMode = GPIO_MODE_QUASI;
+    break;
+  default:
+    /* PAL_MODE_INPUT_PULLDOWN (the chip has no pull-down) and unknown modes. */
+    return;
+  }
 
   for (uint32_t i = 0; i < PAL_IOPORTS_WIDTH; i++) {
     if (mask & (1 << i)) {
       port->MODE = (port->MODE & ~(0x03ul << (i << 1))) | (nucMode << (i << 1));
     }
   }
-
-  if (nucMode == GPIO_MODE_QUASI) {
-    port->DOUT |= (uint32_t)(uint16_t)mask;
-  }
 }
 
 #endif /* HAL_USE_PAL == TRUE */
diff --git a/os/hal/ports/NUMICRO/LLD/GPIOv2/hal_pal_lld.h b/os/hal/ports/NUMICRO/LLD/GPIOv2/hal_pal_lld.h
index 17787252e7..c7db2d1782 100644
--- a/os/hal/ports/NUMICRO/LLD/GPIOv2/hal_pal_lld.h
+++ b/os/hal/ports/NUMICRO/LLD/GPIOv2/hal_pal_lld.h
@@ -47,27 +47,6 @@
 #define GPIO_MODE_OPEN_DRAIN                               0x02ul          /*!< Open-Drain Mode */
 #define GPIO_MODE_QUASI                                    0x03ul          /*!< Quasi-bidirectional Mode */
 
-/**
- * @brief   NUC126 specific alternate input mode.
- */
-#define PAL_MODE_NUC126_ALTERNATE_INPUT                   GPIO_MODE_INPUT
-
-/**
- * @brief   NUC126 specific alternate push-pull output mode.
- */
-#define PAL_MODE_NUC126_ALTERNATE_OUTPUT                  GPIO_MODE_OUTPUT
-/** @} */
-
-/**
- * @brief   NUC126 specific alternate output mode.
- */
-#define PAL_MODE_NUC126_ALTERNATE_OPEN_DRAIN              GPIO_MODE_OPEN_DRAIN
-/** @} */
-
-/**
- * @brief   NUC126 specific alternate output mode.
- */
-#define PAL_MODE_NUC126_ALTERNATE_QUASI                   GPIO_MODE_QUASI
 /** @} */
 
 /**
@@ -907,8 +886,7 @@
  * @brief   Whole port mask.
  * @details This macro specifies all the valid bits into a port.
  */
-/* #define PAL_WHOLE_PORT              ((ioportmask_t)0xFFFFU) */
-#define PAL_WHOLE_PORT ((ioportmask_t)(2^PAL_IOPORTS_WIDTH) - 1)
+#define PAL_WHOLE_PORT              ((ioportmask_t)0xFFFFU)
 /** @} */
 
 /**
diff --git a/os/hal/ports/NUMICRO/LLD/TIMv2/hal_st_lld.h b/os/hal/ports/NUMICRO/LLD/TIMv2/hal_st_lld.h
index 9a52db109b..14a54751e0 100644
--- a/os/hal/ports/NUMICRO/LLD/TIMv2/hal_st_lld.h
+++ b/os/hal/ports/NUMICRO/LLD/TIMv2/hal_st_lld.h
@@ -61,7 +61,7 @@
  * @brief   SysTick timer IRQ priority.
  */
 #if !defined(NUC126_ST_IRQ_PRIORITY) || defined(__DOXYGEN__)
-#define NUC126_ST_IRQ_PRIORITY                     8
+#define NUC126_ST_IRQ_PRIORITY                     2
 #endif
 
 /**
@@ -79,6 +79,10 @@
 /* Derived constants and error checks.                                       */
 /*===========================================================================*/
 
+#if !OSAL_IRQ_IS_VALID_PRIORITY(NUC126_ST_IRQ_PRIORITY)
+#error "Invalid IRQ priority assigned to ST"
+#endif
+
 #if (NUC126_ST_USE_TIMER == 2)
 #if !NUC126_HAS_TIM2
 #error "TIM2 not present"
diff --git a/os/hal/ports/NUMICRO/LLD/USBv2/hal_usb_lld.h b/os/hal/ports/NUMICRO/LLD/USBv2/hal_usb_lld.h
index 6b4d43af7d..5f49800a9b 100644
--- a/os/hal/ports/NUMICRO/LLD/USBv2/hal_usb_lld.h
+++ b/os/hal/ports/NUMICRO/LLD/USBv2/hal_usb_lld.h
@@ -108,6 +108,10 @@
 #error "NUC126 USB subsystem enabled, but no driver configured"
 #endif
 
+#if NUC126_USB_USE_USB1 && !OSAL_IRQ_IS_VALID_PRIORITY(NUC126_USB_IRQ_PRIORITY)
+#error "Invalid IRQ priority assigned to USB1"
+#endif
+
 /*===========================================================================*/
 /* Driver data structures and types.                                         */
 /*===========================================================================*/
diff --git a/os/hal/ports/NUMICRO/NUC126/hal_lld.c b/os/hal/ports/NUMICRO/NUC126/hal_lld.c
index 41dfa9108f..e67e8a0a06 100644
--- a/os/hal/ports/NUMICRO/NUC126/hal_lld.c
+++ b/os/hal/ports/NUMICRO/NUC126/hal_lld.c
@@ -48,7 +48,7 @@
 
 #define CLK_PLLCTL_72MHz_HXT    CLK_PLLCTL(NUC126_PLLSRC_HSE, 4, 48, 2) /*!< Predefined PLLCTL setting for 72MHz PLL output with HXT(12MHz X'tal) */
 #define CLK_PLLCTL_144MHz_HXT    CLK_PLLCTL(NUC126_PLLSRC_HSE, 4, 48, 1) /*!< Predefined PLLCTL setting for 144MHz PLL output with HXT(12MHz X'tal) */
-#define CLK_PLLCTL_72MHz_HIRC    CLK_PLLCTL(NUC126_PLLSRC_HSE, 8, 52, 2) /*!< Predefined PLLCTL setting for 71.8848MHz PLL output with HIRC(22.1184MHz IRC) */
+#define CLK_PLLCTL_72MHz_HIRC    CLK_PLLCTL(NUC126_PLLSRC_HSI, 8, 52, 2) /*!< Predefined PLLCTL setting for 71.8848MHz PLL output with HIRC(22.1184MHz IRC) */
 
 /*===========================================================================*/
 /* Driver exported variables.                                                */
@@ -65,7 +65,11 @@ uint32_t CyclesPerUs      = (__HSI / 1000000);  /*!< Cycles per micro second
 #if NUC126_PLL_ENABLED
 uint32_t PllClock         = __HSI;              /*!< PLL Output Clock Frequency          */
 #endif
+#if NUC126_HSE_ENABLED
+const uint32_t gau32ClkSrcTbl[] = {NUC126_HSECLK, __LXT, __HSI, __LIRC, __HIRC48, 0UL, 0UL, __HIRC};
+#else
 const uint32_t gau32ClkSrcTbl[] = {__HXT, __LXT, __HSI, __LIRC, __HIRC48, 0UL, 0UL, __HIRC};
+#endif
 
 #if (NUC126_CONFIG_ENABLED == TRUE)
 
@@ -351,7 +355,7 @@ uint32_t CLK_EnablePLL(uint32_t pllSrc, uint32_t pllFreq)
   }
 
   /* Enable and apply new PLL setting. */
-  CLK->PLLCTL = CLK_PLLCTL(pllSrc, NO, bestNR, bestNF);
+  CLK->PLLCTL = CLK_PLLCTL(pllSrc, bestNR, bestNF, NO);
 
   /* Wait for PLL clock stable */
   CLK_WaitClockReady(CLK_STATUS_PLLSTB_Msk);
@@ -406,7 +410,7 @@ uint32_t CLK_SetCoreClock(uint32_t u32Hclk)
     }
 
     /* Set HCLK clock source to PLL */
-    CLK_SetHCLK(NUC126_HCLKSRC_PLL, CLK_CLKDIV0_HCLK(1));
+    CLK_SetHCLK(NUC126_HCLKSRC_PLL, CLK_CLKDIV0_HCLK(2));
 
     /* Disable HIRC if HIRC was disabled before we started */
     if(u32HIRCSTB == 0) {